diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf537')
| -rw-r--r-- | include/asm-blackfin/mach-bf537/anomaly.h | 249 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf537/bf537.h | 158 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf537/blackfin.h | 280 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf537/cdefBF534.h | 4 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf537/defBF534.h | 4 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf537/irq.h | 2 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf537/mem_map.h | 60 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf537/portmux.h | 2 |
8 files changed, 173 insertions, 586 deletions
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h index 4453e614c3b1..2b66ecf489f7 100644 --- a/include/asm-blackfin/mach-bf537/anomaly.h +++ b/include/asm-blackfin/mach-bf537/anomaly.h @@ -1,139 +1,144 @@ - /* - * File: include/asm-blackfin/mach-bf537/anomaly.h - * Based on: - * Author: - * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. + * File: include/asm-blackfin/mach-bf537/anomaly.h + * Bugs: Enter bugs at http://blackfin.uclinux.org/ * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Copyright (C) 2004-2007 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ /* This file shoule be up to date with: - * - Revision J, June 1, 2006; ADSP-BF537 Blackfin Processor Anomaly List - * - Revision I, June 1, 2006; ADSP-BF536 Blackfin Processor Anomaly List - * - Revision J, June 1, 2006; ADSP-BF534 Blackfin Processor Anomaly List + * - Revision M, March 13, 2007; ADSP-BF537 Blackfin Processor Anomaly List + * - Revision L, March 13, 2007; ADSP-BF536 Blackfin Processor Anomaly List + * - Revision M, March 13, 2007; ADSP-BF534 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_ /* We do not support 0.1 silicon - sorry */ -#if (defined(CONFIG_BF_REV_0_1)) -#error Kernel will not work on BF537/6/4 Version 0.1 +#if __SILICON_REVISION__ < 2 +# error Kernel will not work on BF537 silicon version 0.0 or 0.1 #endif -#if (defined(CONFIG_BF_REV_0_3) || defined(CONFIG_BF_REV_0_2)) -#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in - slot1 and store of a P register in slot 2 is not - supported */ -#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive - Channel DMA stops */ -#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR - registers. */ -#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out - upper bits*/ -#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame - syncs */ -#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) -#define ANOMALY_05000247 /* CLKIN Buffer Output Enable Reset Behavior Is - Changed */ -#endif -#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on - SPORT external receive and transmit clocks. */ -#define ANOMALY_05000272 /* Certain data cache write through modes fail for - VDDint <=0.9V */ -#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */ -#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after - an edge is detected may clear interrupt */ -#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is - not restored */ -#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic - control */ -#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when - killed in a particular stage*/ -#define ANOMALY_05000310 /* False hardware errors caused by fetches at the - * boundary of reserved memory */ -#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC - registers are interrupted */ -#define ANOMALY_05000313 /* PPI is level sensitive on first transfer */ -#define ANOMALY_05000322 /* EMAC RMII mode at 10-Base-T speed: RX frames not - * received properly */ +#if defined(__ADSPBF534__) +# define ANOMALY_BF534 1 +#else +# define ANOMALY_BF534 0 #endif - -#if defined(CONFIG_BF_REV_0_2) -#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or - IDLE around a Change of Control causes - unpredictable results */ -#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel - (TDM) */ -#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) -#define ANOMALY_05000252 /* EMAC Tx DMA error after an early frame abort */ +#if defined(__ADSPBF536__) +# define ANOMALY_BF536 1 +#else +# define ANOMALY_BF536 0 #endif -#define ANOMALY_05000253 /* Maximum external clock speed for Timers */ -#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event - interrupt not functional */ -#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) -#define ANOMALY_05000256 /* EMAC MDIO input latched on wrong MDC edge */ +#if defined(__ADSPBF537__) +# define ANOMALY_BF537 1 +#else +# define ANOMALY_BF537 0 #endif -#define ANOMALY_05000257 /* An interrupt or exception during short Hardware - loops may cause the instruction fetch unit to - malfunction */ -#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of - the ICPLB Data registers differ */ -#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */ -#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */ -#define ANOMALY_05000262 /* Stores to data cache may be lost */ -#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */ -#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE - instruction will cause an infinite stall in the - second to last instruction in a hardware loop */ -#define ANOMALY_05000268 /* Memory DMA error when peripheral DMA is running - and non-zero DEB_TRAFFIC_PERIOD value */ -#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the - internal voltage regulator (VDDint) to decrease */ -#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after - an edge is detected may clear interrupt */ -#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause - DMA system instability */ -#define ANOMALY_05000280 /* SPI Master boot mode does not work well with - Atmel Dataflash devices */ -#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context - * is not restored */ -#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic - * control */ -#define ANOMALY_05000283 /* System MMR Write Is Stalled Indefinitely When - * Killed in a Particular Stage */ -#define ANOMALY_05000285 /* New Feature: EMAC TX DMA Word Alignment - * (Not Available On Older Silicon) */ -#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */ -#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously - * On Next System MMR Access */ -#define ANOMALY_05000316 /* EMAC RMII mode: collisions occur in Full Duplex - * mode */ -#define ANOMALY_05000321 /* EMAC RMII mode: TX frames in half duplex fail with - * status No Carrier */ -#endif /* CONFIG_BF_REV_0_2 */ -#endif /* _MACH_ANOMALY_H_ */ +/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +#define ANOMALY_05000074 (1) +/* DMA_RUN bit is not valid after a Peripheral Receive Channel DMA stops */ +#define ANOMALY_05000119 (1) +/* Rx.H cannot be used to access 16-bit System MMR registers */ +#define ANOMALY_05000122 (1) +/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ +#define ANOMALY_05000157 (__SILICON_REVISION__ < 2) +/* PPI_DELAY not functional in PPI modes with 0 frame syncs */ +#define ANOMALY_05000180 (1) +/* Instruction Cache Is Not Functional */ +#define ANOMALY_05000237 (__SILICON_REVISION__ < 2) +/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */ +#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) +/* Spurious Hardware Error from an access in the shadow of a conditional branch */ +#define ANOMALY_05000245 (1) +/* CLKIN Buffer Output Enable Reset Behavior Is Changed */ +#define ANOMALY_05000247 (1) +/* Incorrect Bit-Shift of Data Word in Multichannel (TDM) mode in certain conditions */ +#define ANOMALY_05000250 (__SILICON_REVISION__ < 3) +/* EMAC Tx DMA error after an early frame abort */ +#define ANOMALY_05000252 (__SILICON_REVISION__ < 3) +/* Maximum external clock speed for Timers */ +#define ANOMALY_05000253 (__SILICON_REVISION__ < 3) +/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT mode with external clock */ +#define ANOMALY_05000254 (__SILICON_REVISION__ > 2) +/* Entering Hibernate Mode with RTC Seconds event interrupt not functional */ +#define ANOMALY_05000255 (__SILICON_REVISION__ < 3) +/* EMAC MDIO input latched on wrong MDC edge */ +#define ANOMALY_05000256 (__SILICON_REVISION__ < 3) +/* Interrupt/Exception during short hardware loop may cause bad instruction fetches */ +#define ANOMALY_05000257 (__SILICON_REVISION__ < 3) +/* Instruction Cache is corrupted when bits 9 and 12 of the ICPLB Data registers differ */ +#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2) +/* ICPLB_STATUS MMR register may be corrupted */ +#define ANOMALY_05000260 (__SILICON_REVISION__ == 2) +/* DCPLB_FAULT_ADDR MMR register may be corrupted */ +#define ANOMALY_05000261 (__SILICON_REVISION__ < 3) +/* Stores to data cache may be lost */ +#define ANOMALY_05000262 (__SILICON_REVISION__ < 3) +/* Hardware loop corrupted when taking an ICPLB exception */ +#define ANOMALY_05000263 (__SILICON_REVISION__ == 2) +/* CSYNC/SSYNC/IDLE causes infinite stall in second to last instruction in hardware loop */ +#define ANOMALY_05000264 (__SILICON_REVISION__ < 3) +/* Sensitivity to noise with slow input edge rates on external SPORT TX and RX clocks */ +#define ANOMALY_05000265 (1) +/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */ +#define ANOMALY_05000268 (__SILICON_REVISION__ < 3) +/* High I/O activity causes output voltage of internal voltage regulator (VDDint) to decrease */ +#define ANOMALY_05000270 (__SILICON_REVISION__ < 3) +/* Certain data cache write through modes fail for VDDint <=0.9V */ +#define ANOMALY_05000272 (1) +/* Writes to Synchronous SDRAM memory may be lost */ +#define ANOMALY_05000273 (__SILICON_REVISION__ < 3) +/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */ +#define ANOMALY_05000277 (__SILICON_REVISION__ < 3) +/* Disabling Peripherals with DMA running may cause DMA system instability */ +#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) +/* SPI Master boot mode does not work well with Atmel Data flash devices */ +#define ANOMALY_05000280 (1) +/* False Hardware Error Exception when ISR context is not restored */ +#define ANOMALY_05000281 (__SILICON_REVISION__ < 3) +/* Memory DMA corruption with 32-bit data and traffic control */ +#define ANOMALY_05000282 (__SILICON_REVISION__ < 3) +/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ +#define ANOMALY_05000283 (__SILICON_REVISION__ < 3) +/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */ +#define ANOMALY_05000285 (__SILICON_REVISION__ < 3) +/* SPORTs may receive bad data if FIFOs fill up */ +#define ANOMALY_05000288 (__SILICON_REVISION__ < 3) +/* Memory to memory DMA source/destination descriptors must be in same memory space */ +#define ANOMALY_05000301 (1) +/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ +#define ANOMALY_05000304 (__SILICON_REVISION__ < 3) +/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ +#define ANOMALY_05000305 (__SILICON_REVISION__ < 3) +/* SCKELOW Bit Does Not Maintain State Through Hibernate */ +#define ANOMALY_05000307 (__SILICON_REVISION__ < 3) +/* Writing UART_THR while UART clock is disabled sends erroneous start bit */ +#define ANOMALY_05000309 (__SILICON_REVISION__ < 3) +/* False hardware errors caused by fetches at the boundary of reserved memory */ +#define ANOMALY_05000310 (1) +/* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */ +#define ANOMALY_05000312 (1) +/* PPI is level sensitive on first transfer */ +#define ANOMALY_05000313 (1) +/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ +#define ANOMALY_05000315 (__SILICON_REVISION__ < 3) +/* EMAC RMII mode: collisions occur in Full Duplex mode */ +#define ANOMALY_05000316 (__SILICON_REVISION__ < 3) +/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */ +#define ANOMALY_05000321 (__SILICON_REVISION__ < 3) +/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */ +#define ANOMALY_05000322 (1) + +/* Anomalies that don't exist on this proc */ +#define ANOMALY_05000125 (0) +#define ANOMALY_05000158 (0) +#define ANOMALY_05000183 (0) +#define ANOMALY_05000198 (0) +#define ANOMALY_05000230 (0) +#define ANOMALY_05000266 (0) +#define ANOMALY_05000311 (0) +#define ANOMALY_05000323 (0) + +#endif diff --git a/include/asm-blackfin/mach-bf537/bf537.h b/include/asm-blackfin/mach-bf537/bf537.h index b8924cd7730c..cfe2a221112e 100644 --- a/include/asm-blackfin/mach-bf537/bf537.h +++ b/include/asm-blackfin/mach-bf537/bf537.h @@ -62,12 +62,12 @@ /***************************/ -#define BLKFIN_DSUBBANKS 4 -#define BLKFIN_DWAYS 2 -#define BLKFIN_DLINES 64 -#define BLKFIN_ISUBBANKS 4 -#define BLKFIN_IWAYS 4 -#define BLKFIN_ILINES 32 +#define BFIN_DSUBBANKS 4 +#define BFIN_DWAYS 2 +#define BFIN_DLINES 64 +#define BFIN_ISUBBANKS 4 +#define BFIN_IWAYS 4 +#define BFIN_ILINES 32 #define WAY0_L 0x1 #define WAY1_L 0x2 @@ -121,97 +121,6 @@ #define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) -#define MAX_VC 650000000 -#define MIN_VC 50000000 - -/********************************PLL Settings **************************************/ -#ifdef CONFIG_BFIN_KERNEL_CLOCK -#if (CONFIG_VCO_MULT < 0) -#error "VCO Multiplier is less than 0. Please select a different value" -#endif - -#if (CONFIG_VCO_MULT == 0) -#error "VCO Multiplier should be greater than 0. Please select a different value" -#endif - -#if (CONFIG_VCO_MULT > 64) -#error "VCO Multiplier is more than 64. Please select a different value" -#endif - -#ifndef CONFIG_CLKIN_HALF -#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) -#else -#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2) -#endif - -#ifndef CONFIG_PLL_BYPASS -#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV) -#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV) -#else -#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ -#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ -#endif - -#if (CONFIG_SCLK_DIV < 1) -#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" -#endif - -#if (CONFIG_SCLK_DIV > 15) -#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" -#endif - -#if (CONFIG_CCLK_DIV != 1) -#if (CONFIG_CCLK_DIV != 2) -#if (CONFIG_CCLK_DIV != 4) -#if (CONFIG_CCLK_DIV != 8) -#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value" -#endif -#endif -#endif -#endif - -#if (CONFIG_VCO_HZ > MAX_VC) -#error "VCO selected is more than maximum value. Please change the VCO multipler" -#endif - -#if (CONFIG_SCLK_HZ > 133000000) -#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier" -#endif - -#if (CONFIG_SCLK_HZ < 27000000) -#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier" -#endif - -#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ) -#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) -#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ) -#error "Please select sclk less than cclk" -#endif -#endif -#endif - -#if (CONFIG_CCLK_DIV == 1) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 -#endif -#if (CONFIG_CCLK_DIV == 2) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 -#endif -#if (CONFIG_CCLK_DIV == 4) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 -#endif -#if (CONFIG_CCLK_DIV == 8) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 -#endif -#ifndef CONFIG_CCLK_ACT_DIV -#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly -#endif - -#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1) -#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK -#endif - -#endif /* CONFIG_BFIN_KERNEL_CLOCK */ - #ifdef CONFIG_BF537 #define CPU "BF537" #define CPUID 0x027c8000 @@ -229,59 +138,4 @@ #define CPUID 0x0 #endif -#if (CONFIG_MEM_SIZE % 4) -#error "SDRAM mem size must be multible of 4MB" -#endif - -#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) -#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) -#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) -#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) - -/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ - -#define ANOMALY_05000158_WORKAROUND 0x200 -#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ -#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \ - | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) -#else /*Write Through */ -#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \ - | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) -#endif - - -#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY ) -#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) -#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) -#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY ) - -#define SIZE_1K 0x00000400 /* 1K */ -#define SIZE_4K 0x00001000 /* 4K */ -#define SIZE_1M 0x00100000 /* 1M */ -#define SIZE_4M 0x00400000 /* 4M */ - -#define MAX_CPLBS (16 * 2) - -/* -* Number of required data CPLB switchtable entries -* MEMSIZE / 4 (we mostly install 4M page size CPLBs -* approx 16 for smaller 1MB page size CPLBs for allignment purposes -* 1 for L1 Data Memory -* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO -* 1 for ASYNC Memory -*/ - - -#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2) - -/* -* Number of required instruction CPLB switchtable entries -* MEMSIZE / 4 (we mostly install 4M page size CPLBs -* approx 12 for smaller 1MB page size CPLBs for allignment purposes -* 1 for L1 Instruction Memory -* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO -*/ - -#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2) - #endif /* __MACH_BF537_H__ */ diff --git a/include/asm-blackfin/mach-bf537/blackfin.h b/include/asm-blackfin/mach-bf537/blackfin.h index bbd97051ec9c..53fcfa3408d0 100644 --- a/include/asm-blackfin/mach-bf537/blackfin.h +++ b/include/asm-blackfin/mach-bf537/blackfin.h @@ -43,7 +43,7 @@ #include "defBF537.h" #endif -#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY)) +#if !defined(__ASSEMBLY__) #include "cdefBF534.h" /* UART 0*/ @@ -143,284 +143,6 @@ #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) #define STOPCK_OFF STOPCK -/* FIO USE PORT F*/ -#ifdef CONFIG_BF537_PORT_F -#define bfin_read_PORT_FER() bfin_read_PORTF_FER() -#define bfin_write_PORT_FER(val) bfin_write_PORTF_FER(val) -#define bfin_read_FIO_FLAG_D() bfin_read_PORTFIO() -#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTFIO(val) -#define bfin_read_FIO_FLAG_C() bfin_read_PORTFIO_CLEAR() -#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTFIO_CLEAR(val) -#define bfin_read_FIO_FLAG_S() bfin_read_PORTFIO_SET() -#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTFIO_SET(val) -#define bfin_read_FIO_FLAG_T() bfin_read_PORTFIO_TOGGLE() -#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTFIO_TOGGLE(val) -#define bfin_read_FIO_MASKA_D() bfin_read_PORTFIO_MASKA() -#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTFIO_MASKA(val) -#define bfin_read_FIO_MASKA_C() bfin_read_PORTFIO_MASKA_CLEAR() -#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTFIO_MASKA_CLEAR(val) -#define bfin_read_FIO_MASKA_S() bfin_read_PORTFIO_MASKA_SET() -#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTFIO_MASKA_SET(val) -#define bfin_read_FIO_MASKA_T() bfin_read_PORTFIO_MASKA_TOGGLE() -#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTFIO_MASKA_TOGGLE(val) -#define bfin_read_FIO_MASKB_D() bfin_read_PORTFIO_MASKB() -#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTFIO_MASKB(val) -#define bfin_read_FIO_MASKB_C() bfin_read_PORTFIO_MASKB_CLEAR() -#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTFIO_MASKB_CLEAR(val) -#define bfin_read_FIO_MASKB_S() bfin_read_PORTFIO_MASKB_SET() -#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTFIO_MASKB_SET(val) -#define bfin_read_FIO_MASKB_T() bfin_read_PORTFIO_MASKB_TOGGLE() -#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTFIO_MASKB_TOGGLE(val) -#define bfin_read_FIO_DIR() bfin_read_PORTFIO_DIR() -#define bfin_write_FIO_DIR(val) bfin_write_PORTFIO_DIR(val) -#define bfin_read_FIO_POLAR() bfin_read_PORTFIO_POLAR() -#define bfin_write_FIO_POLAR(val) bfin_write_PORTFIO_POLAR(val) -#define bfin_read_FIO_EDGE() bfin_read_PORTFIO_EDGE() -#define bfin_write_FIO_EDGE(val) bfin_write_PORTFIO_EDGE(val) -#define bfin_read_FIO_BOTH() bfin_read_PORTFIO_BOTH() -#define bfin_write_FIO_BOTH(val) bfin_write_PORTFIO_BOTH(val) -#define bfin_read_FIO_INEN() bfin_read_PORTFIO_INEN() -#define bfin_write_FIO_INEN(val) bfin_write_PORTFIO_INEN(val) - -#define bfin_read_FIO_FLAG_D() bfin_read_PORTFIO() -#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTFIO(val) -#define FIO_FLAG_D PORTFIO -#define bfin_read_FIO_FLAG_C() bfin_read_PORTFIO_CLEAR() -#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTFIO_CLEAR(val) -#define FIO_FLAG_C PORTFIO_CLEAR -#define bfin_read_FIO_FLAG_S() bfin_read_PORTFIO_SET() -#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTFIO_SET(val) -#define FIO_FLAG_S PORTFIO_SET -#define bfin_read_FIO_FLAG_T() bfin_read_PORTFIO_TOGGLE() -#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTFIO_TOGGLE(val) -#define FIO_FLAG_T PORTFIO_TOGGLE -#define bfin_read_FIO_MASKA_D() bfin_read_PORTFIO_MASKA() -#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTFIO_MASKA(val) -#define FIO_MASKA_D PORTFIO_MASKA -#define bfin_read_FIO_MASKA_C() bfin_read_PORTFIO_MASKA_CLEAR() -#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTFIO_MASKA_CLEAR(val) -#define FIO_MASKA_C PORTFIO_MASKA_CLEAR -#define bfin_read_FIO_MASKA_S() bfin_read_PORTFIO_MASKA_SET() -#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTFIO_MASKA_SET(val) -#define FIO_MASKA_S PORTFIO_MASKA_SET -#define bfin_read_FIO_MASKA_T() bfin_read_PORTFIO_MASKA_TOGGLE() -#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTFIO_MASKA_TOGGLE(val) -#define FIO_MASKA_T PORTFIO_MASKA_TOGGLE -#define bfin_read_FIO_MASKB_D() bfin_read_PORTFIO_MASKB() -#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTFIO_MASKB(val) -#define FIO_MASKB_D PORTFIO_MASKB -#define bfin_read_FIO_MASKB_C() bfin_read_PORTFIO_MASKB_CLEAR() -#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTFIO_MASKB_CLEAR(val) -#define FIO_MASKB_C PORTFIO_MASKB_CLEAR -#define bfin_read_FIO_MASKB_S() bfin_read_PORTFIO_MASKB_SET() -#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTFIO_MASKB_SET(val) -#define FIO_MASKB_S PORTFIO_MASKB_SET -#define bfin_read_FIO_MASKB_T() bfin_read_PORTFIO_MASKB_TOGGLE() -#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTFIO_MASKB_TOGGLE(val) -#define FIO_MASKB_T PORTFIO_MASKB_TOGGLE -#define bfin_read_FIO_DIR() bfin_read_PORTFIO_DIR() -#define bfin_write_FIO_DIR(val) bfin_write_PORTFIO_DIR(val) -#define FIO_DIR PORTFIO_DIR -#define bfin_read_FIO_POLAR() bfin_read_PORTFIO_POLAR() -#define bfin_write_FIO_POLAR(val) bfin_write_PORTFIO_POLAR(val) -#define FIO_POLAR PORTFIO_POLAR -#define bfin_read_FIO_EDGE() bfin_read_PORTFIO_EDGE() -#define bfin_write_FIO_EDGE(val) bfin_write_PORTFIO_EDGE(val) -#define FIO_EDGE PORTFIO_EDGE -#define bfin_read_FIO_BOTH() bfin_read_PORTFIO_BOTH() -#define bfin_write_FIO_BOTH(val) bfin_write_PORTFIO_BOTH(val) -#define FIO_BOTH PORTFIO_BOTH -#define bfin_read_FIO_INEN() bfin_read_PORTFIO_INEN() -#define bfin_write_FIO_INEN(val) bfin_write_PORTFIO_INEN(val) -#define FIO_INEN PORTFIO_INEN -#endif - -/* FIO USE PORT G*/ -#ifdef CONFIG_BF537_PORT_G -#define bfin_read_PORT_FER() bfin_read_PORTG_FER() -#define bfin_write_PORT_FER(val) bfin_write_PORTG_FER(val) -#define bfin_read_FIO_FLAG_D() bfin_read_PORTGIO() -#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTGIO(val) -#define bfin_read_FIO_FLAG_C() bfin_read_PORTGIO_CLEAR() -#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTGIO_CLEAR(val) -#define bfin_read_FIO_FLAG_S() bfin_read_PORTGIO_SET() -#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTGIO_SET(val) -#define bfin_read_FIO_FLAG_T() bfin_read_PORTGIO_TOGGLE() -#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTGIO_TOGGLE(val) -#define bfin_read_FIO_MASKA_D() bfin_read_PORTGIO_MASKA() -#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTGIO_MASKA(val) -#define bfin_read_FIO_MASKA_C() bfin_read_PORTGIO_MASKA_CLEAR() -#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTGIO_MASKA_CLEAR(val) -#define bfin_read_FIO_MASKA_S() bfin_read_PORTGIO_MASKA_SET() -#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTGIO_MASKA_SET(val) -#define bfin_read_FIO_MASKA_T() bfin_read_PORTGIO_MASKA_TOGGLE() -#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTGIO_MASKA_TOGGLE(val) -#define bfin_read_FIO_MASKB_D() bfin_read_PORTGIO_MASKB() -#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTGIO_MASKB(val) -#define bfin_read_FIO_MASKB_C() bfin_read_PORTGIO_MASKB_CLEAR() -#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTGIO_MASKB_CLEAR(val) -#define bfin_read_FIO_MASKB_S() bfin_read_PORTGIO_MASKB_SET() -#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTGIO_MASKB_SET(val) -#define bfin_read_FIO_MASKB_T() bfin_read_PORTGIO_MASKB_TOGGLE() -#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTGIO_MASKB_TOGGLE(val) -#define bfin_read_FIO_DIR() bfin_read_PORTGIO_DIR() -#define bfin_write_FIO_DIR(val) bfin_write_PORTGIO_DIR(val) -#define bfin_read_FIO_POLAR() bfin_read_PORTGIO_POLAR() -#define bfin_write_FIO_POLAR(val) bfin_write_PORTGIO_POLAR(val) -#define bfin_read_FIO_EDGE() bfin_read_PORTGIO_EDGE() -#define bfin_write_FIO_EDGE(val) bfin_write_PORTGIO_EDGE(val) -#define bfin_read_FIO_BOTH() bfin_read_PORTGIO_BOTH() -#define bfin_write_FIO_BOTH(val) bfin_write_PORTGIO_BOTH(val) -#define bfin_read_FIO_INEN() bfin_read_PORTGIO_INEN() -#define bfin_write_FIO_INEN(val) bfin_write_PORTGIO_INEN(val) - -#define bfin_read_FIO_FLAG_D() bfin_read_PORTGIO() -#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTGIO(val) -#define FIO_FLAG_D PORTGIO -#define bfin_read_FIO_FLAG_C() bfin_read_PORTGIO_CLEAR() -#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTGIO_CLEAR(val) -#define FIO_FLAG_C PORTGIO_CLEAR -#define bfin_read_FIO_FLAG_S() bfin_read_PORTGIO_SET() -#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTGIO_SET(val) -#define FIO_FLAG_S PORTGIO_SET -#define bfin_read_FIO_FLAG_T() bfin_read_PORTGIO_TOGGLE() -#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTGIO_TOGGLE(val) -#define FIO_FLAG_T PORTGIO_TOGGLE -#define bfin_read_FIO_MASKA_D() bfin_read_PORTGIO_MASKA() -#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTGIO_MASKA(val) -#define FIO_MASKA_D PORTGIO_MASKA -#define bfin_read_FIO_MASKA_C() bfin_read_PORTGIO_MASKA_CLEAR() -#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTGIO_MASKA_CLEAR(val) -#define FIO_MASKA_C PORTGIO_MASKA_CLEAR -#define bfin_read_FIO_MASKA_S() bfin_read_PORTGIO_MASKA_SET() -#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTGIO_MASKA_SET(val) -#define FIO_MASKA_S PORTGIO_MASKA_SET -#define bfin_read_FIO_MASKA_T() bfin_read_PORTGIO_MASKA_TOGGLE() -#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTGIO_MASKA_TOGGLE(val) -#define FIO_MASKA_T PORTGIO_MASKA_TOGGLE -#define bfin_read_FIO_MASKB_D() bfin_read_PORTGIO_MASKB() -#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTGIO_MASKB(val) -#define FIO_MASKB_D PORTGIO_MASKB -#define bfin_read_FIO_MASKB_C() bfin_read_PORTGIO_MASKB_CLEAR() -#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTGIO_MASKB_CLEAR(val) -#define FIO_MASKB_C PORTGIO_MASKB_CLEAR -#define bfin_read_FIO_MASKB_S() bfin_read_PORTGIO_MASKB_SET() -#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTGIO_MASKB_SET(val) -#define FIO_MASKB_S PORTGIO_MASKB_SET -#define bfin_read_FIO_MASKB_T() bfin_read_PORTGIO_MASKB_TOGGLE() -#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTGIO_MASKB_TOGGLE(val) -#define FIO_MASKB_T PORTGIO_MASKB_TOGGLE -#define bfin_read_FIO_DIR() bfin_read_PORTGIO_DIR() -#define bfin_write_FIO_DIR(val) bfin_write_PORTGIO_DIR(val) -#define FIO_DIR PORTGIO_DIR -#define bfin_read_FIO_POLAR() bfin_read_PORTGIO_POLAR() -#define bfin_write_FIO_POLAR(val) bfin_write_PORTGIO_POLAR(val) -#define FIO_POLAR PORTGIO_POLAR -#define bfin_read_FIO_EDGE() bfin_read_PORTGIO_EDGE() -#define bfin_write_FIO_EDGE(val) bfin_write_PORTGIO_EDGE(val) -#define FIO_EDGE PORTGIO_EDGE -#define bfin_read_FIO_BOTH() bfin_read_PORTGIO_BOTH() -#define bfin_write_FIO_BOTH(val) bfin_write_PORTGIO_BOTH(val) -#define FIO_BOTH PORTGIO_BOTH -#define bfin_read_FIO_INEN() bfin_read_PORTGIO_INEN() -#define bfin_write_FIO_INEN(val) bfin_write_PORTGIO_INEN(val) -#define FIO_INEN PORTGIO_INEN - -#endif - -/* FIO USE PORT H*/ -#ifdef CONFIG_BF537_PORT_H -#define bfin_read_PORT_FER() bfin_read_PORTH_FER() -#define bfin_write_PORT_FER(val) bfin_write_PORTH_FER(val) -#define bfin_read_FIO_FLAG_D() bfin_read_PORTHIO() -#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTHIO(val) -#define bfin_read_FIO_FLAG_C() bfin_read_PORTHIO_CLEAR() -#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTHIO_CLEAR(val) -#define bfin_read_FIO_FLAG_S() bfin_read_PORTHIO_SET() -#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTHIO_SET(val) -#define bfin_read_FIO_FLAG_T() bfin_read_PORTHIO_TOGGLE() -#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTHIO_TOGGLE(val) -#define bfin_read_FIO_MASKA_D() bfin_read_PORTHIO_MASKA() -#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTHIO_MASKA(val) -#define bfin_read_FIO_MASKA_C() bfin_read_PORTHIO_MASKA_CLEAR() -#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTHIO_MASKA_CLEAR(val) -#define bfin_read_FIO_MASKA_S() bfin_read_PORTHIO_MASKA_SET() -#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTHIO_MASKA_SET(val) -#define bfin_read_FIO_MASKA_T() bfin_read_PORTHIO_MASKA_TOGGLE() -#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTHIO_MASKA_TOGGLE(val) -#define bfin_read_FIO_MASKB_D() bfin_read_PORTHIO_MASKB() -#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTHIO_MASKB(val) -#define bfin_read_FIO_MASKB_C() bfin_read_PORTHIO_MASKB_CLEAR() -#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTHIO_MASKB_CLEAR(val) -#define bfin_read_FIO_MASKB_S() bfin_read_PORTHIO_MASKB_SET() -#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTHIO_MASKB_SET(val) -#define bfin_read_FIO_MASKB_T() bfin_read_PORTHIO_MASKB_TOGGLE() -#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTHIO_MASKB_TOGGLE(val) -#define bfin_read_FIO_DIR() bfin_read_PORTHIO_DIR() -#define bfin_write_FIO_DIR(val) bfin_write_PORTHIO_DIR(val) -#define bfin_read_FIO_POLAR() bfin_read_PORTHIO_POLAR() -#define bfin_write_FIO_POLAR(val) bfin_write_PORTHIO_POLAR(val) -#define bfin_read_FIO_EDGE() bfin_read_PORTHIO_EDGE() -#define bfin_write_FIO_EDGE(val) bfin_write_PORTHIO_EDGE(val) -#define bfin_read_FIO_BOTH() bfin_read_PORTHIO_BOTH() -#define bfin_write_FIO_BOTH(val) bfin_write_PORTHIO_BOTH(val) -#define bfin_read_FIO_INEN() bfin_read_PORTHIO_INEN() -#define bfin_write_FIO_INEN(val) bfin_write_PORTHIO_INEN(val) - -#define bfin_read_FIO_FLAG_D() bfin_read_PORTHIO() -#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTHIO(val) -#define FIO_FLAG_D PORTHIO -#define bfin_read_FIO_FLAG_C() bfin_read_PORTHIO_CLEAR() -#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTHIO_CLEAR(val) -#define FIO_FLAG_C PORTHIO_CLEAR -#define bfin_read_FIO_FLAG_S() bfin_read_PORTHIO_SET() -#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTHIO_SET(val) -#define FIO_FLAG_S PORTHIO_SET -#define bfin_read_FIO_FLAG_T() bfin_read_PORTHIO_TOGGLE() -#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTHIO_TOGGLE(val) -#define FIO_FLAG_T PORTHIO_TOGGLE -#define bfin_read_FIO_MASKA_D() bfin_read_PORTHIO_MASKA() -#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTHIO_MASKA(val) -#define FIO_MASKA_D PORTHIO_MASKA -#define bfin_read_FIO_MASKA_C() bfin_read_PORTHIO_MASKA_CLEAR() -#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTHIO_MASKA_CLEAR(val) -#define FIO_MASKA_C PORTHIO_MASKA_CLEAR -#define bfin_read_FIO_MASKA_S() bfin_read_PORTHIO_MASKA_SET() -#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTHIO_MASKA_SET(val) -#define FIO_MASKA_S PORTHIO_MASKA_SET -#define bfin_read_FIO_MASKA_T() bfin_read_PORTHIO_MASKA_TOGGLE() -#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTHIO_MASKA_TOGGLE(val) -#define FIO_MASKA_T PORTHIO_MASKA_TOGGLE -#define bfin_read_FIO_MASKB_D() bfin_read_PORTHIO_MASKB() -#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTHIO_MASKB(val) -#define FIO_MASKB_D PORTHIO_MASKB -#define bfin_read_FIO_MASKB_C() bfin_read_PORTHIO_MASKB_CLEAR() -#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTHIO_MASKB_CLEAR(val) -#define FIO_MASKB_C PORTHIO_MASKB_CLEAR -#define bfin_read_FIO_MASKB_S() bfin_read_PORTHIO_MASKB_SET() -#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTHIO_MASKB_SET(val) -#define FIO_MASKB_S PORTHIO_MASKB_SET -#define bfin_read_FIO_MASKB_T() bfin_read_PORTHIO_MASKB_TOGGLE() -#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTHIO_MASKB_TOGGLE(val) -#define FIO_MASKB_T PORTHIO_MASKB_TOGGLE -#define bfin_read_FIO_DIR() bfin_read_PORTHIO_DIR() -#define bfin_write_FIO_DIR(val) bfin_write_PORTHIO_DIR(val) -#define FIO_DIR PORTHIO_DIR -#define bfin_read_FIO_POLAR() bfin_read_PORTHIO_POLAR() -#define bfin_write_FIO_POLAR(val) bfin_write_PORTHIO_POLAR(val) -#define FIO_POLAR PORTHIO_POLAR -#define bfin_read_FIO_EDGE() bfin_read_PORTHIO_EDGE() -#define bfin_write_FIO_EDGE(val) bfin_write_PORTHIO_EDGE(val) -#define FIO_EDGE PORTHIO_EDGE -#define bfin_read_FIO_BOTH() bfin_read_PORTHIO_BOTH() -#define bfin_write_FIO_BOTH(val) bfin_write_PORTHIO_BOTH(val) -#define FIO_BOTH PORTHIO_BOTH -#define bfin_read_FIO_INEN() bfin_read_PORTHIO_INEN() -#define bfin_write_FIO_INEN(val) bfin_write_PORTHIO_INEN(val) -#define FIO_INEN PORTHIO_INEN - -#endif - /* PLL_DIV Masks */ #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ diff --git a/include/asm-blackfin/mach-bf537/cdefBF534.h b/include/asm-blackfin/mach-bf537/cdefBF534.h index 84e58fa73dce..78227bc855df 100644 --- a/include/asm-blackfin/mach-bf537/cdefBF534.h +++ b/include/asm-blackfin/mach-bf537/cdefBF534.h @@ -32,6 +32,8 @@ #ifndef _CDEF_BF534_H #define _CDEF_BF534_H +#include <asm/blackfin.h> + /* Include all Core registers and bit definitions */ #include "defBF534.h" @@ -57,7 +59,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) bfin_write32(SIC_IWR, IWR_ENABLE(0)); bfin_write16(VR_CTL, val); - __builtin_bfin_ssync(); + SSYNC(); local_irq_save(flags); asm("IDLE;"); diff --git a/include/asm-blackfin/mach-bf537/defBF534.h b/include/asm-blackfin/mach-bf537/defBF534.h index 1859f2fee5a7..d0d80d3152ba 100644 --- a/include/asm-blackfin/mach-bf537/defBF534.h +++ b/include/asm-blackfin/mach-bf537/defBF534.h @@ -86,6 +86,7 @@ #define UART0_GCTL 0xFFC00424 /* Global Control Register */ /* SPI Controller (0xFFC00500 - 0xFFC005FF) */ +#define SPI0_REGBASE 0xFFC00500 #define SPI_CTL 0xFFC00500 /* SPI Control Register */ #define SPI_FLG 0xFFC00504 /* SPI Flag register */ #define SPI_STAT 0xFFC00508 /* SPI Status register */ @@ -456,6 +457,7 @@ #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ +#define TWI0_REGBASE 0xFFC01400 #define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ #define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ #define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ @@ -1165,7 +1167,7 @@ #define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ #define PSSE 0x0010 /* Slave-Select Input Enable */ #define EMISO 0x0020 /* Enable MISO As Output */ -#define SPI_SIZE 0x0100 /* Size of Words (16/8* Bits) */ +#define SIZE 0x0100 /* Size of Words (16/8* Bits) */ #define LSBF 0x0200 /* LSB First */ #define CPHA 0x0400 /* Clock Phase */ #define CPOL 0x0800 /* Clock Polarity */ diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h index 8af2a832ef6b..36c44bc1a917 100644 --- a/include/asm-blackfin/mach-bf537/irq.h +++ b/include/asm-blackfin/mach-bf537/irq.h @@ -160,6 +160,8 @@ Core Emulation ** #define IRQ_PH14 96 #define IRQ_PH15 97 +#define GPIO_IRQ_BASE IRQ_PF0 + #ifdef CONFIG_IRQCHIP_DEMUX_GPIO #define NR_IRQS (IRQ_PH15+1) #else diff --git a/include/asm-blackfin/mach-bf537/mem_map.h b/include/asm-blackfin/mach-bf537/mem_map.h index 2a808c1202bf..18759e38eaae 100644 --- a/include/asm-blackfin/mach-bf537/mem_map.h +++ b/include/asm-blackfin/mach-bf537/mem_map.h @@ -52,10 +52,10 @@ /* Memory Map for ADSP-BF537 processors */ -#ifdef CONFIG_BLKFIN_CACHE -#define BLKFIN_ICACHESIZE (16*1024) +#ifdef CONFIG_BFIN_ICACHE +#define BFIN_ICACHESIZE (16*1024) #else -#define BLKFIN_ICACHESIZE (0*1024) +#define BFIN_ICACHESIZE (0*1024) #endif @@ -66,29 +66,29 @@ #define L1_CODE_LENGTH 0xC000 -#ifdef CONFIG_BLKFIN_DCACHE +#ifdef CONFIG_BFIN_DCACHE -#ifdef CONFIG_BLKFIN_DCACHE_BANKA +#ifdef CONFIG_BFIN_DCACHE_BANKA #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH 0x8000 -#define BLKFIN_DCACHESIZE (16*1024) -#define BLKFIN_DSUPBANKS 1 +#define BFIN_DCACHESIZE (16*1024) +#define BFIN_DSUPBANKS 1 #else #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH (0x8000 - 0x4000) -#define BLKFIN_DCACHESIZE (32*1024) -#define BLKFIN_DSUPBANKS 2 +#define BFIN_DCACHESIZE (32*1024) +#define BFIN_DSUPBANKS 2 #endif #else #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH 0x8000 #define L1_DATA_B_LENGTH 0x8000 -#define BLKFIN_DCACHESIZE (0*1024) -#define BLKFIN_DSUPBANKS 0 -#endif /*CONFIG_BLKFIN_DCACHE*/ +#define BFIN_DCACHESIZE (0*1024) +#define BFIN_DSUPBANKS 0 +#endif /*CONFIG_BFIN_DCACHE*/ #endif /*CONFIG_BF537*/ @@ -102,30 +102,30 @@ #define L1_CODE_LENGTH 0xC000 -#ifdef CONFIG_BLKFIN_DCACHE +#ifdef CONFIG_BFIN_DCACHE -#ifdef CONFIG_BLKFIN_DCACHE_BANKA +#ifdef CONFIG_BFIN_DCACHE_BANKA #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x4000 - 0x4000) #define L1_DATA_B_LENGTH 0x4000 -#define BLKFIN_DCACHESIZE (16*1024) -#define BLKFIN_DSUPBANKS 1 +#define BFIN_DCACHESIZE (16*1024) +#define BFIN_DSUPBANKS 1 #else #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x4000 - 0x4000) #define L1_DATA_B_LENGTH (0x4000 - 0x4000) -#define BLKFIN_DCACHESIZE (32*1024) -#define BLKFIN_DSUPBANKS 2 +#define BFIN_DCACHESIZE (32*1024) +#define BFIN_DSUPBANKS 2 #endif #else #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH 0x4000 #define L1_DATA_B_LENGTH 0x4000 -#define BLKFIN_DCACHESIZE (0*1024) -#define BLKFIN_DSUPBANKS 0 -#endif /*CONFIG_BLKFIN_DCACHE*/ +#define BFIN_DCACHESIZE (0*1024) +#define BFIN_DSUPBANKS 0 +#endif /*CONFIG_BFIN_DCACHE*/ #endif @@ -138,30 +138,30 @@ #define L1_CODE_LENGTH 0xC000 -#ifdef CONFIG_BLKFIN_DCACHE +#ifdef CONFIG_BFIN_DCACHE -#ifdef CONFIG_BLKFIN_DCACHE_BANKA +#ifdef CONFIG_BFIN_DCACHE_BANKA #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH 0x8000 -#define BLKFIN_DCACHESIZE (16*1024) -#define BLKFIN_DSUPBANKS 1 +#define BFIN_DCACHESIZE (16*1024) +#define BFIN_DSUPBANKS 1 #else #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH (0x8000 - 0x4000) -#define BLKFIN_DCACHESIZE (32*1024) -#define BLKFIN_DSUPBANKS 2 +#define BFIN_DCACHESIZE (32*1024) +#define BFIN_DSUPBANKS 2 #endif #else #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH 0x8000 #define L1_DATA_B_LENGTH 0x8000 -#define BLKFIN_DCACHESIZE (0*1024) -#define BLKFIN_DSUPBANKS 0 -#endif /*CONFIG_BLKFIN_DCACHE*/ +#define BFIN_DCACHESIZE (0*1024) +#define BFIN_DSUPBANKS 0 +#endif /*CONFIG_BFIN_DCACHE*/ #endif diff --git a/include/asm-blackfin/mach-bf537/portmux.h b/include/asm-blackfin/mach-bf537/portmux.h index ae6c53b28452..5a3f7d3bf73d 100644 --- a/include/asm-blackfin/mach-bf537/portmux.h +++ b/include/asm-blackfin/mach-bf537/portmux.h @@ -99,7 +99,7 @@ #define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0)) #define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0)) #define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0)) -#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1)) +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(0)) #define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1)) #define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1)) #define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1)) |