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-rw-r--r--include/asm-x86/acpi.h27
-rw-r--r--include/asm-x86/apic_32.h1
-rw-r--r--include/asm-x86/hpet.h1
3 files changed, 29 insertions, 0 deletions
diff --git a/include/asm-x86/acpi.h b/include/asm-x86/acpi.h
index 0693689d4146..f8a89793ac8c 100644
--- a/include/asm-x86/acpi.h
+++ b/include/asm-x86/acpi.h
@@ -1,5 +1,32 @@
+#ifndef _ASM_X86_ACPI_H
+#define _ASM_X86_ACPI_H
+
#ifdef CONFIG_X86_32
# include "acpi_32.h"
#else
# include "acpi_64.h"
#endif
+
+#include <asm/processor.h>
+
+/*
+ * Check if the CPU can handle C2 and deeper
+ */
+static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate)
+{
+ /*
+ * Early models (<=5) of AMD Opterons are not supposed to go into
+ * C2 state.
+ *
+ * Steppings 0x0A and later are good
+ */
+ if (boot_cpu_data.x86 == 0x0F &&
+ boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
+ boot_cpu_data.x86_model <= 0x05 &&
+ boot_cpu_data.x86_mask < 0x0A)
+ return 1;
+ else
+ return max_cstate;
+}
+
+#endif
diff --git a/include/asm-x86/apic_32.h b/include/asm-x86/apic_32.h
index 4091b33dcb10..be158b27d54b 100644
--- a/include/asm-x86/apic_32.h
+++ b/include/asm-x86/apic_32.h
@@ -120,6 +120,7 @@ extern int local_apic_timer_disabled;
#else /* !CONFIG_X86_LOCAL_APIC */
static inline void lapic_shutdown(void) { }
+#define local_apic_timer_c2_ok 1
#endif /* !CONFIG_X86_LOCAL_APIC */
diff --git a/include/asm-x86/hpet.h b/include/asm-x86/hpet.h
index b1f3c1ea55d9..ad8d6e758785 100644
--- a/include/asm-x86/hpet.h
+++ b/include/asm-x86/hpet.h
@@ -61,6 +61,7 @@ extern unsigned long force_hpet_address;
extern int hpet_force_user;
extern int is_hpet_enabled(void);
extern int hpet_enable(void);
+extern void hpet_disable(void);
extern unsigned long hpet_readl(unsigned long a);
extern void force_hpet_resume(void);