diff options
Diffstat (limited to 'include/dt-bindings')
38 files changed, 2917 insertions, 18 deletions
diff --git a/include/dt-bindings/bus/ti-sysc.h b/include/dt-bindings/bus/ti-sysc.h new file mode 100644 index 000000000000..2c005376ac0e --- /dev/null +++ b/include/dt-bindings/bus/ti-sysc.h @@ -0,0 +1,22 @@ +/* TI sysc interconnect target module defines */ + +/* Generic sysc found on omap2 and later, also known as type1 */ +#define SYSC_OMAP2_CLOCKACTIVITY (3 << 8) +#define SYSC_OMAP2_EMUFREE (1 << 5) +#define SYSC_OMAP2_ENAWAKEUP (1 << 2) +#define SYSC_OMAP2_SOFTRESET (1 << 1) +#define SYSC_OMAP2_AUTOIDLE (1 << 0) + +/* Generic sysc found on omap4 and later, also known as type2 */ +#define SYSC_OMAP4_DMADISABLE (1 << 16) +#define SYSC_OMAP4_FREEEMU (1 << 1) /* Also known as EMUFREE */ +#define SYSC_OMAP4_SOFTRESET (1 << 0) + +/* SmartReflex sysc found on 36xx and later */ +#define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26) + +/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */ +#define SYSC_IDLE_FORCE 0 +#define SYSC_IDLE_NO 1 +#define SYSC_IDLE_SMART 2 +#define SYSC_IDLE_SMART_WKUP 3 diff --git a/include/dt-bindings/clock/am3.h b/include/dt-bindings/clock/am3.h new file mode 100644 index 000000000000..b396f00e481d --- /dev/null +++ b/include/dt-bindings/clock/am3.h @@ -0,0 +1,108 @@ +/* + * Copyright 2017 Texas Instruments, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __DT_BINDINGS_CLK_AM3_H +#define __DT_BINDINGS_CLK_AM3_H + +#define AM3_CLKCTRL_OFFSET 0x0 +#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET) + +/* l4_per clocks */ +#define AM3_L4_PER_CLKCTRL_OFFSET 0x14 +#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET) +#define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14) +#define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18) +#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c) +#define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24) +#define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28) +#define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c) +#define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30) +#define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34) +#define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38) +#define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c) +#define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40) +#define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44) +#define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48) +#define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c) +#define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50) +#define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60) +#define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68) +#define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c) +#define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70) +#define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74) +#define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78) +#define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c) +#define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80) +#define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84) +#define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88) +#define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90) +#define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94) +#define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0) +#define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac) +#define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0) +#define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4) +#define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc) +#define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0) +#define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4) +#define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc) +#define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4) +#define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8) +#define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc) +#define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0) +#define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8) +#define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec) +#define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0) +#define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4) +#define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8) +#define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc) +#define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100) +#define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c) +#define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110) +#define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120) +#define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130) +#define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c) + +/* l4_wkup clocks */ +#define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4 +#define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET) +#define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4) +#define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8) +#define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc) +#define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14) +#define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0) +#define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4) +#define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8) +#define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc) +#define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0) +#define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4) +#define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8) +#define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4) + +/* mpu clocks */ +#define AM3_MPU_CLKCTRL_OFFSET 0x4 +#define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET) +#define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4) + +/* l4_rtc clocks */ +#define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) + +/* gfx_l3 clocks */ +#define AM3_GFX_L3_CLKCTRL_OFFSET 0x4 +#define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET) +#define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4) + +/* l4_cefuse clocks */ +#define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20 +#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET) +#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20) + +#endif diff --git a/include/dt-bindings/clock/am4.h b/include/dt-bindings/clock/am4.h new file mode 100644 index 000000000000..d21df00b3270 --- /dev/null +++ b/include/dt-bindings/clock/am4.h @@ -0,0 +1,113 @@ +/* + * Copyright 2017 Texas Instruments, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __DT_BINDINGS_CLK_AM4_H +#define __DT_BINDINGS_CLK_AM4_H + +#define AM4_CLKCTRL_OFFSET 0x20 +#define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET) + +/* l4_wkup clocks */ +#define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120) +#define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220) +#define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228) +#define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230) +#define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328) +#define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338) +#define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340) +#define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348) +#define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350) +#define AM4_SMARTREFLEX1_CLKCTRL AM4_CLKCTRL_INDEX(0x358) +#define AM4_CONTROL_CLKCTRL AM4_CLKCTRL_INDEX(0x360) +#define AM4_GPIO1_CLKCTRL AM4_CLKCTRL_INDEX(0x368) + +/* mpu clocks */ +#define AM4_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20) + +/* gfx_l3 clocks */ +#define AM4_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20) + +/* l4_rtc clocks */ +#define AM4_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20) + +/* l4_per clocks */ +#define AM4_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20) +#define AM4_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28) +#define AM4_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30) +#define AM4_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40) +#define AM4_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50) +#define AM4_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58) +#define AM4_VPFE0_CLKCTRL AM4_CLKCTRL_INDEX(0x68) +#define AM4_VPFE1_CLKCTRL AM4_CLKCTRL_INDEX(0x70) +#define AM4_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78) +#define AM4_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80) +#define AM4_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88) +#define AM4_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90) +#define AM4_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0) +#define AM4_GPMC_CLKCTRL AM4_CLKCTRL_INDEX(0x220) +#define AM4_MCASP0_CLKCTRL AM4_CLKCTRL_INDEX(0x238) +#define AM4_MCASP1_CLKCTRL AM4_CLKCTRL_INDEX(0x240) +#define AM4_MMC3_CLKCTRL AM4_CLKCTRL_INDEX(0x248) +#define AM4_QSPI_CLKCTRL AM4_CLKCTRL_INDEX(0x258) +#define AM4_USB_OTG_SS0_CLKCTRL AM4_CLKCTRL_INDEX(0x260) +#define AM4_USB_OTG_SS1_CLKCTRL AM4_CLKCTRL_INDEX(0x268) +#define AM4_PRUSS_CLKCTRL AM4_CLKCTRL_INDEX(0x320) +#define AM4_L4_LS_CLKCTRL AM4_CLKCTRL_INDEX(0x420) +#define AM4_D_CAN0_CLKCTRL AM4_CLKCTRL_INDEX(0x428) +#define AM4_D_CAN1_CLKCTRL AM4_CLKCTRL_INDEX(0x430) +#define AM4_EPWMSS0_CLKCTRL AM4_CLKCTRL_INDEX(0x438) +#define AM4_EPWMSS1_CLKCTRL AM4_CLKCTRL_INDEX(0x440) +#define AM4_EPWMSS2_CLKCTRL AM4_CLKCTRL_INDEX(0x448) +#define AM4_EPWMSS3_CLKCTRL AM4_CLKCTRL_INDEX(0x450) +#define AM4_EPWMSS4_CLKCTRL AM4_CLKCTRL_INDEX(0x458) +#define AM4_EPWMSS5_CLKCTRL AM4_CLKCTRL_INDEX(0x460) +#define AM4_ELM_CLKCTRL AM4_CLKCTRL_INDEX(0x468) +#define AM4_GPIO2_CLKCTRL AM4_CLKCTRL_INDEX(0x478) +#define AM4_GPIO3_CLKCTRL AM4_CLKCTRL_INDEX(0x480) +#define AM4_GPIO4_CLKCTRL AM4_CLKCTRL_INDEX(0x488) +#define AM4_GPIO5_CLKCTRL AM4_CLKCTRL_INDEX(0x490) +#define AM4_GPIO6_CLKCTRL AM4_CLKCTRL_INDEX(0x498) +#define AM4_HDQ1W_CLKCTRL AM4_CLKCTRL_INDEX(0x4a0) +#define AM4_I2C2_CLKCTRL AM4_CLKCTRL_INDEX(0x4a8) +#define AM4_I2C3_CLKCTRL AM4_CLKCTRL_INDEX(0x4b0) +#define AM4_MAILBOX_CLKCTRL AM4_CLKCTRL_INDEX(0x4b8) +#define AM4_MMC1_CLKCTRL AM4_CLKCTRL_INDEX(0x4c0) +#define AM4_MMC2_CLKCTRL AM4_CLKCTRL_INDEX(0x4c8) +#define AM4_RNG_CLKCTRL AM4_CLKCTRL_INDEX(0x4e0) +#define AM4_SPI0_CLKCTRL AM4_CLKCTRL_INDEX(0x500) +#define AM4_SPI1_CLKCTRL AM4_CLKCTRL_INDEX(0x508) +#define AM4_SPI2_CLKCTRL AM4_CLKCTRL_INDEX(0x510) +#define AM4_SPI3_CLKCTRL AM4_CLKCTRL_INDEX(0x518) +#define AM4_SPI4_CLKCTRL AM4_CLKCTRL_INDEX(0x520) +#define AM4_SPINLOCK_CLKCTRL AM4_CLKCTRL_INDEX(0x528) +#define AM4_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x530) +#define AM4_TIMER3_CLKCTRL AM4_CLKCTRL_INDEX(0x538) +#define AM4_TIMER4_CLKCTRL AM4_CLKCTRL_INDEX(0x540) +#define AM4_TIMER5_CLKCTRL AM4_CLKCTRL_INDEX(0x548) +#define AM4_TIMER6_CLKCTRL AM4_CLKCTRL_INDEX(0x550) +#define AM4_TIMER7_CLKCTRL AM4_CLKCTRL_INDEX(0x558) +#define AM4_TIMER8_CLKCTRL AM4_CLKCTRL_INDEX(0x560) +#define AM4_TIMER9_CLKCTRL AM4_CLKCTRL_INDEX(0x568) +#define AM4_TIMER10_CLKCTRL AM4_CLKCTRL_INDEX(0x570) +#define AM4_TIMER11_CLKCTRL AM4_CLKCTRL_INDEX(0x578) +#define AM4_UART2_CLKCTRL AM4_CLKCTRL_INDEX(0x580) +#define AM4_UART3_CLKCTRL AM4_CLKCTRL_INDEX(0x588) +#define AM4_UART4_CLKCTRL AM4_CLKCTRL_INDEX(0x590) +#define AM4_UART5_CLKCTRL AM4_CLKCTRL_INDEX(0x598) +#define AM4_UART6_CLKCTRL AM4_CLKCTRL_INDEX(0x5a0) +#define AM4_OCP2SCP0_CLKCTRL AM4_CLKCTRL_INDEX(0x5b8) +#define AM4_OCP2SCP1_CLKCTRL AM4_CLKCTRL_INDEX(0x5c0) +#define AM4_EMIF_CLKCTRL AM4_CLKCTRL_INDEX(0x720) +#define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20) +#define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20) + +#endif diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h new file mode 100644 index 000000000000..d3558d897a4d --- /dev/null +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +#ifndef DT_BINDINGS_ASPEED_CLOCK_H +#define DT_BINDINGS_ASPEED_CLOCK_H + +#define ASPEED_CLK_GATE_ECLK 0 +#define ASPEED_CLK_GATE_GCLK 1 +#define ASPEED_CLK_GATE_MCLK 2 +#define ASPEED_CLK_GATE_VCLK 3 +#define ASPEED_CLK_GATE_BCLK 4 +#define ASPEED_CLK_GATE_DCLK 5 +#define ASPEED_CLK_GATE_REFCLK 6 +#define ASPEED_CLK_GATE_USBPORT2CLK 7 +#define ASPEED_CLK_GATE_LCLK 8 +#define ASPEED_CLK_GATE_USBUHCICLK 9 +#define ASPEED_CLK_GATE_D1CLK 10 +#define ASPEED_CLK_GATE_YCLK 11 +#define ASPEED_CLK_GATE_USBPORT1CLK 12 +#define ASPEED_CLK_GATE_UART1CLK 13 +#define ASPEED_CLK_GATE_UART2CLK 14 +#define ASPEED_CLK_GATE_UART5CLK 15 +#define ASPEED_CLK_GATE_ESPICLK 16 +#define ASPEED_CLK_GATE_MAC1CLK 17 +#define ASPEED_CLK_GATE_MAC2CLK 18 +#define ASPEED_CLK_GATE_RSACLK 19 +#define ASPEED_CLK_GATE_UART3CLK 20 +#define ASPEED_CLK_GATE_UART4CLK 21 +#define ASPEED_CLK_GATE_SDCLKCLK 22 +#define ASPEED_CLK_GATE_LHCCLK 23 +#define ASPEED_CLK_HPLL 24 +#define ASPEED_CLK_AHB 25 +#define ASPEED_CLK_APB 26 +#define ASPEED_CLK_UART 27 +#define ASPEED_CLK_SDIO 28 +#define ASPEED_CLK_ECLK 29 +#define ASPEED_CLK_ECLK_MUX 30 +#define ASPEED_CLK_LHCLK 31 +#define ASPEED_CLK_MAC 32 +#define ASPEED_CLK_BCLK 33 +#define ASPEED_CLK_MPLL 34 + +#define ASPEED_RESET_XDMA 0 +#define ASPEED_RESET_MCTP 1 +#define ASPEED_RESET_ADC 2 +#define ASPEED_RESET_JTAG_MASTER 3 +#define ASPEED_RESET_MIC 4 +#define ASPEED_RESET_PWM 5 +#define ASPEED_RESET_PCIVGA 6 +#define ASPEED_RESET_I2C 7 +#define ASPEED_RESET_AHB 8 + +#endif diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h new file mode 100644 index 000000000000..941ac70e7f30 --- /dev/null +++ b/include/dt-bindings/clock/axg-clkc.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Meson-AXG clock tree IDs + * + * Copyright (c) 2017 Amlogic, Inc. All rights reserved. + */ + +#ifndef __AXG_CLKC_H +#define __AXG_CLKC_H + +#define CLKID_SYS_PLL 0 +#define CLKID_FIXED_PLL 1 +#define CLKID_FCLK_DIV2 2 +#define CLKID_FCLK_DIV3 3 +#define CLKID_FCLK_DIV4 4 +#define CLKID_FCLK_DIV5 5 +#define CLKID_FCLK_DIV7 6 +#define CLKID_GP0_PLL 7 +#define CLKID_CLK81 10 +#define CLKID_MPLL0 11 +#define CLKID_MPLL1 12 +#define CLKID_MPLL2 13 +#define CLKID_MPLL3 14 +#define CLKID_DDR 15 +#define CLKID_AUDIO_LOCKER 16 +#define CLKID_MIPI_DSI_HOST 17 +#define CLKID_ISA 18 +#define CLKID_PL301 19 +#define CLKID_PERIPHS 20 +#define CLKID_SPICC0 21 +#define CLKID_I2C 22 +#define CLKID_RNG0 23 +#define CLKID_UART0 24 +#define CLKID_MIPI_DSI_PHY 25 +#define CLKID_SPICC1 26 +#define CLKID_PCIE_A 27 +#define CLKID_PCIE_B 28 +#define CLKID_HIU_IFACE 29 +#define CLKID_ASSIST_MISC 30 +#define CLKID_SD_EMMC_B 31 +#define CLKID_SD_EMMC_C 32 +#define CLKID_DMA 33 +#define CLKID_SPI 34 +#define CLKID_AUDIO 35 +#define CLKID_ETH 36 +#define CLKID_UART1 37 +#define CLKID_G2D 38 +#define CLKID_USB0 39 +#define CLKID_USB1 40 +#define CLKID_RESET 41 +#define CLKID_USB 42 +#define CLKID_AHB_ARB0 43 +#define CLKID_EFUSE 44 +#define CLKID_BOOT_ROM 45 +#define CLKID_AHB_DATA_BUS 46 +#define CLKID_AHB_CTRL_BUS 47 +#define CLKID_USB1_DDR_BRIDGE 48 +#define CLKID_USB0_DDR_BRIDGE 49 +#define CLKID_MMC_PCLK 50 +#define CLKID_VPU_INTR 51 +#define CLKID_SEC_AHB_AHB3_BRIDGE 52 +#define CLKID_GIC 53 +#define CLKID_AO_MEDIA_CPU 54 +#define CLKID_AO_AHB_SRAM 55 +#define CLKID_AO_AHB_BUS 56 +#define CLKID_AO_IFACE 57 +#define CLKID_AO_I2C 58 +#define CLKID_SD_EMMC_B_CLK0 59 +#define CLKID_SD_EMMC_C_CLK0 60 + +#endif /* __AXG_CLKC_H */ diff --git a/include/dt-bindings/clock/dm814.h b/include/dt-bindings/clock/dm814.h new file mode 100644 index 000000000000..0e7099a344e1 --- /dev/null +++ b/include/dt-bindings/clock/dm814.h @@ -0,0 +1,45 @@ +/* + * Copyright 2017 Texas Instruments, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __DT_BINDINGS_CLK_DM814_H +#define __DT_BINDINGS_CLK_DM814_H + +#define DM814_CLKCTRL_OFFSET 0x0 +#define DM814_CLKCTRL_INDEX(offset) ((offset) - DM814_CLKCTRL_OFFSET) + +/* default clocks */ +#define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58) + +/* alwon clocks */ +#define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150) +#define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154) +#define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158) +#define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c) +#define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160) +#define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164) +#define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168) +#define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c) +#define DM814_MCSPI1_CLKCTRL DM814_CLKCTRL_INDEX(0x190) +#define DM814_GPMC_CLKCTRL DM814_CLKCTRL_INDEX(0x1d0) +#define DM814_CPGMAC0_CLKCTRL DM814_CLKCTRL_INDEX(0x1d4) +#define DM814_MPU_CLKCTRL DM814_CLKCTRL_INDEX(0x1dc) +#define DM814_RTC_CLKCTRL DM814_CLKCTRL_INDEX(0x1f0) +#define DM814_TPCC_CLKCTRL DM814_CLKCTRL_INDEX(0x1f4) +#define DM814_TPTC0_CLKCTRL DM814_CLKCTRL_INDEX(0x1f8) +#define DM814_TPTC1_CLKCTRL DM814_CLKCTRL_INDEX(0x1fc) +#define DM814_TPTC2_CLKCTRL DM814_CLKCTRL_INDEX(0x200) +#define DM814_TPTC3_CLKCTRL DM814_CLKCTRL_INDEX(0x204) +#define DM814_MMC1_CLKCTRL DM814_CLKCTRL_INDEX(0x21c) +#define DM814_MMC2_CLKCTRL DM814_CLKCTRL_INDEX(0x220) +#define DM814_MMC3_CLKCTRL DM814_CLKCTRL_INDEX(0x224) + +#endif diff --git a/include/dt-bindings/clock/dm816.h b/include/dt-bindings/clock/dm816.h new file mode 100644 index 000000000000..69e8a36d783e --- /dev/null +++ b/include/dt-bindings/clock/dm816.h @@ -0,0 +1,53 @@ +/* + * Copyright 2017 Texas Instruments, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __DT_BINDINGS_CLK_DM816_H +#define __DT_BINDINGS_CLK_DM816_H + +#define DM816_CLKCTRL_OFFSET 0x0 +#define DM816_CLKCTRL_INDEX(offset) ((offset) - DM816_CLKCTRL_OFFSET) + +/* default clocks */ +#define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58) + +/* alwon clocks */ +#define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150) +#define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154) +#define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158) +#define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c) +#define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160) +#define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164) +#define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168) +#define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170) +#define DM816_TIMER2_CLKCTRL DM816_CLKCTRL_INDEX(0x174) +#define DM816_TIMER3_CLKCTRL DM816_CLKCTRL_INDEX(0x178) +#define DM816_TIMER4_CLKCTRL DM816_CLKCTRL_INDEX(0x17c) +#define DM816_TIMER5_CLKCTRL DM816_CLKCTRL_INDEX(0x180) +#define DM816_TIMER6_CLKCTRL DM816_CLKCTRL_INDEX(0x184) +#define DM816_TIMER7_CLKCTRL DM816_CLKCTRL_INDEX(0x188) +#define DM816_WD_TIMER_CLKCTRL DM816_CLKCTRL_INDEX(0x18c) +#define DM816_MCSPI1_CLKCTRL DM816_CLKCTRL_INDEX(0x190) +#define DM816_MAILBOX_CLKCTRL DM816_CLKCTRL_INDEX(0x194) +#define DM816_SPINBOX_CLKCTRL DM816_CLKCTRL_INDEX(0x198) +#define DM816_MMC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1b0) +#define DM816_GPMC_CLKCTRL DM816_CLKCTRL_INDEX(0x1d0) +#define DM816_DAVINCI_MDIO_CLKCTRL DM816_CLKCTRL_INDEX(0x1d4) +#define DM816_EMAC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1d8) +#define DM816_MPU_CLKCTRL DM816_CLKCTRL_INDEX(0x1dc) +#define DM816_RTC_CLKCTRL DM816_CLKCTRL_INDEX(0x1f0) +#define DM816_TPCC_CLKCTRL DM816_CLKCTRL_INDEX(0x1f4) +#define DM816_TPTC0_CLKCTRL DM816_CLKCTRL_INDEX(0x1f8) +#define DM816_TPTC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1fc) +#define DM816_TPTC2_CLKCTRL DM816_CLKCTRL_INDEX(0x200) +#define DM816_TPTC3_CLKCTRL DM816_CLKCTRL_INDEX(0x204) + +#endif diff --git a/include/dt-bindings/clock/dra7.h b/include/dt-bindings/clock/dra7.h new file mode 100644 index 000000000000..5e1061b15aed --- /dev/null +++ b/include/dt-bindings/clock/dra7.h @@ -0,0 +1,172 @@ +/* + * Copyright 2017 Texas Instruments, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __DT_BINDINGS_CLK_DRA7_H +#define __DT_BINDINGS_CLK_DRA7_H + +#define DRA7_CLKCTRL_OFFSET 0x20 +#define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET) + +/* mpu clocks */ +#define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) + +/* ipu clocks */ +#define DRA7_IPU_CLKCTRL_OFFSET 0x40 +#define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET) +#define DRA7_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50) +#define DRA7_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58) +#define DRA7_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60) +#define DRA7_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68) +#define DRA7_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70) +#define DRA7_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78) +#define DRA7_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80) + +/* rtc clocks */ +#define DRA7_RTC_CLKCTRL_OFFSET 0x40 +#define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET) +#define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44) + +/* coreaon clocks */ +#define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +#define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) + +/* l3main1 clocks */ +#define DRA7_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +#define DRA7_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +#define DRA7_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) +#define DRA7_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) +#define DRA7_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) +#define DRA7_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) +#define DRA7_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) + +/* dma clocks */ +#define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) + +/* emif clocks */ +#define DRA7_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) + +/* atl clocks */ +#define DRA7_ATL_CLKCTRL_OFFSET 0x0 +#define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET) +#define DRA7_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0) + +/* l4cfg clocks */ +#define DRA7_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +#define DRA7_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +#define DRA7_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) +#define DRA7_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) +#define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) +#define DRA7_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58) +#define DRA7_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60) +#define DRA7_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68) +#define DRA7_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) +#define DRA7_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) +#define DRA7_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) +#define DRA7_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) +#define DRA7_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) +#define DRA7_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98) +#define DRA7_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) + +/* l3instr clocks */ +#define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +#define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) + +/* dss clocks */ +#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) + +/* l3init clocks */ +#define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +#define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) +#define DRA7_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) +#define DRA7_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) +#define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) +#define DRA7_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) +#define DRA7_PCIE1_CLKCTRL DRA7_CLKCTRL_INDEX(0xb0) +#define DRA7_PCIE2_CLKCTRL DRA7_CLKCTRL_INDEX(0xb8) +#define DRA7_GMAC_CLKCTRL DRA7_CLKCTRL_INDEX(0xd0) +#define DRA7_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0) +#define DRA7_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8) +#define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0) + +/* l4per clocks */ +#define DRA7_L4PER_CLKCTRL_OFFSET 0x0 +#define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET) +#define DRA7_L4_PER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc) +#define DRA7_L4_PER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x14) +#define DRA7_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28) +#define DRA7_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30) +#define DRA7_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38) +#define DRA7_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40) +#define DRA7_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48) +#define DRA7_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50) +#define DRA7_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58) +#define DRA7_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60) +#define DRA7_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68) +#define DRA7_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70) +#define DRA7_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78) +#define DRA7_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80) +#define DRA7_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88) +#define DRA7_EPWMSS1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x90) +#define DRA7_EPWMSS2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x98) +#define DRA7_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0) +#define DRA7_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8) +#define DRA7_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0) +#define DRA7_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8) +#define DRA7_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0) +#define DRA7_EPWMSS0_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc4) +#define DRA7_TIMER13_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc8) +#define DRA7_TIMER14_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd0) +#define DRA7_TIMER15_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd8) +#define DRA7_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0) +#define DRA7_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8) +#define DRA7_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100) +#define DRA7_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108) +#define DRA7_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110) +#define DRA7_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118) +#define DRA7_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120) +#define DRA7_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128) +#define DRA7_TIMER16_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x130) +#define DRA7_QSPI_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x138) +#define DRA7_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140) +#define DRA7_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148) +#define DRA7_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150) +#define DRA7_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158) +#define DRA7_MCASP2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x160) +#define DRA7_MCASP3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x168) +#define DRA7_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170) +#define DRA7_MCASP5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x178) +#define DRA7_MCASP8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x190) +#define DRA7_MCASP4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x198) +#define DRA7_AES1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a0) +#define DRA7_AES2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a8) +#define DRA7_DES_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1b0) +#define DRA7_RNG_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c0) +#define DRA7_SHAM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c8) +#define DRA7_UART7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1d0) +#define DRA7_UART8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e0) +#define DRA7_UART9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e8) +#define DRA7_DCAN2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1f0) +#define DRA7_MCASP6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x204) +#define DRA7_MCASP7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x208) + +/* wkupaon clocks */ +#define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +#define DRA7_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) +#define DRA7_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) +#define DRA7_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) +#define DRA7_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) +#define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) +#define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) +#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) + +#endif diff --git a/include/dt-bindings/clock/hi3660-clock.h b/include/dt-bindings/clock/hi3660-clock.h index adb768d447a5..75d583eb84dd 100644 --- a/include/dt-bindings/clock/hi3660-clock.h +++ b/include/dt-bindings/clock/hi3660-clock.h @@ -208,4 +208,11 @@ #define HI3660_CLK_I2C6_IOMCU 3 #define HI3660_CLK_IOMCU_PERI0 4 +/* clk in stub clock */ +#define HI3660_CLK_STUB_CLUSTER0 0 +#define HI3660_CLK_STUB_CLUSTER1 1 +#define HI3660_CLK_STUB_GPU 2 +#define HI3660_CLK_STUB_DDR 3 +#define HI3660_CLK_STUB_NUM 4 + #endif /* __DTS_HI3660_CLOCK_H */ diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h index e2f99ae72d5c..b2325d3e236a 100644 --- a/include/dt-bindings/clock/imx7d-clock.h +++ b/include/dt-bindings/clock/imx7d-clock.h @@ -452,5 +452,8 @@ #define IMX7D_OCOTP_CLK 439 #define IMX7D_NAND_RAWNAND_CLK 440 #define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441 -#define IMX7D_CLK_END 442 +#define IMX7D_SNVS_CLK 442 +#define IMX7D_CAAM_CLK 443 +#define IMX7D_KPP_ROOT_CLK 444 +#define IMX7D_CLK_END 445 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ diff --git a/include/dt-bindings/clock/jz4770-cgu.h b/include/dt-bindings/clock/jz4770-cgu.h new file mode 100644 index 000000000000..d68a7695a1f8 --- /dev/null +++ b/include/dt-bindings/clock/jz4770-cgu.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,jz4770-cgu DT binding. + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ + +#define JZ4770_CLK_EXT 0 +#define JZ4770_CLK_OSC32K 1 +#define JZ4770_CLK_PLL0 2 +#define JZ4770_CLK_PLL1 3 +#define JZ4770_CLK_CCLK 4 +#define JZ4770_CLK_H0CLK 5 +#define JZ4770_CLK_H1CLK 6 +#define JZ4770_CLK_H2CLK 7 +#define JZ4770_CLK_C1CLK 8 +#define JZ4770_CLK_PCLK 9 +#define JZ4770_CLK_MMC0_MUX 10 +#define JZ4770_CLK_MMC0 11 +#define JZ4770_CLK_MMC1_MUX 12 +#define JZ4770_CLK_MMC1 13 +#define JZ4770_CLK_MMC2_MUX 14 +#define JZ4770_CLK_MMC2 15 +#define JZ4770_CLK_CIM 16 +#define JZ4770_CLK_UHC 17 +#define JZ4770_CLK_GPU 18 +#define JZ4770_CLK_BCH 19 +#define JZ4770_CLK_LPCLK_MUX 20 +#define JZ4770_CLK_GPS 21 +#define JZ4770_CLK_SSI_MUX 22 +#define JZ4770_CLK_PCM_MUX 23 +#define JZ4770_CLK_I2S 24 +#define JZ4770_CLK_OTG 25 +#define JZ4770_CLK_SSI0 26 +#define JZ4770_CLK_SSI1 27 +#define JZ4770_CLK_SSI2 28 +#define JZ4770_CLK_PCM0 29 +#define JZ4770_CLK_PCM1 30 +#define JZ4770_CLK_DMA 31 +#define JZ4770_CLK_I2C0 32 +#define JZ4770_CLK_I2C1 33 +#define JZ4770_CLK_I2C2 34 +#define JZ4770_CLK_UART0 35 +#define JZ4770_CLK_UART1 36 +#define JZ4770_CLK_UART2 37 +#define JZ4770_CLK_UART3 38 +#define JZ4770_CLK_IPU 39 +#define JZ4770_CLK_ADC 40 +#define JZ4770_CLK_AIC 41 +#define JZ4770_CLK_AUX 42 +#define JZ4770_CLK_VPU 43 +#define JZ4770_CLK_UHC_PHY 44 +#define JZ4770_CLK_OTG_PHY 45 +#define JZ4770_CLK_EXT512 46 +#define JZ4770_CLK_RTC 47 + +#endif /* __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ */ diff --git a/include/dt-bindings/clock/omap5.h b/include/dt-bindings/clock/omap5.h new file mode 100644 index 000000000000..f51821a91216 --- /dev/null +++ b/include/dt-bindings/clock/omap5.h @@ -0,0 +1,118 @@ +/* + * Copyright 2017 Texas Instruments, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __DT_BINDINGS_CLK_OMAP5_H +#define __DT_BINDINGS_CLK_OMAP5_H + +#define OMAP5_CLKCTRL_OFFSET 0x20 +#define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET) + +/* mpu clocks */ +#define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* dsp clocks */ +#define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* abe clocks */ +#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) +#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) +#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) +#define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) +#define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) +#define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) +#define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) +#define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) +#define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) + +/* l3main1 clocks */ +#define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* l3main2 clocks */ +#define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* ipu clocks */ +#define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* dma clocks */ +#define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* emif clocks */ +#define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) +#define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) + +/* l4cfg clocks */ +#define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) +#define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) + +/* l3instr clocks */ +#define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) + +/* l4per clocks */ +#define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) +#define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) +#define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) +#define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) +#define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) +#define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) +#define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60) +#define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) +#define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) +#define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) +#define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) +#define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0) +#define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8) +#define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0) +#define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8) +#define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0) +#define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) +#define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8) +#define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100) +#define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108) +#define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110) +#define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118) +#define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120) +#define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128) +#define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140) +#define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148) +#define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150) +#define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158) +#define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160) +#define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168) +#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170) +#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178) + +/* dss clocks */ +#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* l3init clocks */ +#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) +#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) +#define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) +#define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) +#define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88) +#define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0) +#define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8) +#define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) + +/* wkupaon clocks */ +#define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) +#define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) +#define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) +#define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) +#define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h index 370c83c3bccc..238f872e52f4 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -58,6 +58,186 @@ #define GCC_QPIC_AHB_CLK 41 #define GCC_QPIC_CLK 42 #define PCNOC_BFDCD_CLK_SRC 43 +#define GPLL2_MAIN 44 +#define GPLL2 45 +#define GPLL4_MAIN 46 +#define GPLL4 47 +#define GPLL6_MAIN 48 +#define GPLL6 49 +#define UBI32_PLL_MAIN 50 +#define UBI32_PLL 51 +#define NSS_CRYPTO_PLL_MAIN 52 +#define NSS_CRYPTO_PLL 53 +#define PCIE0_AXI_CLK_SRC 54 +#define PCIE0_AUX_CLK_SRC 55 +#define PCIE0_PIPE_CLK_SRC 56 +#define PCIE1_AXI_CLK_SRC 57 +#define PCIE1_AUX_CLK_SRC 58 +#define PCIE1_PIPE_CLK_SRC 59 +#define SDCC1_APPS_CLK_SRC 60 +#define SDCC1_ICE_CORE_CLK_SRC 61 +#define SDCC2_APPS_CLK_SRC 62 +#define USB0_MASTER_CLK_SRC 63 +#define USB0_AUX_CLK_SRC 64 +#define USB0_MOCK_UTMI_CLK_SRC 65 +#define USB0_PIPE_CLK_SRC 66 +#define USB1_MASTER_CLK_SRC 67 +#define USB1_AUX_CLK_SRC 68 +#define USB1_MOCK_UTMI_CLK_SRC 69 +#define USB1_PIPE_CLK_SRC 70 +#define GCC_XO_CLK_SRC 71 +#define SYSTEM_NOC_BFDCD_CLK_SRC 72 +#define NSS_CE_CLK_SRC 73 +#define NSS_NOC_BFDCD_CLK_SRC 74 +#define NSS_CRYPTO_CLK_SRC 75 +#define NSS_UBI0_CLK_SRC 76 +#define NSS_UBI0_DIV_CLK_SRC 77 +#define NSS_UBI1_CLK_SRC 78 +#define NSS_UBI1_DIV_CLK_SRC 79 +#define UBI_MPT_CLK_SRC 80 +#define NSS_IMEM_CLK_SRC 81 +#define NSS_PPE_CLK_SRC 82 +#define NSS_PORT1_RX_CLK_SRC 83 +#define NSS_PORT1_RX_DIV_CLK_SRC 84 +#define NSS_PORT1_TX_CLK_SRC 85 +#define NSS_PORT1_TX_DIV_CLK_SRC 86 +#define NSS_PORT2_RX_CLK_SRC 87 +#define NSS_PORT2_RX_DIV_CLK_SRC 88 +#define NSS_PORT2_TX_CLK_SRC 89 +#define NSS_PORT2_TX_DIV_CLK_SRC 90 +#define NSS_PORT3_RX_CLK_SRC 91 +#define NSS_PORT3_RX_DIV_CLK_SRC 92 +#define NSS_PORT3_TX_CLK_SRC 93 +#define NSS_PORT3_TX_DIV_CLK_SRC 94 +#define NSS_PORT4_RX_CLK_SRC 95 +#define NSS_PORT4_RX_DIV_CLK_SRC 96 +#define NSS_PORT4_TX_CLK_SRC 97 +#define NSS_PORT4_TX_DIV_CLK_SRC 98 +#define NSS_PORT5_RX_CLK_SRC 99 +#define NSS_PORT5_RX_DIV_CLK_SRC 100 +#define NSS_PORT5_TX_CLK_SRC 101 +#define NSS_PORT5_TX_DIV_CLK_SRC 102 +#define NSS_PORT6_RX_CLK_SRC 103 +#define NSS_PORT6_RX_DIV_CLK_SRC 104 +#define NSS_PORT6_TX_CLK_SRC 105 +#define NSS_PORT6_TX_DIV_CLK_SRC 106 +#define CRYPTO_CLK_SRC 107 +#define GP1_CLK_SRC 108 +#define GP2_CLK_SRC 109 +#define GP3_CLK_SRC 110 +#define GCC_PCIE0_AHB_CLK 111 +#define GCC_PCIE0_AUX_CLK 112 +#define GCC_PCIE0_AXI_M_CLK 113 +#define GCC_PCIE0_AXI_S_CLK 114 +#define GCC_PCIE0_PIPE_CLK 115 +#define GCC_SYS_NOC_PCIE0_AXI_CLK 116 +#define GCC_PCIE1_AHB_CLK 117 +#define GCC_PCIE1_AUX_CLK 118 +#define GCC_PCIE1_AXI_M_CLK 119 +#define GCC_PCIE1_AXI_S_CLK 120 +#define GCC_PCIE1_PIPE_CLK 121 +#define GCC_SYS_NOC_PCIE1_AXI_CLK 122 +#define GCC_USB0_AUX_CLK 123 +#define GCC_SYS_NOC_USB0_AXI_CLK 124 +#define GCC_USB0_MASTER_CLK 125 +#define GCC_USB0_MOCK_UTMI_CLK 126 +#define GCC_USB0_PHY_CFG_AHB_CLK 127 +#define GCC_USB0_PIPE_CLK 128 +#define GCC_USB0_SLEEP_CLK 129 +#define GCC_USB1_AUX_CLK 130 +#define GCC_SYS_NOC_USB1_AXI_CLK 131 +#define GCC_USB1_MASTER_CLK 132 +#define GCC_USB1_MOCK_UTMI_CLK 133 +#define GCC_USB1_PHY_CFG_AHB_CLK 134 +#define GCC_USB1_PIPE_CLK 135 +#define GCC_USB1_SLEEP_CLK 136 +#define GCC_SDCC1_AHB_CLK 137 +#define GCC_SDCC1_APPS_CLK 138 +#define GCC_SDCC1_ICE_CORE_CLK 139 +#define GCC_SDCC2_AHB_CLK 140 +#define GCC_SDCC2_APPS_CLK 141 +#define GCC_MEM_NOC_NSS_AXI_CLK 142 +#define GCC_NSS_CE_APB_CLK 143 +#define GCC_NSS_CE_AXI_CLK 144 +#define GCC_NSS_CFG_CLK 145 +#define GCC_NSS_CRYPTO_CLK 146 +#define GCC_NSS_CSR_CLK 147 +#define GCC_NSS_EDMA_CFG_CLK 148 +#define GCC_NSS_EDMA_CLK 149 +#define GCC_NSS_IMEM_CLK 150 +#define GCC_NSS_NOC_CLK 151 +#define GCC_NSS_PPE_BTQ_CLK 152 +#define GCC_NSS_PPE_CFG_CLK 153 +#define GCC_NSS_PPE_CLK 154 +#define GCC_NSS_PPE_IPE_CLK 155 +#define GCC_NSS_PTP_REF_CLK 156 +#define GCC_NSSNOC_CE_APB_CLK 157 +#define GCC_NSSNOC_CE_AXI_CLK 158 +#define GCC_NSSNOC_CRYPTO_CLK 159 +#define GCC_NSSNOC_PPE_CFG_CLK 160 +#define GCC_NSSNOC_PPE_CLK 161 +#define GCC_NSSNOC_QOSGEN_REF_CLK 162 +#define GCC_NSSNOC_SNOC_CLK 163 +#define GCC_NSSNOC_TIMEOUT_REF_CLK 164 +#define GCC_NSSNOC_UBI0_AHB_CLK 165 +#define GCC_NSSNOC_UBI1_AHB_CLK 166 +#define GCC_UBI0_AHB_CLK 167 +#define GCC_UBI0_AXI_CLK 168 +#define GCC_UBI0_NC_AXI_CLK 169 +#define GCC_UBI0_CORE_CLK 170 +#define GCC_UBI0_MPT_CLK 171 +#define GCC_UBI1_AHB_CLK 172 +#define GCC_UBI1_AXI_CLK 173 +#define GCC_UBI1_NC_AXI_CLK 174 +#define GCC_UBI1_CORE_CLK 175 +#define GCC_UBI1_MPT_CLK 176 +#define GCC_CMN_12GPLL_AHB_CLK 177 +#define GCC_CMN_12GPLL_SYS_CLK 178 +#define GCC_MDIO_AHB_CLK 179 +#define GCC_UNIPHY0_AHB_CLK 180 +#define GCC_UNIPHY0_SYS_CLK 181 +#define GCC_UNIPHY1_AHB_CLK 182 +#define GCC_UNIPHY1_SYS_CLK 183 +#define GCC_UNIPHY2_AHB_CLK 184 +#define GCC_UNIPHY2_SYS_CLK 185 +#define GCC_NSS_PORT1_RX_CLK 186 +#define GCC_NSS_PORT1_TX_CLK 187 +#define GCC_NSS_PORT2_RX_CLK 188 +#define GCC_NSS_PORT2_TX_CLK 189 +#define GCC_NSS_PORT3_RX_CLK 190 +#define GCC_NSS_PORT3_TX_CLK 191 +#define GCC_NSS_PORT4_RX_CLK 192 +#define GCC_NSS_PORT4_TX_CLK 193 +#define GCC_NSS_PORT5_RX_CLK 194 +#define GCC_NSS_PORT5_TX_CLK 195 +#define GCC_NSS_PORT6_RX_CLK 196 +#define GCC_NSS_PORT6_TX_CLK 197 +#define GCC_PORT1_MAC_CLK 198 +#define GCC_PORT2_MAC_CLK 199 +#define GCC_PORT3_MAC_CLK 200 +#define GCC_PORT4_MAC_CLK 201 +#define GCC_PORT5_MAC_CLK 202 +#define GCC_PORT6_MAC_CLK 203 +#define GCC_UNIPHY0_PORT1_RX_CLK 204 +#define GCC_UNIPHY0_PORT1_TX_CLK 205 +#define GCC_UNIPHY0_PORT2_RX_CLK 206 +#define GCC_UNIPHY0_PORT2_TX_CLK 207 +#define GCC_UNIPHY0_PORT3_RX_CLK 208 +#define GCC_UNIPHY0_PORT3_TX_CLK 209 +#define GCC_UNIPHY0_PORT4_RX_CLK 210 +#define GCC_UNIPHY0_PORT4_TX_CLK 211 +#define GCC_UNIPHY0_PORT5_RX_CLK 212 +#define GCC_UNIPHY0_PORT5_TX_CLK 213 +#define GCC_UNIPHY1_PORT5_RX_CLK 214 +#define GCC_UNIPHY1_PORT5_TX_CLK 215 +#define GCC_UNIPHY2_PORT6_RX_CLK 216 +#define GCC_UNIPHY2_PORT6_TX_CLK 217 +#define GCC_CRYPTO_AHB_CLK 218 +#define GCC_CRYPTO_AXI_CLK 219 +#define GCC_CRYPTO_CLK 220 +#define GCC_GP1_CLK 221 +#define GCC_GP2_CLK 222 +#define GCC_GP3_CLK 223 #define GCC_BLSP1_BCR 0 #define GCC_BLSP1_QUP1_BCR 1 @@ -148,5 +328,47 @@ #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 86 #define GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR 87 #define GCC_SMMU_CATS_BCR 88 +#define GCC_UBI0_AXI_ARES 89 +#define GCC_UBI0_AHB_ARES 90 +#define GCC_UBI0_NC_AXI_ARES 91 +#define GCC_UBI0_DBG_ARES 92 +#define GCC_UBI0_CORE_CLAMP_ENABLE 93 +#define GCC_UBI0_CLKRST_CLAMP_ENABLE 94 +#define GCC_UBI1_AXI_ARES 95 +#define GCC_UBI1_AHB_ARES 96 +#define GCC_UBI1_NC_AXI_ARES 97 +#define GCC_UBI1_DBG_ARES 98 +#define GCC_UBI1_CORE_CLAMP_ENABLE 99 +#define GCC_UBI1_CLKRST_CLAMP_ENABLE 100 +#define GCC_NSS_CFG_ARES 101 +#define GCC_NSS_IMEM_ARES 102 +#define GCC_NSS_NOC_ARES 103 +#define GCC_NSS_CRYPTO_ARES 104 +#define GCC_NSS_CSR_ARES 105 +#define GCC_NSS_CE_APB_ARES 106 +#define GCC_NSS_CE_AXI_ARES 107 +#define GCC_NSSNOC_CE_APB_ARES 108 +#define GCC_NSSNOC_CE_AXI_ARES 109 +#define GCC_NSSNOC_UBI0_AHB_ARES 110 +#define GCC_NSSNOC_UBI1_AHB_ARES 111 +#define GCC_NSSNOC_SNOC_ARES 112 +#define GCC_NSSNOC_CRYPTO_ARES 113 +#define GCC_NSSNOC_ATB_ARES 114 +#define GCC_NSSNOC_QOSGEN_REF_ARES 115 +#define GCC_NSSNOC_TIMEOUT_REF_ARES 116 +#define GCC_PCIE0_PIPE_ARES 117 +#define GCC_PCIE0_SLEEP_ARES 118 +#define GCC_PCIE0_CORE_STICKY_ARES 119 +#define GCC_PCIE0_AXI_MASTER_ARES 120 +#define GCC_PCIE0_AXI_SLAVE_ARES 121 +#define GCC_PCIE0_AHB_ARES 122 +#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 123 +#define GCC_PCIE1_PIPE_ARES 124 +#define GCC_PCIE1_SLEEP_ARES 125 +#define GCC_PCIE1_CORE_STICKY_ARES 126 +#define GCC_PCIE1_AXI_MASTER_ARES 127 +#define GCC_PCIE1_AXI_SLAVE_ARES 128 +#define GCC_PCIE1_AHB_ARES 129 +#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 #endif diff --git a/include/dt-bindings/clock/sprd,sc9860-clk.h b/include/dt-bindings/clock/sprd,sc9860-clk.h new file mode 100644 index 000000000000..4cb202f090c2 --- /dev/null +++ b/include/dt-bindings/clock/sprd,sc9860-clk.h @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// +// Spreadtrum SC9860 platform clocks +// +// Copyright (C) 2017, Spreadtrum Communications Inc. + +#ifndef _DT_BINDINGS_CLK_SC9860_H_ +#define _DT_BINDINGS_CLK_SC9860_H_ + +#define CLK_FAC_4M 0 +#define CLK_FAC_2M 1 +#define CLK_FAC_1M 2 +#define CLK_FAC_250K 3 +#define CLK_FAC_RPLL0_26M 4 +#define CLK_FAC_RPLL1_26M 5 +#define CLK_FAC_RCO25M 6 +#define CLK_FAC_RCO4M 7 +#define CLK_FAC_RCO2M 8 +#define CLK_FAC_3K2 9 +#define CLK_FAC_1K 10 +#define CLK_MPLL0_GATE 11 +#define CLK_MPLL1_GATE 12 +#define CLK_DPLL0_GATE 13 +#define CLK_DPLL1_GATE 14 +#define CLK_LTEPLL0_GATE 15 +#define CLK_TWPLL_GATE 16 +#define CLK_LTEPLL1_GATE 17 +#define CLK_RPLL0_GATE 18 +#define CLK_RPLL1_GATE 19 +#define CLK_CPPLL_GATE 20 +#define CLK_GPLL_GATE 21 +#define CLK_PMU_GATE_NUM (CLK_GPLL_GATE + 1) + +#define CLK_MPLL0 0 +#define CLK_MPLL1 1 +#define CLK_DPLL0 2 +#define CLK_DPLL1 3 +#define CLK_RPLL0 4 +#define CLK_RPLL1 5 +#define CLK_TWPLL 6 +#define CLK_LTEPLL0 7 +#define CLK_LTEPLL1 8 +#define CLK_GPLL 9 +#define CLK_CPPLL 10 +#define CLK_GPLL_42M5 11 +#define CLK_TWPLL_768M 12 +#define CLK_TWPLL_384M 13 +#define CLK_TWPLL_192M 14 +#define CLK_TWPLL_96M 15 +#define CLK_TWPLL_48M 16 +#define CLK_TWPLL_24M 17 +#define CLK_TWPLL_12M 18 +#define CLK_TWPLL_512M 19 +#define CLK_TWPLL_256M 20 +#define CLK_TWPLL_128M 21 +#define CLK_TWPLL_64M 22 +#define CLK_TWPLL_307M2 23 +#define CLK_TWPLL_153M6 24 +#define CLK_TWPLL_76M8 25 +#define CLK_TWPLL_51M2 26 +#define CLK_TWPLL_38M4 27 +#define CLK_TWPLL_19M2 28 +#define CLK_L0_614M4 29 +#define CLK_L0_409M6 30 +#define CLK_L0_38M 31 +#define CLK_L1_38M 32 +#define CLK_RPLL0_192M 33 +#define CLK_RPLL0_96M 34 +#define CLK_RPLL0_48M 35 +#define CLK_RPLL1_468M 36 +#define CLK_RPLL1_192M 37 +#define CLK_RPLL1_96M 38 +#define CLK_RPLL1_64M 39 +#define CLK_RPLL1_48M 40 +#define CLK_DPLL0_50M 41 +#define CLK_DPLL1_50M 42 +#define CLK_CPPLL_50M 43 +#define CLK_M0_39M 44 +#define CLK_M1_63M 45 +#define CLK_PLL_NUM (CLK_M1_63M + 1) + + +#define CLK_AP_APB 0 +#define CLK_AP_USB3 1 +#define CLK_UART0 2 +#define CLK_UART1 3 +#define CLK_UART2 4 +#define CLK_UART3 5 +#define CLK_UART4 6 +#define CLK_I2C0 7 +#define CLK_I2C1 8 +#define CLK_I2C2 9 +#define CLK_I2C3 10 +#define CLK_I2C4 11 +#define CLK_I2C5 12 +#define CLK_SPI0 13 +#define CLK_SPI1 14 +#define CLK_SPI2 15 +#define CLK_SPI3 16 +#define CLK_IIS0 17 +#define CLK_IIS1 18 +#define CLK_IIS2 19 +#define CLK_IIS3 20 +#define CLK_AP_CLK_NUM (CLK_IIS3 + 1) + +#define CLK_AON_APB 0 +#define CLK_AUX0 1 +#define CLK_AUX1 2 +#define CLK_AUX2 3 +#define CLK_PROBE 4 +#define CLK_SP_AHB 5 +#define CLK_CCI 6 +#define CLK_GIC 7 +#define CLK_CSSYS 8 +#define CLK_SDIO0_2X 9 +#define CLK_SDIO1_2X 10 +#define CLK_SDIO2_2X 11 +#define CLK_EMMC_2X 12 +#define CLK_SDIO0_1X 13 +#define CLK_SDIO1_1X 14 +#define CLK_SDIO2_1X 15 +#define CLK_EMMC_1X 16 +#define CLK_ADI 17 +#define CLK_PWM0 18 +#define CLK_PWM1 19 +#define CLK_PWM2 20 +#define CLK_PWM3 21 +#define CLK_EFUSE 22 +#define CLK_CM3_UART0 23 +#define CLK_CM3_UART1 24 +#define CLK_THM 25 +#define CLK_CM3_I2C0 26 +#define CLK_CM3_I2C1 27 +#define CLK_CM4_SPI 28 +#define CLK_AON_I2C 29 +#define CLK_AVS 30 +#define CLK_CA53_DAP 31 +#define CLK_CA53_TS 32 +#define CLK_DJTAG_TCK 33 +#define CLK_PMU 34 +#define CLK_PMU_26M 35 +#define CLK_DEBOUNCE 36 +#define CLK_OTG2_REF 37 +#define CLK_USB3_REF 38 +#define CLK_AP_AXI 39 +#define CLK_AON_PREDIV_NUM (CLK_AP_AXI + 1) + +#define CLK_USB3_EB 0 +#define CLK_USB3_SUSPEND_EB 1 +#define CLK_USB3_REF_EB 2 +#define CLK_DMA_EB 3 +#define CLK_SDIO0_EB 4 +#define CLK_SDIO1_EB 5 +#define CLK_SDIO2_EB 6 +#define CLK_EMMC_EB 7 +#define CLK_ROM_EB 8 +#define CLK_BUSMON_EB 9 +#define CLK_CC63S_EB 10 +#define CLK_CC63P_EB 11 +#define CLK_CE0_EB 12 +#define CLK_CE1_EB 13 +#define CLK_APAHB_GATE_NUM (CLK_CE1_EB + 1) + +#define CLK_AVS_LIT_EB 0 +#define CLK_AVS_BIG_EB 1 +#define CLK_AP_INTC5_EB 2 +#define CLK_GPIO_EB 3 +#define CLK_PWM0_EB 4 +#define CLK_PWM1_EB 5 +#define CLK_PWM2_EB 6 +#define CLK_PWM3_EB 7 +#define CLK_KPD_EB 8 +#define CLK_AON_SYS_EB 9 +#define CLK_AP_SYS_EB 10 +#define CLK_AON_TMR_EB 11 +#define CLK_AP_TMR0_EB 12 +#define CLK_EFUSE_EB 13 +#define CLK_EIC_EB 14 +#define CLK_PUB1_REG_EB 15 +#define CLK_ADI_EB 16 +#define CLK_AP_INTC0_EB 17 +#define CLK_AP_INTC1_EB 18 +#define CLK_AP_INTC2_EB 19 +#define CLK_AP_INTC3_EB 20 +#define CLK_AP_INTC4_EB 21 +#define CLK_SPLK_EB 22 +#define CLK_MSPI_EB 23 +#define CLK_PUB0_REG_EB 24 +#define CLK_PIN_EB 25 +#define CLK_AON_CKG_EB 26 +#define CLK_GPU_EB 27 +#define CLK_APCPU_TS0_EB 28 +#define CLK_APCPU_TS1_EB 29 +#define CLK_DAP_EB 30 +#define CLK_I2C_EB 31 +#define CLK_PMU_EB 32 +#define CLK_THM_EB 33 +#define CLK_AUX0_EB 34 +#define CLK_AUX1_EB 35 +#define CLK_AUX2_EB 36 +#define CLK_PROBE_EB 37 +#define CLK_GPU0_AVS_EB 38 +#define CLK_GPU1_AVS_EB 39 +#define CLK_APCPU_WDG_EB 40 +#define CLK_AP_TMR1_EB 41 +#define CLK_AP_TMR2_EB 42 +#define CLK_DISP_EMC_EB 43 +#define CLK_ZIP_EMC_EB 44 +#define CLK_GSP_EMC_EB 45 +#define CLK_OSC_AON_EB 46 +#define CLK_LVDS_TRX_EB 47 +#define CLK_LVDS_TCXO_EB 48 +#define CLK_MDAR_EB 49 +#define CLK_RTC4M0_CAL_EB 50 +#define CLK_RCT100M_CAL_EB 51 +#define CLK_DJTAG_EB 52 +#define CLK_MBOX_EB 53 +#define CLK_AON_DMA_EB 54 +#define CLK_DBG_EMC_EB 55 +#define CLK_LVDS_PLL_DIV_EN 56 +#define CLK_DEF_EB 57 +#define CLK_AON_APB_RSV0 58 +#define CLK_ORP_JTAG_EB 59 +#define CLK_VSP_EB 60 +#define CLK_CAM_EB 61 +#define CLK_DISP_EB 62 +#define CLK_DBG_AXI_IF_EB 63 +#define CLK_SDIO0_2X_EN 64 +#define CLK_SDIO1_2X_EN 65 +#define CLK_SDIO2_2X_EN 66 +#define CLK_EMMC_2X_EN 67 +#define CLK_AON_GATE_NUM (CLK_EMMC_2X_EN + 1) + +#define CLK_LIT_MCU 0 +#define CLK_BIG_MCU 1 +#define CLK_AONSECURE_NUM (CLK_BIG_MCU + 1) + +#define CLK_AGCP_IIS0_EB 0 +#define CLK_AGCP_IIS1_EB 1 +#define CLK_AGCP_IIS2_EB 2 +#define CLK_AGCP_IIS3_EB 3 +#define CLK_AGCP_UART_EB 4 +#define CLK_AGCP_DMACP_EB 5 +#define CLK_AGCP_DMAAP_EB 6 +#define CLK_AGCP_ARC48K_EB 7 +#define CLK_AGCP_SRC44P1K_EB 8 +#define CLK_AGCP_MCDT_EB 9 +#define CLK_AGCP_VBCIFD_EB 10 +#define CLK_AGCP_VBC_EB 11 +#define CLK_AGCP_SPINLOCK_EB 12 +#define CLK_AGCP_ICU_EB 13 +#define CLK_AGCP_AP_ASHB_EB 14 +#define CLK_AGCP_CP_ASHB_EB 15 +#define CLK_AGCP_AUD_EB 16 +#define CLK_AGCP_AUDIF_EB 17 +#define CLK_AGCP_GATE_NUM (CLK_AGCP_AUDIF_EB + 1) + +#define CLK_GPU 0 +#define CLK_GPU_NUM (CLK_GPU + 1) + +#define CLK_AHB_VSP 0 +#define CLK_VSP 1 +#define CLK_VSP_ENC 2 +#define CLK_VPP 3 +#define CLK_VSP_26M 4 +#define CLK_VSP_NUM (CLK_VSP_26M + 1) + +#define CLK_VSP_DEC_EB 0 +#define CLK_VSP_CKG_EB 1 +#define CLK_VSP_MMU_EB 2 +#define CLK_VSP_ENC_EB 3 +#define CLK_VPP_EB 4 +#define CLK_VSP_26M_EB 5 +#define CLK_VSP_AXI_GATE 6 +#define CLK_VSP_ENC_GATE 7 +#define CLK_VPP_AXI_GATE 8 +#define CLK_VSP_BM_GATE 9 +#define CLK_VSP_ENC_BM_GATE 10 +#define CLK_VPP_BM_GATE 11 +#define CLK_VSP_GATE_NUM (CLK_VPP_BM_GATE + 1) + +#define CLK_AHB_CAM 0 +#define CLK_SENSOR0 1 +#define CLK_SENSOR1 2 +#define CLK_SENSOR2 3 +#define CLK_MIPI_CSI0_EB 4 +#define CLK_MIPI_CSI1_EB 5 +#define CLK_CAM_NUM (CLK_MIPI_CSI1_EB + 1) + +#define CLK_DCAM0_EB 0 +#define CLK_DCAM1_EB 1 +#define CLK_ISP0_EB 2 +#define CLK_CSI0_EB 3 +#define CLK_CSI1_EB 4 +#define CLK_JPG0_EB 5 +#define CLK_JPG1_EB 6 +#define CLK_CAM_CKG_EB 7 +#define CLK_CAM_MMU_EB 8 +#define CLK_ISP1_EB 9 +#define CLK_CPP_EB 10 +#define CLK_MMU_PF_EB 11 +#define CLK_ISP2_EB 12 +#define CLK_DCAM2ISP_IF_EB 13 +#define CLK_ISP2DCAM_IF_EB 14 +#define CLK_ISP_LCLK_EB 15 +#define CLK_ISP_ICLK_EB 16 +#define CLK_ISP_MCLK_EB 17 +#define CLK_ISP_PCLK_EB 18 +#define CLK_ISP_ISP2DCAM_EB 19 +#define CLK_DCAM0_IF_EB 20 +#define CLK_CLK26M_IF_EB 21 +#define CLK_CPHY0_GATE 22 +#define CLK_MIPI_CSI0_GATE 23 +#define CLK_CPHY1_GATE 24 +#define CLK_MIPI_CSI1 25 +#define CLK_DCAM0_AXI_GATE 26 +#define CLK_DCAM1_AXI_GATE 27 +#define CLK_SENSOR0_GATE 28 +#define CLK_SENSOR1_GATE 29 +#define CLK_JPG0_AXI_GATE 30 +#define CLK_GPG1_AXI_GATE 31 +#define CLK_ISP0_AXI_GATE 32 +#define CLK_ISP1_AXI_GATE 33 +#define CLK_ISP2_AXI_GATE 34 +#define CLK_CPP_AXI_GATE 35 +#define CLK_D0_IF_AXI_GATE 36 +#define CLK_D2I_IF_AXI_GATE 37 +#define CLK_I2D_IF_AXI_GATE 38 +#define CLK_SPARE_AXI_GATE 39 +#define CLK_SENSOR2_GATE 40 +#define CLK_D0IF_IN_D_EN 41 +#define CLK_D1IF_IN_D_EN 42 +#define CLK_D0IF_IN_D2I_EN 43 +#define CLK_D1IF_IN_D2I_EN 44 +#define CLK_IA_IN_D2I_EN 45 +#define CLK_IB_IN_D2I_EN 46 +#define CLK_IC_IN_D2I_EN 47 +#define CLK_IA_IN_I_EN 48 +#define CLK_IB_IN_I_EN 49 +#define CLK_IC_IN_I_EN 50 +#define CLK_CAM_GATE_NUM (CLK_IC_IN_I_EN + 1) + +#define CLK_AHB_DISP 0 +#define CLK_DISPC0_DPI 1 +#define CLK_DISPC1_DPI 2 +#define CLK_DISP_NUM (CLK_DISPC1_DPI + 1) + +#define CLK_DISPC0_EB 0 +#define CLK_DISPC1_EB 1 +#define CLK_DISPC_MMU_EB 2 +#define CLK_GSP0_EB 3 +#define CLK_GSP1_EB 4 +#define CLK_GSP0_MMU_EB 5 +#define CLK_GSP1_MMU_EB 6 +#define CLK_DSI0_EB 7 +#define CLK_DSI1_EB 8 +#define CLK_DISP_CKG_EB 9 +#define CLK_DISP_GPU_EB 10 +#define CLK_GPU_MTX_EB 11 +#define CLK_GSP_MTX_EB 12 +#define CLK_TMC_MTX_EB 13 +#define CLK_DISPC_MTX_EB 14 +#define CLK_DPHY0_GATE 15 +#define CLK_DPHY1_GATE 16 +#define CLK_GSP0_A_GATE 17 +#define CLK_GSP1_A_GATE 18 +#define CLK_GSP0_F_GATE 19 +#define CLK_GSP1_F_GATE 20 +#define CLK_D_MTX_F_GATE 21 +#define CLK_D_MTX_A_GATE 22 +#define CLK_D_NOC_F_GATE 23 +#define CLK_D_NOC_A_GATE 24 +#define CLK_GSP_MTX_F_GATE 25 +#define CLK_GSP_MTX_A_GATE 26 +#define CLK_GSP_NOC_F_GATE 27 +#define CLK_GSP_NOC_A_GATE 28 +#define CLK_DISPM0IDLE_GATE 29 +#define CLK_GSPM0IDLE_GATE 30 +#define CLK_DISP_GATE_NUM (CLK_GSPM0IDLE_GATE + 1) + +#define CLK_SIM0_EB 0 +#define CLK_IIS0_EB 1 +#define CLK_IIS1_EB 2 +#define CLK_IIS2_EB 3 +#define CLK_IIS3_EB 4 +#define CLK_SPI0_EB 5 +#define CLK_SPI1_EB 6 +#define CLK_SPI2_EB 7 +#define CLK_I2C0_EB 8 +#define CLK_I2C1_EB 9 +#define CLK_I2C2_EB 10 +#define CLK_I2C3_EB 11 +#define CLK_I2C4_EB 12 +#define CLK_I2C5_EB 13 +#define CLK_UART0_EB 14 +#define CLK_UART1_EB 15 +#define CLK_UART2_EB 16 +#define CLK_UART3_EB 17 +#define CLK_UART4_EB 18 +#define CLK_AP_CKG_EB 19 +#define CLK_SPI3_EB 20 +#define CLK_APAPB_GATE_NUM (CLK_SPI3_EB + 1) + +#endif /* _DT_BINDINGS_CLK_SC9860_H_ */ diff --git a/include/dt-bindings/clock/tegra194-clock.h b/include/dt-bindings/clock/tegra194-clock.h new file mode 100644 index 000000000000..a2ff66342d69 --- /dev/null +++ b/include/dt-bindings/clock/tegra194-clock.h @@ -0,0 +1,321 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef __ABI_MACH_T194_CLOCK_H +#define __ABI_MACH_T194_CLOCK_H + +#define TEGRA194_CLK_ACTMON 1 +#define TEGRA194_CLK_ADSP 2 +#define TEGRA194_CLK_ADSPNEON 3 +#define TEGRA194_CLK_AHUB 4 +#define TEGRA194_CLK_APB2APE 5 +#define TEGRA194_CLK_APE 6 +#define TEGRA194_CLK_AUD_MCLK 7 +#define TEGRA194_CLK_AXI_CBB 8 +#define TEGRA194_CLK_CAN1 9 +#define TEGRA194_CLK_CAN1_HOST 10 +#define TEGRA194_CLK_CAN2 11 +#define TEGRA194_CLK_CAN2_HOST 12 +#define TEGRA194_CLK_CEC 13 +#define TEGRA194_CLK_CLK_M 14 +#define TEGRA194_CLK_DMIC1 15 +#define TEGRA194_CLK_DMIC2 16 +#define TEGRA194_CLK_DMIC3 17 +#define TEGRA194_CLK_DMIC4 18 +#define TEGRA194_CLK_DPAUX 19 +#define TEGRA194_CLK_DPAUX1 20 +#define TEGRA194_CLK_ACLK 21 +#define TEGRA194_CLK_MSS_ENCRYPT 22 +#define TEGRA194_CLK_EQOS_RX_INPUT 23 +#define TEGRA194_CLK_IQC2 24 +#define TEGRA194_CLK_AON_APB 25 +#define TEGRA194_CLK_AON_NIC 26 +#define TEGRA194_CLK_AON_CPU_NIC 27 +#define TEGRA194_CLK_PLLA1 28 +#define TEGRA194_CLK_DSPK1 29 +#define TEGRA194_CLK_DSPK2 30 +#define TEGRA194_CLK_EMC 31 +#define TEGRA194_CLK_EQOS_AXI 32 +#define TEGRA194_CLK_EQOS_PTP_REF 33 +#define TEGRA194_CLK_EQOS_RX 34 +#define TEGRA194_CLK_EQOS_TX 35 +#define TEGRA194_CLK_EXTPERIPH1 36 +#define TEGRA194_CLK_EXTPERIPH2 37 +#define TEGRA194_CLK_EXTPERIPH3 38 +#define TEGRA194_CLK_EXTPERIPH4 39 +#define TEGRA194_CLK_FUSE 40 +#define TEGRA194_CLK_GPCCLK 41 +#define TEGRA194_CLK_GPU_PWR 42 +#define TEGRA194_CLK_HDA 43 +#define TEGRA194_CLK_HDA2CODEC_2X 44 +#define TEGRA194_CLK_HDA2HDMICODEC 45 +#define TEGRA194_CLK_HOST1X 46 +#define TEGRA194_CLK_HSIC_TRK 47 +#define TEGRA194_CLK_I2C1 48 +#define TEGRA194_CLK_I2C2 49 +#define TEGRA194_CLK_I2C3 50 +#define TEGRA194_CLK_I2C4 51 +#define TEGRA194_CLK_I2C6 52 +#define TEGRA194_CLK_I2C7 53 +#define TEGRA194_CLK_I2C8 54 +#define TEGRA194_CLK_I2C9 55 +#define TEGRA194_CLK_I2S1 56 +#define TEGRA194_CLK_I2S1_SYNC_INPUT 57 +#define TEGRA194_CLK_I2S2 58 +#define TEGRA194_CLK_I2S2_SYNC_INPUT 59 +#define TEGRA194_CLK_I2S3 60 +#define TEGRA194_CLK_I2S3_SYNC_INPUT 61 +#define TEGRA194_CLK_I2S4 62 +#define TEGRA194_CLK_I2S4_SYNC_INPUT 63 +#define TEGRA194_CLK_I2S5 64 +#define TEGRA194_CLK_I2S5_SYNC_INPUT 65 +#define TEGRA194_CLK_I2S6 66 +#define TEGRA194_CLK_I2S6_SYNC_INPUT 67 +#define TEGRA194_CLK_IQC1 68 +#define TEGRA194_CLK_ISP 69 +#define TEGRA194_CLK_KFUSE 70 +#define TEGRA194_CLK_MAUD 71 +#define TEGRA194_CLK_MIPI_CAL 72 +#define TEGRA194_CLK_MPHY_CORE_PLL_FIXED 73 +#define TEGRA194_CLK_MPHY_L0_RX_ANA 74 +#define TEGRA194_CLK_MPHY_L0_RX_LS_BIT 75 +#define TEGRA194_CLK_MPHY_L0_RX_SYMB 76 +#define TEGRA194_CLK_MPHY_L0_TX_LS_3XBIT 77 +#define TEGRA194_CLK_MPHY_L0_TX_SYMB 78 +#define TEGRA194_CLK_MPHY_L1_RX_ANA 79 +#define TEGRA194_CLK_MPHY_TX_1MHZ_REF 80 +#define TEGRA194_CLK_NVCSI 81 +#define TEGRA194_CLK_NVCSILP 82 +#define TEGRA194_CLK_NVDEC 83 +#define TEGRA194_CLK_NVDISPLAYHUB 84 +#define TEGRA194_CLK_NVDISPLAY_DISP 85 +#define TEGRA194_CLK_NVDISPLAY_P0 86 +#define TEGRA194_CLK_NVDISPLAY_P1 87 +#define TEGRA194_CLK_NVDISPLAY_P2 88 +#define TEGRA194_CLK_NVENC 89 +#define TEGRA194_CLK_NVJPG 90 +#define TEGRA194_CLK_OSC 91 +#define TEGRA194_CLK_AON_TOUCH 92 +#define TEGRA194_CLK_PLLA 93 +#define TEGRA194_CLK_PLLAON 94 +#define TEGRA194_CLK_PLLD 95 +#define TEGRA194_CLK_PLLD2 96 +#define TEGRA194_CLK_PLLD3 97 +#define TEGRA194_CLK_PLLDP 98 +#define TEGRA194_CLK_PLLD4 99 +#define TEGRA194_CLK_PLLE 100 +#define TEGRA194_CLK_PLLP 101 +#define TEGRA194_CLK_PLLP_OUT0 102 +#define TEGRA194_CLK_UTMIPLL 103 +#define TEGRA194_CLK_PLLA_OUT0 104 +#define TEGRA194_CLK_PWM1 105 +#define TEGRA194_CLK_PWM2 106 +#define TEGRA194_CLK_PWM3 107 +#define TEGRA194_CLK_PWM4 108 +#define TEGRA194_CLK_PWM5 109 +#define TEGRA194_CLK_PWM6 110 +#define TEGRA194_CLK_PWM7 111 +#define TEGRA194_CLK_PWM8 112 +#define TEGRA194_CLK_RCE_CPU_NIC 113 +#define TEGRA194_CLK_RCE_NIC 114 +#define TEGRA194_CLK_SATA 115 +#define TEGRA194_CLK_SATA_OOB 116 +#define TEGRA194_CLK_AON_I2C_SLOW 117 +#define TEGRA194_CLK_SCE_CPU_NIC 118 +#define TEGRA194_CLK_SCE_NIC 119 +#define TEGRA194_CLK_SDMMC1 120 +#define TEGRA194_CLK_UPHY_PLL3 121 +#define TEGRA194_CLK_SDMMC3 122 +#define TEGRA194_CLK_SDMMC4 123 +#define TEGRA194_CLK_SE 124 +#define TEGRA194_CLK_SOR0_OUT 125 +#define TEGRA194_CLK_SOR0_REF 126 +#define TEGRA194_CLK_SOR0_PAD_CLKOUT 127 +#define TEGRA194_CLK_SOR1_OUT 128 +#define TEGRA194_CLK_SOR1_REF 129 +#define TEGRA194_CLK_SOR1_PAD_CLKOUT 130 +#define TEGRA194_CLK_SOR_SAFE 131 +#define TEGRA194_CLK_IQC1_IN 132 +#define TEGRA194_CLK_IQC2_IN 133 +#define TEGRA194_CLK_DMIC5 134 +#define TEGRA194_CLK_SPI1 135 +#define TEGRA194_CLK_SPI2 136 +#define TEGRA194_CLK_SPI3 137 +#define TEGRA194_CLK_I2C_SLOW 138 +#define TEGRA194_CLK_SYNC_DMIC1 139 +#define TEGRA194_CLK_SYNC_DMIC2 140 +#define TEGRA194_CLK_SYNC_DMIC3 141 +#define TEGRA194_CLK_SYNC_DMIC4 142 +#define TEGRA194_CLK_SYNC_DSPK1 143 +#define TEGRA194_CLK_SYNC_DSPK2 144 +#define TEGRA194_CLK_SYNC_I2S1 145 +#define TEGRA194_CLK_SYNC_I2S2 146 +#define TEGRA194_CLK_SYNC_I2S3 147 +#define TEGRA194_CLK_SYNC_I2S4 148 +#define TEGRA194_CLK_SYNC_I2S5 149 +#define TEGRA194_CLK_SYNC_I2S6 150 +#define TEGRA194_CLK_MPHY_FORCE_LS_MODE 151 +#define TEGRA194_CLK_TACH 152 +#define TEGRA194_CLK_TSEC 153 +#define TEGRA194_CLK_TSECB 154 +#define TEGRA194_CLK_UARTA 155 +#define TEGRA194_CLK_UARTB 156 +#define TEGRA194_CLK_UARTC 157 +#define TEGRA194_CLK_UARTD 158 +#define TEGRA194_CLK_UARTE 159 +#define TEGRA194_CLK_UARTF 160 +#define TEGRA194_CLK_UARTG 161 +#define TEGRA194_CLK_UART_FST_MIPI_CAL 162 +#define TEGRA194_CLK_UFSDEV_REF 163 +#define TEGRA194_CLK_UFSHC 164 +#define TEGRA194_CLK_USB2_TRK 165 +#define TEGRA194_CLK_VI 166 +#define TEGRA194_CLK_VIC 167 +#define TEGRA194_CLK_PVA0_AXI 168 +#define TEGRA194_CLK_PVA0_VPS0 169 +#define TEGRA194_CLK_PVA0_VPS1 170 +#define TEGRA194_CLK_PVA1_AXI 171 +#define TEGRA194_CLK_PVA1_VPS0 172 +#define TEGRA194_CLK_PVA1_VPS1 173 +#define TEGRA194_CLK_DLA0_FALCON 174 +#define TEGRA194_CLK_DLA0_CORE 175 +#define TEGRA194_CLK_DLA1_FALCON 176 +#define TEGRA194_CLK_DLA1_CORE 177 +#define TEGRA194_CLK_SOR2_OUT 178 +#define TEGRA194_CLK_SOR2_REF 179 +#define TEGRA194_CLK_SOR2_PAD_CLKOUT 180 +#define TEGRA194_CLK_SOR3_OUT 181 +#define TEGRA194_CLK_SOR3_REF 182 +#define TEGRA194_CLK_SOR3_PAD_CLKOUT 183 +#define TEGRA194_CLK_NVDISPLAY_P3 184 +#define TEGRA194_CLK_DPAUX2 185 +#define TEGRA194_CLK_DPAUX3 186 +#define TEGRA194_CLK_NVDEC1 187 +#define TEGRA194_CLK_NVENC1 188 +#define TEGRA194_CLK_SE_FREE 189 +#define TEGRA194_CLK_UARTH 190 +#define TEGRA194_CLK_FUSE_SERIAL 191 +#define TEGRA194_CLK_QSPI0 192 +#define TEGRA194_CLK_QSPI1 193 +#define TEGRA194_CLK_QSPI0_PM 194 +#define TEGRA194_CLK_QSPI1_PM 195 +#define TEGRA194_CLK_VI_CONST 196 +#define TEGRA194_CLK_NAFLL_BPMP 197 +#define TEGRA194_CLK_NAFLL_SCE 198 +#define TEGRA194_CLK_NAFLL_NVDEC 199 +#define TEGRA194_CLK_NAFLL_NVJPG 200 +#define TEGRA194_CLK_NAFLL_TSEC 201 +#define TEGRA194_CLK_NAFLL_TSECB 202 +#define TEGRA194_CLK_NAFLL_VI 203 +#define TEGRA194_CLK_NAFLL_SE 204 +#define TEGRA194_CLK_NAFLL_NVENC 205 +#define TEGRA194_CLK_NAFLL_ISP 206 +#define TEGRA194_CLK_NAFLL_VIC 207 +#define TEGRA194_CLK_NAFLL_NVDISPLAYHUB 208 +#define TEGRA194_CLK_NAFLL_AXICBB 209 +#define TEGRA194_CLK_NAFLL_DLA 210 +#define TEGRA194_CLK_NAFLL_PVA_CORE 211 +#define TEGRA194_CLK_NAFLL_PVA_VPS 212 +#define TEGRA194_CLK_NAFLL_CVNAS 213 +#define TEGRA194_CLK_NAFLL_RCE 214 +#define TEGRA194_CLK_NAFLL_NVENC1 215 +#define TEGRA194_CLK_NAFLL_DLA_FALCON 216 +#define TEGRA194_CLK_NAFLL_NVDEC1 217 +#define TEGRA194_CLK_NAFLL_GPU 218 +#define TEGRA194_CLK_SDMMC_LEGACY_TM 219 +#define TEGRA194_CLK_PEX0_CORE_0 220 +#define TEGRA194_CLK_PEX0_CORE_1 221 +#define TEGRA194_CLK_PEX0_CORE_2 222 +#define TEGRA194_CLK_PEX0_CORE_3 223 +#define TEGRA194_CLK_PEX0_CORE_4 224 +#define TEGRA194_CLK_PEX1_CORE_5 225 +#define TEGRA194_CLK_PEX_REF1 226 +#define TEGRA194_CLK_PEX_REF2 227 +#define TEGRA194_CLK_CSI_A 229 +#define TEGRA194_CLK_CSI_B 230 +#define TEGRA194_CLK_CSI_C 231 +#define TEGRA194_CLK_CSI_D 232 +#define TEGRA194_CLK_CSI_E 233 +#define TEGRA194_CLK_CSI_F 234 +#define TEGRA194_CLK_CSI_G 235 +#define TEGRA194_CLK_CSI_H 236 +#define TEGRA194_CLK_PLLC4 237 +#define TEGRA194_CLK_PLLC4_OUT 238 +#define TEGRA194_CLK_PLLC4_OUT1 239 +#define TEGRA194_CLK_PLLC4_OUT2 240 +#define TEGRA194_CLK_PLLC4_MUXED 241 +#define TEGRA194_CLK_PLLC4_VCO_DIV2 242 +#define TEGRA194_CLK_CSI_A_PAD 244 +#define TEGRA194_CLK_CSI_B_PAD 245 +#define TEGRA194_CLK_CSI_C_PAD 246 +#define TEGRA194_CLK_CSI_D_PAD 247 +#define TEGRA194_CLK_CSI_E_PAD 248 +#define TEGRA194_CLK_CSI_F_PAD 249 +#define TEGRA194_CLK_CSI_G_PAD 250 +#define TEGRA194_CLK_CSI_H_PAD 251 +#define TEGRA194_CLK_PEX_SATA_USB_RX_BYP 254 +#define TEGRA194_CLK_PEX_USB_PAD_PLL0_MGMT 255 +#define TEGRA194_CLK_PEX_USB_PAD_PLL1_MGMT 256 +#define TEGRA194_CLK_PEX_USB_PAD_PLL2_MGMT 257 +#define TEGRA194_CLK_PEX_USB_PAD_PLL3_MGMT 258 +#define TEGRA194_CLK_XUSB_CORE_DEV 265 +#define TEGRA194_CLK_XUSB_CORE_MUX 266 +#define TEGRA194_CLK_XUSB_CORE_HOST 267 +#define TEGRA194_CLK_XUSB_CORE_SS 268 +#define TEGRA194_CLK_XUSB_FALCON 269 +#define TEGRA194_CLK_XUSB_FALCON_HOST 270 +#define TEGRA194_CLK_XUSB_FALCON_SS 271 +#define TEGRA194_CLK_XUSB_FS 272 +#define TEGRA194_CLK_XUSB_FS_HOST 273 +#define TEGRA194_CLK_XUSB_FS_DEV 274 +#define TEGRA194_CLK_XUSB_SS 275 +#define TEGRA194_CLK_XUSB_SS_DEV 276 +#define TEGRA194_CLK_XUSB_SS_SUPERSPEED 277 +#define TEGRA194_CLK_PLLDISPHUB 278 +#define TEGRA194_CLK_PLLDISPHUB_DIV 279 +#define TEGRA194_CLK_NAFLL_CLUSTER0 280 +#define TEGRA194_CLK_NAFLL_CLUSTER1 281 +#define TEGRA194_CLK_NAFLL_CLUSTER2 282 +#define TEGRA194_CLK_NAFLL_CLUSTER3 283 +#define TEGRA194_CLK_CAN1_CORE 284 +#define TEGRA194_CLK_CAN2_CORE 285 +#define TEGRA194_CLK_PLLA1_OUT1 286 +#define TEGRA194_CLK_PLLREFE_VCOOUT 288 +#define TEGRA194_CLK_CLK_32K 289 +#define TEGRA194_CLK_SPDIFIN_SYNC_INPUT 290 +#define TEGRA194_CLK_UTMIPLL_CLKOUT48 291 +#define TEGRA194_CLK_UTMIPLL_CLKOUT480 292 +#define TEGRA194_CLK_CVNAS 293 +#define TEGRA194_CLK_PLLNVCSI 294 +#define TEGRA194_CLK_PVA0_CPU_AXI 295 +#define TEGRA194_CLK_PVA1_CPU_AXI 296 +#define TEGRA194_CLK_PVA0_VPS 297 +#define TEGRA194_CLK_PVA1_VPS 298 +#define TEGRA194_CLK_DLA0_FALCON_MUX 299 +#define TEGRA194_CLK_DLA1_FALCON_MUX 300 +#define TEGRA194_CLK_DLA0_CORE_MUX 301 +#define TEGRA194_CLK_DLA1_CORE_MUX 302 +#define TEGRA194_CLK_UTMIPLL_HPS 304 +#define TEGRA194_CLK_I2C5 305 +#define TEGRA194_CLK_I2C10 306 +#define TEGRA194_CLK_BPMP_CPU_NIC 307 +#define TEGRA194_CLK_BPMP_APB 308 +#define TEGRA194_CLK_TSC 309 +#define TEGRA194_CLK_EMCSA 310 +#define TEGRA194_CLK_EMCSB 311 +#define TEGRA194_CLK_EMCSC 312 +#define TEGRA194_CLK_EMCSD 313 +#define TEGRA194_CLK_PLLC 314 +#define TEGRA194_CLK_PLLC2 315 +#define TEGRA194_CLK_PLLC3 316 +#define TEGRA194_CLK_TSC_REF 317 +#define TEGRA194_CLK_FUSE_BURN 318 +#define TEGRA194_CLK_PEX0_CORE_0M 319 +#define TEGRA194_CLK_PEX0_CORE_1M 320 +#define TEGRA194_CLK_PEX0_CORE_2M 321 +#define TEGRA194_CLK_PEX0_CORE_3M 322 +#define TEGRA194_CLK_PEX0_CORE_4M 323 +#define TEGRA194_CLK_PEX1_CORE_5M 324 +#define TEGRA194_CLK_PLLE_HPS 326 + +#endif diff --git a/include/dt-bindings/gpio/aspeed-gpio.h b/include/dt-bindings/gpio/aspeed-gpio.h new file mode 100644 index 000000000000..56fc4889b2c4 --- /dev/null +++ b/include/dt-bindings/gpio/aspeed-gpio.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * This header provides constants for binding aspeed,*-gpio. + * + * The first cell in Aspeed's GPIO specifier is the GPIO ID. The macros below + * provide names for this. + * + * The second cell contains standard flag values specified in gpio.h. + */ + +#ifndef _DT_BINDINGS_GPIO_ASPEED_GPIO_H +#define _DT_BINDINGS_GPIO_ASPEED_GPIO_H + +#include <dt-bindings/gpio/gpio.h> + +#define ASPEED_GPIO_PORT_A 0 +#define ASPEED_GPIO_PORT_B 1 +#define ASPEED_GPIO_PORT_C 2 +#define ASPEED_GPIO_PORT_D 3 +#define ASPEED_GPIO_PORT_E 4 +#define ASPEED_GPIO_PORT_F 5 +#define ASPEED_GPIO_PORT_G 6 +#define ASPEED_GPIO_PORT_H 7 +#define ASPEED_GPIO_PORT_I 8 +#define ASPEED_GPIO_PORT_J 9 +#define ASPEED_GPIO_PORT_K 10 +#define ASPEED_GPIO_PORT_L 11 +#define ASPEED_GPIO_PORT_M 12 +#define ASPEED_GPIO_PORT_N 13 +#define ASPEED_GPIO_PORT_O 14 +#define ASPEED_GPIO_PORT_P 15 +#define ASPEED_GPIO_PORT_Q 16 +#define ASPEED_GPIO_PORT_R 17 +#define ASPEED_GPIO_PORT_S 18 +#define ASPEED_GPIO_PORT_T 19 +#define ASPEED_GPIO_PORT_U 20 +#define ASPEED_GPIO_PORT_V 21 +#define ASPEED_GPIO_PORT_W 22 +#define ASPEED_GPIO_PORT_X 23 +#define ASPEED_GPIO_PORT_Y 24 +#define ASPEED_GPIO_PORT_Z 25 +#define ASPEED_GPIO_PORT_AA 26 +#define ASPEED_GPIO_PORT_AB 27 +#define ASPEED_GPIO_PORT_AC 28 + +#define ASPEED_GPIO(port, offset) \ + ((ASPEED_GPIO_PORT_##port * 8) + offset) + +#endif diff --git a/include/dt-bindings/gpio/gpio.h b/include/dt-bindings/gpio/gpio.h index dd549ff04295..2cc10ae4bbb7 100644 --- a/include/dt-bindings/gpio/gpio.h +++ b/include/dt-bindings/gpio/gpio.h @@ -29,8 +29,8 @@ #define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) #define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) -/* Bit 3 express GPIO suspend/resume persistence */ -#define GPIO_SLEEP_MAINTAIN_VALUE 0 -#define GPIO_SLEEP_MAY_LOSE_VALUE 8 +/* Bit 3 express GPIO suspend/resume and reset persistence */ +#define GPIO_PERSISTENT 0 +#define GPIO_TRANSITORY 8 #endif diff --git a/include/dt-bindings/gpio/meson-axg-gpio.h b/include/dt-bindings/gpio/meson-axg-gpio.h new file mode 100644 index 000000000000..25bb1fffa97a --- /dev/null +++ b/include/dt-bindings/gpio/meson-axg-gpio.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2017 Amlogic, Inc. All rights reserved. + * Author: Xingyu Chen <xingyu.chen@amlogic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_MESON_AXG_GPIO_H +#define _DT_BINDINGS_MESON_AXG_GPIO_H + +/* First GPIO chip */ +#define GPIOAO_0 0 +#define GPIOAO_1 1 +#define GPIOAO_2 2 +#define GPIOAO_3 3 +#define GPIOAO_4 4 +#define GPIOAO_5 5 +#define GPIOAO_6 6 +#define GPIOAO_7 7 +#define GPIOAO_8 8 +#define GPIOAO_9 9 +#define GPIOAO_10 10 +#define GPIOAO_11 11 +#define GPIOAO_12 12 +#define GPIOAO_13 13 +#define GPIO_TEST_N 14 + +/* Second GPIO chip */ +#define GPIOZ_0 0 +#define GPIOZ_1 1 +#define GPIOZ_2 2 +#define GPIOZ_3 3 +#define GPIOZ_4 4 +#define GPIOZ_5 5 +#define GPIOZ_6 6 +#define GPIOZ_7 7 +#define GPIOZ_8 8 +#define GPIOZ_9 9 +#define GPIOZ_10 10 +#define BOOT_0 11 +#define BOOT_1 12 +#define BOOT_2 13 +#define BOOT_3 14 +#define BOOT_4 15 +#define BOOT_5 16 +#define BOOT_6 17 +#define BOOT_7 18 +#define BOOT_8 19 +#define BOOT_9 20 +#define BOOT_10 21 +#define BOOT_11 22 +#define BOOT_12 23 +#define BOOT_13 24 +#define BOOT_14 25 +#define GPIOA_0 26 +#define GPIOA_1 27 +#define GPIOA_2 28 +#define GPIOA_3 29 +#define GPIOA_4 30 +#define GPIOA_5 31 +#define GPIOA_6 32 +#define GPIOA_7 33 +#define GPIOA_8 34 +#define GPIOA_9 35 +#define GPIOA_10 36 +#define GPIOA_11 37 +#define GPIOA_12 38 +#define GPIOA_13 39 +#define GPIOA_14 40 +#define GPIOA_15 41 +#define GPIOA_16 42 +#define GPIOA_17 43 +#define GPIOA_18 44 +#define GPIOA_19 45 +#define GPIOA_20 46 +#define GPIOX_0 47 +#define GPIOX_1 48 +#define GPIOX_2 49 +#define GPIOX_3 50 +#define GPIOX_4 51 +#define GPIOX_5 52 +#define GPIOX_6 53 +#define GPIOX_7 54 +#define GPIOX_8 55 +#define GPIOX_9 56 +#define GPIOX_10 57 +#define GPIOX_11 58 +#define GPIOX_12 59 +#define GPIOX_13 60 +#define GPIOX_14 61 +#define GPIOX_15 62 +#define GPIOX_16 63 +#define GPIOX_17 64 +#define GPIOX_18 65 +#define GPIOX_19 66 +#define GPIOX_20 67 +#define GPIOX_21 68 +#define GPIOX_22 69 +#define GPIOY_0 70 +#define GPIOY_1 71 +#define GPIOY_2 72 +#define GPIOY_3 73 +#define GPIOY_4 74 +#define GPIOY_5 75 +#define GPIOY_6 76 +#define GPIOY_7 77 +#define GPIOY_8 78 +#define GPIOY_9 79 +#define GPIOY_10 80 +#define GPIOY_11 81 +#define GPIOY_12 82 +#define GPIOY_13 83 +#define GPIOY_14 84 +#define GPIOY_15 85 + +#endif /* _DT_BINDINGS_MESON_AXG_GPIO_H */ diff --git a/include/dt-bindings/gpio/meson8b-gpio.h b/include/dt-bindings/gpio/meson8b-gpio.h index c38cb20d7182..bf0d76fa0e7b 100644 --- a/include/dt-bindings/gpio/meson8b-gpio.h +++ b/include/dt-bindings/gpio/meson8b-gpio.h @@ -15,18 +15,113 @@ #ifndef _DT_BINDINGS_MESON8B_GPIO_H #define _DT_BINDINGS_MESON8B_GPIO_H -#include <dt-bindings/gpio/meson8-gpio.h> - -/* GPIO Bank DIF */ -#define DIF_0_P 120 -#define DIF_0_N 121 -#define DIF_1_P 122 -#define DIF_1_N 123 -#define DIF_2_P 124 -#define DIF_2_N 125 -#define DIF_3_P 126 -#define DIF_3_N 127 -#define DIF_4_P 128 -#define DIF_4_N 129 +/* EE (CBUS) GPIO chip */ +#define GPIOX_0 0 +#define GPIOX_1 1 +#define GPIOX_2 2 +#define GPIOX_3 3 +#define GPIOX_4 4 +#define GPIOX_5 5 +#define GPIOX_6 6 +#define GPIOX_7 7 +#define GPIOX_8 8 +#define GPIOX_9 9 +#define GPIOX_10 10 +#define GPIOX_11 11 +#define GPIOX_16 12 +#define GPIOX_17 13 +#define GPIOX_18 14 +#define GPIOX_19 15 +#define GPIOX_20 16 +#define GPIOX_21 17 + +#define GPIOY_0 18 +#define GPIOY_1 19 +#define GPIOY_3 20 +#define GPIOY_6 21 +#define GPIOY_7 22 +#define GPIOY_8 23 +#define GPIOY_9 24 +#define GPIOY_10 25 +#define GPIOY_11 26 +#define GPIOY_12 27 +#define GPIOY_13 28 +#define GPIOY_14 29 + +#define GPIODV_9 30 +#define GPIODV_24 31 +#define GPIODV_25 32 +#define GPIODV_26 33 +#define GPIODV_27 34 +#define GPIODV_28 35 +#define GPIODV_29 36 + +#define GPIOH_0 37 +#define GPIOH_1 38 +#define GPIOH_2 39 +#define GPIOH_3 40 +#define GPIOH_4 41 +#define GPIOH_5 42 +#define GPIOH_6 43 +#define GPIOH_7 44 +#define GPIOH_8 45 +#define GPIOH_9 46 + +#define CARD_0 47 +#define CARD_1 48 +#define CARD_2 49 +#define CARD_3 50 +#define CARD_4 51 +#define CARD_5 52 +#define CARD_6 53 + +#define BOOT_0 54 +#define BOOT_1 55 +#define BOOT_2 56 +#define BOOT_3 57 +#define BOOT_4 58 +#define BOOT_5 59 +#define BOOT_6 60 +#define BOOT_7 61 +#define BOOT_8 62 +#define BOOT_9 63 +#define BOOT_10 64 +#define BOOT_11 65 +#define BOOT_12 66 +#define BOOT_13 67 +#define BOOT_14 68 +#define BOOT_15 69 +#define BOOT_16 70 +#define BOOT_17 71 +#define BOOT_18 72 + +#define DIF_0_P 73 +#define DIF_0_N 74 +#define DIF_1_P 75 +#define DIF_1_N 76 +#define DIF_2_P 77 +#define DIF_2_N 78 +#define DIF_3_P 79 +#define DIF_3_N 80 +#define DIF_4_P 81 +#define DIF_4_N 82 + +/* AO GPIO chip */ +#define GPIOAO_0 0 +#define GPIOAO_1 1 +#define GPIOAO_2 2 +#define GPIOAO_3 3 +#define GPIOAO_4 4 +#define GPIOAO_5 5 +#define GPIOAO_6 6 +#define GPIOAO_7 7 +#define GPIOAO_8 8 +#define GPIOAO_9 9 +#define GPIOAO_10 10 +#define GPIOAO_11 11 +#define GPIOAO_12 12 +#define GPIOAO_13 13 +#define GPIO_BSD_EN 14 +#define GPIO_TEST_N 15 #endif /* _DT_BINDINGS_MESON8B_GPIO_H */ diff --git a/include/dt-bindings/gpio/tegra194-gpio.h b/include/dt-bindings/gpio/tegra194-gpio.h new file mode 100644 index 000000000000..ede860225f6b --- /dev/null +++ b/include/dt-bindings/gpio/tegra194-gpio.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ + +/* + * This header provides constants for binding nvidia,tegra194-gpio*. + * + * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below + * provide names for this. + * + * The second cell contains standard flag values specified in gpio.h. + */ + +#ifndef _DT_BINDINGS_GPIO_TEGRA194_GPIO_H +#define _DT_BINDINGS_GPIO_TEGRA194_GPIO_H + +#include <dt-bindings/gpio/gpio.h> + +/* GPIOs implemented by main GPIO controller */ +#define TEGRA194_MAIN_GPIO_PORT_A 0 +#define TEGRA194_MAIN_GPIO_PORT_B 1 +#define TEGRA194_MAIN_GPIO_PORT_C 2 +#define TEGRA194_MAIN_GPIO_PORT_D 3 +#define TEGRA194_MAIN_GPIO_PORT_E 4 +#define TEGRA194_MAIN_GPIO_PORT_F 5 +#define TEGRA194_MAIN_GPIO_PORT_G 6 +#define TEGRA194_MAIN_GPIO_PORT_H 7 +#define TEGRA194_MAIN_GPIO_PORT_I 8 +#define TEGRA194_MAIN_GPIO_PORT_J 9 +#define TEGRA194_MAIN_GPIO_PORT_K 10 +#define TEGRA194_MAIN_GPIO_PORT_L 11 +#define TEGRA194_MAIN_GPIO_PORT_M 12 +#define TEGRA194_MAIN_GPIO_PORT_N 13 +#define TEGRA194_MAIN_GPIO_PORT_O 14 +#define TEGRA194_MAIN_GPIO_PORT_P 15 +#define TEGRA194_MAIN_GPIO_PORT_Q 16 +#define TEGRA194_MAIN_GPIO_PORT_R 17 +#define TEGRA194_MAIN_GPIO_PORT_S 18 +#define TEGRA194_MAIN_GPIO_PORT_T 19 +#define TEGRA194_MAIN_GPIO_PORT_U 20 +#define TEGRA194_MAIN_GPIO_PORT_V 21 +#define TEGRA194_MAIN_GPIO_PORT_W 22 +#define TEGRA194_MAIN_GPIO_PORT_X 23 +#define TEGRA194_MAIN_GPIO_PORT_Y 24 +#define TEGRA194_MAIN_GPIO_PORT_Z 25 +#define TEGRA194_MAIN_GPIO_PORT_FF 26 +#define TEGRA194_MAIN_GPIO_PORT_GG 27 + +#define TEGRA194_MAIN_GPIO(port, offset) \ + ((TEGRA194_MAIN_GPIO_PORT_##port * 8) + offset) + +/* GPIOs implemented by AON GPIO controller */ +#define TEGRA194_AON_GPIO_PORT_AA 0 +#define TEGRA194_AON_GPIO_PORT_BB 1 +#define TEGRA194_AON_GPIO_PORT_CC 2 +#define TEGRA194_AON_GPIO_PORT_DD 3 +#define TEGRA194_AON_GPIO_PORT_EE 4 + +#define TEGRA194_AON_GPIO(port, offset) \ + ((TEGRA194_AON_GPIO_PORT_##port * 8) + offset) + +#endif diff --git a/include/dt-bindings/input/gpio-keys.h b/include/dt-bindings/input/gpio-keys.h new file mode 100644 index 000000000000..8962df79e753 --- /dev/null +++ b/include/dt-bindings/input/gpio-keys.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for gpio keys bindings. + */ + +#ifndef _DT_BINDINGS_GPIO_KEYS_H +#define _DT_BINDINGS_GPIO_KEYS_H + +#define EV_ACT_ANY 0x00 /* asserted or deasserted */ +#define EV_ACT_ASSERTED 0x01 /* asserted */ +#define EV_ACT_DEASSERTED 0x02 /* deasserted */ + +#endif /* _DT_BINDINGS_GPIO_KEYS_H */ diff --git a/include/dt-bindings/media/tda1997x.h b/include/dt-bindings/media/tda1997x.h new file mode 100644 index 000000000000..bd9fbd718ec9 --- /dev/null +++ b/include/dt-bindings/media/tda1997x.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017 Gateworks Corporation + */ +#ifndef _DT_BINDINGS_MEDIA_TDA1997X_H +#define _DT_BINDINGS_MEDIA_TDA1997X_H + +/* TDA19973 36bit Video Port control registers */ +#define TDA1997X_VP36_35_32 0 +#define TDA1997X_VP36_31_28 1 +#define TDA1997X_VP36_27_24 2 +#define TDA1997X_VP36_23_20 3 +#define TDA1997X_VP36_19_16 4 +#define TDA1997X_VP36_15_12 5 +#define TDA1997X_VP36_11_08 6 +#define TDA1997X_VP36_07_04 7 +#define TDA1997X_VP36_03_00 8 + +/* TDA19971 24bit Video Port control registers */ +#define TDA1997X_VP24_V23_20 0 +#define TDA1997X_VP24_V19_16 1 +#define TDA1997X_VP24_V15_12 3 +#define TDA1997X_VP24_V11_08 4 +#define TDA1997X_VP24_V07_04 6 +#define TDA1997X_VP24_V03_00 7 + +/* Pin groups */ +#define TDA1997X_VP_OUT_EN 0x80 /* enable output group */ +#define TDA1997X_VP_HIZ 0x40 /* hi-Z output group when not used */ +#define TDA1997X_VP_SWP 0x10 /* pin-swap output group */ +#define TDA1997X_R_CR_CBCR_3_0 (0 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_R_CR_CBCR_7_4 (1 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_R_CR_CBCR_11_8 (2 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_B_CB_3_0 (3 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_B_CB_7_4 (4 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_B_CB_11_8 (5 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_G_Y_3_0 (6 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_G_Y_7_4 (7 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_G_Y_11_8 (8 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +/* pinswapped groups */ +#define TDA1997X_R_CR_CBCR_3_0_S (TDA1997X_R_CR_CBCR_3_0 | TDA1997X_VP_SWAP) +#define TDA1997X_R_CR_CBCR_7_4_S (TDA1997X_R_CR_CBCR_7_4 | TDA1997X_VP_SWAP) +#define TDA1997X_R_CR_CBCR_11_8_S (TDA1997X_R_CR_CBCR_11_8 | TDA1997X_VP_SWAP) +#define TDA1997X_B_CB_3_0_S (TDA1997X_B_CB_3_0 | TDA1997X_VP_SWAP) +#define TDA1997X_B_CB_7_4_S (TDA1997X_B_CB_7_4 | TDA1997X_VP_SWAP) +#define TDA1997X_B_CB_11_8_S (TDA1997X_B_CB_11_8 | TDA1997X_VP_SWAP) +#define TDA1997X_G_Y_3_0_S (TDA1997X_G_Y_3_0 | TDA1997X_VP_SWAP) +#define TDA1997X_G_Y_7_4_S (TDA1997X_G_Y_7_4 | TDA1997X_VP_SWAP) +#define TDA1997X_G_Y_11_8_S (TDA1997X_G_Y_11_8 | TDA1997X_VP_SWAP) + +/* Audio bus DAI format */ +#define TDA1997X_I2S16 1 /* I2S 16bit */ +#define TDA1997X_I2S32 2 /* I2S 32bit */ +#define TDA1997X_SPDIF 3 /* SPDIF */ +#define TDA1997X_OBA 4 /* One Bit Audio */ +#define TDA1997X_DST 5 /* Direct Stream Transfer */ +#define TDA1997X_I2S16_HBR 6 /* HBR straight in I2S 16bit mode */ +#define TDA1997X_I2S16_HBR_DEMUX 7 /* HBR demux in I2S 16bit mode */ +#define TDA1997X_I2S32_HBR_DEMUX 8 /* HBR demux in I2S 32bit mode */ +#define TDA1997X_SPDIF_HBR_DEMUX 9 /* HBR demux in SPDIF mode */ + +/* Audio bus channel layout */ +#define TDA1997X_LAYOUT0 0 /* 2-channel */ +#define TDA1997X_LAYOUT1 1 /* 8-channel */ + +/* Audio bus clock */ +#define TDA1997X_ACLK_16FS 0 +#define TDA1997X_ACLK_32FS 1 +#define TDA1997X_ACLK_64FS 2 +#define TDA1997X_ACLK_128FS 3 +#define TDA1997X_ACLK_256FS 4 +#define TDA1997X_ACLK_512FS 5 + +#endif /* _DT_BINDINGS_MEDIA_TDA1997X_H */ diff --git a/include/dt-bindings/memory/tegra186-mc.h b/include/dt-bindings/memory/tegra186-mc.h new file mode 100644 index 000000000000..64813536aec9 --- /dev/null +++ b/include/dt-bindings/memory/tegra186-mc.h @@ -0,0 +1,111 @@ +#ifndef DT_BINDINGS_MEMORY_TEGRA186_MC_H +#define DT_BINDINGS_MEMORY_TEGRA186_MC_H + +/* special clients */ +#define TEGRA186_SID_INVALID 0x00 +#define TEGRA186_SID_PASSTHROUGH 0x7f + +/* host1x clients */ +#define TEGRA186_SID_HOST1X 0x01 +#define TEGRA186_SID_CSI 0x02 +#define TEGRA186_SID_VIC 0x03 +#define TEGRA186_SID_VI 0x04 +#define TEGRA186_SID_ISP 0x05 +#define TEGRA186_SID_NVDEC 0x06 +#define TEGRA186_SID_NVENC 0x07 +#define TEGRA186_SID_NVJPG 0x08 +#define TEGRA186_SID_NVDISPLAY 0x09 +#define TEGRA186_SID_TSEC 0x0a +#define TEGRA186_SID_TSECB 0x0b +#define TEGRA186_SID_SE 0x0c +#define TEGRA186_SID_SE1 0x0d +#define TEGRA186_SID_SE2 0x0e +#define TEGRA186_SID_SE3 0x0f + +/* GPU clients */ +#define TEGRA186_SID_GPU 0x10 + +/* other SoC clients */ +#define TEGRA186_SID_AFI 0x11 +#define TEGRA186_SID_HDA 0x12 +#define TEGRA186_SID_ETR 0x13 +#define TEGRA186_SID_EQOS 0x14 +#define TEGRA186_SID_UFSHC 0x15 +#define TEGRA186_SID_AON 0x16 +#define TEGRA186_SID_SDMMC4 0x17 +#define TEGRA186_SID_SDMMC3 0x18 +#define TEGRA186_SID_SDMMC2 0x19 +#define TEGRA186_SID_SDMMC1 0x1a +#define TEGRA186_SID_XUSB_HOST 0x1b +#define TEGRA186_SID_XUSB_DEV 0x1c +#define TEGRA186_SID_SATA 0x1d +#define TEGRA186_SID_APE 0x1e +#define TEGRA186_SID_SCE 0x1f + +/* GPC DMA clients */ +#define TEGRA186_SID_GPCDMA_0 0x20 +#define TEGRA186_SID_GPCDMA_1 0x21 +#define TEGRA186_SID_GPCDMA_2 0x22 +#define TEGRA186_SID_GPCDMA_3 0x23 +#define TEGRA186_SID_GPCDMA_4 0x24 +#define TEGRA186_SID_GPCDMA_5 0x25 +#define TEGRA186_SID_GPCDMA_6 0x26 +#define TEGRA186_SID_GPCDMA_7 0x27 + +/* APE DMA clients */ +#define TEGRA186_SID_APE_1 0x28 +#define TEGRA186_SID_APE_2 0x29 + +/* camera RTCPU */ +#define TEGRA186_SID_RCE 0x2a + +/* camera RTCPU on host1x address space */ +#define TEGRA186_SID_RCE_1X 0x2b + +/* APE DMA clients */ +#define TEGRA186_SID_APE_3 0x2c + +/* camera RTCPU running on APE */ +#define TEGRA186_SID_APE_CAM 0x2d +#define TEGRA186_SID_APE_CAM_1X 0x2e + +/* + * The BPMP has its SID value hardcoded in the firmware. Changing it requires + * considerable effort. + */ +#define TEGRA186_SID_BPMP 0x32 + +/* for SMMU tests */ +#define TEGRA186_SID_SMMU_TEST 0x33 + +/* host1x virtualization channels */ +#define TEGRA186_SID_HOST1X_CTX0 0x38 +#define TEGRA186_SID_HOST1X_CTX1 0x39 +#define TEGRA186_SID_HOST1X_CTX2 0x3a +#define TEGRA186_SID_HOST1X_CTX3 0x3b +#define TEGRA186_SID_HOST1X_CTX4 0x3c +#define TEGRA186_SID_HOST1X_CTX5 0x3d +#define TEGRA186_SID_HOST1X_CTX6 0x3e +#define TEGRA186_SID_HOST1X_CTX7 0x3f + +/* host1x command buffers */ +#define TEGRA186_SID_HOST1X_VM0 0x40 +#define TEGRA186_SID_HOST1X_VM1 0x41 +#define TEGRA186_SID_HOST1X_VM2 0x42 +#define TEGRA186_SID_HOST1X_VM3 0x43 +#define TEGRA186_SID_HOST1X_VM4 0x44 +#define TEGRA186_SID_HOST1X_VM5 0x45 +#define TEGRA186_SID_HOST1X_VM6 0x46 +#define TEGRA186_SID_HOST1X_VM7 0x47 + +/* SE data buffers */ +#define TEGRA186_SID_SE_VM0 0x48 +#define TEGRA186_SID_SE_VM1 0x49 +#define TEGRA186_SID_SE_VM2 0x4a +#define TEGRA186_SID_SE_VM3 0x4b +#define TEGRA186_SID_SE_VM4 0x4c +#define TEGRA186_SID_SE_VM5 0x4d +#define TEGRA186_SID_SE_VM6 0x4e +#define TEGRA186_SID_SE_VM7 0x4f + +#endif diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h index 8b7b7197ffd7..a90f3613c584 100644 --- a/include/dt-bindings/mfd/stm32f7-rcc.h +++ b/include/dt-bindings/mfd/stm32f7-rcc.h @@ -91,6 +91,7 @@ #define STM32F7_RCC_APB2_TIM8 1 #define STM32F7_RCC_APB2_USART1 4 #define STM32F7_RCC_APB2_USART6 5 +#define STM32F7_RCC_APB2_SDMMC2 7 #define STM32F7_RCC_APB2_ADC1 8 #define STM32F7_RCC_APB2_ADC2 9 #define STM32F7_RCC_APB2_ADC3 10 diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h index 172744a72eb7..7b1656427cbe 100644 --- a/include/dt-bindings/net/ti-dp83867.h +++ b/include/dt-bindings/net/ti-dp83867.h @@ -42,4 +42,18 @@ #define DP83867_RGMIIDCTL_3_75_NS 0xe #define DP83867_RGMIIDCTL_4_00_NS 0xf +/* IO_MUX_CFG - Clock output selection */ +#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 +#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 +#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 +#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 +#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 +#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 +#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 +#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 +#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 +#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 +#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA +#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB +#define DP83867_CLK_O_SEL_REF_CLK 0xC #endif diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h index a69e310789c5..6ce4a32f77d4 100644 --- a/include/dt-bindings/pinctrl/am43xx.h +++ b/include/dt-bindings/pinctrl/am43xx.h @@ -25,7 +25,8 @@ #define DS0_FORCE_OFF_MODE (1 << 24) #define DS0_INPUT (1 << 25) #define DS0_FORCE_OUT_HIGH (1 << 26) -#define DS0_PULL_UP_DOWN_EN (1 << 27) +#define DS0_PULL_UP_DOWN_EN (0 << 27) +#define DS0_PULL_UP_DOWN_DIS (1 << 27) #define DS0_PULL_UP_SEL (1 << 28) #define WAKEUP_ENABLE (1 << 29) diff --git a/include/dt-bindings/pinctrl/mt7623-pinfunc.h b/include/dt-bindings/pinctrl/mt7623-pinfunc.h index 2d6a7b1d7be2..4878a67a844c 100644 --- a/include/dt-bindings/pinctrl/mt7623-pinfunc.h +++ b/include/dt-bindings/pinctrl/mt7623-pinfunc.h @@ -251,6 +251,12 @@ #define MT7623_PIN_76_SCL0_FUNC_GPIO76 (MTK_PIN_NO(76) | 0) #define MT7623_PIN_76_SCL0_FUNC_SCL0 (MTK_PIN_NO(76) | 1) +#define MT7623_PIN_77_SDA2_FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define MT7623_PIN_77_SDA2_FUNC_SDA2 (MTK_PIN_NO(77) | 1) + +#define MT7623_PIN_78_SCL2_FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define MT7623_PIN_78_SCL2_FUNC_SCL2 (MTK_PIN_NO(78) | 1) + #define MT7623_PIN_79_URXD0_FUNC_GPIO79 (MTK_PIN_NO(79) | 0) #define MT7623_PIN_79_URXD0_FUNC_URXD0 (MTK_PIN_NO(79) | 1) #define MT7623_PIN_79_URXD0_FUNC_UTXD0 (MTK_PIN_NO(79) | 2) @@ -291,6 +297,24 @@ #define MT7623_PIN_100_MIPI_TDP0_FUNC_GPIO100 (MTK_PIN_NO(100) | 0) #define MT7623_PIN_100_MIPI_TDP0_FUNC_TDP0 (MTK_PIN_NO(100) | 1) +#define MT7623_PIN_101_SPI2_CSN_FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS (MTK_PIN_NO(101) | 1) +#define MT7623_PIN_101_SPI2_CSN_FUNC_SCL3 (MTK_PIN_NO(101) | 3) + +#define MT7623_PIN_102_SPI2_MI_FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI (MTK_PIN_NO(102) | 1) +#define MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MO (MTK_PIN_NO(102) | 2) +#define MT7623_PIN_102_SPI2_MI_FUNC_SDA3 (MTK_PIN_NO(102) | 3) + +#define MT7623_PIN_103_SPI2_MO_FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO (MTK_PIN_NO(103) | 1) +#define MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MI (MTK_PIN_NO(103) | 2) +#define MT7623_PIN_103_SPI2_MO_FUNC_SCL3 (MTK_PIN_NO(103) | 3) + +#define MT7623_PIN_104_SPI2_CK_FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK (MTK_PIN_NO(104) | 1) +#define MT7623_PIN_104_SPI2_CK_FUNC_SDA3 (MTK_PIN_NO(104) | 3) + #define MT7623_PIN_105_MSDC1_CMD_FUNC_GPIO105 (MTK_PIN_NO(105) | 0) #define MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1) #define MT7623_PIN_105_MSDC1_CMD_FUNC_SDA1 (MTK_PIN_NO(105) | 3) diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h index b8dfe31821e6..b5a2174a6386 100644 --- a/include/dt-bindings/pinctrl/stm32-pinfunc.h +++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h @@ -1,3 +1,9 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Torgue Alexandre <alexandre.torgue@st.com> for STMicroelectronics. + */ + #ifndef _DT_BINDINGS_STM32_PINFUNC_H #define _DT_BINDINGS_STM32_PINFUNC_H diff --git a/include/dt-bindings/power/mt2712-power.h b/include/dt-bindings/power/mt2712-power.h new file mode 100644 index 000000000000..2c147817efc2 --- /dev/null +++ b/include/dt-bindings/power/mt2712-power.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2017 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See http://www.gnu.org/licenses/gpl-2.0.html for more details. + */ + +#ifndef _DT_BINDINGS_POWER_MT2712_POWER_H +#define _DT_BINDINGS_POWER_MT2712_POWER_H + +#define MT2712_POWER_DOMAIN_MM 0 +#define MT2712_POWER_DOMAIN_VDEC 1 +#define MT2712_POWER_DOMAIN_VENC 2 +#define MT2712_POWER_DOMAIN_ISP 3 +#define MT2712_POWER_DOMAIN_AUDIO 4 +#define MT2712_POWER_DOMAIN_USB 5 +#define MT2712_POWER_DOMAIN_USB2 6 +#define MT2712_POWER_DOMAIN_MFG 7 +#define MT2712_POWER_DOMAIN_MFG_SC1 8 +#define MT2712_POWER_DOMAIN_MFG_SC2 9 +#define MT2712_POWER_DOMAIN_MFG_SC3 10 + +#endif /* _DT_BINDINGS_POWER_MT2712_POWER_H */ diff --git a/include/dt-bindings/power/mt7623a-power.h b/include/dt-bindings/power/mt7623a-power.h new file mode 100644 index 000000000000..2544822aa76b --- /dev/null +++ b/include/dt-bindings/power/mt7623a-power.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _DT_BINDINGS_POWER_MT7623A_POWER_H +#define _DT_BINDINGS_POWER_MT7623A_POWER_H + +#define MT7623A_POWER_DOMAIN_CONN 0 +#define MT7623A_POWER_DOMAIN_ETH 1 +#define MT7623A_POWER_DOMAIN_HIF 2 +#define MT7623A_POWER_DOMAIN_IFR_MSC 3 + +#endif /* _DT_BINDINGS_POWER_MT7623A_POWER_H */ diff --git a/include/dt-bindings/power/owl-s700-powergate.h b/include/dt-bindings/power/owl-s700-powergate.h new file mode 100644 index 000000000000..4cf1aefbf09c --- /dev/null +++ b/include/dt-bindings/power/owl-s700-powergate.h @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Actions Semi S700 SPS + * + * Copyright (c) 2017 Andreas Färber + */ +#ifndef DT_BINDINGS_POWER_OWL_S700_POWERGATE_H +#define DT_BINDINGS_POWER_OWL_S700_POWERGATE_H + +#define S700_PD_VDE 0 +#define S700_PD_VCE_SI 1 +#define S700_PD_USB2_1 2 +#define S700_PD_HDE 3 +#define S700_PD_DMA 4 +#define S700_PD_DS 5 +#define S700_PD_USB3 6 +#define S700_PD_USB2_0 7 + +#endif diff --git a/include/dt-bindings/power/r8a77965-sysc.h b/include/dt-bindings/power/r8a77965-sysc.h new file mode 100644 index 000000000000..05a4b5917314 --- /dev/null +++ b/include/dt-bindings/power/r8a77965-sysc.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> + * Copyright (C) 2016 Glider bvba + */ + +#ifndef __DT_BINDINGS_POWER_R8A77965_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A77965_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A77965_PD_CA57_CPU0 0 +#define R8A77965_PD_CA57_CPU1 1 +#define R8A77965_PD_A3VP 9 +#define R8A77965_PD_CA57_SCU 12 +#define R8A77965_PD_CR7 13 +#define R8A77965_PD_A3VC 14 +#define R8A77965_PD_3DG_A 17 +#define R8A77965_PD_3DG_B 18 +#define R8A77965_PD_A3IR 24 +#define R8A77965_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A77965_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A77965_SYSC_H__ */ diff --git a/include/dt-bindings/power/r8a77980-sysc.h b/include/dt-bindings/power/r8a77980-sysc.h new file mode 100644 index 000000000000..2c90c1237725 --- /dev/null +++ b/include/dt-bindings/power/r8a77980-sysc.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + */ +#ifndef __DT_BINDINGS_POWER_R8A77980_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A77980_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A77980_PD_A2SC2 0 +#define R8A77980_PD_A2SC3 1 +#define R8A77980_PD_A2SC4 2 +#define R8A77980_PD_A2PD0 3 +#define R8A77980_PD_A2PD1 4 +#define R8A77980_PD_CA53_CPU0 5 +#define R8A77980_PD_CA53_CPU1 6 +#define R8A77980_PD_CA53_CPU2 7 +#define R8A77980_PD_CA53_CPU3 8 +#define R8A77980_PD_A2CN 10 +#define R8A77980_PD_A3VIP 11 +#define R8A77980_PD_A2IR5 12 +#define R8A77980_PD_CR7 13 +#define R8A77980_PD_A2IR4 15 +#define R8A77980_PD_CA53_SCU 21 +#define R8A77980_PD_A2IR0 23 +#define R8A77980_PD_A3IR 24 +#define R8A77980_PD_A3VIP1 25 +#define R8A77980_PD_A3VIP2 26 +#define R8A77980_PD_A2IR1 27 +#define R8A77980_PD_A2IR2 28 +#define R8A77980_PD_A2IR3 29 +#define R8A77980_PD_A2SC0 30 +#define R8A77980_PD_A2SC1 31 + +/* Always-on power area */ +#define R8A77980_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A77980_SYSC_H__ */ diff --git a/include/dt-bindings/power/tegra194-powergate.h b/include/dt-bindings/power/tegra194-powergate.h new file mode 100644 index 000000000000..82253742a493 --- /dev/null +++ b/include/dt-bindings/power/tegra194-powergate.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef __ABI_MACH_T194_POWERGATE_T194_H_ +#define __ABI_MACH_T194_POWERGATE_T194_H_ + +#define TEGRA194_POWER_DOMAIN_AUD 1 +#define TEGRA194_POWER_DOMAIN_DISP 2 +#define TEGRA194_POWER_DOMAIN_DISPB 3 +#define TEGRA194_POWER_DOMAIN_DISPC 4 +#define TEGRA194_POWER_DOMAIN_ISPA 5 +#define TEGRA194_POWER_DOMAIN_NVDECA 6 +#define TEGRA194_POWER_DOMAIN_NVJPG 7 +#define TEGRA194_POWER_DOMAIN_NVENCA 8 +#define TEGRA194_POWER_DOMAIN_NVENCB 9 +#define TEGRA194_POWER_DOMAIN_NVDECB 10 +#define TEGRA194_POWER_DOMAIN_SAX 11 +#define TEGRA194_POWER_DOMAIN_VE 12 +#define TEGRA194_POWER_DOMAIN_VIC 13 +#define TEGRA194_POWER_DOMAIN_XUSBA 14 +#define TEGRA194_POWER_DOMAIN_XUSBB 15 +#define TEGRA194_POWER_DOMAIN_XUSBC 16 +#define TEGRA194_POWER_DOMAIN_PCIEX8A 17 +#define TEGRA194_POWER_DOMAIN_PCIEX4A 18 +#define TEGRA194_POWER_DOMAIN_PCIEX1A 19 +#define TEGRA194_POWER_DOMAIN_PCIEX8B 21 +#define TEGRA194_POWER_DOMAIN_PVAA 22 +#define TEGRA194_POWER_DOMAIN_PVAB 23 +#define TEGRA194_POWER_DOMAIN_DLAA 24 +#define TEGRA194_POWER_DOMAIN_DLAB 25 +#define TEGRA194_POWER_DOMAIN_CV 26 +#define TEGRA194_POWER_DOMAIN_GPU 27 +#define TEGRA194_POWER_DOMAIN_MAX 27 + +#endif diff --git a/include/dt-bindings/reset/amlogic,meson-axg-reset.h b/include/dt-bindings/reset/amlogic,meson-axg-reset.h new file mode 100644 index 000000000000..ad6f55dabd6d --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-axg-reset.h @@ -0,0 +1,124 @@ +/* + * + * Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * Copyright (c) 2017 Amlogic, inc. + * Author: Yixun Lan <yixun.lan@amlogic.com> + * + * SPDX-License-Identifier: (GPL-2.0+ OR BSD) + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H + +/* RESET0 */ +#define RESET_HIU 0 +#define RESET_PCIE_A 1 +#define RESET_PCIE_B 2 +#define RESET_DDR_TOP 3 +/* 4 */ +#define RESET_VIU 5 +#define RESET_PCIE_PHY 6 +#define RESET_PCIE_APB 7 +/* 8 */ +/* 9 */ +#define RESET_VENC 10 +#define RESET_ASSIST 11 +/* 12 */ +#define RESET_VCBUS 13 +/* 14 */ +/* 15 */ +#define RESET_GIC 16 +#define RESET_CAPB3_DECODE 17 +/* 18-21 */ +#define RESET_SYS_CPU_CAPB3 22 +#define RESET_CBUS_CAPB3 23 +#define RESET_AHB_CNTL 24 +#define RESET_AHB_DATA 25 +#define RESET_VCBUS_CLK81 26 +#define RESET_MMC 27 +/* 28-31 */ +/* RESET1 */ +/* 32 */ +/* 33 */ +#define RESET_USB_OTG 34 +#define RESET_DDR 35 +#define RESET_AO_RESET 36 +/* 37 */ +#define RESET_AHB_SRAM 38 +/* 39 */ +/* 40 */ +#define RESET_DMA 41 +#define RESET_ISA 42 +#define RESET_ETHERNET 43 +/* 44 */ +#define RESET_SD_EMMC_B 45 +#define RESET_SD_EMMC_C 46 +#define RESET_ROM_BOOT 47 +#define RESET_SYS_CPU_0 48 +#define RESET_SYS_CPU_1 49 +#define RESET_SYS_CPU_2 50 +#define RESET_SYS_CPU_3 51 +#define RESET_SYS_CPU_CORE_0 52 +#define RESET_SYS_CPU_CORE_1 53 +#define RESET_SYS_CPU_CORE_2 54 +#define RESET_SYS_CPU_CORE_3 55 +#define RESET_SYS_PLL_DIV 56 +#define RESET_SYS_CPU_AXI 57 +#define RESET_SYS_CPU_L2 58 +#define RESET_SYS_CPU_P 59 +#define RESET_SYS_CPU_MBIST 60 +/* 61-63 */ +/* RESET2 */ +/* 64 */ +/* 65 */ +#define RESET_AUDIO 66 +/* 67 */ +#define RESET_MIPI_HOST 68 +#define RESET_AUDIO_LOCKER 69 +#define RESET_GE2D 70 +/* 71-76 */ +#define RESET_AO_CPU_RESET 77 +/* 78-95 */ +/* RESET3 */ +#define RESET_RING_OSCILLATOR 96 +/* 97-127 */ +/* RESET4 */ +/* 128 */ +/* 129 */ +#define RESET_MIPI_PHY 130 +/* 131-140 */ +#define RESET_VENCL 141 +#define RESET_I2C_MASTER_2 142 +#define RESET_I2C_MASTER_1 143 +/* 144-159 */ +/* RESET5 */ +/* 160-191 */ +/* RESET6 */ +#define RESET_PERIPHS_GENERAL 192 +#define RESET_PERIPHS_SPICC 193 +/* 194 */ +/* 195 */ +#define RESET_PERIPHS_I2C_MASTER_0 196 +/* 197-200 */ +#define RESET_PERIPHS_UART_0 201 +#define RESET_PERIPHS_UART_1 202 +/* 203-204 */ +#define RESET_PERIPHS_SPI_0 205 +#define RESET_PERIPHS_I2C_MASTER_3 206 +/* 207-223 */ +/* RESET7 */ +#define RESET_USB_DDR_0 224 +#define RESET_USB_DDR_1 225 +#define RESET_USB_DDR_2 226 +#define RESET_USB_DDR_3 227 +/* 228 */ +#define RESET_DEVICE_MMC_ARB 229 +/* 230 */ +#define RESET_VID_LOCK 231 +#define RESET_A9_DMC_PIPEL 232 +#define RESET_DMC_VPU_PIPEL 233 +/* 234-255 */ + +#endif diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h new file mode 100644 index 000000000000..f0c3aaef67a0 --- /dev/null +++ b/include/dt-bindings/reset/stm32mp1-resets.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved + * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP1_RESET_H_ +#define _DT_BINDINGS_STM32MP1_RESET_H_ + +#define LTDC_R 3072 +#define DSI_R 3076 +#define DDRPERFM_R 3080 +#define USBPHY_R 3088 +#define SPI6_R 3136 +#define I2C4_R 3138 +#define I2C6_R 3139 +#define USART1_R 3140 +#define STGEN_R 3156 +#define GPIOZ_R 3200 +#define CRYP1_R 3204 +#define HASH1_R 3205 +#define RNG1_R 3206 +#define AXIM_R 3216 +#define GPU_R 3269 +#define ETHMAC_R 3274 +#define FMC_R 3276 +#define QSPI_R 3278 +#define SDMMC1_R 3280 +#define SDMMC2_R 3281 +#define CRC1_R 3284 +#define USBH_R 3288 +#define MDMA_R 3328 +#define MCU_R 8225 +#define TIM2_R 19456 +#define TIM3_R 19457 +#define TIM4_R 19458 +#define TIM5_R 19459 +#define TIM6_R 19460 +#define TIM7_R 19461 +#define TIM12_R 16462 +#define TIM13_R 16463 +#define TIM14_R 16464 +#define LPTIM1_R 19465 +#define SPI2_R 19467 +#define SPI3_R 19468 +#define USART2_R 19470 +#define USART3_R 19471 +#define UART4_R 19472 +#define UART5_R 19473 +#define UART7_R 19474 +#define UART8_R 19475 +#define I2C1_R 19477 +#define I2C2_R 19478 +#define I2C3_R 19479 +#define I2C5_R 19480 +#define SPDIF_R 19482 +#define CEC_R 19483 +#define DAC12_R 19485 +#define MDIO_R 19847 +#define TIM1_R 19520 +#define TIM8_R 19521 +#define TIM15_R 19522 +#define TIM16_R 19523 +#define TIM17_R 19524 +#define SPI1_R 19528 +#define SPI4_R 19529 +#define SPI5_R 19530 +#define USART6_R 19533 +#define SAI1_R 19536 +#define SAI2_R 19537 +#define SAI3_R 19538 +#define DFSDM_R 19540 +#define FDCAN_R 19544 +#define LPTIM2_R 19584 +#define LPTIM3_R 19585 +#define LPTIM4_R 19586 +#define LPTIM5_R 19587 +#define SAI4_R 19592 +#define SYSCFG_R 19595 +#define VREF_R 19597 +#define TMPSENS_R 19600 +#define PMBCTRL_R 19601 +#define DMA1_R 19648 +#define DMA2_R 19649 +#define DMAMUX_R 19650 +#define ADC12_R 19653 +#define USBO_R 19656 +#define SDMMC3_R 19664 +#define CAMITF_R 19712 +#define CRYP2_R 19716 +#define HASH2_R 19717 +#define RNG2_R 19718 +#define CRC2_R 19719 +#define HSEM_R 19723 +#define MBOX_R 19724 +#define GPIOA_R 19776 +#define GPIOB_R 19777 +#define GPIOC_R 19778 +#define GPIOD_R 19779 +#define GPIOE_R 19780 +#define GPIOF_R 19781 +#define GPIOG_R 19782 +#define GPIOH_R 19783 +#define GPIOI_R 19784 +#define GPIOJ_R 19785 +#define GPIOK_R 19786 + +#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ diff --git a/include/dt-bindings/reset/tegra194-reset.h b/include/dt-bindings/reset/tegra194-reset.h new file mode 100644 index 000000000000..473afaa25bfb --- /dev/null +++ b/include/dt-bindings/reset/tegra194-reset.h @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef __ABI_MACH_T194_RESET_H +#define __ABI_MACH_T194_RESET_H + +#define TEGRA194_RESET_ACTMON 1 +#define TEGRA194_RESET_ADSP_ALL 2 +#define TEGRA194_RESET_AFI 3 +#define TEGRA194_RESET_CAN1 4 +#define TEGRA194_RESET_CAN2 5 +#define TEGRA194_RESET_DLA0 6 +#define TEGRA194_RESET_DLA1 7 +#define TEGRA194_RESET_DPAUX 8 +#define TEGRA194_RESET_DPAUX1 9 +#define TEGRA194_RESET_DPAUX2 10 +#define TEGRA194_RESET_DPAUX3 11 +#define TEGRA194_RESET_EQOS 17 +#define TEGRA194_RESET_GPCDMA 18 +#define TEGRA194_RESET_GPU 19 +#define TEGRA194_RESET_HDA 20 +#define TEGRA194_RESET_HDA2CODEC_2X 21 +#define TEGRA194_RESET_HDA2HDMICODEC 22 +#define TEGRA194_RESET_HOST1X 23 +#define TEGRA194_RESET_I2C1 24 +#define TEGRA194_RESET_I2C10 25 +#define TEGRA194_RESET_RSVD_26 26 +#define TEGRA194_RESET_RSVD_27 27 +#define TEGRA194_RESET_RSVD_28 28 +#define TEGRA194_RESET_I2C2 29 +#define TEGRA194_RESET_I2C3 30 +#define TEGRA194_RESET_I2C4 31 +#define TEGRA194_RESET_I2C6 32 +#define TEGRA194_RESET_I2C7 33 +#define TEGRA194_RESET_I2C8 34 +#define TEGRA194_RESET_I2C9 35 +#define TEGRA194_RESET_ISP 36 +#define TEGRA194_RESET_MIPI_CAL 37 +#define TEGRA194_RESET_MPHY_CLK_CTL 38 +#define TEGRA194_RESET_MPHY_L0_RX 39 +#define TEGRA194_RESET_MPHY_L0_TX 40 +#define TEGRA194_RESET_MPHY_L1_RX 41 +#define TEGRA194_RESET_MPHY_L1_TX 42 +#define TEGRA194_RESET_NVCSI 43 +#define TEGRA194_RESET_NVDEC 44 +#define TEGRA194_RESET_NVDISPLAY0_HEAD0 45 +#define TEGRA194_RESET_NVDISPLAY0_HEAD1 46 +#define TEGRA194_RESET_NVDISPLAY0_HEAD2 47 +#define TEGRA194_RESET_NVDISPLAY0_HEAD3 48 +#define TEGRA194_RESET_NVDISPLAY0_MISC 49 +#define TEGRA194_RESET_NVDISPLAY0_WGRP0 50 +#define TEGRA194_RESET_NVDISPLAY0_WGRP1 51 +#define TEGRA194_RESET_NVDISPLAY0_WGRP2 52 +#define TEGRA194_RESET_NVDISPLAY0_WGRP3 53 +#define TEGRA194_RESET_NVDISPLAY0_WGRP4 54 +#define TEGRA194_RESET_NVDISPLAY0_WGRP5 55 +#define TEGRA194_RESET_RSVD_56 56 +#define TEGRA194_RESET_RSVD_57 57 +#define TEGRA194_RESET_RSVD_58 58 +#define TEGRA194_RESET_NVENC 59 +#define TEGRA194_RESET_NVENC1 60 +#define TEGRA194_RESET_NVJPG 61 +#define TEGRA194_RESET_PCIE 62 +#define TEGRA194_RESET_PCIEXCLK 63 +#define TEGRA194_RESET_RSVD_64 64 +#define TEGRA194_RESET_RSVD_65 65 +#define TEGRA194_RESET_PVA0_ALL 66 +#define TEGRA194_RESET_PVA1_ALL 67 +#define TEGRA194_RESET_PWM1 68 +#define TEGRA194_RESET_PWM2 69 +#define TEGRA194_RESET_PWM3 70 +#define TEGRA194_RESET_PWM4 71 +#define TEGRA194_RESET_PWM5 72 +#define TEGRA194_RESET_PWM6 73 +#define TEGRA194_RESET_PWM7 74 +#define TEGRA194_RESET_PWM8 75 +#define TEGRA194_RESET_QSPI0 76 +#define TEGRA194_RESET_QSPI1 77 +#define TEGRA194_RESET_SATA 78 +#define TEGRA194_RESET_SATACOLD 79 +#define TEGRA194_RESET_SCE_ALL 80 +#define TEGRA194_RESET_RCE_ALL 81 +#define TEGRA194_RESET_SDMMC1 82 +#define TEGRA194_RESET_RSVD_83 83 +#define TEGRA194_RESET_SDMMC3 84 +#define TEGRA194_RESET_SDMMC4 85 +#define TEGRA194_RESET_SE 86 +#define TEGRA194_RESET_SOR0 87 +#define TEGRA194_RESET_SOR1 88 +#define TEGRA194_RESET_SOR2 89 +#define TEGRA194_RESET_SOR3 90 +#define TEGRA194_RESET_SPI1 91 +#define TEGRA194_RESET_SPI2 92 +#define TEGRA194_RESET_SPI3 93 +#define TEGRA194_RESET_SPI4 94 +#define TEGRA194_RESET_TACH 95 +#define TEGRA194_RESET_RSVD_96 96 +#define TEGRA194_RESET_TSCTNVI 97 +#define TEGRA194_RESET_TSEC 98 +#define TEGRA194_RESET_TSECB 99 +#define TEGRA194_RESET_UARTA 100 +#define TEGRA194_RESET_UARTB 101 +#define TEGRA194_RESET_UARTC 102 +#define TEGRA194_RESET_UARTD 103 +#define TEGRA194_RESET_UARTE 104 +#define TEGRA194_RESET_UARTF 105 +#define TEGRA194_RESET_UARTG 106 +#define TEGRA194_RESET_UARTH 107 +#define TEGRA194_RESET_UFSHC 108 +#define TEGRA194_RESET_UFSHC_AXI_M 109 +#define TEGRA194_RESET_UFSHC_LP_SEQ 110 +#define TEGRA194_RESET_RSVD_111 111 +#define TEGRA194_RESET_VI 112 +#define TEGRA194_RESET_VIC 113 +#define TEGRA194_RESET_XUSB_PADCTL 114 +#define TEGRA194_RESET_NVDEC1 115 +#define TEGRA194_RESET_PEX0_CORE_0 116 +#define TEGRA194_RESET_PEX0_CORE_1 117 +#define TEGRA194_RESET_PEX0_CORE_2 118 +#define TEGRA194_RESET_PEX0_CORE_3 119 +#define TEGRA194_RESET_PEX0_CORE_4 120 +#define TEGRA194_RESET_PEX0_CORE_0_APB 121 +#define TEGRA194_RESET_PEX0_CORE_1_APB 122 +#define TEGRA194_RESET_PEX0_CORE_2_APB 123 +#define TEGRA194_RESET_PEX0_CORE_3_APB 124 +#define TEGRA194_RESET_PEX0_CORE_4_APB 125 +#define TEGRA194_RESET_PEX0_COMMON_APB 126 +#define TEGRA194_RESET_PEX1_CORE_5 129 +#define TEGRA194_RESET_PEX1_CORE_5_APB 130 +#define TEGRA194_RESET_CVNAS 131 +#define TEGRA194_RESET_CVNAS_FCM 132 +#define TEGRA194_RESET_DMIC5 144 +#define TEGRA194_RESET_APE 145 +#define TEGRA194_RESET_PEX_USB_UPHY 146 +#define TEGRA194_RESET_PEX_USB_UPHY_L0 147 +#define TEGRA194_RESET_PEX_USB_UPHY_L1 148 +#define TEGRA194_RESET_PEX_USB_UPHY_L2 149 +#define TEGRA194_RESET_PEX_USB_UPHY_L3 150 +#define TEGRA194_RESET_PEX_USB_UPHY_L4 151 +#define TEGRA194_RESET_PEX_USB_UPHY_L5 152 +#define TEGRA194_RESET_PEX_USB_UPHY_L6 153 +#define TEGRA194_RESET_PEX_USB_UPHY_L7 154 +#define TEGRA194_RESET_PEX_USB_UPHY_L8 155 +#define TEGRA194_RESET_PEX_USB_UPHY_L9 156 +#define TEGRA194_RESET_PEX_USB_UPHY_L10 157 +#define TEGRA194_RESET_PEX_USB_UPHY_L11 158 +#define TEGRA194_RESET_PEX_USB_UPHY_PLL0 159 +#define TEGRA194_RESET_PEX_USB_UPHY_PLL1 160 +#define TEGRA194_RESET_PEX_USB_UPHY_PLL2 161 +#define TEGRA194_RESET_PEX_USB_UPHY_PLL3 162 + +#endif diff --git a/include/dt-bindings/sound/rt5651.h b/include/dt-bindings/sound/rt5651.h new file mode 100644 index 000000000000..2f2dac915168 --- /dev/null +++ b/include/dt-bindings/sound/rt5651.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_RT5651_H +#define __DT_RT5651_H + +#define RT5651_JD_NULL 0 +#define RT5651_JD1_1 1 +#define RT5651_JD1_2 2 +#define RT5651_JD2 3 + +#define RT5651_OVCD_SF_0P5 0 +#define RT5651_OVCD_SF_0P75 1 +#define RT5651_OVCD_SF_1P0 2 +#define RT5651_OVCD_SF_1P5 3 + +#endif /* __DT_RT5651_H */ |