diff options
Diffstat (limited to 'include/linux/mfd')
30 files changed, 3604 insertions, 507 deletions
diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h index ee96cd51d8b2..1318ca622633 100644 --- a/include/linux/mfd/abx500.h +++ b/include/linux/mfd/abx500.h @@ -6,7 +6,7 @@ * * ABX500 core access functions. * The abx500 interface is used for the Analog Baseband chip - * ab3100, ab5500, and ab8500. + * ab3100 and ab8500. * * Author: Mattias Wallin <mattias.wallin@stericsson.com> * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> @@ -30,9 +30,6 @@ struct device; #define AB3100_P1G 0xc6 #define AB3100_R2A 0xc7 #define AB3100_R2B 0xc8 -#define AB5500_1_0 0x20 -#define AB5500_1_1 0x21 -#define AB5500_2_0 0x24 /* * AB3100, EVENTA1, A2 and A3 event register flags diff --git a/include/linux/mfd/abx500/ab5500.h b/include/linux/mfd/abx500/ab5500.h deleted file mode 100644 index 54f820ed73bb..000000000000 --- a/include/linux/mfd/abx500/ab5500.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (C) ST-Ericsson 2011 - * - * License Terms: GNU General Public License v2 - */ -#ifndef MFD_AB5500_H -#define MFD_AB5500_H - -struct device; - -enum ab5500_devid { - AB5500_DEVID_ADC, - AB5500_DEVID_LEDS, - AB5500_DEVID_POWER, - AB5500_DEVID_REGULATORS, - AB5500_DEVID_SIM, - AB5500_DEVID_RTC, - AB5500_DEVID_CHARGER, - AB5500_DEVID_FUELGAUGE, - AB5500_DEVID_VIBRATOR, - AB5500_DEVID_CODEC, - AB5500_DEVID_USB, - AB5500_DEVID_OTP, - AB5500_DEVID_VIDEO, - AB5500_DEVID_DBIECI, - AB5500_DEVID_ONSWA, - AB5500_NUM_DEVICES, -}; - -enum ab5500_banks { - AB5500_BANK_VIT_IO_I2C_CLK_TST_OTP = 0, - AB5500_BANK_VDDDIG_IO_I2C_CLK_TST = 1, - AB5500_BANK_VDENC = 2, - AB5500_BANK_SIM_USBSIM = 3, - AB5500_BANK_LED = 4, - AB5500_BANK_ADC = 5, - AB5500_BANK_RTC = 6, - AB5500_BANK_STARTUP = 7, - AB5500_BANK_DBI_ECI = 8, - AB5500_BANK_CHG = 9, - AB5500_BANK_FG_BATTCOM_ACC = 10, - AB5500_BANK_USB = 11, - AB5500_BANK_IT = 12, - AB5500_BANK_VIBRA = 13, - AB5500_BANK_AUDIO_HEADSETUSB = 14, - AB5500_NUM_BANKS = 15, -}; - -enum ab5500_banks_addr { - AB5500_ADDR_VIT_IO_I2C_CLK_TST_OTP = 0x4A, - AB5500_ADDR_VDDDIG_IO_I2C_CLK_TST = 0x4B, - AB5500_ADDR_VDENC = 0x06, - AB5500_ADDR_SIM_USBSIM = 0x04, - AB5500_ADDR_LED = 0x10, - AB5500_ADDR_ADC = 0x0A, - AB5500_ADDR_RTC = 0x0F, - AB5500_ADDR_STARTUP = 0x03, - AB5500_ADDR_DBI_ECI = 0x07, - AB5500_ADDR_CHG = 0x0B, - AB5500_ADDR_FG_BATTCOM_ACC = 0x0C, - AB5500_ADDR_USB = 0x05, - AB5500_ADDR_IT = 0x0E, - AB5500_ADDR_VIBRA = 0x02, - AB5500_ADDR_AUDIO_HEADSETUSB = 0x0D, -}; - -/* - * Interrupt register offsets - * Bank : 0x0E - */ -#define AB5500_IT_SOURCE0_REG 0x20 -#define AB5500_IT_SOURCE1_REG 0x21 -#define AB5500_IT_SOURCE2_REG 0x22 -#define AB5500_IT_SOURCE3_REG 0x23 -#define AB5500_IT_SOURCE4_REG 0x24 -#define AB5500_IT_SOURCE5_REG 0x25 -#define AB5500_IT_SOURCE6_REG 0x26 -#define AB5500_IT_SOURCE7_REG 0x27 -#define AB5500_IT_SOURCE8_REG 0x28 -#define AB5500_IT_SOURCE9_REG 0x29 -#define AB5500_IT_SOURCE10_REG 0x2A -#define AB5500_IT_SOURCE11_REG 0x2B -#define AB5500_IT_SOURCE12_REG 0x2C -#define AB5500_IT_SOURCE13_REG 0x2D -#define AB5500_IT_SOURCE14_REG 0x2E -#define AB5500_IT_SOURCE15_REG 0x2F -#define AB5500_IT_SOURCE16_REG 0x30 -#define AB5500_IT_SOURCE17_REG 0x31 -#define AB5500_IT_SOURCE18_REG 0x32 -#define AB5500_IT_SOURCE19_REG 0x33 -#define AB5500_IT_SOURCE20_REG 0x34 -#define AB5500_IT_SOURCE21_REG 0x35 -#define AB5500_IT_SOURCE22_REG 0x36 -#define AB5500_IT_SOURCE23_REG 0x37 - -#define AB5500_NUM_IRQ_REGS 23 - -/** - * struct ab5500 - * @access_mutex: lock out concurrent accesses to the AB registers - * @dev: a pointer to the device struct for this chip driver - * @ab5500_irq: the analog baseband irq - * @irq_base: the platform configuration irq base for subdevices - * @chip_name: name of this chip variant - * @chip_id: 8 bit chip ID for this chip variant - * @irq_lock: a lock to protect the mask - * @abb_events: a local bit mask of the prcmu wakeup events - * @event_mask: a local copy of the mask event registers - * @last_event_mask: a copy of the last event_mask written to hardware - * @startup_events: a copy of the first reading of the event registers - * @startup_events_read: whether the first events have been read - */ -struct ab5500 { - struct mutex access_mutex; - struct device *dev; - unsigned int ab5500_irq; - unsigned int irq_base; - char chip_name[32]; - u8 chip_id; - struct mutex irq_lock; - u32 abb_events; - u8 mask[AB5500_NUM_IRQ_REGS]; - u8 oldmask[AB5500_NUM_IRQ_REGS]; - u8 startup_events[AB5500_NUM_IRQ_REGS]; - bool startup_events_read; -#ifdef CONFIG_DEBUG_FS - unsigned int debug_bank; - unsigned int debug_address; -#endif -}; - -struct ab5500_platform_data { - struct {unsigned int base; unsigned int count; } irq; - void *dev_data[AB5500_NUM_DEVICES]; - struct abx500_init_settings *init_settings; - unsigned int init_settings_sz; - bool pm_power_off; -}; - -#endif /* MFD_AB5500_H */ diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h index fccc3002f271..91dd3ef63e99 100644 --- a/include/linux/mfd/abx500/ab8500.h +++ b/include/linux/mfd/abx500/ab8500.h @@ -7,6 +7,7 @@ #ifndef MFD_AB8500_H #define MFD_AB8500_H +#include <linux/atomic.h> #include <linux/mutex.h> struct device; @@ -194,6 +195,14 @@ enum ab8500_version { #define AB9540_INT_GPIO52F 123 #define AB9540_INT_GPIO53F 124 #define AB9540_INT_GPIO54F 125 /* not 8505 */ +/* ab8500_irq_regoffset[16] -> IT[Source|Latch|Mask]25 */ +#define AB8505_INT_KEYSTUCK 128 +#define AB8505_INT_IKR 129 +#define AB8505_INT_IKP 130 +#define AB8505_INT_KP 131 +#define AB8505_INT_KEYDEGLITCH 132 +#define AB8505_INT_MODPWRSTATUSF 134 +#define AB8505_INT_MODPWRSTATUSR 135 /* * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the @@ -203,8 +212,8 @@ enum ab8500_version { * which is larger. */ #define AB8500_NR_IRQS 112 -#define AB8505_NR_IRQS 128 -#define AB9540_NR_IRQS 128 +#define AB8505_NR_IRQS 136 +#define AB9540_NR_IRQS 136 /* This is set to the roof of any AB8500 chip variant IRQ counts */ #define AB8500_MAX_NR_IRQS AB9540_NR_IRQS @@ -216,6 +225,7 @@ enum ab8500_version { * @dev: parent device * @lock: read/write operations lock * @irq_lock: genirq bus lock + * @transfer_ongoing: 0 if no transfer ongoing * @irq: irq line * @version: chip version id (e.g. ab8500 or ab9540) * @chip_id: chip revision id @@ -234,7 +244,7 @@ struct ab8500 { struct device *dev; struct mutex lock; struct mutex irq_lock; - + atomic_t transfer_ongoing; int irq_base; int irq; enum ab8500_version version; @@ -280,6 +290,8 @@ extern int __devinit ab8500_init(struct ab8500 *ab8500, enum ab8500_version version); extern int __devexit ab8500_exit(struct ab8500 *ab8500); +extern int ab8500_suspend(struct ab8500 *ab8500); + static inline int is_ab8500(struct ab8500 *ab) { return ab->version == AB8500_VERSION_AB8500; diff --git a/include/linux/mfd/anatop.h b/include/linux/mfd/anatop.h index 22c1007d3ec5..7f92acf03d9e 100644 --- a/include/linux/mfd/anatop.h +++ b/include/linux/mfd/anatop.h @@ -34,7 +34,7 @@ struct anatop { spinlock_t reglock; }; -extern u32 anatop_get_bits(struct anatop *, u32, int, int); -extern void anatop_set_bits(struct anatop *, u32, int, int, u32); +extern u32 anatop_read_reg(struct anatop *, u32); +extern void anatop_write_reg(struct anatop *, u32, u32, u32); #endif /* __LINUX_MFD_ANATOP_H */ diff --git a/include/linux/mfd/asic3.h b/include/linux/mfd/asic3.h index ed793b77a1c5..e1148d037e7b 100644 --- a/include/linux/mfd/asic3.h +++ b/include/linux/mfd/asic3.h @@ -31,6 +31,8 @@ struct asic3_platform_data { unsigned int gpio_base; + unsigned int clock_rate; + struct asic3_led *leds; }; @@ -138,6 +140,7 @@ struct asic3_platform_data { #define ASIC3_GPIOC13_nPWAIT ASIC3_CONFIG_GPIO(45, 1, 1, 0) #define ASIC3_GPIOC14_nPIOIS16 ASIC3_CONFIG_GPIO(46, 1, 1, 0) #define ASIC3_GPIOC15_nPIOR ASIC3_CONFIG_GPIO(47, 1, 0, 0) +#define ASIC3_GPIOD4_CF_nCD ASIC3_CONFIG_GPIO(52, 1, 0, 0) #define ASIC3_GPIOD11_nCIOIS16 ASIC3_CONFIG_GPIO(59, 1, 0, 0) #define ASIC3_GPIOD12_nCWAIT ASIC3_CONFIG_GPIO(60, 1, 0, 0) #define ASIC3_GPIOD15_nPIOW ASIC3_CONFIG_GPIO(63, 1, 0, 0) diff --git a/include/linux/mfd/da9052/da9052.h b/include/linux/mfd/da9052/da9052.h index 7ffbd6e9e7fc..0507c4c21a7d 100644 --- a/include/linux/mfd/da9052/da9052.h +++ b/include/linux/mfd/da9052/da9052.h @@ -33,6 +33,18 @@ #include <linux/mfd/da9052/reg.h> +/* Common - HWMON Channel Definations */ +#define DA9052_ADC_VDDOUT 0 +#define DA9052_ADC_ICH 1 +#define DA9052_ADC_TBAT 2 +#define DA9052_ADC_VBAT 3 +#define DA9052_ADC_IN4 4 +#define DA9052_ADC_IN5 5 +#define DA9052_ADC_IN6 6 +#define DA9052_ADC_TSI 7 +#define DA9052_ADC_TJUNC 8 +#define DA9052_ADC_VBBAT 9 + #define DA9052_IRQ_DCIN 0 #define DA9052_IRQ_VBUS 1 #define DA9052_IRQ_DCINREM 2 @@ -79,12 +91,20 @@ struct da9052 { struct device *dev; struct regmap *regmap; + struct mutex auxadc_lock; + struct completion done; + int irq_base; + struct regmap_irq_chip_data *irq_data; u8 chip_id; int chip_irq; }; +/* ADC API */ +int da9052_adc_manual_read(struct da9052 *da9052, unsigned char channel); +int da9052_adc_read_temp(struct da9052 *da9052); + /* Device I/O API */ static inline int da9052_reg_read(struct da9052 *da9052, unsigned char reg) { diff --git a/include/linux/mfd/db5500-prcmu.h b/include/linux/mfd/db5500-prcmu.h deleted file mode 100644 index 5a049dfaf153..000000000000 --- a/include/linux/mfd/db5500-prcmu.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License Terms: GNU General Public License v2 - * - * U5500 PRCMU API. - */ -#ifndef __MFD_DB5500_PRCMU_H -#define __MFD_DB5500_PRCMU_H - -static inline int prcmu_resetout(u8 resoutn, u8 state) -{ - return 0; -} - -static inline int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state) -{ - return 0; -} - -static inline int db5500_prcmu_request_clock(u8 clock, bool enable) -{ - return 0; -} - -static inline int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, - bool keep_ap_pll) -{ - return 0; -} - -static inline int db5500_prcmu_config_esram0_deep_sleep(u8 state) -{ - return 0; -} - -static inline u16 db5500_prcmu_get_reset_code(void) -{ - return 0; -} - -static inline bool db5500_prcmu_is_ac_wake_requested(void) -{ - return 0; -} - -static inline int db5500_prcmu_set_arm_opp(u8 opp) -{ - return 0; -} - -static inline int db5500_prcmu_get_arm_opp(void) -{ - return 0; -} - -static inline void db5500_prcmu_config_abb_event_readout(u32 abb_events) {} - -static inline void db5500_prcmu_get_abb_event_buffer(void __iomem **buf) {} - -static inline void db5500_prcmu_system_reset(u16 reset_code) {} - -static inline void db5500_prcmu_enable_wakeups(u32 wakeups) {} - -#ifdef CONFIG_MFD_DB5500_PRCMU - -void db5500_prcmu_early_init(void); -int db5500_prcmu_set_display_clocks(void); -int db5500_prcmu_disable_dsipll(void); -int db5500_prcmu_enable_dsipll(void); -int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); -int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); - -#else /* !CONFIG_UX500_SOC_DB5500 */ - -static inline void db5500_prcmu_early_init(void) {} - -static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) -{ - return -ENOSYS; -} - -static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) -{ - return -ENOSYS; -} - -static inline int db5500_prcmu_set_display_clocks(void) -{ - return 0; -} - -static inline int db5500_prcmu_disable_dsipll(void) -{ - return 0; -} - -static inline int db5500_prcmu_enable_dsipll(void) -{ - return 0; -} - -#endif /* CONFIG_MFD_DB5500_PRCMU */ - -#endif /* __MFD_DB5500_PRCMU_H */ diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h index d7674eb7305f..5a13f93d8f1c 100644 --- a/include/linux/mfd/dbx500-prcmu.h +++ b/include/linux/mfd/dbx500-prcmu.h @@ -55,17 +55,6 @@ enum prcmu_wakeup_index { #define NUM_EPOD_ID 8 /* - * DB5500 EPODs - */ -#define DB5500_EPOD_ID_BASE 0x0100 -#define DB5500_EPOD_ID_SGA (DB5500_EPOD_ID_BASE + 0) -#define DB5500_EPOD_ID_HVA (DB5500_EPOD_ID_BASE + 1) -#define DB5500_EPOD_ID_SIA (DB5500_EPOD_ID_BASE + 2) -#define DB5500_EPOD_ID_DISP (DB5500_EPOD_ID_BASE + 3) -#define DB5500_EPOD_ID_ESRAM12 (DB5500_EPOD_ID_BASE + 6) -#define DB5500_NUM_EPOD_ID 7 - -/* * state definition for EPOD (power domain) * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged * - EPOD_STATE_OFF: The EPOD is switched off @@ -80,29 +69,6 @@ enum prcmu_wakeup_index { #define EPOD_STATE_ON_CLK_OFF 0x03 #define EPOD_STATE_ON 0x04 -/* DB5500 CLKOUT IDs */ -enum { - DB5500_CLKOUT0 = 0, - DB5500_CLKOUT1, -}; - -/* DB5500 CLKOUTx sources */ -enum { - DB5500_CLKOUT_REF_CLK_SEL0, - DB5500_CLKOUT_RTC_CLK0_SEL0, - DB5500_CLKOUT_ULP_CLK_SEL0, - DB5500_CLKOUT_STATIC0, - DB5500_CLKOUT_REFCLK, - DB5500_CLKOUT_ULPCLK, - DB5500_CLKOUT_ARMCLK, - DB5500_CLKOUT_SYSACC0CLK, - DB5500_CLKOUT_SOC0PLLCLK, - DB5500_CLKOUT_SOC1PLLCLK, - DB5500_CLKOUT_DDRPLLCLK, - DB5500_CLKOUT_TVCLK, - DB5500_CLKOUT_IRDACLK, -}; - /* * CLKOUT sources */ @@ -248,101 +214,66 @@ enum ddr_pwrst { }; #include <linux/mfd/db8500-prcmu.h> -#include <linux/mfd/db5500-prcmu.h> -#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500) +#if defined(CONFIG_UX500_SOC_DB8500) #include <mach/id.h> static inline void __init prcmu_early_init(void) { - if (cpu_is_u5500()) - return db5500_prcmu_early_init(); - else - return db8500_prcmu_early_init(); + return db8500_prcmu_early_init(); } static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) { - if (cpu_is_u5500()) - return db5500_prcmu_set_power_state(state, keep_ulp_clk, - keep_ap_pll); - else - return db8500_prcmu_set_power_state(state, keep_ulp_clk, - keep_ap_pll); + return db8500_prcmu_set_power_state(state, keep_ulp_clk, + keep_ap_pll); } static inline u8 prcmu_get_power_state_result(void) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_get_power_state_result(); + return db8500_prcmu_get_power_state_result(); } static inline int prcmu_gic_decouple(void) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_gic_decouple(); + return db8500_prcmu_gic_decouple(); } static inline int prcmu_gic_recouple(void) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_gic_recouple(); + return db8500_prcmu_gic_recouple(); } static inline bool prcmu_gic_pending_irq(void) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_gic_pending_irq(); + return db8500_prcmu_gic_pending_irq(); } static inline bool prcmu_is_cpu_in_wfi(int cpu) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_is_cpu_in_wfi(cpu); + return db8500_prcmu_is_cpu_in_wfi(cpu); } static inline int prcmu_copy_gic_settings(void) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_copy_gic_settings(); + return db8500_prcmu_copy_gic_settings(); } static inline bool prcmu_pending_irq(void) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_pending_irq(); + return db8500_prcmu_pending_irq(); } static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_set_epod(epod_id, epod_state); + return db8500_prcmu_set_epod(epod_id, epod_state); } static inline void prcmu_enable_wakeups(u32 wakeups) { - if (cpu_is_u5500()) - db5500_prcmu_enable_wakeups(wakeups); - else - db8500_prcmu_enable_wakeups(wakeups); + db8500_prcmu_enable_wakeups(wakeups); } static inline void prcmu_disable_wakeups(void) @@ -352,18 +283,12 @@ static inline void prcmu_disable_wakeups(void) static inline void prcmu_config_abb_event_readout(u32 abb_events) { - if (cpu_is_u5500()) - db5500_prcmu_config_abb_event_readout(abb_events); - else - db8500_prcmu_config_abb_event_readout(abb_events); + db8500_prcmu_config_abb_event_readout(abb_events); } static inline void prcmu_get_abb_event_buffer(void __iomem **buf) { - if (cpu_is_u5500()) - db5500_prcmu_get_abb_event_buffer(buf); - else - db8500_prcmu_get_abb_event_buffer(buf); + db8500_prcmu_get_abb_event_buffer(buf); } int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); @@ -374,10 +299,7 @@ int prcmu_config_clkout(u8 clkout, u8 source, u8 div); static inline int prcmu_request_clock(u8 clock, bool enable) { - if (cpu_is_u5500()) - return db5500_prcmu_request_clock(clock, enable); - else - return db8500_prcmu_request_clock(clock, enable); + return db8500_prcmu_request_clock(clock, enable); } unsigned long prcmu_clock_rate(u8 clock); @@ -386,211 +308,133 @@ int prcmu_set_clock_rate(u8 clock, unsigned long rate); static inline int prcmu_set_ddr_opp(u8 opp) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_set_ddr_opp(opp); + return db8500_prcmu_set_ddr_opp(opp); } static inline int prcmu_get_ddr_opp(void) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_get_ddr_opp(); + return db8500_prcmu_get_ddr_opp(); } static inline int prcmu_set_arm_opp(u8 opp) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_set_arm_opp(opp); + return db8500_prcmu_set_arm_opp(opp); } static inline int prcmu_get_arm_opp(void) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_get_arm_opp(); + return db8500_prcmu_get_arm_opp(); } static inline int prcmu_set_ape_opp(u8 opp) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_set_ape_opp(opp); + return db8500_prcmu_set_ape_opp(opp); } static inline int prcmu_get_ape_opp(void) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_get_ape_opp(); + return db8500_prcmu_get_ape_opp(); } static inline void prcmu_system_reset(u16 reset_code) { - if (cpu_is_u5500()) - return db5500_prcmu_system_reset(reset_code); - else - return db8500_prcmu_system_reset(reset_code); + return db8500_prcmu_system_reset(reset_code); } static inline u16 prcmu_get_reset_code(void) { - if (cpu_is_u5500()) - return db5500_prcmu_get_reset_code(); - else - return db8500_prcmu_get_reset_code(); + return db8500_prcmu_get_reset_code(); } void prcmu_ac_wake_req(void); void prcmu_ac_sleep_req(void); static inline void prcmu_modem_reset(void) { - if (cpu_is_u5500()) - return; - else - return db8500_prcmu_modem_reset(); + return db8500_prcmu_modem_reset(); } static inline bool prcmu_is_ac_wake_requested(void) { - if (cpu_is_u5500()) - return db5500_prcmu_is_ac_wake_requested(); - else - return db8500_prcmu_is_ac_wake_requested(); + return db8500_prcmu_is_ac_wake_requested(); } static inline int prcmu_set_display_clocks(void) { - if (cpu_is_u5500()) - return db5500_prcmu_set_display_clocks(); - else - return db8500_prcmu_set_display_clocks(); + return db8500_prcmu_set_display_clocks(); } static inline int prcmu_disable_dsipll(void) { - if (cpu_is_u5500()) - return db5500_prcmu_disable_dsipll(); - else - return db8500_prcmu_disable_dsipll(); + return db8500_prcmu_disable_dsipll(); } static inline int prcmu_enable_dsipll(void) { - if (cpu_is_u5500()) - return db5500_prcmu_enable_dsipll(); - else - return db8500_prcmu_enable_dsipll(); + return db8500_prcmu_enable_dsipll(); } static inline int prcmu_config_esram0_deep_sleep(u8 state) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_config_esram0_deep_sleep(state); + return db8500_prcmu_config_esram0_deep_sleep(state); } static inline int prcmu_config_hotdog(u8 threshold) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_config_hotdog(threshold); + return db8500_prcmu_config_hotdog(threshold); } static inline int prcmu_config_hotmon(u8 low, u8 high) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_config_hotmon(low, high); + return db8500_prcmu_config_hotmon(low, high); } static inline int prcmu_start_temp_sense(u16 cycles32k) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_start_temp_sense(cycles32k); + return db8500_prcmu_start_temp_sense(cycles32k); } static inline int prcmu_stop_temp_sense(void) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_stop_temp_sense(); + return db8500_prcmu_stop_temp_sense(); } static inline u32 prcmu_read(unsigned int reg) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_read(reg); + return db8500_prcmu_read(reg); } static inline void prcmu_write(unsigned int reg, u32 value) { - if (cpu_is_u5500()) - return; - else - db8500_prcmu_write(reg, value); + db8500_prcmu_write(reg, value); } static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) { - if (cpu_is_u5500()) - return; - else - db8500_prcmu_write_masked(reg, mask, value); + db8500_prcmu_write_masked(reg, mask, value); } static inline int prcmu_enable_a9wdog(u8 id) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_enable_a9wdog(id); + return db8500_prcmu_enable_a9wdog(id); } static inline int prcmu_disable_a9wdog(u8 id) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_disable_a9wdog(id); + return db8500_prcmu_disable_a9wdog(id); } static inline int prcmu_kick_a9wdog(u8 id) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_kick_a9wdog(id); + return db8500_prcmu_kick_a9wdog(id); } static inline int prcmu_load_a9wdog(u8 id, u32 timeout) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_load_a9wdog(id, timeout); + return db8500_prcmu_load_a9wdog(id, timeout); } static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) { - if (cpu_is_u5500()) - return -EINVAL; - else - return db8500_prcmu_config_a9wdog(num, sleep_auto_off); + return db8500_prcmu_config_a9wdog(num, sleep_auto_off); } #else @@ -768,7 +612,7 @@ static inline void prcmu_clear(unsigned int reg, u32 bits) prcmu_write_masked(reg, bits, 0); } -#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500) +#if defined(CONFIG_UX500_SOC_DB8500) /** * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1. diff --git a/include/linux/mfd/lm3533.h b/include/linux/mfd/lm3533.h new file mode 100644 index 000000000000..594bc591f256 --- /dev/null +++ b/include/linux/mfd/lm3533.h @@ -0,0 +1,104 @@ +/* + * lm3533.h -- LM3533 interface + * + * Copyright (C) 2011-2012 Texas Instruments + * + * Author: Johan Hovold <jhovold@gmail.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __LINUX_MFD_LM3533_H +#define __LINUX_MFD_LM3533_H + +#define LM3533_ATTR_RO(_name) \ + DEVICE_ATTR(_name, S_IRUGO, show_##_name, NULL) +#define LM3533_ATTR_RW(_name) \ + DEVICE_ATTR(_name, S_IRUGO | S_IWUSR , show_##_name, store_##_name) + +struct device; +struct regmap; + +struct lm3533 { + struct device *dev; + + struct regmap *regmap; + + int gpio_hwen; + int irq; + + unsigned have_als:1; + unsigned have_backlights:1; + unsigned have_leds:1; +}; + +struct lm3533_ctrlbank { + struct lm3533 *lm3533; + struct device *dev; + int id; +}; + +struct lm3533_als_platform_data { + unsigned pwm_mode:1; /* PWM input mode (default analog) */ + u8 r_select; /* 1 - 127 (ignored in PWM-mode) */ +}; + +struct lm3533_bl_platform_data { + char *name; + u16 max_current; /* 5000 - 29800 uA (800 uA step) */ + u8 default_brightness; /* 0 - 255 */ + u8 pwm; /* 0 - 0x3f */ +}; + +struct lm3533_led_platform_data { + char *name; + const char *default_trigger; + u16 max_current; /* 5000 - 29800 uA (800 uA step) */ + u8 pwm; /* 0 - 0x3f */ +}; + +enum lm3533_boost_freq { + LM3533_BOOST_FREQ_500KHZ, + LM3533_BOOST_FREQ_1000KHZ, +}; + +enum lm3533_boost_ovp { + LM3533_BOOST_OVP_16V, + LM3533_BOOST_OVP_24V, + LM3533_BOOST_OVP_32V, + LM3533_BOOST_OVP_40V, +}; + +struct lm3533_platform_data { + int gpio_hwen; + + enum lm3533_boost_ovp boost_ovp; + enum lm3533_boost_freq boost_freq; + + struct lm3533_als_platform_data *als; + + struct lm3533_bl_platform_data *backlights; + int num_backlights; + + struct lm3533_led_platform_data *leds; + int num_leds; +}; + +extern int lm3533_ctrlbank_enable(struct lm3533_ctrlbank *cb); +extern int lm3533_ctrlbank_disable(struct lm3533_ctrlbank *cb); + +extern int lm3533_ctrlbank_set_brightness(struct lm3533_ctrlbank *cb, u8 val); +extern int lm3533_ctrlbank_get_brightness(struct lm3533_ctrlbank *cb, u8 *val); +extern int lm3533_ctrlbank_set_max_current(struct lm3533_ctrlbank *cb, + u16 imax); +extern int lm3533_ctrlbank_set_pwm(struct lm3533_ctrlbank *cb, u8 val); +extern int lm3533_ctrlbank_get_pwm(struct lm3533_ctrlbank *cb, u8 *val); + +extern int lm3533_read(struct lm3533 *lm3533, u8 reg, u8 *val); +extern int lm3533_write(struct lm3533 *lm3533, u8 reg, u8 val); +extern int lm3533_update(struct lm3533 *lm3533, u8 reg, u8 val, u8 mask); + +#endif /* __LINUX_MFD_LM3533_H */ diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h new file mode 100644 index 000000000000..fec5256c3f5d --- /dev/null +++ b/include/linux/mfd/lpc_ich.h @@ -0,0 +1,48 @@ +/* + * linux/drivers/mfd/lpc_ich.h + * + * Copyright (c) 2012 Extreme Engineering Solution, Inc. + * Author: Aaron Sierra <asierra@xes-inc.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. If not, write to + * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef LPC_ICH_H +#define LPC_ICH_H + +/* Watchdog resources */ +#define ICH_RES_IO_TCO 0 +#define ICH_RES_IO_SMI 1 +#define ICH_RES_MEM_OFF 2 +#define ICH_RES_MEM_GCS 0 + +/* GPIO resources */ +#define ICH_RES_GPIO 0 +#define ICH_RES_GPE0 1 + +/* GPIO compatibility */ +#define ICH_I3100_GPIO 0x401 +#define ICH_V5_GPIO 0x501 +#define ICH_V6_GPIO 0x601 +#define ICH_V7_GPIO 0x701 +#define ICH_V9_GPIO 0x801 +#define ICH_V10CORP_GPIO 0xa01 +#define ICH_V10CONS_GPIO 0xa11 + +struct lpc_ich_info { + char name[32]; + unsigned int iTCO_version; + unsigned int gpio_version; +}; + +#endif diff --git a/include/linux/mfd/max77693-private.h b/include/linux/mfd/max77693-private.h new file mode 100644 index 000000000000..68263c5fa53c --- /dev/null +++ b/include/linux/mfd/max77693-private.h @@ -0,0 +1,227 @@ +/* + * max77693-private.h - Voltage regulator driver for the Maxim 77693 + * + * Copyright (C) 2012 Samsung Electrnoics + * SangYoung Son <hello.son@samsung.com> + * + * This program is not provided / owned by Maxim Integrated Products. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __LINUX_MFD_MAX77693_PRIV_H +#define __LINUX_MFD_MAX77693_PRIV_H + +#include <linux/i2c.h> + +#define MAX77693_NUM_IRQ_MUIC_REGS 3 +#define MAX77693_REG_INVALID (0xff) + +/* Slave addr = 0xCC: PMIC, Charger, Flash LED */ +enum max77693_pmic_reg { + MAX77693_LED_REG_IFLASH1 = 0x00, + MAX77693_LED_REG_IFLASH2 = 0x01, + MAX77693_LED_REG_ITORCH = 0x02, + MAX77693_LED_REG_ITORCHTIMER = 0x03, + MAX77693_LED_REG_FLASH_TIMER = 0x04, + MAX77693_LED_REG_FLASH_EN = 0x05, + MAX77693_LED_REG_MAX_FLASH1 = 0x06, + MAX77693_LED_REG_MAX_FLASH2 = 0x07, + MAX77693_LED_REG_MAX_FLASH3 = 0x08, + MAX77693_LED_REG_MAX_FLASH4 = 0x09, + MAX77693_LED_REG_VOUT_CNTL = 0x0A, + MAX77693_LED_REG_VOUT_FLASH1 = 0x0B, + MAX77693_LED_REG_VOUT_FLASH2 = 0x0C, + MAX77693_LED_REG_FLASH_INT = 0x0E, + MAX77693_LED_REG_FLASH_INT_MASK = 0x0F, + MAX77693_LED_REG_FLASH_INT_STATUS = 0x10, + + MAX77693_PMIC_REG_PMIC_ID1 = 0x20, + MAX77693_PMIC_REG_PMIC_ID2 = 0x21, + MAX77693_PMIC_REG_INTSRC = 0x22, + MAX77693_PMIC_REG_INTSRC_MASK = 0x23, + MAX77693_PMIC_REG_TOPSYS_INT = 0x24, + MAX77693_PMIC_REG_TOPSYS_INT_MASK = 0x26, + MAX77693_PMIC_REG_TOPSYS_STAT = 0x28, + MAX77693_PMIC_REG_MAINCTRL1 = 0x2A, + MAX77693_PMIC_REG_LSCNFG = 0x2B, + + MAX77693_CHG_REG_CHG_INT = 0xB0, + MAX77693_CHG_REG_CHG_INT_MASK = 0xB1, + MAX77693_CHG_REG_CHG_INT_OK = 0xB2, + MAX77693_CHG_REG_CHG_DETAILS_00 = 0xB3, + MAX77693_CHG_REG_CHG_DETAILS_01 = 0xB4, + MAX77693_CHG_REG_CHG_DETAILS_02 = 0xB5, + MAX77693_CHG_REG_CHG_DETAILS_03 = 0xB6, + MAX77693_CHG_REG_CHG_CNFG_00 = 0xB7, + MAX77693_CHG_REG_CHG_CNFG_01 = 0xB8, + MAX77693_CHG_REG_CHG_CNFG_02 = 0xB9, + MAX77693_CHG_REG_CHG_CNFG_03 = 0xBA, + MAX77693_CHG_REG_CHG_CNFG_04 = 0xBB, + MAX77693_CHG_REG_CHG_CNFG_05 = 0xBC, + MAX77693_CHG_REG_CHG_CNFG_06 = 0xBD, + MAX77693_CHG_REG_CHG_CNFG_07 = 0xBE, + MAX77693_CHG_REG_CHG_CNFG_08 = 0xBF, + MAX77693_CHG_REG_CHG_CNFG_09 = 0xC0, + MAX77693_CHG_REG_CHG_CNFG_10 = 0xC1, + MAX77693_CHG_REG_CHG_CNFG_11 = 0xC2, + MAX77693_CHG_REG_CHG_CNFG_12 = 0xC3, + MAX77693_CHG_REG_CHG_CNFG_13 = 0xC4, + MAX77693_CHG_REG_CHG_CNFG_14 = 0xC5, + MAX77693_CHG_REG_SAFEOUT_CTRL = 0xC6, + + MAX77693_PMIC_REG_END, +}; + +/* Slave addr = 0x4A: MUIC */ +enum max77693_muic_reg { + MAX77693_MUIC_REG_ID = 0x00, + MAX77693_MUIC_REG_INT1 = 0x01, + MAX77693_MUIC_REG_INT2 = 0x02, + MAX77693_MUIC_REG_INT3 = 0x03, + MAX77693_MUIC_REG_STATUS1 = 0x04, + MAX77693_MUIC_REG_STATUS2 = 0x05, + MAX77693_MUIC_REG_STATUS3 = 0x06, + MAX77693_MUIC_REG_INTMASK1 = 0x07, + MAX77693_MUIC_REG_INTMASK2 = 0x08, + MAX77693_MUIC_REG_INTMASK3 = 0x09, + MAX77693_MUIC_REG_CDETCTRL1 = 0x0A, + MAX77693_MUIC_REG_CDETCTRL2 = 0x0B, + MAX77693_MUIC_REG_CTRL1 = 0x0C, + MAX77693_MUIC_REG_CTRL2 = 0x0D, + MAX77693_MUIC_REG_CTRL3 = 0x0E, + + MAX77693_MUIC_REG_END, +}; + +/* Slave addr = 0x90: Haptic */ +enum max77693_haptic_reg { + MAX77693_HAPTIC_REG_STATUS = 0x00, + MAX77693_HAPTIC_REG_CONFIG1 = 0x01, + MAX77693_HAPTIC_REG_CONFIG2 = 0x02, + MAX77693_HAPTIC_REG_CONFIG_CHNL = 0x03, + MAX77693_HAPTIC_REG_CONFG_CYC1 = 0x04, + MAX77693_HAPTIC_REG_CONFG_CYC2 = 0x05, + MAX77693_HAPTIC_REG_CONFIG_PER1 = 0x06, + MAX77693_HAPTIC_REG_CONFIG_PER2 = 0x07, + MAX77693_HAPTIC_REG_CONFIG_PER3 = 0x08, + MAX77693_HAPTIC_REG_CONFIG_PER4 = 0x09, + MAX77693_HAPTIC_REG_CONFIG_DUTY1 = 0x0A, + MAX77693_HAPTIC_REG_CONFIG_DUTY2 = 0x0B, + MAX77693_HAPTIC_REG_CONFIG_PWM1 = 0x0C, + MAX77693_HAPTIC_REG_CONFIG_PWM2 = 0x0D, + MAX77693_HAPTIC_REG_CONFIG_PWM3 = 0x0E, + MAX77693_HAPTIC_REG_CONFIG_PWM4 = 0x0F, + MAX77693_HAPTIC_REG_REV = 0x10, + + MAX77693_HAPTIC_REG_END, +}; + +enum max77693_irq_source { + LED_INT = 0, + TOPSYS_INT, + CHG_INT, + MUIC_INT1, + MUIC_INT2, + MUIC_INT3, + + MAX77693_IRQ_GROUP_NR, +}; + +enum max77693_irq { + /* PMIC - FLASH */ + MAX77693_LED_IRQ_FLED2_OPEN, + MAX77693_LED_IRQ_FLED2_SHORT, + MAX77693_LED_IRQ_FLED1_OPEN, + MAX77693_LED_IRQ_FLED1_SHORT, + MAX77693_LED_IRQ_MAX_FLASH, + + /* PMIC - TOPSYS */ + MAX77693_TOPSYS_IRQ_T120C_INT, + MAX77693_TOPSYS_IRQ_T140C_INT, + MAX77693_TOPSYS_IRQ_LOWSYS_INT, + + /* PMIC - Charger */ + MAX77693_CHG_IRQ_BYP_I, + MAX77693_CHG_IRQ_THM_I, + MAX77693_CHG_IRQ_BAT_I, + MAX77693_CHG_IRQ_CHG_I, + MAX77693_CHG_IRQ_CHGIN_I, + + /* MUIC INT1 */ + MAX77693_MUIC_IRQ_INT1_ADC, + MAX77693_MUIC_IRQ_INT1_ADC_LOW, + MAX77693_MUIC_IRQ_INT1_ADC_ERR, + MAX77693_MUIC_IRQ_INT1_ADC1K, + + /* MUIC INT2 */ + MAX77693_MUIC_IRQ_INT2_CHGTYP, + MAX77693_MUIC_IRQ_INT2_CHGDETREUN, + MAX77693_MUIC_IRQ_INT2_DCDTMR, + MAX77693_MUIC_IRQ_INT2_DXOVP, + MAX77693_MUIC_IRQ_INT2_VBVOLT, + MAX77693_MUIC_IRQ_INT2_VIDRM, + + /* MUIC INT3 */ + MAX77693_MUIC_IRQ_INT3_EOC, + MAX77693_MUIC_IRQ_INT3_CGMBC, + MAX77693_MUIC_IRQ_INT3_OVP, + MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR, + MAX77693_MUIC_IRQ_INT3_CHG_ENABLED, + MAX77693_MUIC_IRQ_INT3_BAT_DET, + + MAX77693_IRQ_NR, +}; + +struct max77693_dev { + struct device *dev; + struct i2c_client *i2c; /* 0xCC , PMIC, Charger, Flash LED */ + struct i2c_client *muic; /* 0x4A , MUIC */ + struct i2c_client *haptic; /* 0x90 , Haptic */ + struct mutex iolock; + + int type; + + struct regmap *regmap; + struct regmap *regmap_muic; + struct regmap *regmap_haptic; + + struct irq_domain *irq_domain; + + int irq; + int irq_gpio; + bool wakeup; + struct mutex irqlock; + int irq_masks_cur[MAX77693_IRQ_GROUP_NR]; + int irq_masks_cache[MAX77693_IRQ_GROUP_NR]; +}; + +enum max77693_types { + TYPE_MAX77693, +}; + +extern int max77693_read_reg(struct regmap *map, u8 reg, u8 *dest); +extern int max77693_bulk_read(struct regmap *map, u8 reg, int count, + u8 *buf); +extern int max77693_write_reg(struct regmap *map, u8 reg, u8 value); +extern int max77693_bulk_write(struct regmap *map, u8 reg, int count, + u8 *buf); +extern int max77693_update_reg(struct regmap *map, u8 reg, u8 val, u8 mask); + +extern int max77693_irq_init(struct max77693_dev *max77686); +extern void max77693_irq_exit(struct max77693_dev *max77686); +extern int max77693_irq_resume(struct max77693_dev *max77686); + +#endif /* __LINUX_MFD_MAX77693_PRIV_H */ diff --git a/include/linux/mfd/max77693.h b/include/linux/mfd/max77693.h new file mode 100644 index 000000000000..1d28ae90384e --- /dev/null +++ b/include/linux/mfd/max77693.h @@ -0,0 +1,36 @@ +/* + * max77693.h - Driver for the Maxim 77693 + * + * Copyright (C) 2012 Samsung Electrnoics + * SangYoung Son <hello.son@samsung.com> + * + * This program is not provided / owned by Maxim Integrated Products. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This driver is based on max8997.h + * + * MAX77693 has PMIC, Charger, Flash LED, Haptic, MUIC devices. + * The devices share the same I2C bus and included in + * this mfd driver. + */ + +#ifndef __LINUX_MFD_MAX77693_H +#define __LINUX_MFD_MAX77693_H + +struct max77693_platform_data { + int wakeup; +}; +#endif /* __LINUX_MFD_MAX77693_H */ diff --git a/include/linux/mfd/max8997.h b/include/linux/mfd/max8997.h index 28726dd540f2..b40c08cd30bc 100644 --- a/include/linux/mfd/max8997.h +++ b/include/linux/mfd/max8997.h @@ -99,34 +99,11 @@ struct max8997_muic_reg_data { /** * struct max8997_muic_platform_data - * @usb_callback: callback function for USB - * inform callee of USB type (HOST or DEVICE) - * and attached state(true or false) - * @charger_callback: callback function for charger - * inform callee of charger_type - * and attached state(true or false) - * @deskdock_callback: callback function for desk dock - * inform callee of attached state(true or false) - * @cardock_callback: callback function for car dock - * inform callee of attached state(true or false) - * @mhl_callback: callback function for MHL (Mobile High-definition Link) - * inform callee of attached state(true or false) - * @uart_callback: callback function for JIG UART - * inform callee of attached state(true or false) * @init_data: array of max8997_muic_reg_data * used for initializing registers of MAX8997 MUIC device * @num_init_data: array size of init_data */ struct max8997_muic_platform_data { - void (*usb_callback)(enum max8997_muic_usb_type usb_type, - bool attached); - void (*charger_callback)(bool attached, - enum max8997_muic_charger_type charger_type); - void (*deskdock_callback) (bool attached); - void (*cardock_callback) (bool attached); - void (*mhl_callback) (bool attached); - void (*uart_callback) (bool attached); - struct max8997_muic_reg_data *init_data; int num_init_data; }; diff --git a/include/linux/mfd/mc13xxx.h b/include/linux/mfd/mc13xxx.h index 10e038bac8dd..bf070755982e 100644 --- a/include/linux/mfd/mc13xxx.h +++ b/include/linux/mfd/mc13xxx.h @@ -170,6 +170,16 @@ struct mc13xxx_ts_platform_data { bool atox; }; +enum mc13783_ssi_port { + MC13783_SSI1_PORT, + MC13783_SSI2_PORT, +}; + +struct mc13xxx_codec_platform_data { + enum mc13783_ssi_port adc_ssi_port; + enum mc13783_ssi_port dac_ssi_port; +}; + struct mc13xxx_platform_data { #define MC13XXX_USE_TOUCHSCREEN (1 << 0) #define MC13XXX_USE_CODEC (1 << 1) @@ -181,6 +191,7 @@ struct mc13xxx_platform_data { struct mc13xxx_leds_platform_data *leds; struct mc13xxx_buttons_platform_data *buttons; struct mc13xxx_ts_platform_data touch; + struct mc13xxx_codec_platform_data *codec; }; #define MC13XXX_ADC_MODE_TS 1 diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h new file mode 100644 index 000000000000..9cbc642d40ad --- /dev/null +++ b/include/linux/mfd/palmas.h @@ -0,0 +1,2620 @@ +/* + * TI Palmas + * + * Copyright 2011 Texas Instruments Inc. + * + * Author: Graeme Gregory <gg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __LINUX_MFD_PALMAS_H +#define __LINUX_MFD_PALMAS_H + +#include <linux/usb/otg.h> +#include <linux/leds.h> +#include <linux/regmap.h> +#include <linux/regulator/driver.h> + +#define PALMAS_NUM_CLIENTS 3 + +struct palmas_pmic; + +struct palmas { + struct device *dev; + + struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS]; + struct regmap *regmap[PALMAS_NUM_CLIENTS]; + + /* Stored chip id */ + int id; + + /* IRQ Data */ + int irq; + u32 irq_mask; + struct mutex irq_lock; + struct regmap_irq_chip_data *irq_data; + + /* Child Devices */ + struct palmas_pmic *pmic; + + /* GPIO MUXing */ + u8 gpio_muxed; + u8 led_muxed; + u8 pwm_muxed; +}; + +struct palmas_reg_init { + /* warm_rest controls the voltage levels after a warm reset + * + * 0: reload default values from OTP on warm reset + * 1: maintain voltage from VSEL on warm reset + */ + int warm_reset; + + /* roof_floor controls whether the regulator uses the i2c style + * of DVS or uses the method where a GPIO or other control method is + * attached to the NSLEEP/ENABLE1/ENABLE2 pins + * + * For SMPS + * + * 0: i2c selection of voltage + * 1: pin selection of voltage. + * + * For LDO unused + */ + int roof_floor; + + /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in + * the data sheet. + * + * For SMPS + * + * 0: Off + * 1: AUTO + * 2: ECO + * 3: Forced PWM + * + * For LDO + * + * 0: Off + * 1: On + */ + int mode_sleep; + + /* tstep is the timestep loaded to the TSTEP register + * + * For SMPS + * + * 0: Jump (no slope control) + * 1: 10mV/us + * 2: 5mV/us + * 3: 2.5mV/us + * + * For LDO unused + */ + int tstep; + + /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE + * register. Set this is the default voltage set in OTP needs + * to be overridden. + */ + u8 vsel; + +}; + +struct palmas_pmic_platform_data { + /* An array of pointers to regulator init data indexed by regulator + * ID + */ + struct regulator_init_data **reg_data; + + /* An array of pointers to structures containing sleep mode and DVS + * configuration for regulators indexed by ID + */ + struct palmas_reg_init **reg_init; + + /* use LDO6 for vibrator control */ + int ldo6_vibrator; + + +}; + +struct palmas_platform_data { + int gpio_base; + + /* bit value to be loaded to the POWER_CTRL register */ + u8 power_ctrl; + + /* + * boolean to select if we want to configure muxing here + * then the two value to load into the registers if true + */ + int mux_from_pdata; + u8 pad1, pad2; + + struct palmas_pmic_platform_data *pmic_pdata; +}; + +/* Define the palmas IRQ numbers */ +enum palmas_irqs { + /* INT1 registers */ + PALMAS_CHARG_DET_N_VBUS_OVV_IRQ, + PALMAS_PWRON_IRQ, + PALMAS_LONG_PRESS_KEY_IRQ, + PALMAS_RPWRON_IRQ, + PALMAS_PWRDOWN_IRQ, + PALMAS_HOTDIE_IRQ, + PALMAS_VSYS_MON_IRQ, + PALMAS_VBAT_MON_IRQ, + /* INT2 registers */ + PALMAS_RTC_ALARM_IRQ, + PALMAS_RTC_TIMER_IRQ, + PALMAS_WDT_IRQ, + PALMAS_BATREMOVAL_IRQ, + PALMAS_RESET_IN_IRQ, + PALMAS_FBI_BB_IRQ, + PALMAS_SHORT_IRQ, + PALMAS_VAC_ACOK_IRQ, + /* INT3 registers */ + PALMAS_GPADC_AUTO_0_IRQ, + PALMAS_GPADC_AUTO_1_IRQ, + PALMAS_GPADC_EOC_SW_IRQ, + PALMAS_GPADC_EOC_RT_IRQ, + PALMAS_ID_OTG_IRQ, + PALMAS_ID_IRQ, + PALMAS_VBUS_OTG_IRQ, + PALMAS_VBUS_IRQ, + /* INT4 registers */ + PALMAS_GPIO_0_IRQ, + PALMAS_GPIO_1_IRQ, + PALMAS_GPIO_2_IRQ, + PALMAS_GPIO_3_IRQ, + PALMAS_GPIO_4_IRQ, + PALMAS_GPIO_5_IRQ, + PALMAS_GPIO_6_IRQ, + PALMAS_GPIO_7_IRQ, + /* Total Number IRQs */ + PALMAS_NUM_IRQ, +}; + +enum palmas_regulators { + /* SMPS regulators */ + PALMAS_REG_SMPS12, + PALMAS_REG_SMPS123, + PALMAS_REG_SMPS3, + PALMAS_REG_SMPS45, + PALMAS_REG_SMPS457, + PALMAS_REG_SMPS6, + PALMAS_REG_SMPS7, + PALMAS_REG_SMPS8, + PALMAS_REG_SMPS9, + PALMAS_REG_SMPS10, + /* LDO regulators */ + PALMAS_REG_LDO1, + PALMAS_REG_LDO2, + PALMAS_REG_LDO3, + PALMAS_REG_LDO4, + PALMAS_REG_LDO5, + PALMAS_REG_LDO6, + PALMAS_REG_LDO7, + PALMAS_REG_LDO8, + PALMAS_REG_LDO9, + PALMAS_REG_LDOLN, + PALMAS_REG_LDOUSB, + /* Total number of regulators */ + PALMAS_NUM_REGS, +}; + +struct palmas_pmic { + struct palmas *palmas; + struct device *dev; + struct regulator_desc desc[PALMAS_NUM_REGS]; + struct regulator_dev *rdev[PALMAS_NUM_REGS]; + struct mutex mutex; + + int smps123; + int smps457; + + int range[PALMAS_REG_SMPS10]; +}; + +/* defines so we can store the mux settings */ +#define PALMAS_GPIO_0_MUXED (1 << 0) +#define PALMAS_GPIO_1_MUXED (1 << 1) +#define PALMAS_GPIO_2_MUXED (1 << 2) +#define PALMAS_GPIO_3_MUXED (1 << 3) +#define PALMAS_GPIO_4_MUXED (1 << 4) +#define PALMAS_GPIO_5_MUXED (1 << 5) +#define PALMAS_GPIO_6_MUXED (1 << 6) +#define PALMAS_GPIO_7_MUXED (1 << 7) + +#define PALMAS_LED1_MUXED (1 << 0) +#define PALMAS_LED2_MUXED (1 << 1) + +#define PALMAS_PWM1_MUXED (1 << 0) +#define PALMAS_PWM2_MUXED (1 << 1) + +/* helper macro to get correct slave number */ +#define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1) +#define PALMAS_BASE_TO_REG(x, y) ((x & 0xff) + y) + +/* Base addresses of IP blocks in Palmas */ +#define PALMAS_SMPS_DVS_BASE 0x20 +#define PALMAS_RTC_BASE 0x100 +#define PALMAS_VALIDITY_BASE 0x118 +#define PALMAS_SMPS_BASE 0x120 +#define PALMAS_LDO_BASE 0x150 +#define PALMAS_DVFS_BASE 0x180 +#define PALMAS_PMU_CONTROL_BASE 0x1A0 +#define PALMAS_RESOURCE_BASE 0x1D4 +#define PALMAS_PU_PD_OD_BASE 0x1F4 +#define PALMAS_LED_BASE 0x200 +#define PALMAS_INTERRUPT_BASE 0x210 +#define PALMAS_USB_OTG_BASE 0x250 +#define PALMAS_VIBRATOR_BASE 0x270 +#define PALMAS_GPIO_BASE 0x280 +#define PALMAS_USB_BASE 0x290 +#define PALMAS_GPADC_BASE 0x2C0 +#define PALMAS_TRIM_GPADC_BASE 0x3CD + +/* Registers for function RTC */ +#define PALMAS_SECONDS_REG 0x0 +#define PALMAS_MINUTES_REG 0x1 +#define PALMAS_HOURS_REG 0x2 +#define PALMAS_DAYS_REG 0x3 +#define PALMAS_MONTHS_REG 0x4 +#define PALMAS_YEARS_REG 0x5 +#define PALMAS_WEEKS_REG 0x6 +#define PALMAS_ALARM_SECONDS_REG 0x8 +#define PALMAS_ALARM_MINUTES_REG 0x9 +#define PALMAS_ALARM_HOURS_REG 0xA +#define PALMAS_ALARM_DAYS_REG 0xB +#define PALMAS_ALARM_MONTHS_REG 0xC +#define PALMAS_ALARM_YEARS_REG 0xD +#define PALMAS_RTC_CTRL_REG 0x10 +#define PALMAS_RTC_STATUS_REG 0x11 +#define PALMAS_RTC_INTERRUPTS_REG 0x12 +#define PALMAS_RTC_COMP_LSB_REG 0x13 +#define PALMAS_RTC_COMP_MSB_REG 0x14 +#define PALMAS_RTC_RES_PROG_REG 0x15 +#define PALMAS_RTC_RESET_STATUS_REG 0x16 + +/* Bit definitions for SECONDS_REG */ +#define PALMAS_SECONDS_REG_SEC1_MASK 0x70 +#define PALMAS_SECONDS_REG_SEC1_SHIFT 4 +#define PALMAS_SECONDS_REG_SEC0_MASK 0x0f +#define PALMAS_SECONDS_REG_SEC0_SHIFT 0 + +/* Bit definitions for MINUTES_REG */ +#define PALMAS_MINUTES_REG_MIN1_MASK 0x70 +#define PALMAS_MINUTES_REG_MIN1_SHIFT 4 +#define PALMAS_MINUTES_REG_MIN0_MASK 0x0f +#define PALMAS_MINUTES_REG_MIN0_SHIFT 0 + +/* Bit definitions for HOURS_REG */ +#define PALMAS_HOURS_REG_PM_NAM 0x80 +#define PALMAS_HOURS_REG_PM_NAM_SHIFT 7 +#define PALMAS_HOURS_REG_HOUR1_MASK 0x30 +#define PALMAS_HOURS_REG_HOUR1_SHIFT 4 +#define PALMAS_HOURS_REG_HOUR0_MASK 0x0f +#define PALMAS_HOURS_REG_HOUR0_SHIFT 0 + +/* Bit definitions for DAYS_REG */ +#define PALMAS_DAYS_REG_DAY1_MASK 0x30 +#define PALMAS_DAYS_REG_DAY1_SHIFT 4 +#define PALMAS_DAYS_REG_DAY0_MASK 0x0f +#define PALMAS_DAYS_REG_DAY0_SHIFT 0 + +/* Bit definitions for MONTHS_REG */ +#define PALMAS_MONTHS_REG_MONTH1 0x10 +#define PALMAS_MONTHS_REG_MONTH1_SHIFT 4 +#define PALMAS_MONTHS_REG_MONTH0_MASK 0x0f +#define PALMAS_MONTHS_REG_MONTH0_SHIFT 0 + +/* Bit definitions for YEARS_REG */ +#define PALMAS_YEARS_REG_YEAR1_MASK 0xf0 +#define PALMAS_YEARS_REG_YEAR1_SHIFT 4 +#define PALMAS_YEARS_REG_YEAR0_MASK 0x0f +#define PALMAS_YEARS_REG_YEAR0_SHIFT 0 + +/* Bit definitions for WEEKS_REG */ +#define PALMAS_WEEKS_REG_WEEK_MASK 0x07 +#define PALMAS_WEEKS_REG_WEEK_SHIFT 0 + +/* Bit definitions for ALARM_SECONDS_REG */ +#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70 +#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 4 +#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0f +#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0 + +/* Bit definitions for ALARM_MINUTES_REG */ +#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70 +#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 4 +#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0f +#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0 + +/* Bit definitions for ALARM_HOURS_REG */ +#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80 +#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 7 +#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30 +#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 4 +#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0f +#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0 + +/* Bit definitions for ALARM_DAYS_REG */ +#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30 +#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 4 +#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0f +#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0 + +/* Bit definitions for ALARM_MONTHS_REG */ +#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10 +#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 4 +#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0f +#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0 + +/* Bit definitions for ALARM_YEARS_REG */ +#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0 +#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 4 +#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0f +#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0 + +/* Bit definitions for RTC_CTRL_REG */ +#define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80 +#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 7 +#define PALMAS_RTC_CTRL_REG_GET_TIME 0x40 +#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 6 +#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20 +#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 5 +#define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10 +#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 4 +#define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08 +#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 3 +#define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04 +#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 2 +#define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02 +#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 1 +#define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01 +#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0 + +/* Bit definitions for RTC_STATUS_REG */ +#define PALMAS_RTC_STATUS_REG_POWER_UP 0x80 +#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 7 +#define PALMAS_RTC_STATUS_REG_ALARM 0x40 +#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 6 +#define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20 +#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 5 +#define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10 +#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 4 +#define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08 +#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 3 +#define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04 +#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 2 +#define PALMAS_RTC_STATUS_REG_RUN 0x02 +#define PALMAS_RTC_STATUS_REG_RUN_SHIFT 1 + +/* Bit definitions for RTC_INTERRUPTS_REG */ +#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10 +#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 4 +#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08 +#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 3 +#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04 +#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 2 +#define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03 +#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0 + +/* Bit definitions for RTC_COMP_LSB_REG */ +#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xff +#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0 + +/* Bit definitions for RTC_COMP_MSB_REG */ +#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xff +#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0 + +/* Bit definitions for RTC_RES_PROG_REG */ +#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3f +#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0 + +/* Bit definitions for RTC_RESET_STATUS_REG */ +#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01 +#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0 + +/* Registers for function BACKUP */ +#define PALMAS_BACKUP0 0x0 +#define PALMAS_BACKUP1 0x1 +#define PALMAS_BACKUP2 0x2 +#define PALMAS_BACKUP3 0x3 +#define PALMAS_BACKUP4 0x4 +#define PALMAS_BACKUP5 0x5 +#define PALMAS_BACKUP6 0x6 +#define PALMAS_BACKUP7 0x7 + +/* Bit definitions for BACKUP0 */ +#define PALMAS_BACKUP0_BACKUP_MASK 0xff +#define PALMAS_BACKUP0_BACKUP_SHIFT 0 + +/* Bit definitions for BACKUP1 */ +#define PALMAS_BACKUP1_BACKUP_MASK 0xff +#define PALMAS_BACKUP1_BACKUP_SHIFT 0 + +/* Bit definitions for BACKUP2 */ +#define PALMAS_BACKUP2_BACKUP_MASK 0xff +#define PALMAS_BACKUP2_BACKUP_SHIFT 0 + +/* Bit definitions for BACKUP3 */ +#define PALMAS_BACKUP3_BACKUP_MASK 0xff +#define PALMAS_BACKUP3_BACKUP_SHIFT 0 + +/* Bit definitions for BACKUP4 */ +#define PALMAS_BACKUP4_BACKUP_MASK 0xff +#define PALMAS_BACKUP4_BACKUP_SHIFT 0 + +/* Bit definitions for BACKUP5 */ +#define PALMAS_BACKUP5_BACKUP_MASK 0xff +#define PALMAS_BACKUP5_BACKUP_SHIFT 0 + +/* Bit definitions for BACKUP6 */ +#define PALMAS_BACKUP6_BACKUP_MASK 0xff +#define PALMAS_BACKUP6_BACKUP_SHIFT 0 + +/* Bit definitions for BACKUP7 */ +#define PALMAS_BACKUP7_BACKUP_MASK 0xff +#define PALMAS_BACKUP7_BACKUP_SHIFT 0 + +/* Registers for function SMPS */ +#define PALMAS_SMPS12_CTRL 0x0 +#define PALMAS_SMPS12_TSTEP 0x1 +#define PALMAS_SMPS12_FORCE 0x2 +#define PALMAS_SMPS12_VOLTAGE 0x3 +#define PALMAS_SMPS3_CTRL 0x4 +#define PALMAS_SMPS3_VOLTAGE 0x7 +#define PALMAS_SMPS45_CTRL 0x8 +#define PALMAS_SMPS45_TSTEP 0x9 +#define PALMAS_SMPS45_FORCE 0xA +#define PALMAS_SMPS45_VOLTAGE 0xB +#define PALMAS_SMPS6_CTRL 0xC +#define PALMAS_SMPS6_TSTEP 0xD +#define PALMAS_SMPS6_FORCE 0xE +#define PALMAS_SMPS6_VOLTAGE 0xF +#define PALMAS_SMPS7_CTRL 0x10 +#define PALMAS_SMPS7_VOLTAGE 0x13 +#define PALMAS_SMPS8_CTRL 0x14 +#define PALMAS_SMPS8_TSTEP 0x15 +#define PALMAS_SMPS8_FORCE 0x16 +#define PALMAS_SMPS8_VOLTAGE 0x17 +#define PALMAS_SMPS9_CTRL 0x18 +#define PALMAS_SMPS9_VOLTAGE 0x1B +#define PALMAS_SMPS10_CTRL 0x1C +#define PALMAS_SMPS10_STATUS 0x1F +#define PALMAS_SMPS_CTRL 0x24 +#define PALMAS_SMPS_PD_CTRL 0x25 +#define PALMAS_SMPS_DITHER_EN 0x26 +#define PALMAS_SMPS_THERMAL_EN 0x27 +#define PALMAS_SMPS_THERMAL_STATUS 0x28 +#define PALMAS_SMPS_SHORT_STATUS 0x29 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A +#define PALMAS_SMPS_POWERGOOD_MASK1 0x2B +#define PALMAS_SMPS_POWERGOOD_MASK2 0x2C + +/* Bit definitions for SMPS12_CTRL */ +#define PALMAS_SMPS12_CTRL_WR_S 0x80 +#define PALMAS_SMPS12_CTRL_WR_S_SHIFT 7 +#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40 +#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 6 +#define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30 +#define PALMAS_SMPS12_CTRL_STATUS_SHIFT 4 +#define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c +#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03 +#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for SMPS12_TSTEP */ +#define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03 +#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0 + +/* Bit definitions for SMPS12_FORCE */ +#define PALMAS_SMPS12_FORCE_CMD 0x80 +#define PALMAS_SMPS12_FORCE_CMD_SHIFT 7 +#define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7f +#define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0 + +/* Bit definitions for SMPS12_VOLTAGE */ +#define PALMAS_SMPS12_VOLTAGE_RANGE 0x80 +#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 7 +#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7f +#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for SMPS3_CTRL */ +#define PALMAS_SMPS3_CTRL_WR_S 0x80 +#define PALMAS_SMPS3_CTRL_WR_S_SHIFT 7 +#define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30 +#define PALMAS_SMPS3_CTRL_STATUS_SHIFT 4 +#define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c +#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 +#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for SMPS3_VOLTAGE */ +#define PALMAS_SMPS3_VOLTAGE_RANGE 0x80 +#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 7 +#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7f +#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for SMPS45_CTRL */ +#define PALMAS_SMPS45_CTRL_WR_S 0x80 +#define PALMAS_SMPS45_CTRL_WR_S_SHIFT 7 +#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40 +#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 6 +#define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30 +#define PALMAS_SMPS45_CTRL_STATUS_SHIFT 4 +#define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c +#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03 +#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for SMPS45_TSTEP */ +#define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03 +#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0 + +/* Bit definitions for SMPS45_FORCE */ +#define PALMAS_SMPS45_FORCE_CMD 0x80 +#define PALMAS_SMPS45_FORCE_CMD_SHIFT 7 +#define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7f +#define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0 + +/* Bit definitions for SMPS45_VOLTAGE */ +#define PALMAS_SMPS45_VOLTAGE_RANGE 0x80 +#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 7 +#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7f +#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for SMPS6_CTRL */ +#define PALMAS_SMPS6_CTRL_WR_S 0x80 +#define PALMAS_SMPS6_CTRL_WR_S_SHIFT 7 +#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40 +#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 6 +#define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30 +#define PALMAS_SMPS6_CTRL_STATUS_SHIFT 4 +#define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c +#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03 +#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for SMPS6_TSTEP */ +#define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03 +#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0 + +/* Bit definitions for SMPS6_FORCE */ +#define PALMAS_SMPS6_FORCE_CMD 0x80 +#define PALMAS_SMPS6_FORCE_CMD_SHIFT 7 +#define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7f +#define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0 + +/* Bit definitions for SMPS6_VOLTAGE */ +#define PALMAS_SMPS6_VOLTAGE_RANGE 0x80 +#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 7 +#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7f +#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for SMPS7_CTRL */ +#define PALMAS_SMPS7_CTRL_WR_S 0x80 +#define PALMAS_SMPS7_CTRL_WR_S_SHIFT 7 +#define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30 +#define PALMAS_SMPS7_CTRL_STATUS_SHIFT 4 +#define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c +#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03 +#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for SMPS7_VOLTAGE */ +#define PALMAS_SMPS7_VOLTAGE_RANGE 0x80 +#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 7 +#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7f +#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for SMPS8_CTRL */ +#define PALMAS_SMPS8_CTRL_WR_S 0x80 +#define PALMAS_SMPS8_CTRL_WR_S_SHIFT 7 +#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40 +#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 6 +#define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30 +#define PALMAS_SMPS8_CTRL_STATUS_SHIFT 4 +#define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c +#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03 +#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for SMPS8_TSTEP */ +#define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03 +#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0 + +/* Bit definitions for SMPS8_FORCE */ +#define PALMAS_SMPS8_FORCE_CMD 0x80 +#define PALMAS_SMPS8_FORCE_CMD_SHIFT 7 +#define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7f +#define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0 + +/* Bit definitions for SMPS8_VOLTAGE */ +#define PALMAS_SMPS8_VOLTAGE_RANGE 0x80 +#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 7 +#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7f +#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for SMPS9_CTRL */ +#define PALMAS_SMPS9_CTRL_WR_S 0x80 +#define PALMAS_SMPS9_CTRL_WR_S_SHIFT 7 +#define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30 +#define PALMAS_SMPS9_CTRL_STATUS_SHIFT 4 +#define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c +#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03 +#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for SMPS9_VOLTAGE */ +#define PALMAS_SMPS9_VOLTAGE_RANGE 0x80 +#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 7 +#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7f +#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for SMPS10_CTRL */ +#define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0 +#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 4 +#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0f +#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for SMPS10_STATUS */ +#define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0f +#define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0 + +/* Bit definitions for SMPS_CTRL */ +#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20 +#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 5 +#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10 +#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 4 +#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c +#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 2 +#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03 +#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0 + +/* Bit definitions for SMPS_PD_CTRL */ +#define PALMAS_SMPS_PD_CTRL_SMPS9 0x40 +#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 6 +#define PALMAS_SMPS_PD_CTRL_SMPS8 0x20 +#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 5 +#define PALMAS_SMPS_PD_CTRL_SMPS7 0x10 +#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 4 +#define PALMAS_SMPS_PD_CTRL_SMPS6 0x08 +#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 3 +#define PALMAS_SMPS_PD_CTRL_SMPS45 0x04 +#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 2 +#define PALMAS_SMPS_PD_CTRL_SMPS3 0x02 +#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 1 +#define PALMAS_SMPS_PD_CTRL_SMPS12 0x01 +#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0 + +/* Bit definitions for SMPS_THERMAL_EN */ +#define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40 +#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 6 +#define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20 +#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 5 +#define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08 +#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 3 +#define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04 +#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 2 +#define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01 +#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0 + +/* Bit definitions for SMPS_THERMAL_STATUS */ +#define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 6 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 5 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 3 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 2 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0 + +/* Bit definitions for SMPS_SHORT_STATUS */ +#define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80 +#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 7 +#define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40 +#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 6 +#define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20 +#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 5 +#define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10 +#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 4 +#define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08 +#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 3 +#define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04 +#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 2 +#define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02 +#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 1 +#define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01 +#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0 + +/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 6 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 5 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 4 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 3 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 2 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 1 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0 + +/* Bit definitions for SMPS_POWERGOOD_MASK1 */ +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 7 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 6 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 5 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 4 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 3 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 2 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 1 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0 + +/* Bit definitions for SMPS_POWERGOOD_MASK2 */ +#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 +#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7 +#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04 +#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 2 +#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02 +#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 1 +#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01 +#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0 + +/* Registers for function LDO */ +#define PALMAS_LDO1_CTRL 0x0 +#define PALMAS_LDO1_VOLTAGE 0x1 +#define PALMAS_LDO2_CTRL 0x2 +#define PALMAS_LDO2_VOLTAGE 0x3 +#define PALMAS_LDO3_CTRL 0x4 +#define PALMAS_LDO3_VOLTAGE 0x5 +#define PALMAS_LDO4_CTRL 0x6 +#define PALMAS_LDO4_VOLTAGE 0x7 +#define PALMAS_LDO5_CTRL 0x8 +#define PALMAS_LDO5_VOLTAGE 0x9 +#define PALMAS_LDO6_CTRL 0xA +#define PALMAS_LDO6_VOLTAGE 0xB +#define PALMAS_LDO7_CTRL 0xC +#define PALMAS_LDO7_VOLTAGE 0xD +#define PALMAS_LDO8_CTRL 0xE +#define PALMAS_LDO8_VOLTAGE 0xF +#define PALMAS_LDO9_CTRL 0x10 +#define PALMAS_LDO9_VOLTAGE 0x11 +#define PALMAS_LDOLN_CTRL 0x12 +#define PALMAS_LDOLN_VOLTAGE 0x13 +#define PALMAS_LDOUSB_CTRL 0x14 +#define PALMAS_LDOUSB_VOLTAGE 0x15 +#define PALMAS_LDO_CTRL 0x1A +#define PALMAS_LDO_PD_CTRL1 0x1B +#define PALMAS_LDO_PD_CTRL2 0x1C +#define PALMAS_LDO_SHORT_STATUS1 0x1D +#define PALMAS_LDO_SHORT_STATUS2 0x1E + +/* Bit definitions for LDO1_CTRL */ +#define PALMAS_LDO1_CTRL_WR_S 0x80 +#define PALMAS_LDO1_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO1_CTRL_STATUS 0x10 +#define PALMAS_LDO1_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04 +#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for LDO1_VOLTAGE */ +#define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3f +#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for LDO2_CTRL */ +#define PALMAS_LDO2_CTRL_WR_S 0x80 +#define PALMAS_LDO2_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO2_CTRL_STATUS 0x10 +#define PALMAS_LDO2_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04 +#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for LDO2_VOLTAGE */ +#define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3f +#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for LDO3_CTRL */ +#define PALMAS_LDO3_CTRL_WR_S 0x80 +#define PALMAS_LDO3_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO3_CTRL_STATUS 0x10 +#define PALMAS_LDO3_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04 +#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for LDO3_VOLTAGE */ +#define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3f +#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for LDO4_CTRL */ +#define PALMAS_LDO4_CTRL_WR_S 0x80 +#define PALMAS_LDO4_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO4_CTRL_STATUS 0x10 +#define PALMAS_LDO4_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04 +#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for LDO4_VOLTAGE */ +#define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3f +#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for LDO5_CTRL */ +#define PALMAS_LDO5_CTRL_WR_S 0x80 +#define PALMAS_LDO5_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO5_CTRL_STATUS 0x10 +#define PALMAS_LDO5_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04 +#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for LDO5_VOLTAGE */ +#define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3f +#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for LDO6_CTRL */ +#define PALMAS_LDO6_CTRL_WR_S 0x80 +#define PALMAS_LDO6_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40 +#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 6 +#define PALMAS_LDO6_CTRL_STATUS 0x10 +#define PALMAS_LDO6_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04 +#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for LDO6_VOLTAGE */ +#define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3f +#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for LDO7_CTRL */ +#define PALMAS_LDO7_CTRL_WR_S 0x80 +#define PALMAS_LDO7_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO7_CTRL_STATUS 0x10 +#define PALMAS_LDO7_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04 +#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for LDO7_VOLTAGE */ +#define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3f +#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for LDO8_CTRL */ +#define PALMAS_LDO8_CTRL_WR_S 0x80 +#define PALMAS_LDO8_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40 +#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 6 +#define PALMAS_LDO8_CTRL_STATUS 0x10 +#define PALMAS_LDO8_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04 +#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for LDO8_VOLTAGE */ +#define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3f +#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for LDO9_CTRL */ +#define PALMAS_LDO9_CTRL_WR_S 0x80 +#define PALMAS_LDO9_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40 +#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 6 +#define PALMAS_LDO9_CTRL_STATUS 0x10 +#define PALMAS_LDO9_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04 +#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for LDO9_VOLTAGE */ +#define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3f +#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for LDOLN_CTRL */ +#define PALMAS_LDOLN_CTRL_WR_S 0x80 +#define PALMAS_LDOLN_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDOLN_CTRL_STATUS 0x10 +#define PALMAS_LDOLN_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04 +#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for LDOLN_VOLTAGE */ +#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3f +#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for LDOUSB_CTRL */ +#define PALMAS_LDOUSB_CTRL_WR_S 0x80 +#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDOUSB_CTRL_STATUS 0x10 +#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04 +#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for LDOUSB_VOLTAGE */ +#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3f +#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0 + +/* Bit definitions for LDO_CTRL */ +#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01 +#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0 + +/* Bit definitions for LDO_PD_CTRL1 */ +#define PALMAS_LDO_PD_CTRL1_LDO8 0x80 +#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 7 +#define PALMAS_LDO_PD_CTRL1_LDO7 0x40 +#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 6 +#define PALMAS_LDO_PD_CTRL1_LDO6 0x20 +#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 5 +#define PALMAS_LDO_PD_CTRL1_LDO5 0x10 +#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 4 +#define PALMAS_LDO_PD_CTRL1_LDO4 0x08 +#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 3 +#define PALMAS_LDO_PD_CTRL1_LDO3 0x04 +#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 2 +#define PALMAS_LDO_PD_CTRL1_LDO2 0x02 +#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 1 +#define PALMAS_LDO_PD_CTRL1_LDO1 0x01 +#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0 + +/* Bit definitions for LDO_PD_CTRL2 */ +#define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04 +#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 2 +#define PALMAS_LDO_PD_CTRL2_LDOLN 0x02 +#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 1 +#define PALMAS_LDO_PD_CTRL2_LDO9 0x01 +#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0 + +/* Bit definitions for LDO_SHORT_STATUS1 */ +#define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80 +#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 7 +#define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40 +#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 6 +#define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20 +#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 5 +#define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10 +#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 4 +#define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08 +#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 3 +#define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04 +#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 2 +#define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02 +#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 1 +#define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01 +#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0 + +/* Bit definitions for LDO_SHORT_STATUS2 */ +#define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08 +#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 3 +#define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04 +#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 2 +#define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02 +#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 1 +#define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01 +#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0 + +/* Registers for function PMU_CONTROL */ +#define PALMAS_DEV_CTRL 0x0 +#define PALMAS_POWER_CTRL 0x1 +#define PALMAS_VSYS_LO 0x2 +#define PALMAS_VSYS_MON 0x3 +#define PALMAS_VBAT_MON 0x4 +#define PALMAS_WATCHDOG 0x5 +#define PALMAS_BOOT_STATUS 0x6 +#define PALMAS_BATTERY_BOUNCE 0x7 +#define PALMAS_BACKUP_BATTERY_CTRL 0x8 +#define PALMAS_LONG_PRESS_KEY 0x9 +#define PALMAS_OSC_THERM_CTRL 0xA +#define PALMAS_BATDEBOUNCING 0xB +#define PALMAS_SWOFF_HWRST 0xF +#define PALMAS_SWOFF_COLDRST 0x10 +#define PALMAS_SWOFF_STATUS 0x11 +#define PALMAS_PMU_CONFIG 0x12 +#define PALMAS_SPARE 0x14 +#define PALMAS_PMU_SECONDARY_INT 0x15 +#define PALMAS_SW_REVISION 0x17 +#define PALMAS_EXT_CHRG_CTRL 0x18 +#define PALMAS_PMU_SECONDARY_INT2 0x19 + +/* Bit definitions for DEV_CTRL */ +#define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c +#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 2 +#define PALMAS_DEV_CTRL_SW_RST 0x02 +#define PALMAS_DEV_CTRL_SW_RST_SHIFT 1 +#define PALMAS_DEV_CTRL_DEV_ON 0x01 +#define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0 + +/* Bit definitions for POWER_CTRL */ +#define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04 +#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 2 +#define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02 +#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 1 +#define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01 +#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0 + +/* Bit definitions for VSYS_LO */ +#define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1f +#define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0 + +/* Bit definitions for VSYS_MON */ +#define PALMAS_VSYS_MON_ENABLE 0x80 +#define PALMAS_VSYS_MON_ENABLE_SHIFT 7 +#define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3f +#define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0 + +/* Bit definitions for VBAT_MON */ +#define PALMAS_VBAT_MON_ENABLE 0x80 +#define PALMAS_VBAT_MON_ENABLE_SHIFT 7 +#define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3f +#define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0 + +/* Bit definitions for WATCHDOG */ +#define PALMAS_WATCHDOG_LOCK 0x20 +#define PALMAS_WATCHDOG_LOCK_SHIFT 5 +#define PALMAS_WATCHDOG_ENABLE 0x10 +#define PALMAS_WATCHDOG_ENABLE_SHIFT 4 +#define PALMAS_WATCHDOG_MODE 0x08 +#define PALMAS_WATCHDOG_MODE_SHIFT 3 +#define PALMAS_WATCHDOG_TIMER_MASK 0x07 +#define PALMAS_WATCHDOG_TIMER_SHIFT 0 + +/* Bit definitions for BOOT_STATUS */ +#define PALMAS_BOOT_STATUS_BOOT1 0x02 +#define PALMAS_BOOT_STATUS_BOOT1_SHIFT 1 +#define PALMAS_BOOT_STATUS_BOOT0 0x01 +#define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0 + +/* Bit definitions for BATTERY_BOUNCE */ +#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3f +#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0 + +/* Bit definitions for BACKUP_BATTERY_CTRL */ +#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80 +#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 7 +#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40 +#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 6 +#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20 +#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 5 +#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10 +#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 4 +#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08 +#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 3 +#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06 +#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 1 +#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01 +#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0 + +/* Bit definitions for LONG_PRESS_KEY */ +#define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80 +#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 7 +#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10 +#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 4 +#define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c +#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 2 +#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03 +#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0 + +/* Bit definitions for OSC_THERM_CTRL */ +#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80 +#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 7 +#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40 +#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 6 +#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20 +#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 5 +#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10 +#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 4 +#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c +#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 2 +#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02 +#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 1 +#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01 +#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0 + +/* Bit definitions for BATDEBOUNCING */ +#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80 +#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 7 +#define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78 +#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 3 +#define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07 +#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0 + +/* Bit definitions for SWOFF_HWRST */ +#define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80 +#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 7 +#define PALMAS_SWOFF_HWRST_PWRDOWN 0x40 +#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 6 +#define PALMAS_SWOFF_HWRST_WTD 0x20 +#define PALMAS_SWOFF_HWRST_WTD_SHIFT 5 +#define PALMAS_SWOFF_HWRST_TSHUT 0x10 +#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 4 +#define PALMAS_SWOFF_HWRST_RESET_IN 0x08 +#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 3 +#define PALMAS_SWOFF_HWRST_SW_RST 0x04 +#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 2 +#define PALMAS_SWOFF_HWRST_VSYS_LO 0x02 +#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 1 +#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01 +#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0 + +/* Bit definitions for SWOFF_COLDRST */ +#define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80 +#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 7 +#define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40 +#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 6 +#define PALMAS_SWOFF_COLDRST_WTD 0x20 +#define PALMAS_SWOFF_COLDRST_WTD_SHIFT 5 +#define PALMAS_SWOFF_COLDRST_TSHUT 0x10 +#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 4 +#define PALMAS_SWOFF_COLDRST_RESET_IN 0x08 +#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 3 +#define PALMAS_SWOFF_COLDRST_SW_RST 0x04 +#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 2 +#define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02 +#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 1 +#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01 +#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0 + +/* Bit definitions for SWOFF_STATUS */ +#define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80 +#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 7 +#define PALMAS_SWOFF_STATUS_PWRDOWN 0x40 +#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 6 +#define PALMAS_SWOFF_STATUS_WTD 0x20 +#define PALMAS_SWOFF_STATUS_WTD_SHIFT 5 +#define PALMAS_SWOFF_STATUS_TSHUT 0x10 +#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 4 +#define PALMAS_SWOFF_STATUS_RESET_IN 0x08 +#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 3 +#define PALMAS_SWOFF_STATUS_SW_RST 0x04 +#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 2 +#define PALMAS_SWOFF_STATUS_VSYS_LO 0x02 +#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 1 +#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01 +#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0 + +/* Bit definitions for PMU_CONFIG */ +#define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40 +#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 6 +#define PALMAS_PMU_CONFIG_SPARE_MASK 0x30 +#define PALMAS_PMU_CONFIG_SPARE_SHIFT 4 +#define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c +#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 2 +#define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02 +#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 1 +#define PALMAS_PMU_CONFIG_AUTODEVON 0x01 +#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0 + +/* Bit definitions for SPARE */ +#define PALMAS_SPARE_SPARE_MASK 0xf8 +#define PALMAS_SPARE_SPARE_SHIFT 3 +#define PALMAS_SPARE_REGEN3_OD 0x04 +#define PALMAS_SPARE_REGEN3_OD_SHIFT 2 +#define PALMAS_SPARE_REGEN2_OD 0x02 +#define PALMAS_SPARE_REGEN2_OD_SHIFT 1 +#define PALMAS_SPARE_REGEN1_OD 0x01 +#define PALMAS_SPARE_REGEN1_OD_SHIFT 0 + +/* Bit definitions for PMU_SECONDARY_INT */ +#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80 +#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 7 +#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40 +#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 6 +#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20 +#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 5 +#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10 +#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 4 +#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08 +#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 3 +#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04 +#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 2 +#define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02 +#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 1 +#define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01 +#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0 + +/* Bit definitions for SW_REVISION */ +#define PALMAS_SW_REVISION_SW_REVISION_MASK 0xff +#define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0 + +/* Bit definitions for EXT_CHRG_CTRL */ +#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80 +#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 7 +#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40 +#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 6 +#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08 +#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 3 +#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04 +#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 2 +#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02 +#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 1 +#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01 +#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0 + +/* Bit definitions for PMU_SECONDARY_INT2 */ +#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20 +#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 5 +#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10 +#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 4 +#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02 +#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 1 +#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01 +#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0 + +/* Registers for function RESOURCE */ +#define PALMAS_CLK32KG_CTRL 0x0 +#define PALMAS_CLK32KGAUDIO_CTRL 0x1 +#define PALMAS_REGEN1_CTRL 0x2 +#define PALMAS_REGEN2_CTRL 0x3 +#define PALMAS_SYSEN1_CTRL 0x4 +#define PALMAS_SYSEN2_CTRL 0x5 +#define PALMAS_NSLEEP_RES_ASSIGN 0x6 +#define PALMAS_NSLEEP_SMPS_ASSIGN 0x7 +#define PALMAS_NSLEEP_LDO_ASSIGN1 0x8 +#define PALMAS_NSLEEP_LDO_ASSIGN2 0x9 +#define PALMAS_ENABLE1_RES_ASSIGN 0xA +#define PALMAS_ENABLE1_SMPS_ASSIGN 0xB +#define PALMAS_ENABLE1_LDO_ASSIGN1 0xC +#define PALMAS_ENABLE1_LDO_ASSIGN2 0xD +#define PALMAS_ENABLE2_RES_ASSIGN 0xE +#define PALMAS_ENABLE2_SMPS_ASSIGN 0xF +#define PALMAS_ENABLE2_LDO_ASSIGN1 0x10 +#define PALMAS_ENABLE2_LDO_ASSIGN2 0x11 +#define PALMAS_REGEN3_CTRL 0x12 + +/* Bit definitions for CLK32KG_CTRL */ +#define PALMAS_CLK32KG_CTRL_STATUS 0x10 +#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 4 +#define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04 +#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for CLK32KGAUDIO_CTRL */ +#define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10 +#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 4 +#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08 +#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 3 +#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04 +#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for REGEN1_CTRL */ +#define PALMAS_REGEN1_CTRL_STATUS 0x10 +#define PALMAS_REGEN1_CTRL_STATUS_SHIFT 4 +#define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04 +#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for REGEN2_CTRL */ +#define PALMAS_REGEN2_CTRL_STATUS 0x10 +#define PALMAS_REGEN2_CTRL_STATUS_SHIFT 4 +#define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04 +#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for SYSEN1_CTRL */ +#define PALMAS_SYSEN1_CTRL_STATUS 0x10 +#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 4 +#define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04 +#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for SYSEN2_CTRL */ +#define PALMAS_SYSEN2_CTRL_STATUS 0x10 +#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 4 +#define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04 +#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Bit definitions for NSLEEP_RES_ASSIGN */ +#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40 +#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 6 +#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20 +#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 +#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10 +#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 4 +#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08 +#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 3 +#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04 +#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 2 +#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02 +#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 1 +#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01 +#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0 + +/* Bit definitions for NSLEEP_SMPS_ASSIGN */ +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 7 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 6 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 5 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 4 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 3 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 2 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 1 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0 + +/* Bit definitions for NSLEEP_LDO_ASSIGN1 */ +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 7 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 6 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 5 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 4 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 3 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 2 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 1 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0 + +/* Bit definitions for NSLEEP_LDO_ASSIGN2 */ +#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04 +#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 2 +#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02 +#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 1 +#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01 +#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0 + +/* Bit definitions for ENABLE1_RES_ASSIGN */ +#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40 +#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 6 +#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20 +#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 +#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10 +#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 4 +#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08 +#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 3 +#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04 +#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 2 +#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02 +#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 1 +#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01 +#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0 + +/* Bit definitions for ENABLE1_SMPS_ASSIGN */ +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 7 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 6 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 5 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 4 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 3 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 2 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 1 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0 + +/* Bit definitions for ENABLE1_LDO_ASSIGN1 */ +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 7 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 6 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 5 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 4 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 3 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 2 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 1 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0 + +/* Bit definitions for ENABLE1_LDO_ASSIGN2 */ +#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04 +#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 2 +#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02 +#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 1 +#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01 +#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0 + +/* Bit definitions for ENABLE2_RES_ASSIGN */ +#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40 +#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 6 +#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20 +#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 +#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10 +#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 4 +#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08 +#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 3 +#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04 +#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 2 +#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02 +#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 1 +#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01 +#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0 + +/* Bit definitions for ENABLE2_SMPS_ASSIGN */ +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 7 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 6 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 5 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 4 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 3 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 2 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 1 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0 + +/* Bit definitions for ENABLE2_LDO_ASSIGN1 */ +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 7 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 6 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 5 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 4 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 3 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 2 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 1 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0 + +/* Bit definitions for ENABLE2_LDO_ASSIGN2 */ +#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04 +#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 2 +#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02 +#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 1 +#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01 +#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0 + +/* Bit definitions for REGEN3_CTRL */ +#define PALMAS_REGEN3_CTRL_STATUS 0x10 +#define PALMAS_REGEN3_CTRL_STATUS_SHIFT 4 +#define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04 +#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01 +#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0 + +/* Registers for function PAD_CONTROL */ +#define PALMAS_PU_PD_INPUT_CTRL1 0x0 +#define PALMAS_PU_PD_INPUT_CTRL2 0x1 +#define PALMAS_PU_PD_INPUT_CTRL3 0x2 +#define PALMAS_OD_OUTPUT_CTRL 0x4 +#define PALMAS_POLARITY_CTRL 0x5 +#define PALMAS_PRIMARY_SECONDARY_PAD1 0x6 +#define PALMAS_PRIMARY_SECONDARY_PAD2 0x7 +#define PALMAS_I2C_SPI 0x8 +#define PALMAS_PU_PD_INPUT_CTRL4 0x9 +#define PALMAS_PRIMARY_SECONDARY_PAD3 0xA + +/* Bit definitions for PU_PD_INPUT_CTRL1 */ +#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40 +#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 6 +#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20 +#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 5 +#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10 +#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 4 +#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04 +#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 2 +#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02 +#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 1 + +/* Bit definitions for PU_PD_INPUT_CTRL2 */ +#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20 +#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 5 +#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10 +#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 4 +#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08 +#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 3 +#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04 +#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 2 +#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02 +#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 1 +#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01 +#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0 + +/* Bit definitions for PU_PD_INPUT_CTRL3 */ +#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40 +#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 6 +#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10 +#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 4 +#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04 +#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 2 +#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01 +#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0 + +/* Bit definitions for OD_OUTPUT_CTRL */ +#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80 +#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 7 +#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40 +#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 6 +#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20 +#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 5 +#define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08 +#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 3 + +/* Bit definitions for POLARITY_CTRL */ +#define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80 +#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 7 +#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40 +#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 6 +#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20 +#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 5 +#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10 +#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 4 +#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08 +#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 3 +#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04 +#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 2 +#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02 +#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 1 +#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01 +#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0 + +/* Bit definitions for PRIMARY_SECONDARY_PAD1 */ +#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80 +#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 7 +#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60 +#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 5 +#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18 +#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 3 +#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04 +#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 2 +#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02 +#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 1 +#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01 +#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0 + +/* Bit definitions for PRIMARY_SECONDARY_PAD2 */ +#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30 +#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 4 +#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08 +#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 3 +#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06 +#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 1 +#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01 +#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0 + +/* Bit definitions for I2C_SPI */ +#define PALMAS_I2C_SPI_I2C2OTP_EN 0x80 +#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 7 +#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40 +#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 6 +#define PALMAS_I2C_SPI_ID_I2C2 0x20 +#define PALMAS_I2C_SPI_ID_I2C2_SHIFT 5 +#define PALMAS_I2C_SPI_I2C_SPI 0x10 +#define PALMAS_I2C_SPI_I2C_SPI_SHIFT 4 +#define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0f +#define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0 + +/* Bit definitions for PU_PD_INPUT_CTRL4 */ +#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40 +#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 6 +#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10 +#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 4 +#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04 +#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 2 +#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01 +#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0 + +/* Bit definitions for PRIMARY_SECONDARY_PAD3 */ +#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02 +#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 1 +#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01 +#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0 + +/* Registers for function LED_PWM */ +#define PALMAS_LED_PERIOD_CTRL 0x0 +#define PALMAS_LED_CTRL 0x1 +#define PALMAS_PWM_CTRL1 0x2 +#define PALMAS_PWM_CTRL2 0x3 + +/* Bit definitions for LED_PERIOD_CTRL */ +#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38 +#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 3 +#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07 +#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0 + +/* Bit definitions for LED_CTRL */ +#define PALMAS_LED_CTRL_LED_2_SEQ 0x20 +#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 5 +#define PALMAS_LED_CTRL_LED_1_SEQ 0x10 +#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 4 +#define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c +#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 2 +#define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03 +#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0 + +/* Bit definitions for PWM_CTRL1 */ +#define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02 +#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 1 +#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01 +#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0 + +/* Bit definitions for PWM_CTRL2 */ +#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xff +#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0 + +/* Registers for function INTERRUPT */ +#define PALMAS_INT1_STATUS 0x0 +#define PALMAS_INT1_MASK 0x1 +#define PALMAS_INT1_LINE_STATE 0x2 +#define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x3 +#define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x4 +#define PALMAS_INT2_STATUS 0x5 +#define PALMAS_INT2_MASK 0x6 +#define PALMAS_INT2_LINE_STATE 0x7 +#define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x8 +#define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x9 +#define PALMAS_INT3_STATUS 0xA +#define PALMAS_INT3_MASK 0xB +#define PALMAS_INT3_LINE_STATE 0xC +#define PALMAS_INT3_EDGE_DETECT1_RESERVED 0xD +#define PALMAS_INT3_EDGE_DETECT2_RESERVED 0xE +#define PALMAS_INT4_STATUS 0xF +#define PALMAS_INT4_MASK 0x10 +#define PALMAS_INT4_LINE_STATE 0x11 +#define PALMAS_INT4_EDGE_DETECT1 0x12 +#define PALMAS_INT4_EDGE_DETECT2 0x13 +#define PALMAS_INT_CTRL 0x14 + +/* Bit definitions for INT1_STATUS */ +#define PALMAS_INT1_STATUS_VBAT_MON 0x80 +#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 7 +#define PALMAS_INT1_STATUS_VSYS_MON 0x40 +#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 6 +#define PALMAS_INT1_STATUS_HOTDIE 0x20 +#define PALMAS_INT1_STATUS_HOTDIE_SHIFT 5 +#define PALMAS_INT1_STATUS_PWRDOWN 0x10 +#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 4 +#define PALMAS_INT1_STATUS_RPWRON 0x08 +#define PALMAS_INT1_STATUS_RPWRON_SHIFT 3 +#define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04 +#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 2 +#define PALMAS_INT1_STATUS_PWRON 0x02 +#define PALMAS_INT1_STATUS_PWRON_SHIFT 1 +#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01 +#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0 + +/* Bit definitions for INT1_MASK */ +#define PALMAS_INT1_MASK_VBAT_MON 0x80 +#define PALMAS_INT1_MASK_VBAT_MON_SHIFT 7 +#define PALMAS_INT1_MASK_VSYS_MON 0x40 +#define PALMAS_INT1_MASK_VSYS_MON_SHIFT 6 +#define PALMAS_INT1_MASK_HOTDIE 0x20 +#define PALMAS_INT1_MASK_HOTDIE_SHIFT 5 +#define PALMAS_INT1_MASK_PWRDOWN 0x10 +#define PALMAS_INT1_MASK_PWRDOWN_SHIFT 4 +#define PALMAS_INT1_MASK_RPWRON 0x08 +#define PALMAS_INT1_MASK_RPWRON_SHIFT 3 +#define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04 +#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 2 +#define PALMAS_INT1_MASK_PWRON 0x02 +#define PALMAS_INT1_MASK_PWRON_SHIFT 1 +#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01 +#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0 + +/* Bit definitions for INT1_LINE_STATE */ +#define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80 +#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 7 +#define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40 +#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 6 +#define PALMAS_INT1_LINE_STATE_HOTDIE 0x20 +#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 5 +#define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10 +#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 4 +#define PALMAS_INT1_LINE_STATE_RPWRON 0x08 +#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 3 +#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 +#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 2 +#define PALMAS_INT1_LINE_STATE_PWRON 0x02 +#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 1 +#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01 +#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0 + +/* Bit definitions for INT2_STATUS */ +#define PALMAS_INT2_STATUS_VAC_ACOK 0x80 +#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 7 +#define PALMAS_INT2_STATUS_SHORT 0x40 +#define PALMAS_INT2_STATUS_SHORT_SHIFT 6 +#define PALMAS_INT2_STATUS_FBI_BB 0x20 +#define PALMAS_INT2_STATUS_FBI_BB_SHIFT 5 +#define PALMAS_INT2_STATUS_RESET_IN 0x10 +#define PALMAS_INT2_STATUS_RESET_IN_SHIFT 4 +#define PALMAS_INT2_STATUS_BATREMOVAL 0x08 +#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 3 +#define PALMAS_INT2_STATUS_WDT 0x04 +#define PALMAS_INT2_STATUS_WDT_SHIFT 2 +#define PALMAS_INT2_STATUS_RTC_TIMER 0x02 +#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 1 +#define PALMAS_INT2_STATUS_RTC_ALARM 0x01 +#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0 + +/* Bit definitions for INT2_MASK */ +#define PALMAS_INT2_MASK_VAC_ACOK 0x80 +#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 7 +#define PALMAS_INT2_MASK_SHORT 0x40 +#define PALMAS_INT2_MASK_SHORT_SHIFT 6 +#define PALMAS_INT2_MASK_FBI_BB 0x20 +#define PALMAS_INT2_MASK_FBI_BB_SHIFT 5 +#define PALMAS_INT2_MASK_RESET_IN 0x10 +#define PALMAS_INT2_MASK_RESET_IN_SHIFT 4 +#define PALMAS_INT2_MASK_BATREMOVAL 0x08 +#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 3 +#define PALMAS_INT2_MASK_WDT 0x04 +#define PALMAS_INT2_MASK_WDT_SHIFT 2 +#define PALMAS_INT2_MASK_RTC_TIMER 0x02 +#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 1 +#define PALMAS_INT2_MASK_RTC_ALARM 0x01 +#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0 + +/* Bit definitions for INT2_LINE_STATE */ +#define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80 +#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 7 +#define PALMAS_INT2_LINE_STATE_SHORT 0x40 +#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 6 +#define PALMAS_INT2_LINE_STATE_FBI_BB 0x20 +#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 5 +#define PALMAS_INT2_LINE_STATE_RESET_IN 0x10 +#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 4 +#define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08 +#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 3 +#define PALMAS_INT2_LINE_STATE_WDT 0x04 +#define PALMAS_INT2_LINE_STATE_WDT_SHIFT 2 +#define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02 +#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 1 +#define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01 +#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0 + +/* Bit definitions for INT3_STATUS */ +#define PALMAS_INT3_STATUS_VBUS 0x80 +#define PALMAS_INT3_STATUS_VBUS_SHIFT 7 +#define PALMAS_INT3_STATUS_VBUS_OTG 0x40 +#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 6 +#define PALMAS_INT3_STATUS_ID 0x20 +#define PALMAS_INT3_STATUS_ID_SHIFT 5 +#define PALMAS_INT3_STATUS_ID_OTG 0x10 +#define PALMAS_INT3_STATUS_ID_OTG_SHIFT 4 +#define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08 +#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 3 +#define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04 +#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 2 +#define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02 +#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 1 +#define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01 +#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0 + +/* Bit definitions for INT3_MASK */ +#define PALMAS_INT3_MASK_VBUS 0x80 +#define PALMAS_INT3_MASK_VBUS_SHIFT 7 +#define PALMAS_INT3_MASK_VBUS_OTG 0x40 +#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 6 +#define PALMAS_INT3_MASK_ID 0x20 +#define PALMAS_INT3_MASK_ID_SHIFT 5 +#define PALMAS_INT3_MASK_ID_OTG 0x10 +#define PALMAS_INT3_MASK_ID_OTG_SHIFT 4 +#define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08 +#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 3 +#define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04 +#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 2 +#define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02 +#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 1 +#define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01 +#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0 + +/* Bit definitions for INT3_LINE_STATE */ +#define PALMAS_INT3_LINE_STATE_VBUS 0x80 +#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 7 +#define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40 +#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 6 +#define PALMAS_INT3_LINE_STATE_ID 0x20 +#define PALMAS_INT3_LINE_STATE_ID_SHIFT 5 +#define PALMAS_INT3_LINE_STATE_ID_OTG 0x10 +#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 4 +#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08 +#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 3 +#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04 +#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 2 +#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02 +#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 1 +#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01 +#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0 + +/* Bit definitions for INT4_STATUS */ +#define PALMAS_INT4_STATUS_GPIO_7 0x80 +#define PALMAS_INT4_STATUS_GPIO_7_SHIFT 7 +#define PALMAS_INT4_STATUS_GPIO_6 0x40 +#define PALMAS_INT4_STATUS_GPIO_6_SHIFT 6 +#define PALMAS_INT4_STATUS_GPIO_5 0x20 +#define PALMAS_INT4_STATUS_GPIO_5_SHIFT 5 +#define PALMAS_INT4_STATUS_GPIO_4 0x10 +#define PALMAS_INT4_STATUS_GPIO_4_SHIFT 4 +#define PALMAS_INT4_STATUS_GPIO_3 0x08 +#define PALMAS_INT4_STATUS_GPIO_3_SHIFT 3 +#define PALMAS_INT4_STATUS_GPIO_2 0x04 +#define PALMAS_INT4_STATUS_GPIO_2_SHIFT 2 +#define PALMAS_INT4_STATUS_GPIO_1 0x02 +#define PALMAS_INT4_STATUS_GPIO_1_SHIFT 1 +#define PALMAS_INT4_STATUS_GPIO_0 0x01 +#define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0 + +/* Bit definitions for INT4_MASK */ +#define PALMAS_INT4_MASK_GPIO_7 0x80 +#define PALMAS_INT4_MASK_GPIO_7_SHIFT 7 +#define PALMAS_INT4_MASK_GPIO_6 0x40 +#define PALMAS_INT4_MASK_GPIO_6_SHIFT 6 +#define PALMAS_INT4_MASK_GPIO_5 0x20 +#define PALMAS_INT4_MASK_GPIO_5_SHIFT 5 +#define PALMAS_INT4_MASK_GPIO_4 0x10 +#define PALMAS_INT4_MASK_GPIO_4_SHIFT 4 +#define PALMAS_INT4_MASK_GPIO_3 0x08 +#define PALMAS_INT4_MASK_GPIO_3_SHIFT 3 +#define PALMAS_INT4_MASK_GPIO_2 0x04 +#define PALMAS_INT4_MASK_GPIO_2_SHIFT 2 +#define PALMAS_INT4_MASK_GPIO_1 0x02 +#define PALMAS_INT4_MASK_GPIO_1_SHIFT 1 +#define PALMAS_INT4_MASK_GPIO_0 0x01 +#define PALMAS_INT4_MASK_GPIO_0_SHIFT 0 + +/* Bit definitions for INT4_LINE_STATE */ +#define PALMAS_INT4_LINE_STATE_GPIO_7 0x80 +#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 7 +#define PALMAS_INT4_LINE_STATE_GPIO_6 0x40 +#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 6 +#define PALMAS_INT4_LINE_STATE_GPIO_5 0x20 +#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 5 +#define PALMAS_INT4_LINE_STATE_GPIO_4 0x10 +#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 4 +#define PALMAS_INT4_LINE_STATE_GPIO_3 0x08 +#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 3 +#define PALMAS_INT4_LINE_STATE_GPIO_2 0x04 +#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 2 +#define PALMAS_INT4_LINE_STATE_GPIO_1 0x02 +#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 1 +#define PALMAS_INT4_LINE_STATE_GPIO_0 0x01 +#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0 + +/* Bit definitions for INT4_EDGE_DETECT1 */ +#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 7 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 6 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 5 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 4 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 3 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 2 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 1 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0 + +/* Bit definitions for INT4_EDGE_DETECT2 */ +#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 7 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 6 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 5 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 4 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 3 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 2 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 1 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0 + +/* Bit definitions for INT_CTRL */ +#define PALMAS_INT_CTRL_INT_PENDING 0x04 +#define PALMAS_INT_CTRL_INT_PENDING_SHIFT 2 +#define PALMAS_INT_CTRL_INT_CLEAR 0x01 +#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0 + +/* Registers for function USB_OTG */ +#define PALMAS_USB_WAKEUP 0x3 +#define PALMAS_USB_VBUS_CTRL_SET 0x4 +#define PALMAS_USB_VBUS_CTRL_CLR 0x5 +#define PALMAS_USB_ID_CTRL_SET 0x6 +#define PALMAS_USB_ID_CTRL_CLEAR 0x7 +#define PALMAS_USB_VBUS_INT_SRC 0x8 +#define PALMAS_USB_VBUS_INT_LATCH_SET 0x9 +#define PALMAS_USB_VBUS_INT_LATCH_CLR 0xA +#define PALMAS_USB_VBUS_INT_EN_LO_SET 0xB +#define PALMAS_USB_VBUS_INT_EN_LO_CLR 0xC +#define PALMAS_USB_VBUS_INT_EN_HI_SET 0xD +#define PALMAS_USB_VBUS_INT_EN_HI_CLR 0xE +#define PALMAS_USB_ID_INT_SRC 0xF +#define PALMAS_USB_ID_INT_LATCH_SET 0x10 +#define PALMAS_USB_ID_INT_LATCH_CLR 0x11 +#define PALMAS_USB_ID_INT_EN_LO_SET 0x12 +#define PALMAS_USB_ID_INT_EN_LO_CLR 0x13 +#define PALMAS_USB_ID_INT_EN_HI_SET 0x14 +#define PALMAS_USB_ID_INT_EN_HI_CLR 0x15 +#define PALMAS_USB_OTG_ADP_CTRL 0x16 +#define PALMAS_USB_OTG_ADP_HIGH 0x17 +#define PALMAS_USB_OTG_ADP_LOW 0x18 +#define PALMAS_USB_OTG_ADP_RISE 0x19 +#define PALMAS_USB_OTG_REVISION 0x1A + +/* Bit definitions for USB_WAKEUP */ +#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01 +#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0 + +/* Bit definitions for USB_VBUS_CTRL_SET */ +#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80 +#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 7 +#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20 +#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 5 +#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10 +#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 4 +#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08 +#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 3 +#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04 +#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 2 + +/* Bit definitions for USB_VBUS_CTRL_CLR */ +#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80 +#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 7 +#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20 +#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 5 +#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10 +#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 4 +#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08 +#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 3 +#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04 +#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 2 + +/* Bit definitions for USB_ID_CTRL_SET */ +#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80 +#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 7 +#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40 +#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 6 +#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20 +#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 5 +#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10 +#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 4 +#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08 +#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 3 +#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04 +#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 2 + +/* Bit definitions for USB_ID_CTRL_CLEAR */ +#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80 +#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 7 +#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40 +#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 6 +#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20 +#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 5 +#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10 +#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 4 +#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08 +#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 3 +#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04 +#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 2 + +/* Bit definitions for USB_VBUS_INT_SRC */ +#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80 +#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 7 +#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40 +#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 6 +#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20 +#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 5 +#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08 +#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 3 +#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04 +#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 2 +#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02 +#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 1 +#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01 +#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0 + +/* Bit definitions for USB_VBUS_INT_LATCH_SET */ +#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80 +#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 7 +#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40 +#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 6 +#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20 +#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 5 +#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10 +#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 4 +#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08 +#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 3 +#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04 +#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 2 +#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02 +#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 1 +#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01 +#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0 + +/* Bit definitions for USB_VBUS_INT_LATCH_CLR */ +#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 7 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 6 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 5 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 4 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 3 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 2 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 1 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0 + +/* Bit definitions for USB_VBUS_INT_EN_LO_SET */ +#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80 +#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 7 +#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40 +#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 6 +#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20 +#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 5 +#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08 +#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 3 +#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04 +#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 2 +#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02 +#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 1 +#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01 +#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0 + +/* Bit definitions for USB_VBUS_INT_EN_LO_CLR */ +#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80 +#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 7 +#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40 +#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 6 +#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20 +#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 5 +#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08 +#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 3 +#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04 +#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 2 +#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02 +#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 1 +#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01 +#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0 + +/* Bit definitions for USB_VBUS_INT_EN_HI_SET */ +#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 7 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 6 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 5 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 4 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 3 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 2 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 1 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0 + +/* Bit definitions for USB_VBUS_INT_EN_HI_CLR */ +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 7 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 6 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 5 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 4 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 3 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 2 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 1 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0 + +/* Bit definitions for USB_ID_INT_SRC */ +#define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10 +#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 4 +#define PALMAS_USB_ID_INT_SRC_ID_A 0x08 +#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 3 +#define PALMAS_USB_ID_INT_SRC_ID_B 0x04 +#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 2 +#define PALMAS_USB_ID_INT_SRC_ID_C 0x02 +#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 1 +#define PALMAS_USB_ID_INT_SRC_ID_GND 0x01 +#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0 + +/* Bit definitions for USB_ID_INT_LATCH_SET */ +#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10 +#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 4 +#define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08 +#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 3 +#define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04 +#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 2 +#define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02 +#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 1 +#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01 +#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0 + +/* Bit definitions for USB_ID_INT_LATCH_CLR */ +#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10 +#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 4 +#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08 +#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 3 +#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04 +#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 2 +#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02 +#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 1 +#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01 +#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0 + +/* Bit definitions for USB_ID_INT_EN_LO_SET */ +#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10 +#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 4 +#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08 +#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 3 +#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04 +#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 2 +#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02 +#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 1 +#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01 +#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0 + +/* Bit definitions for USB_ID_INT_EN_LO_CLR */ +#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10 +#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 4 +#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08 +#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 3 +#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04 +#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 2 +#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02 +#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 1 +#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01 +#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0 + +/* Bit definitions for USB_ID_INT_EN_HI_SET */ +#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10 +#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 4 +#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08 +#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 3 +#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04 +#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 2 +#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02 +#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 1 +#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01 +#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0 + +/* Bit definitions for USB_ID_INT_EN_HI_CLR */ +#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10 +#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 4 +#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08 +#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 3 +#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04 +#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 2 +#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02 +#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 1 +#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01 +#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0 + +/* Bit definitions for USB_OTG_ADP_CTRL */ +#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04 +#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 2 +#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03 +#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0 + +/* Bit definitions for USB_OTG_ADP_HIGH */ +#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xff +#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0 + +/* Bit definitions for USB_OTG_ADP_LOW */ +#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xff +#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0 + +/* Bit definitions for USB_OTG_ADP_RISE */ +#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xff +#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0 + +/* Bit definitions for USB_OTG_REVISION */ +#define PALMAS_USB_OTG_REVISION_OTG_REV 0x01 +#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0 + +/* Registers for function VIBRATOR */ +#define PALMAS_VIBRA_CTRL 0x0 + +/* Bit definitions for VIBRA_CTRL */ +#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06 +#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 1 +#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01 +#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0 + +/* Registers for function GPIO */ +#define PALMAS_GPIO_DATA_IN 0x0 +#define PALMAS_GPIO_DATA_DIR 0x1 +#define PALMAS_GPIO_DATA_OUT 0x2 +#define PALMAS_GPIO_DEBOUNCE_EN 0x3 +#define PALMAS_GPIO_CLEAR_DATA_OUT 0x4 +#define PALMAS_GPIO_SET_DATA_OUT 0x5 +#define PALMAS_PU_PD_GPIO_CTRL1 0x6 +#define PALMAS_PU_PD_GPIO_CTRL2 0x7 +#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x8 + +/* Bit definitions for GPIO_DATA_IN */ +#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80 +#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 7 +#define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40 +#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 6 +#define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20 +#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 5 +#define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10 +#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 4 +#define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08 +#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 3 +#define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04 +#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 2 +#define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02 +#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 1 +#define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01 +#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0 + +/* Bit definitions for GPIO_DATA_DIR */ +#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80 +#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 7 +#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40 +#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 6 +#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20 +#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 5 +#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10 +#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 4 +#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08 +#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 3 +#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04 +#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 2 +#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02 +#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 1 +#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01 +#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0 + +/* Bit definitions for GPIO_DATA_OUT */ +#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80 +#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 7 +#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40 +#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 6 +#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20 +#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 5 +#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10 +#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 4 +#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08 +#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 3 +#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04 +#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 2 +#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02 +#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 1 +#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01 +#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0 + +/* Bit definitions for GPIO_DEBOUNCE_EN */ +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 7 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 6 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 5 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 4 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 3 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 2 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 1 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0 + +/* Bit definitions for GPIO_CLEAR_DATA_OUT */ +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 7 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 6 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 5 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 4 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 3 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 2 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 1 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0 + +/* Bit definitions for GPIO_SET_DATA_OUT */ +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 7 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 6 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 5 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 4 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 3 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 2 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 1 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0 + +/* Bit definitions for PU_PD_GPIO_CTRL1 */ +#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40 +#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 6 +#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20 +#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 5 +#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10 +#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 4 +#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08 +#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 3 +#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04 +#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 2 +#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01 +#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0 + +/* Bit definitions for PU_PD_GPIO_CTRL2 */ +#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40 +#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 6 +#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20 +#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 5 +#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10 +#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 4 +#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08 +#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 3 +#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04 +#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 2 +#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02 +#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 1 +#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01 +#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0 + +/* Bit definitions for OD_OUTPUT_GPIO_CTRL */ +#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20 +#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 5 +#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04 +#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 2 +#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02 +#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 1 + +/* Registers for function GPADC */ +#define PALMAS_GPADC_CTRL1 0x0 +#define PALMAS_GPADC_CTRL2 0x1 +#define PALMAS_GPADC_RT_CTRL 0x2 +#define PALMAS_GPADC_AUTO_CTRL 0x3 +#define PALMAS_GPADC_STATUS 0x4 +#define PALMAS_GPADC_RT_SELECT 0x5 +#define PALMAS_GPADC_RT_CONV0_LSB 0x6 +#define PALMAS_GPADC_RT_CONV0_MSB 0x7 +#define PALMAS_GPADC_AUTO_SELECT 0x8 +#define PALMAS_GPADC_AUTO_CONV0_LSB 0x9 +#define PALMAS_GPADC_AUTO_CONV0_MSB 0xA +#define PALMAS_GPADC_AUTO_CONV1_LSB 0xB +#define PALMAS_GPADC_AUTO_CONV1_MSB 0xC +#define PALMAS_GPADC_SW_SELECT 0xD +#define PALMAS_GPADC_SW_CONV0_LSB 0xE +#define PALMAS_GPADC_SW_CONV0_MSB 0xF +#define PALMAS_GPADC_THRES_CONV0_LSB 0x10 +#define PALMAS_GPADC_THRES_CONV0_MSB 0x11 +#define PALMAS_GPADC_THRES_CONV1_LSB 0x12 +#define PALMAS_GPADC_THRES_CONV1_MSB 0x13 +#define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14 +#define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15 + +/* Bit definitions for GPADC_CTRL1 */ +#define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0 +#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 6 +#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30 +#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 4 +#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c +#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 2 +#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02 +#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 1 +#define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01 +#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0 + +/* Bit definitions for GPADC_CTRL2 */ +#define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06 +#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 1 + +/* Bit definitions for GPADC_RT_CTRL */ +#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02 +#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 1 +#define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01 +#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0 + +/* Bit definitions for GPADC_AUTO_CTRL */ +#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80 +#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 7 +#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40 +#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 6 +#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20 +#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 5 +#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10 +#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 4 +#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0f +#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0 + +/* Bit definitions for GPADC_STATUS */ +#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10 +#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 4 + +/* Bit definitions for GPADC_RT_SELECT */ +#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80 +#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 7 +#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0f +#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0 + +/* Bit definitions for GPADC_RT_CONV0_LSB */ +#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xff +#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0 + +/* Bit definitions for GPADC_RT_CONV0_MSB */ +#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0f +#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0 + +/* Bit definitions for GPADC_AUTO_SELECT */ +#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xf0 +#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 4 +#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0f +#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0 + +/* Bit definitions for GPADC_AUTO_CONV0_LSB */ +#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xff +#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0 + +/* Bit definitions for GPADC_AUTO_CONV0_MSB */ +#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0f +#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0 + +/* Bit definitions for GPADC_AUTO_CONV1_LSB */ +#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xff +#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0 + +/* Bit definitions for GPADC_AUTO_CONV1_MSB */ +#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0f +#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0 + +/* Bit definitions for GPADC_SW_SELECT */ +#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80 +#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 7 +#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10 +#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 4 +#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0f +#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0 + +/* Bit definitions for GPADC_SW_CONV0_LSB */ +#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xff +#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0 + +/* Bit definitions for GPADC_SW_CONV0_MSB */ +#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0f +#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0 + +/* Bit definitions for GPADC_THRES_CONV0_LSB */ +#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xff +#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0 + +/* Bit definitions for GPADC_THRES_CONV0_MSB */ +#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80 +#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 7 +#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0f +#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0 + +/* Bit definitions for GPADC_THRES_CONV1_LSB */ +#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xff +#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0 + +/* Bit definitions for GPADC_THRES_CONV1_MSB */ +#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80 +#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 7 +#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0f +#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0 + +/* Bit definitions for GPADC_SMPS_ILMONITOR_EN */ +#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20 +#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 5 +#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10 +#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 4 +#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0f +#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0 + +/* Bit definitions for GPADC_SMPS_VSEL_MONITORING */ +#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80 +#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 7 +#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7f +#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0 + +/* Registers for function GPADC */ +#define PALMAS_GPADC_TRIM1 0x0 +#define PALMAS_GPADC_TRIM2 0x1 +#define PALMAS_GPADC_TRIM3 0x2 +#define PALMAS_GPADC_TRIM4 0x3 +#define PALMAS_GPADC_TRIM5 0x4 +#define PALMAS_GPADC_TRIM6 0x5 +#define PALMAS_GPADC_TRIM7 0x6 +#define PALMAS_GPADC_TRIM8 0x7 +#define PALMAS_GPADC_TRIM9 0x8 +#define PALMAS_GPADC_TRIM10 0x9 +#define PALMAS_GPADC_TRIM11 0xA +#define PALMAS_GPADC_TRIM12 0xB +#define PALMAS_GPADC_TRIM13 0xC +#define PALMAS_GPADC_TRIM14 0xD +#define PALMAS_GPADC_TRIM15 0xE +#define PALMAS_GPADC_TRIM16 0xF + +#endif /* __LINUX_MFD_PALMAS_H */ diff --git a/include/linux/mfd/rc5t583.h b/include/linux/mfd/rc5t583.h index 0b64b19d81ab..3661c59aa1e9 100644 --- a/include/linux/mfd/rc5t583.h +++ b/include/linux/mfd/rc5t583.h @@ -250,6 +250,26 @@ enum { RC5T583_EXT_PWRREQ2_CONTROL = 0x2, }; +enum { + RC5T583_REGULATOR_DC0, + RC5T583_REGULATOR_DC1, + RC5T583_REGULATOR_DC2, + RC5T583_REGULATOR_DC3, + RC5T583_REGULATOR_LDO0, + RC5T583_REGULATOR_LDO1, + RC5T583_REGULATOR_LDO2, + RC5T583_REGULATOR_LDO3, + RC5T583_REGULATOR_LDO4, + RC5T583_REGULATOR_LDO5, + RC5T583_REGULATOR_LDO6, + RC5T583_REGULATOR_LDO7, + RC5T583_REGULATOR_LDO8, + RC5T583_REGULATOR_LDO9, + + /* Should be last entry */ + RC5T583_REGULATOR_MAX, +}; + struct rc5t583 { struct device *dev; struct regmap *regmap; @@ -272,12 +292,23 @@ struct rc5t583 { * rc5t583_platform_data: Platform data for ricoh rc5t583 pmu. * The board specific data is provided through this structure. * @irq_base: Irq base number on which this device registers their interrupts. + * @gpio_base: GPIO base from which gpio of this device will start. * @enable_shutdown: Enable shutdown through the input pin "shutdown". + * @regulator_deepsleep_slot: The slot number on which device goes to sleep + * in device sleep mode. + * @regulator_ext_pwr_control: External power request regulator control. The + * regulator output enable/disable is controlled by the external + * power request input state. + * @reg_init_data: Regulator init data. */ struct rc5t583_platform_data { int irq_base; + int gpio_base; bool enable_shutdown; + int regulator_deepsleep_slot[RC5T583_REGULATOR_MAX]; + unsigned long regulator_ext_pwr_control[RC5T583_REGULATOR_MAX]; + struct regulator_init_data *reg_init_data[RC5T583_REGULATOR_MAX]; }; static inline int rc5t583_write(struct device *dev, uint8_t reg, uint8_t val) diff --git a/include/linux/mfd/s5m87xx/s5m-core.h b/include/linux/mfd/s5m87xx/s5m-core.h index a7480b57f92d..21603b42f22f 100644 --- a/include/linux/mfd/s5m87xx/s5m-core.h +++ b/include/linux/mfd/s5m87xx/s5m-core.h @@ -335,6 +335,7 @@ extern int s5m_reg_update(struct s5m87xx_dev *s5m87xx, u8 reg, u8 val, u8 mask); struct s5m_platform_data { struct s5m_regulator_data *regulators; + struct s5m_opmode_data *opmode; int device_type; int num_regulators; diff --git a/include/linux/mfd/s5m87xx/s5m-pmic.h b/include/linux/mfd/s5m87xx/s5m-pmic.h index a72a5d27e62e..7c719f20f58a 100644 --- a/include/linux/mfd/s5m87xx/s5m-pmic.h +++ b/include/linux/mfd/s5m87xx/s5m-pmic.h @@ -58,6 +58,8 @@ enum s5m8767_regulators { S5M8767_REG_MAX, }; +#define S5M8767_ENCTRL_SHIFT 6 + /* S5M8763 regulator ids */ enum s5m8763_regulators { S5M8763_LDO1, @@ -97,4 +99,31 @@ struct s5m_regulator_data { struct regulator_init_data *initdata; }; +/* + * s5m_opmode_data - regulator operation mode data + * @id: regulator id + * @mode: regulator operation mode + */ +struct s5m_opmode_data { + int id; + int mode; +}; + +/* + * s5m regulator operation mode + * S5M_OPMODE_OFF Regulator always OFF + * S5M_OPMODE_ON Regulator always ON + * S5M_OPMODE_LOWPOWER Regulator is on in low-power mode + * S5M_OPMODE_SUSPEND Regulator is changed by PWREN pin + * If PWREN is high, regulator is on + * If PWREN is low, regulator is off + */ + +enum s5m_opmode { + S5M_OPMODE_OFF, + S5M_OPMODE_ON, + S5M_OPMODE_LOWPOWER, + S5M_OPMODE_SUSPEND, +}; + #endif /* __LINUX_MFD_S5M_PMIC_H */ diff --git a/include/linux/mfd/sta2x11-mfd.h b/include/linux/mfd/sta2x11-mfd.h new file mode 100644 index 000000000000..d179227e866f --- /dev/null +++ b/include/linux/mfd/sta2x11-mfd.h @@ -0,0 +1,324 @@ +/* + * Copyright (c) 2009-2011 Wind River Systems, Inc. + * Copyright (c) 2011 ST Microelectronics (Alessandro Rubini) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * The STMicroelectronics ConneXt (STA2X11) chip has several unrelated + * functions in one PCI endpoint functions. This driver simply + * registers the platform devices in this iomemregion and exports a few + * functions to access common registers + */ + +#ifndef __STA2X11_MFD_H +#define __STA2X11_MFD_H +#include <linux/types.h> +#include <linux/pci.h> + +/* + * The MFD PCI block includes the GPIO peripherals and other register blocks. + * For GPIO, we have 32*4 bits (I use "gsta" for "gpio sta2x11".) + */ +#define GSTA_GPIO_PER_BLOCK 32 +#define GSTA_NR_BLOCKS 4 +#define GSTA_NR_GPIO (GSTA_GPIO_PER_BLOCK * GSTA_NR_BLOCKS) + +/* Pinconfig is set by the board definition: altfunc, pull-up, pull-down */ +struct sta2x11_gpio_pdata { + unsigned pinconfig[GSTA_NR_GPIO]; +}; + +/* Macros below lifted from sh_pfc.h, with minor differences */ +#define PINMUX_TYPE_NONE 0 +#define PINMUX_TYPE_FUNCTION 1 +#define PINMUX_TYPE_OUTPUT_LOW 2 +#define PINMUX_TYPE_OUTPUT_HIGH 3 +#define PINMUX_TYPE_INPUT 4 +#define PINMUX_TYPE_INPUT_PULLUP 5 +#define PINMUX_TYPE_INPUT_PULLDOWN 6 + +/* Give names to GPIO pins, like PXA does, taken from the manual */ +#define STA2X11_GPIO0 0 +#define STA2X11_GPIO1 1 +#define STA2X11_GPIO2 2 +#define STA2X11_GPIO3 3 +#define STA2X11_GPIO4 4 +#define STA2X11_GPIO5 5 +#define STA2X11_GPIO6 6 +#define STA2X11_GPIO7 7 +#define STA2X11_GPIO8_RGBOUT_RED7 8 +#define STA2X11_GPIO9_RGBOUT_RED6 9 +#define STA2X11_GPIO10_RGBOUT_RED5 10 +#define STA2X11_GPIO11_RGBOUT_RED4 11 +#define STA2X11_GPIO12_RGBOUT_RED3 12 +#define STA2X11_GPIO13_RGBOUT_RED2 13 +#define STA2X11_GPIO14_RGBOUT_RED1 14 +#define STA2X11_GPIO15_RGBOUT_RED0 15 +#define STA2X11_GPIO16_RGBOUT_GREEN7 16 +#define STA2X11_GPIO17_RGBOUT_GREEN6 17 +#define STA2X11_GPIO18_RGBOUT_GREEN5 18 +#define STA2X11_GPIO19_RGBOUT_GREEN4 19 +#define STA2X11_GPIO20_RGBOUT_GREEN3 20 +#define STA2X11_GPIO21_RGBOUT_GREEN2 21 +#define STA2X11_GPIO22_RGBOUT_GREEN1 22 +#define STA2X11_GPIO23_RGBOUT_GREEN0 23 +#define STA2X11_GPIO24_RGBOUT_BLUE7 24 +#define STA2X11_GPIO25_RGBOUT_BLUE6 25 +#define STA2X11_GPIO26_RGBOUT_BLUE5 26 +#define STA2X11_GPIO27_RGBOUT_BLUE4 27 +#define STA2X11_GPIO28_RGBOUT_BLUE3 28 +#define STA2X11_GPIO29_RGBOUT_BLUE2 29 +#define STA2X11_GPIO30_RGBOUT_BLUE1 30 +#define STA2X11_GPIO31_RGBOUT_BLUE0 31 +#define STA2X11_GPIO32_RGBOUT_VSYNCH 32 +#define STA2X11_GPIO33_RGBOUT_HSYNCH 33 +#define STA2X11_GPIO34_RGBOUT_DEN 34 +#define STA2X11_GPIO35_ETH_CRS_DV 35 +#define STA2X11_GPIO36_ETH_TXD1 36 +#define STA2X11_GPIO37_ETH_TXD0 37 +#define STA2X11_GPIO38_ETH_TX_EN 38 +#define STA2X11_GPIO39_MDIO 39 +#define STA2X11_GPIO40_ETH_REF_CLK 40 +#define STA2X11_GPIO41_ETH_RXD1 41 +#define STA2X11_GPIO42_ETH_RXD0 42 +#define STA2X11_GPIO43_MDC 43 +#define STA2X11_GPIO44_CAN_TX 44 +#define STA2X11_GPIO45_CAN_RX 45 +#define STA2X11_GPIO46_MLB_DAT 46 +#define STA2X11_GPIO47_MLB_SIG 47 +#define STA2X11_GPIO48_SPI0_CLK 48 +#define STA2X11_GPIO49_SPI0_TXD 49 +#define STA2X11_GPIO50_SPI0_RXD 50 +#define STA2X11_GPIO51_SPI0_FRM 51 +#define STA2X11_GPIO52_SPI1_CLK 52 +#define STA2X11_GPIO53_SPI1_TXD 53 +#define STA2X11_GPIO54_SPI1_RXD 54 +#define STA2X11_GPIO55_SPI1_FRM 55 +#define STA2X11_GPIO56_SPI2_CLK 56 +#define STA2X11_GPIO57_SPI2_TXD 57 +#define STA2X11_GPIO58_SPI2_RXD 58 +#define STA2X11_GPIO59_SPI2_FRM 59 +#define STA2X11_GPIO60_I2C0_SCL 60 +#define STA2X11_GPIO61_I2C0_SDA 61 +#define STA2X11_GPIO62_I2C1_SCL 62 +#define STA2X11_GPIO63_I2C1_SDA 63 +#define STA2X11_GPIO64_I2C2_SCL 64 +#define STA2X11_GPIO65_I2C2_SDA 65 +#define STA2X11_GPIO66_I2C3_SCL 66 +#define STA2X11_GPIO67_I2C3_SDA 67 +#define STA2X11_GPIO68_MSP0_RCK 68 +#define STA2X11_GPIO69_MSP0_RXD 69 +#define STA2X11_GPIO70_MSP0_RFS 70 +#define STA2X11_GPIO71_MSP0_TCK 71 +#define STA2X11_GPIO72_MSP0_TXD 72 +#define STA2X11_GPIO73_MSP0_TFS 73 +#define STA2X11_GPIO74_MSP0_SCK 74 +#define STA2X11_GPIO75_MSP1_CK 75 +#define STA2X11_GPIO76_MSP1_RXD 76 +#define STA2X11_GPIO77_MSP1_FS 77 +#define STA2X11_GPIO78_MSP1_TXD 78 +#define STA2X11_GPIO79_MSP2_CK 79 +#define STA2X11_GPIO80_MSP2_RXD 80 +#define STA2X11_GPIO81_MSP2_FS 81 +#define STA2X11_GPIO82_MSP2_TXD 82 +#define STA2X11_GPIO83_MSP3_CK 83 +#define STA2X11_GPIO84_MSP3_RXD 84 +#define STA2X11_GPIO85_MSP3_FS 85 +#define STA2X11_GPIO86_MSP3_TXD 86 +#define STA2X11_GPIO87_MSP4_CK 87 +#define STA2X11_GPIO88_MSP4_RXD 88 +#define STA2X11_GPIO89_MSP4_FS 89 +#define STA2X11_GPIO90_MSP4_TXD 90 +#define STA2X11_GPIO91_MSP5_CK 91 +#define STA2X11_GPIO92_MSP5_RXD 92 +#define STA2X11_GPIO93_MSP5_FS 93 +#define STA2X11_GPIO94_MSP5_TXD 94 +#define STA2X11_GPIO95_SDIO3_DAT3 95 +#define STA2X11_GPIO96_SDIO3_DAT2 96 +#define STA2X11_GPIO97_SDIO3_DAT1 97 +#define STA2X11_GPIO98_SDIO3_DAT0 98 +#define STA2X11_GPIO99_SDIO3_CLK 99 +#define STA2X11_GPIO100_SDIO3_CMD 100 +#define STA2X11_GPIO101 101 +#define STA2X11_GPIO102 102 +#define STA2X11_GPIO103 103 +#define STA2X11_GPIO104 104 +#define STA2X11_GPIO105_SDIO2_DAT3 105 +#define STA2X11_GPIO106_SDIO2_DAT2 106 +#define STA2X11_GPIO107_SDIO2_DAT1 107 +#define STA2X11_GPIO108_SDIO2_DAT0 108 +#define STA2X11_GPIO109_SDIO2_CLK 109 +#define STA2X11_GPIO110_SDIO2_CMD 110 +#define STA2X11_GPIO111 111 +#define STA2X11_GPIO112 112 +#define STA2X11_GPIO113 113 +#define STA2X11_GPIO114 114 +#define STA2X11_GPIO115_SDIO1_DAT3 115 +#define STA2X11_GPIO116_SDIO1_DAT2 116 +#define STA2X11_GPIO117_SDIO1_DAT1 117 +#define STA2X11_GPIO118_SDIO1_DAT0 118 +#define STA2X11_GPIO119_SDIO1_CLK 119 +#define STA2X11_GPIO120_SDIO1_CMD 120 +#define STA2X11_GPIO121 121 +#define STA2X11_GPIO122 122 +#define STA2X11_GPIO123 123 +#define STA2X11_GPIO124 124 +#define STA2X11_GPIO125_UART2_TXD 125 +#define STA2X11_GPIO126_UART2_RXD 126 +#define STA2X11_GPIO127_UART3_TXD 127 + +/* + * The APB bridge has its own registers, needed by our users as well. + * They are accessed with the following read/mask/write function. + */ +u32 sta2x11_apbreg_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val); + +/* CAN and MLB */ +#define APBREG_BSR 0x00 /* Bridge Status Reg */ +#define APBREG_PAER 0x08 /* Peripherals Address Error Reg */ +#define APBREG_PWAC 0x20 /* Peripheral Write Access Control reg */ +#define APBREG_PRAC 0x40 /* Peripheral Read Access Control reg */ +#define APBREG_PCG 0x60 /* Peripheral Clock Gating Reg */ +#define APBREG_PUR 0x80 /* Peripheral Under Reset Reg */ +#define APBREG_EMU_PCG 0xA0 /* Emulator Peripheral Clock Gating Reg */ + +#define APBREG_CAN (1 << 1) +#define APBREG_MLB (1 << 3) + +/* SARAC */ +#define APBREG_BSR_SARAC 0x100 /* Bridge Status Reg */ +#define APBREG_PAER_SARAC 0x108 /* Peripherals Address Error Reg */ +#define APBREG_PWAC_SARAC 0x120 /* Peripheral Write Access Control reg */ +#define APBREG_PRAC_SARAC 0x140 /* Peripheral Read Access Control reg */ +#define APBREG_PCG_SARAC 0x160 /* Peripheral Clock Gating Reg */ +#define APBREG_PUR_SARAC 0x180 /* Peripheral Under Reset Reg */ +#define APBREG_EMU_PCG_SARAC 0x1A0 /* Emulator Peripheral Clock Gating Reg */ + +#define APBREG_SARAC (1 << 2) + +/* + * The system controller has its own registers. Some of these are accessed + * by out users as well, using the following read/mask/write/function + */ +u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val); + +#define SCTL_SCCTL 0x00 /* System controller control register */ +#define SCTL_ARMCFG 0x04 /* ARM configuration register */ +#define SCTL_SCPLLCTL 0x08 /* PLL control status register */ +#define SCTL_SCPLLFCTRL 0x0c /* PLL frequency control register */ +#define SCTL_SCRESFRACT 0x10 /* PLL fractional input register */ +#define SCTL_SCRESCTRL1 0x14 /* Peripheral reset control 1 */ +#define SCTL_SCRESXTRL2 0x18 /* Peripheral reset control 2 */ +#define SCTL_SCPEREN0 0x1c /* Peripheral clock enable register 0 */ +#define SCTL_SCPEREN1 0x20 /* Peripheral clock enable register 1 */ +#define SCTL_SCPEREN2 0x24 /* Peripheral clock enable register 2 */ +#define SCTL_SCGRST 0x28 /* Peripheral global reset */ +#define SCTL_SCPCIPMCR1 0x30 /* PCI power management control 1 */ +#define SCTL_SCPCIPMCR2 0x34 /* PCI power management control 2 */ +#define SCTL_SCPCIPMSR1 0x38 /* PCI power management status 1 */ +#define SCTL_SCPCIPMSR2 0x3c /* PCI power management status 2 */ +#define SCTL_SCPCIPMSR3 0x40 /* PCI power management status 3 */ +#define SCTL_SCINTREN 0x44 /* Interrupt enable */ +#define SCTL_SCRISR 0x48 /* RAW interrupt status */ +#define SCTL_SCCLKSTAT0 0x4c /* Peripheral clocks status 0 */ +#define SCTL_SCCLKSTAT1 0x50 /* Peripheral clocks status 1 */ +#define SCTL_SCCLKSTAT2 0x54 /* Peripheral clocks status 2 */ +#define SCTL_SCRSTSTA 0x58 /* Reset status register */ + +#define SCTL_SCRESCTRL1_USB_PHY_POR (1 << 0) +#define SCTL_SCRESCTRL1_USB_OTG (1 << 1) +#define SCTL_SCRESCTRL1_USB_HRST (1 << 2) +#define SCTL_SCRESCTRL1_USB_PHY_HOST (1 << 3) +#define SCTL_SCRESCTRL1_SATAII (1 << 4) +#define SCTL_SCRESCTRL1_VIP (1 << 5) +#define SCTL_SCRESCTRL1_PER_MMC0 (1 << 6) +#define SCTL_SCRESCTRL1_PER_MMC1 (1 << 7) +#define SCTL_SCRESCTRL1_PER_GPIO0 (1 << 8) +#define SCTL_SCRESCTRL1_PER_GPIO1 (1 << 9) +#define SCTL_SCRESCTRL1_PER_GPIO2 (1 << 10) +#define SCTL_SCRESCTRL1_PER_GPIO3 (1 << 11) +#define SCTL_SCRESCTRL1_PER_MTU0 (1 << 12) +#define SCTL_SCRESCTRL1_KER_SPI0 (1 << 13) +#define SCTL_SCRESCTRL1_KER_SPI1 (1 << 14) +#define SCTL_SCRESCTRL1_KER_SPI2 (1 << 15) +#define SCTL_SCRESCTRL1_KER_MCI0 (1 << 16) +#define SCTL_SCRESCTRL1_KER_MCI1 (1 << 17) +#define SCTL_SCRESCTRL1_PRE_HSI2C0 (1 << 18) +#define SCTL_SCRESCTRL1_PER_HSI2C1 (1 << 19) +#define SCTL_SCRESCTRL1_PER_HSI2C2 (1 << 20) +#define SCTL_SCRESCTRL1_PER_HSI2C3 (1 << 21) +#define SCTL_SCRESCTRL1_PER_MSP0 (1 << 22) +#define SCTL_SCRESCTRL1_PER_MSP1 (1 << 23) +#define SCTL_SCRESCTRL1_PER_MSP2 (1 << 24) +#define SCTL_SCRESCTRL1_PER_MSP3 (1 << 25) +#define SCTL_SCRESCTRL1_PER_MSP4 (1 << 26) +#define SCTL_SCRESCTRL1_PER_MSP5 (1 << 27) +#define SCTL_SCRESCTRL1_PER_MMC (1 << 28) +#define SCTL_SCRESCTRL1_KER_MSP0 (1 << 29) +#define SCTL_SCRESCTRL1_KER_MSP1 (1 << 30) +#define SCTL_SCRESCTRL1_KER_MSP2 (1 << 31) + +#define SCTL_SCPEREN0_UART0 (1 << 0) +#define SCTL_SCPEREN0_UART1 (1 << 1) +#define SCTL_SCPEREN0_UART2 (1 << 2) +#define SCTL_SCPEREN0_UART3 (1 << 3) +#define SCTL_SCPEREN0_MSP0 (1 << 4) +#define SCTL_SCPEREN0_MSP1 (1 << 5) +#define SCTL_SCPEREN0_MSP2 (1 << 6) +#define SCTL_SCPEREN0_MSP3 (1 << 7) +#define SCTL_SCPEREN0_MSP4 (1 << 8) +#define SCTL_SCPEREN0_MSP5 (1 << 9) +#define SCTL_SCPEREN0_SPI0 (1 << 10) +#define SCTL_SCPEREN0_SPI1 (1 << 11) +#define SCTL_SCPEREN0_SPI2 (1 << 12) +#define SCTL_SCPEREN0_I2C0 (1 << 13) +#define SCTL_SCPEREN0_I2C1 (1 << 14) +#define SCTL_SCPEREN0_I2C2 (1 << 15) +#define SCTL_SCPEREN0_I2C3 (1 << 16) +#define SCTL_SCPEREN0_SVDO_LVDS (1 << 17) +#define SCTL_SCPEREN0_USB_HOST (1 << 18) +#define SCTL_SCPEREN0_USB_OTG (1 << 19) +#define SCTL_SCPEREN0_MCI0 (1 << 20) +#define SCTL_SCPEREN0_MCI1 (1 << 21) +#define SCTL_SCPEREN0_MCI2 (1 << 22) +#define SCTL_SCPEREN0_MCI3 (1 << 23) +#define SCTL_SCPEREN0_SATA (1 << 24) +#define SCTL_SCPEREN0_ETHERNET (1 << 25) +#define SCTL_SCPEREN0_VIC (1 << 26) +#define SCTL_SCPEREN0_DMA_AUDIO (1 << 27) +#define SCTL_SCPEREN0_DMA_SOC (1 << 28) +#define SCTL_SCPEREN0_RAM (1 << 29) +#define SCTL_SCPEREN0_VIP (1 << 30) +#define SCTL_SCPEREN0_ARM (1 << 31) + +#define SCTL_SCPEREN1_UART0 (1 << 0) +#define SCTL_SCPEREN1_UART1 (1 << 1) +#define SCTL_SCPEREN1_UART2 (1 << 2) +#define SCTL_SCPEREN1_UART3 (1 << 3) +#define SCTL_SCPEREN1_MSP0 (1 << 4) +#define SCTL_SCPEREN1_MSP1 (1 << 5) +#define SCTL_SCPEREN1_MSP2 (1 << 6) +#define SCTL_SCPEREN1_MSP3 (1 << 7) +#define SCTL_SCPEREN1_MSP4 (1 << 8) +#define SCTL_SCPEREN1_MSP5 (1 << 9) +#define SCTL_SCPEREN1_SPI0 (1 << 10) +#define SCTL_SCPEREN1_SPI1 (1 << 11) +#define SCTL_SCPEREN1_SPI2 (1 << 12) +#define SCTL_SCPEREN1_I2C0 (1 << 13) +#define SCTL_SCPEREN1_I2C1 (1 << 14) +#define SCTL_SCPEREN1_I2C2 (1 << 15) +#define SCTL_SCPEREN1_I2C3 (1 << 16) +#define SCTL_SCPEREN1_USB_PHY (1 << 17) + +#endif /* __STA2X11_MFD_H */ diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h index 8516fd1eaabc..f8d5b4d5843f 100644 --- a/include/linux/mfd/stmpe.h +++ b/include/linux/mfd/stmpe.h @@ -117,7 +117,7 @@ struct matrix_keymap_data; * @no_autorepeat: disable key autorepeat */ struct stmpe_keypad_platform_data { - struct matrix_keymap_data *keymap_data; + const struct matrix_keymap_data *keymap_data; unsigned int debounce_ms; unsigned int scan_count; bool no_autorepeat; diff --git a/include/linux/mfd/tps65090.h b/include/linux/mfd/tps65090.h index 38e31c55adbb..6bc31d854626 100644 --- a/include/linux/mfd/tps65090.h +++ b/include/linux/mfd/tps65090.h @@ -22,6 +22,19 @@ #ifndef __LINUX_MFD_TPS65090_H #define __LINUX_MFD_TPS65090_H +#include <linux/irq.h> + +struct tps65090 { + struct mutex lock; + struct device *dev; + struct i2c_client *client; + struct regmap *rmap; + struct irq_chip irq_chip; + struct mutex irq_lock; + int irq_base; + unsigned int id; +}; + struct tps65090_subdev_info { int id; const char *name; diff --git a/include/linux/mfd/tps6586x.h b/include/linux/mfd/tps6586x.h index b19176eab44d..f350fd0ba1df 100644 --- a/include/linux/mfd/tps6586x.h +++ b/include/linux/mfd/tps6586x.h @@ -68,6 +68,7 @@ struct tps6586x_subdev_info { int id; const char *name; void *platform_data; + struct device_node *of_node; }; struct tps6586x_platform_data { diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h index 1c6c2860d1a6..dd8dc0a6c462 100644 --- a/include/linux/mfd/tps65910.h +++ b/include/linux/mfd/tps65910.h @@ -18,6 +18,7 @@ #define __LINUX_MFD_TPS65910_H #include <linux/gpio.h> +#include <linux/regmap.h> /* TPS chip id list */ #define TPS65910 0 @@ -783,6 +784,18 @@ #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 0x4 #define TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP 0x8 +/* + * Sleep keepon data: Maintains the state in sleep mode + * @therm_keepon: Keep on the thermal monitoring in sleep state. + * @clkout32k_keepon: Keep on the 32KHz clock output in sleep state. + * @i2chs_keepon: Keep on high speed internal clock in sleep state. + */ +struct tps65910_sleep_keepon_data { + unsigned therm_keepon:1; + unsigned clkout32k_keepon:1; + unsigned i2chs_keepon:1; +}; + /** * struct tps65910_board * Board platform data may be used to initialize regulators. @@ -794,6 +807,8 @@ struct tps65910_board { int irq_base; int vmbch_threshold; int vmbch2_threshold; + bool en_dev_slp; + struct tps65910_sleep_keepon_data *slp_keepon; bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO]; unsigned long regulator_ext_sleep_control[TPS65910_NUM_REGS]; struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS]; @@ -809,16 +824,14 @@ struct tps65910 { struct regmap *regmap; struct mutex io_mutex; unsigned int id; - int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest); - int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src); /* Client devices */ struct tps65910_pmic *pmic; struct tps65910_rtc *rtc; struct tps65910_power *power; - /* GPIO Handling */ - struct gpio_chip gpio; + /* Device node parsed board data */ + struct tps65910_board *of_plat_data; /* IRQ Handling */ struct mutex irq_lock; @@ -826,6 +839,7 @@ struct tps65910 { int irq_base; int irq_num; u32 irq_mask; + struct irq_domain *domain; }; struct tps65910_platform_data { @@ -833,9 +847,6 @@ struct tps65910_platform_data { int irq_base; }; -int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask); -int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask); -void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base); int tps65910_irq_init(struct tps65910 *tps65910, int irq, struct tps65910_platform_data *pdata); int tps65910_irq_exit(struct tps65910 *tps65910); @@ -845,4 +856,28 @@ static inline int tps65910_chip_id(struct tps65910 *tps65910) return tps65910->id; } +static inline int tps65910_reg_read(struct tps65910 *tps65910, u8 reg, + unsigned int *val) +{ + return regmap_read(tps65910->regmap, reg, val); +} + +static inline int tps65910_reg_write(struct tps65910 *tps65910, u8 reg, + unsigned int val) +{ + return regmap_write(tps65910->regmap, reg, val); +} + +static inline int tps65910_reg_set_bits(struct tps65910 *tps65910, u8 reg, + u8 mask) +{ + return regmap_update_bits(tps65910->regmap, reg, mask, mask); +} + +static inline int tps65910_reg_clear_bits(struct tps65910 *tps65910, u8 reg, + u8 mask) +{ + return regmap_update_bits(tps65910->regmap, reg, mask, 0); +} + #endif /* __LINUX_MFD_TPS65910_H */ diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h index b15b5f03f5c4..6659487c31e7 100644 --- a/include/linux/mfd/twl6040.h +++ b/include/linux/mfd/twl6040.h @@ -27,6 +27,7 @@ #include <linux/interrupt.h> #include <linux/mfd/core.h> +#include <linux/regulator/consumer.h> #define TWL6040_REG_ASICID 0x01 #define TWL6040_REG_ASICREV 0x02 @@ -203,6 +204,7 @@ struct regmap; struct twl6040 { struct device *dev; struct regmap *regmap; + struct regulator_bulk_data supplies[2]; /* supplies for vio, v2v1 */ struct mutex mutex; struct mutex io_mutex; struct mutex irq_mutex; diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h index 4b1211859f74..4a3b83a77614 100644 --- a/include/linux/mfd/wm831x/core.h +++ b/include/linux/mfd/wm831x/core.h @@ -17,6 +17,7 @@ #include <linux/completion.h> #include <linux/interrupt.h> +#include <linux/irqdomain.h> #include <linux/list.h> #include <linux/regmap.h> @@ -338,6 +339,7 @@ #define WM831X_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [1:0] */ struct regulator_dev; +struct irq_domain; #define WM831X_NUM_IRQ_REGS 5 #define WM831X_NUM_GPIO_REGS 16 @@ -367,7 +369,7 @@ struct wm831x { int irq; /* Our chip IRQ */ struct mutex irq_lock; - int irq_base; + struct irq_domain *irq_domain; int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */ int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */ @@ -382,7 +384,8 @@ struct wm831x { /* Used by the interrupt controller code to post writes */ int gpio_update[WM831X_NUM_GPIO_REGS]; - bool gpio_level[WM831X_NUM_GPIO_REGS]; + bool gpio_level_high[WM831X_NUM_GPIO_REGS]; + bool gpio_level_low[WM831X_NUM_GPIO_REGS]; struct mutex auxadc_lock; struct list_head auxadc_pending; @@ -417,6 +420,11 @@ int wm831x_irq_init(struct wm831x *wm831x, int irq); void wm831x_irq_exit(struct wm831x *wm831x); void wm831x_auxadc_init(struct wm831x *wm831x); +static inline int wm831x_irq(struct wm831x *wm831x, int irq) +{ + return irq_create_mapping(wm831x->irq_domain, irq); +} + extern struct regmap_config wm831x_regmap_config; #endif diff --git a/include/linux/mfd/wm831x/pdata.h b/include/linux/mfd/wm831x/pdata.h index 1d7a3f7b3b5d..dcc9631b3052 100644 --- a/include/linux/mfd/wm831x/pdata.h +++ b/include/linux/mfd/wm831x/pdata.h @@ -26,7 +26,7 @@ struct wm831x_backlight_pdata { struct wm831x_backup_pdata { int charger_enable; int no_constant_voltage; /** Disable constant voltage charging */ - int vlim; /** Voltage limit in milivolts */ + int vlim; /** Voltage limit in millivolts */ int ilim; /** Current limit in microamps */ }; diff --git a/include/linux/mfd/wm8350/core.h b/include/linux/mfd/wm8350/core.h index 98fcc977e82b..9192b6404a73 100644 --- a/include/linux/mfd/wm8350/core.h +++ b/include/linux/mfd/wm8350/core.h @@ -602,6 +602,7 @@ extern const u16 wm8352_mode2_defaults[]; extern const u16 wm8352_mode3_defaults[]; struct wm8350; +struct regmap; struct wm8350_hwmon { struct platform_device *pdev; @@ -612,13 +613,7 @@ struct wm8350 { struct device *dev; /* device IO */ - union { - struct i2c_client *i2c_client; - struct spi_device *spi_device; - }; - int (*read_dev)(struct wm8350 *wm8350, char reg, int size, void *dest); - int (*write_dev)(struct wm8350 *wm8350, char reg, int size, - void *src); + struct regmap *regmap; u16 *reg_cache; struct mutex auxadc_mutex; diff --git a/include/linux/mfd/wm8400-private.h b/include/linux/mfd/wm8400-private.h index 0147b6968510..2de565b94d0c 100644 --- a/include/linux/mfd/wm8400-private.h +++ b/include/linux/mfd/wm8400-private.h @@ -24,19 +24,14 @@ #include <linux/mfd/wm8400.h> #include <linux/mutex.h> #include <linux/platform_device.h> - -struct regmap; +#include <linux/regmap.h> #define WM8400_REGISTER_COUNT 0x55 struct wm8400 { struct device *dev; - - struct mutex io_lock; struct regmap *regmap; - u16 reg_cache[WM8400_REGISTER_COUNT]; - struct platform_device regulators[6]; }; @@ -930,6 +925,11 @@ struct wm8400 { u16 wm8400_reg_read(struct wm8400 *wm8400, u8 reg); int wm8400_block_read(struct wm8400 *wm8400, u8 reg, int count, u16 *data); -int wm8400_set_bits(struct wm8400 *wm8400, u8 reg, u16 mask, u16 val); + +static inline int wm8400_set_bits(struct wm8400 *wm8400, u8 reg, + u16 mask, u16 val) +{ + return regmap_update_bits(wm8400->regmap, reg, mask, val); +} #endif diff --git a/include/linux/mfd/wm8994/core.h b/include/linux/mfd/wm8994/core.h index 9eff2a351ec5..1f173306bf05 100644 --- a/include/linux/mfd/wm8994/core.h +++ b/include/linux/mfd/wm8994/core.h @@ -17,6 +17,7 @@ #include <linux/mutex.h> #include <linux/interrupt.h> +#include <linux/regmap.h> enum wm8994_type { WM8994 = 0, @@ -26,7 +27,6 @@ enum wm8994_type { struct regulator_dev; struct regulator_bulk_data; -struct regmap; #define WM8994_NUM_GPIO_REGS 11 #define WM8994_NUM_LDO_REGS 2 @@ -57,6 +57,7 @@ struct wm8994 { enum wm8994_type type; int revision; + int cust_id; struct device *dev; struct regmap *regmap; @@ -94,17 +95,17 @@ static inline int wm8994_request_irq(struct wm8994 *wm8994, int irq, irq_handler_t handler, const char *name, void *data) { - if (!wm8994->irq_base) + if (!wm8994->irq_data) return -EINVAL; - return request_threaded_irq(wm8994->irq_base + irq, NULL, handler, - IRQF_TRIGGER_RISING, name, + return request_threaded_irq(regmap_irq_get_virq(wm8994->irq_data, irq), + NULL, handler, IRQF_TRIGGER_RISING, name, data); } static inline void wm8994_free_irq(struct wm8994 *wm8994, int irq, void *data) { - if (!wm8994->irq_base) + if (!wm8994->irq_data) return; - free_irq(wm8994->irq_base + irq, data); + free_irq(regmap_irq_get_virq(wm8994->irq_data, irq), data); } int wm8994_irq_init(struct wm8994 *wm8994); diff --git a/include/linux/mfd/wm8994/registers.h b/include/linux/mfd/wm8994/registers.h index 86e6a032a078..053548961c15 100644 --- a/include/linux/mfd/wm8994/registers.h +++ b/include/linux/mfd/wm8994/registers.h @@ -2212,6 +2212,9 @@ /* * R256 (0x100) - Chip Revision */ +#define WM8994_CUST_ID_MASK 0xFF00 /* CUST_ID - [15:8] */ +#define WM8994_CUST_ID_SHIFT 8 /* CUST_ID - [15:8] */ +#define WM8994_CUST_ID_WIDTH 8 /* CUST_ID - [15:8] */ #define WM8994_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */ #define WM8994_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */ #define WM8994_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */ |