diff options
Diffstat (limited to 'include')
50 files changed, 1259 insertions, 598 deletions
diff --git a/include/asm-arm/arch-ixp2000/enp2611.h b/include/asm-arm/arch-ixp2000/enp2611.h index 31ae88674968..95128d9f5026 100644 --- a/include/asm-arm/arch-ixp2000/enp2611.h +++ b/include/asm-arm/arch-ixp2000/enp2611.h @@ -21,8 +21,20 @@ #ifndef __ENP2611_H #define __ENP2611_H -#define ENP2611_GPIO_SCL 0x07 -#define ENP2611_GPIO_SDA 0x06 +#define ENP2611_CALEB_PHYS_BASE 0xc5000000 +#define ENP2611_CALEB_VIRT_BASE 0xfe000000 +#define ENP2611_CALEB_SIZE 0x00100000 + +#define ENP2611_PM3386_0_PHYS_BASE 0xc6000000 +#define ENP2611_PM3386_0_VIRT_BASE 0xfe100000 +#define ENP2611_PM3386_0_SIZE 0x00100000 + +#define ENP2611_PM3386_1_PHYS_BASE 0xc6400000 +#define ENP2611_PM3386_1_VIRT_BASE 0xfe200000 +#define ENP2611_PM3386_1_SIZE 0x00100000 + +#define ENP2611_GPIO_SCL 7 +#define ENP2611_GPIO_SDA 6 #endif diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h index def089d693d2..fc5ac6aec4f2 100644 --- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h +++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h @@ -59,14 +59,15 @@ #define IXP2000_CAP_SIZE 0x00100000 /* - * Addresses for specific on-chip peripherals + * Addresses for specific on-chip peripherals. */ #define IXP2000_SLOWPORT_CSR_VIRT_BASE 0xfef80000 #define IXP2000_GLOBAL_REG_VIRT_BASE 0xfef04000 #define IXP2000_UART_PHYS_BASE 0xc0030000 #define IXP2000_UART_VIRT_BASE 0xfef30000 #define IXP2000_TIMER_VIRT_BASE 0xfef20000 -#define IXP2000_GPIO_VIRT_BASE 0Xfef10000 +#define IXP2000_UENGINE_CSR_VIRT_BASE 0xfef18000 +#define IXP2000_GPIO_VIRT_BASE 0xfef10000 /* * Devices outside of the 0xc0000000 -> 0xc0100000 range. The virtual @@ -252,7 +253,7 @@ #define IXP2000_PCI_XSCALE_INT_ENABLE IXP2000_PCI_CSR(0x15C) #define IXP2000_PCICNTL_PNR (1<<17) /* PCI not Reset bit of PCI_CONTROL */ -#define IXP2000_PCICNTL_PCF (1<<28) /* PCI Centrolfunction bit */ +#define IXP2000_PCICNTL_PCF (1<<28) /* PCI Central function bit */ #define IXP2000_XSCALE_INT (1<<1) /* Interrupt from XScale to PCI */ /* These are from the IRQ register in the PCI ISR register */ diff --git a/include/asm-arm/arch-ixp2000/system.h b/include/asm-arm/arch-ixp2000/system.h index 4f489cc0dfa5..ddbbb34b5f95 100644 --- a/include/asm-arm/arch-ixp2000/system.h +++ b/include/asm-arm/arch-ixp2000/system.h @@ -26,29 +26,24 @@ static inline void arch_reset(char mode) * RedBoot bank. */ if (machine_is_ixdp2401()) { - *IXDP2X01_CPLD_FLASH_REG = ((0 >> IXDP2X01_FLASH_WINDOW_BITS) - | IXDP2X01_CPLD_FLASH_INTERN); - *IXDP2X01_CPLD_RESET_REG = 0xffffffff; + ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG, + ((0 >> IXDP2X01_FLASH_WINDOW_BITS) + | IXDP2X01_CPLD_FLASH_INTERN)); + ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff); } /* * On IXDP2801 we need to write this magic sequence to the CPLD * to cause a complete reset of the CPU and all external devices - * and moves the flash bank register back to 0. + * and move the flash bank register back to 0. */ if (machine_is_ixdp2801()) { unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG; + reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF); - *IXDP2X01_CPLD_RESET_REG = reset_reg; - mb(); - *IXDP2X01_CPLD_RESET_REG = 0x80000000; + ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg); + ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000); } - /* - * We do a reset all if we are PCI master. We could be a slave and we - * don't want to do anything funky on the PCI bus. - */ - if (*IXP2000_STRAP_OPTIONS & CFG_PCI_BOOT_HOST) { - *(IXP2000_RESET0) |= (RSTALL); - } + ixp2000_reg_wrb(IXP2000_RESET0, RSTALL); } diff --git a/include/asm-arm/arch-ixp2000/uengine.h b/include/asm-arm/arch-ixp2000/uengine.h new file mode 100644 index 000000000000..b442d65c6593 --- /dev/null +++ b/include/asm-arm/arch-ixp2000/uengine.h @@ -0,0 +1,62 @@ +/* + * Generic library functions for the microengines found on the Intel + * IXP2000 series of network processors. + * + * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org> + * Dedicated to Marija Kulikova. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as + * published by the Free Software Foundation; either version 2.1 of the + * License, or (at your option) any later version. + */ + +#ifndef __IXP2000_UENGINE_H +#define __IXP2000_UENGINE_H + +extern u32 ixp2000_uengine_mask; + +struct ixp2000_uengine_code +{ + u32 cpu_model_bitmask; + u8 cpu_min_revision; + u8 cpu_max_revision; + + u32 uengine_parameters; + + struct ixp2000_reg_value { + int reg; + u32 value; + } *initial_reg_values; + + int num_insns; + u8 *insns; +}; + +u32 ixp2000_uengine_csr_read(int uengine, int offset); +void ixp2000_uengine_csr_write(int uengine, int offset, u32 value); +void ixp2000_uengine_reset(u32 uengine_mask); +void ixp2000_uengine_set_mode(int uengine, u32 mode); +void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns); +void ixp2000_uengine_init_context(int uengine, int context, int pc); +void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask); +void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask); +int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c); + +#define IXP2000_UENGINE_8_CONTEXTS 0x00000000 +#define IXP2000_UENGINE_4_CONTEXTS 0x80000000 +#define IXP2000_UENGINE_PRN_UPDATE_EVERY 0x40000000 +#define IXP2000_UENGINE_PRN_UPDATE_ON_ACCESS 0x00000000 +#define IXP2000_UENGINE_NN_FROM_SELF 0x00100000 +#define IXP2000_UENGINE_NN_FROM_PREVIOUS 0x00000000 +#define IXP2000_UENGINE_ASSERT_EMPTY_AT_3 0x000c0000 +#define IXP2000_UENGINE_ASSERT_EMPTY_AT_2 0x00080000 +#define IXP2000_UENGINE_ASSERT_EMPTY_AT_1 0x00040000 +#define IXP2000_UENGINE_ASSERT_EMPTY_AT_0 0x00000000 +#define IXP2000_UENGINE_LM_ADDR1_GLOBAL 0x00020000 +#define IXP2000_UENGINE_LM_ADDR1_PER_CONTEXT 0x00000000 +#define IXP2000_UENGINE_LM_ADDR0_GLOBAL 0x00010000 +#define IXP2000_UENGINE_LM_ADDR0_PER_CONTEXT 0x00000000 + + +#endif diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h index 80d05ecad2f0..688f7f90d93e 100644 --- a/include/asm-arm/arch-ixp4xx/io.h +++ b/include/asm-arm/arch-ixp4xx/io.h @@ -80,9 +80,9 @@ __ixp4xx_iounmap(void __iomem *addr) #define __arch_ioremap(a, s, f, x) __ixp4xx_ioremap(a, s, f, x) #define __arch_iounmap(a) __ixp4xx_iounmap(a) -#define writeb(p, v) __ixp4xx_writeb(p, v) -#define writew(p, v) __ixp4xx_writew(p, v) -#define writel(p, v) __ixp4xx_writel(p, v) +#define writeb(v, p) __ixp4xx_writeb(v, p) +#define writew(v, p) __ixp4xx_writew(v, p) +#define writel(v, p) __ixp4xx_writel(v, p) #define writesb(p, v, l) __ixp4xx_writesb(p, v, l) #define writesw(p, v, l) __ixp4xx_writesw(p, v, l) @@ -97,8 +97,9 @@ __ixp4xx_iounmap(void __iomem *addr) #define readsl(p, v, l) __ixp4xx_readsl(p, v, l) static inline void -__ixp4xx_writeb(u8 value, u32 addr) +__ixp4xx_writeb(u8 value, volatile void __iomem *p) { + u32 addr = (u32)p; u32 n, byte_enables, data; if (addr >= VMALLOC_START) { @@ -113,15 +114,16 @@ __ixp4xx_writeb(u8 value, u32 addr) } static inline void -__ixp4xx_writesb(u32 bus_addr, const u8 *vaddr, int count) +__ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count) { while (count--) writeb(*vaddr++, bus_addr); } static inline void -__ixp4xx_writew(u16 value, u32 addr) +__ixp4xx_writew(u16 value, volatile void __iomem *p) { + u32 addr = (u32)p; u32 n, byte_enables, data; if (addr >= VMALLOC_START) { @@ -136,15 +138,16 @@ __ixp4xx_writew(u16 value, u32 addr) } static inline void -__ixp4xx_writesw(u32 bus_addr, const u16 *vaddr, int count) +__ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count) { while (count--) writew(*vaddr++, bus_addr); } static inline void -__ixp4xx_writel(u32 value, u32 addr) +__ixp4xx_writel(u32 value, volatile void __iomem *p) { + u32 addr = (u32)p; if (addr >= VMALLOC_START) { __raw_writel(value, addr); return; @@ -154,15 +157,16 @@ __ixp4xx_writel(u32 value, u32 addr) } static inline void -__ixp4xx_writesl(u32 bus_addr, const u32 *vaddr, int count) +__ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count) { while (count--) writel(*vaddr++, bus_addr); } static inline unsigned char -__ixp4xx_readb(u32 addr) +__ixp4xx_readb(const volatile void __iomem *p) { + u32 addr = (u32)p; u32 n, byte_enables, data; if (addr >= VMALLOC_START) @@ -177,15 +181,16 @@ __ixp4xx_readb(u32 addr) } static inline void -__ixp4xx_readsb(u32 bus_addr, u8 *vaddr, u32 count) +__ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count) { while (count--) *vaddr++ = readb(bus_addr); } static inline unsigned short -__ixp4xx_readw(u32 addr) +__ixp4xx_readw(const volatile void __iomem *p) { + u32 addr = (u32)p; u32 n, byte_enables, data; if (addr >= VMALLOC_START) @@ -200,15 +205,16 @@ __ixp4xx_readw(u32 addr) } static inline void -__ixp4xx_readsw(u32 bus_addr, u16 *vaddr, u32 count) +__ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count) { while (count--) *vaddr++ = readw(bus_addr); } static inline unsigned long -__ixp4xx_readl(u32 addr) +__ixp4xx_readl(const volatile void __iomem *p) { + u32 addr = (u32)p; u32 data; if (addr >= VMALLOC_START) @@ -221,7 +227,7 @@ __ixp4xx_readl(u32 addr) } static inline void -__ixp4xx_readsl(u32 bus_addr, u32 *vaddr, u32 count) +__ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count) { while (count--) *vaddr++ = readl(bus_addr); @@ -239,7 +245,7 @@ __ixp4xx_readsl(u32 bus_addr, u32 *vaddr, u32 count) eth_copy_and_sum((s),__mem_pci(c),(l),(b)) static inline int -check_signature(unsigned long bus_addr, const unsigned char *signature, +check_signature(const unsigned char __iomem *bus_addr, const unsigned char *signature, int length) { int retval = 0; @@ -389,7 +395,7 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count) #define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \ ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) static inline unsigned int -__ixp4xx_ioread8(void __iomem *addr) +__ixp4xx_ioread8(const void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) @@ -398,12 +404,12 @@ __ixp4xx_ioread8(void __iomem *addr) #ifndef CONFIG_IXP4XX_INDIRECT_PCI return (unsigned int)__raw_readb(port); #else - return (unsigned int)__ixp4xx_readb(port); + return (unsigned int)__ixp4xx_readb(addr); #endif } static inline void -__ixp4xx_ioread8_rep(void __iomem *addr, void *vaddr, u32 count) +__ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) @@ -412,12 +418,12 @@ __ixp4xx_ioread8_rep(void __iomem *addr, void *vaddr, u32 count) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsb(addr, vaddr, count); #else - __ixp4xx_readsb(port, vaddr, count); + __ixp4xx_readsb(addr, vaddr, count); #endif } static inline unsigned int -__ixp4xx_ioread16(void __iomem *addr) +__ixp4xx_ioread16(const void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) @@ -426,12 +432,12 @@ __ixp4xx_ioread16(void __iomem *addr) #ifndef CONFIG_IXP4XX_INDIRECT_PCI return le16_to_cpu(__raw_readw((u32)port)); #else - return (unsigned int)__ixp4xx_readw((u32)port); + return (unsigned int)__ixp4xx_readw(addr); #endif } static inline void -__ixp4xx_ioread16_rep(void __iomem *addr, void *vaddr, u32 count) +__ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) @@ -440,12 +446,12 @@ __ixp4xx_ioread16_rep(void __iomem *addr, void *vaddr, u32 count) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsw(addr, vaddr, count); #else - __ixp4xx_readsw(port, vaddr, count); + __ixp4xx_readsw(addr, vaddr, count); #endif } static inline unsigned int -__ixp4xx_ioread32(void __iomem *addr) +__ixp4xx_ioread32(const void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) @@ -454,13 +460,13 @@ __ixp4xx_ioread32(void __iomem *addr) #ifndef CONFIG_IXP4XX_INDIRECT_PCI return le32_to_cpu(__raw_readl((u32)port)); #else - return (unsigned int)__ixp4xx_readl((u32)port); + return (unsigned int)__ixp4xx_readl(addr); #endif } } static inline void -__ixp4xx_ioread32_rep(void __iomem *addr, void *vaddr, u32 count) +__ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) @@ -469,7 +475,7 @@ __ixp4xx_ioread32_rep(void __iomem *addr, void *vaddr, u32 count) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsl(addr, vaddr, count); #else - __ixp4xx_readsl(port, vaddr, count); + __ixp4xx_readsl(addr, vaddr, count); #endif } @@ -483,7 +489,7 @@ __ixp4xx_iowrite8(u8 value, void __iomem *addr) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writeb(value, port); #else - __ixp4xx_writeb(value, port); + __ixp4xx_writeb(value, addr); #endif } @@ -497,7 +503,7 @@ __ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesb(addr, vaddr, count); #else - __ixp4xx_writesb(port, vaddr, count); + __ixp4xx_writesb(addr, vaddr, count); #endif } @@ -511,7 +517,7 @@ __ixp4xx_iowrite16(u16 value, void __iomem *addr) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writew(cpu_to_le16(value), addr); #else - __ixp4xx_writew(value, port); + __ixp4xx_writew(value, addr); #endif } @@ -525,7 +531,7 @@ __ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesw(addr, vaddr, count); #else - __ixp4xx_writesw(port, vaddr, count); + __ixp4xx_writesw(addr, vaddr, count); #endif } @@ -539,7 +545,7 @@ __ixp4xx_iowrite32(u32 value, void __iomem *addr) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writel(cpu_to_le32(value), port); #else - __ixp4xx_writel(value, port); + __ixp4xx_writel(value, addr); #endif } @@ -553,7 +559,7 @@ __ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesl(addr, vaddr, count); #else - __ixp4xx_writesl(port, vaddr, count); + __ixp4xx_writesl(addr, vaddr, count); #endif } diff --git a/include/asm-arm/arch-realview/debug-macro.S b/include/asm-arm/arch-realview/debug-macro.S new file mode 100644 index 000000000000..ed28bd012236 --- /dev/null +++ b/include/asm-arm/arch-realview/debug-macro.S @@ -0,0 +1,38 @@ +/* linux/include/asm-arm/arch-realview/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + +#include <asm/hardware/amba_serial.h> + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + moveq \rx, #0x10000000 + movne \rx, #0xf1000000 @ virtual base + orr \rx, \rx, #0x00009000 + .endm + + .macro senduart,rd,rx + strb \rd, [\rx, #UART01x_DR] + .endm + + .macro waituart,rd,rx +1001: ldr \rd, [\rx, #0x18] @ UARTFLG + tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full + bne 1001b + .endm + + .macro busyuart,rd,rx +1001: ldr \rd, [\rx, #0x18] @ UARTFLG + tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy + bne 1001b + .endm diff --git a/include/asm-arm/arch-realview/dma.h b/include/asm-arm/arch-realview/dma.h new file mode 100644 index 000000000000..744491a74bd9 --- /dev/null +++ b/include/asm-arm/arch-realview/dma.h @@ -0,0 +1,27 @@ +/* + * linux/include/asm-arm/arch-realview/dma.h + * + * Copyright (C) 2003 ARM Limited. + * Copyright (C) 1997,1998 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +#define MAX_DMA_ADDRESS 0xffffffff +#define MAX_DMA_CHANNELS 0 + +#endif /* _ASM_ARCH_DMA_H */ diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S new file mode 100644 index 000000000000..2712ba77bb3a --- /dev/null +++ b/include/asm-arm/arch-realview/entry-macro.S @@ -0,0 +1,49 @@ +/* + * include/asm-arm/arch-realview/entry-macro.S + * + * Low-level IRQ helper macros for RealView platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <asm/hardware/gic.h> + + .macro disable_fiq + .endm + + /* + * The interrupt numbering scheme is defined in the + * interrupt controller spec. To wit: + * + * Interrupts 0-15 are IPI + * 16-28 are reserved + * 29-31 are local. We allow 30 to be used for the watchdog. + * 32-1020 are global + * 1021-1022 are reserved + * 1023 is "spurious" (no interrupt) + * + * For now, we ignore all local interrupts so only return an interrupt if it's + * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs. + * + * A simple read from the controller will tell us the number of the highest + * priority enabled interrupt. We then just need to check whether it is in the + * valid range for an IRQ (30-1020 inclusive). + */ + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE) + ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */ + + ldr \tmp, =1021 + + bic \irqnr, \irqstat, #0x1c00 + + cmp \irqnr, #29 + cmpcc \irqnr, \irqnr + cmpne \irqnr, \tmp + cmpcs \irqnr, \irqnr + + .endm diff --git a/include/asm-arm/arch-realview/hardware.h b/include/asm-arm/arch-realview/hardware.h new file mode 100644 index 000000000000..67879cdb6ef2 --- /dev/null +++ b/include/asm-arm/arch-realview/hardware.h @@ -0,0 +1,31 @@ +/* + * linux/include/asm-arm/arch-realview/hardware.h + * + * This file contains the hardware definitions of the RealView boards. + * + * Copyright (C) 2003 ARM Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <asm/sizes.h> +#include <asm/arch/platform.h> + +/* macro to get at IO space when running virtually */ +#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) + +#endif diff --git a/include/asm-arm/arch-realview/io.h b/include/asm-arm/arch-realview/io.h new file mode 100644 index 000000000000..d444a68ac330 --- /dev/null +++ b/include/asm-arm/arch-realview/io.h @@ -0,0 +1,34 @@ +/* + * linux/include/asm-arm/arch-realview/io.h + * + * Copyright (C) 2003 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +static inline void __iomem *__io(unsigned long addr) +{ + return (void __iomem *)addr; +} + +#define __io(a) __io(a) +#define __mem_pci(a) (a) +#define __mem_isa(a) (a) + +#endif diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h new file mode 100644 index 000000000000..ff376494e5b1 --- /dev/null +++ b/include/asm-arm/arch-realview/irqs.h @@ -0,0 +1,103 @@ +/* + * linux/include/asm-arm/arch-realview/irqs.h + * + * Copyright (C) 2003 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <asm/arch/platform.h> + +/* + * IRQ interrupts definitions are the same the INT definitions + * held within platform.h + */ +#define IRQ_GIC_START 32 +#define IRQ_WDOGINT (IRQ_GIC_START + INT_WDOGINT) +#define IRQ_SOFTINT (IRQ_GIC_START + INT_SOFTINT) +#define IRQ_COMMRx (IRQ_GIC_START + INT_COMMRx) +#define IRQ_COMMTx (IRQ_GIC_START + INT_COMMTx) +#define IRQ_TIMERINT0_1 (IRQ_GIC_START + INT_TIMERINT0_1) +#define IRQ_TIMERINT2_3 (IRQ_GIC_START + INT_TIMERINT2_3) +#define IRQ_GPIOINT0 (IRQ_GIC_START + INT_GPIOINT0) +#define IRQ_GPIOINT1 (IRQ_GIC_START + INT_GPIOINT1) +#define IRQ_GPIOINT2 (IRQ_GIC_START + INT_GPIOINT2) +#define IRQ_GPIOINT3 (IRQ_GIC_START + INT_GPIOINT3) +#define IRQ_RTCINT (IRQ_GIC_START + INT_RTCINT) +#define IRQ_SSPINT (IRQ_GIC_START + INT_SSPINT) +#define IRQ_UARTINT0 (IRQ_GIC_START + INT_UARTINT0) +#define IRQ_UARTINT1 (IRQ_GIC_START + INT_UARTINT1) +#define IRQ_UARTINT2 (IRQ_GIC_START + INT_UARTINT2) +#define IRQ_UART3 (IRQ_GIC_START + INT_UARTINT3) +#define IRQ_SCIINT (IRQ_GIC_START + INT_SCIINT) +#define IRQ_CLCDINT (IRQ_GIC_START + INT_CLCDINT) +#define IRQ_DMAINT (IRQ_GIC_START + INT_DMAINT) +#define IRQ_PWRFAILINT (IRQ_GIC_START + INT_PWRFAILINT) +#define IRQ_MBXINT (IRQ_GIC_START + INT_MBXINT) +#define IRQ_GNDINT (IRQ_GIC_START + INT_GNDINT) +#define IRQ_MMCI0B (IRQ_GIC_START + INT_MMCI0B) +#define IRQ_MMCI1B (IRQ_GIC_START + INT_MMCI1B) +#define IRQ_KMI0 (IRQ_GIC_START + INT_KMI0) +#define IRQ_KMI1 (IRQ_GIC_START + INT_KMI1) +#define IRQ_SCI3 (IRQ_GIC_START + INT_SCI3) +#define IRQ_CLCD (IRQ_GIC_START + INT_CLCD) +#define IRQ_TOUCH (IRQ_GIC_START + INT_TOUCH) +#define IRQ_KEYPAD (IRQ_GIC_START + INT_KEYPAD) +#define IRQ_DoC (IRQ_GIC_START + INT_DoC) +#define IRQ_MMCI0A (IRQ_GIC_START + INT_MMCI0A) +#define IRQ_MMCI1A (IRQ_GIC_START + INT_MMCI1A) +#define IRQ_AACI (IRQ_GIC_START + INT_AACI) +#define IRQ_ETH (IRQ_GIC_START + INT_ETH) +#define IRQ_USB (IRQ_GIC_START + INT_USB) + +#define IRQMASK_WDOGINT INTMASK_WDOGINT +#define IRQMASK_SOFTINT INTMASK_SOFTINT +#define IRQMASK_COMMRx INTMASK_COMMRx +#define IRQMASK_COMMTx INTMASK_COMMTx +#define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1 +#define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3 +#define IRQMASK_GPIOINT0 INTMASK_GPIOINT0 +#define IRQMASK_GPIOINT1 INTMASK_GPIOINT1 +#define IRQMASK_GPIOINT2 INTMASK_GPIOINT2 +#define IRQMASK_GPIOINT3 INTMASK_GPIOINT3 +#define IRQMASK_RTCINT INTMASK_RTCINT +#define IRQMASK_SSPINT INTMASK_SSPINT +#define IRQMASK_UARTINT0 INTMASK_UARTINT0 +#define IRQMASK_UARTINT1 INTMASK_UARTINT1 +#define IRQMASK_UARTINT2 INTMASK_UARTINT2 +#define IRQMASK_SCIINT INTMASK_SCIINT +#define IRQMASK_CLCDINT INTMASK_CLCDINT +#define IRQMASK_DMAINT INTMASK_DMAINT +#define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT +#define IRQMASK_MBXINT INTMASK_MBXINT +#define IRQMASK_GNDINT INTMASK_GNDINT +#define IRQMASK_MMCI0B INTMASK_MMCI0B +#define IRQMASK_MMCI1B INTMASK_MMCI1B +#define IRQMASK_KMI0 INTMASK_KMI0 +#define IRQMASK_KMI1 INTMASK_KMI1 +#define IRQMASK_SCI3 INTMASK_SCI3 +#define IRQMASK_UART3 INTMASK_UART3 +#define IRQMASK_CLCD INTMASK_CLCD +#define IRQMASK_TOUCH INTMASK_TOUCH +#define IRQMASK_KEYPAD INTMASK_KEYPAD +#define IRQMASK_DoC INTMASK_DoC +#define IRQMASK_MMCI0A INTMASK_MMCI0A +#define IRQMASK_MMCI1A INTMASK_MMCI1A +#define IRQMASK_AACI INTMASK_AACI +#define IRQMASK_ETH INTMASK_ETH +#define IRQMASK_USB INTMASK_USB + +#define NR_IRQS (IRQ_GIC_START + 64) diff --git a/include/asm-arm/arch-realview/memory.h b/include/asm-arm/arch-realview/memory.h new file mode 100644 index 000000000000..ed370abb638f --- /dev/null +++ b/include/asm-arm/arch-realview/memory.h @@ -0,0 +1,38 @@ +/* + * linux/include/asm-arm/arch-realview/memory.h + * + * Copyright (C) 2003 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +/* + * Physical DRAM offset. + */ +#define PHYS_OFFSET UL(0x00000000) + +/* + * Virtual view <-> DMA view memory address translations + * virt_to_bus: Used to translate the virtual address to an + * address suitable to be passed to set_dma_addr + * bus_to_virt: Used to convert an address for DMA operations + * to an address that the kernel can use. + */ +#define __virt_to_bus(x) ((x) - PAGE_OFFSET) +#define __bus_to_virt(x) ((x) + PAGE_OFFSET) + +#endif diff --git a/include/asm-arm/arch-realview/param.h b/include/asm-arm/arch-realview/param.h new file mode 100644 index 000000000000..89b1235d32bd --- /dev/null +++ b/include/asm-arm/arch-realview/param.h @@ -0,0 +1,19 @@ +/* + * linux/include/asm-arm/arch-realview/param.h + * + * Copyright (C) 2002 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h new file mode 100644 index 000000000000..4b6de13a6b9a --- /dev/null +++ b/include/asm-arm/arch-realview/platform.h @@ -0,0 +1,395 @@ +/* + * linux/include/asm-arm/arch-realview/platform.h + * + * Copyright (c) ARM Limited 2003. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __address_h +#define __address_h 1 + +/* + * Memory definitions + */ +#define REALVIEW_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)...*/ +#define REALVIEW_BOOT_ROM_HI 0x30000000 +#define REALVIEW_BOOT_ROM_BASE REALVIEW_BOOT_ROM_HI /* Normal position */ +#define REALVIEW_BOOT_ROM_SIZE SZ_64M + +#define REALVIEW_SSRAM_BASE /* REALVIEW_SSMC_BASE ? */ +#define REALVIEW_SSRAM_SIZE SZ_2M + +#define REALVIEW_FLASH_BASE 0x40000000 +#define REALVIEW_FLASH_SIZE SZ_64M + +/* + * SDRAM + */ +#define REALVIEW_SDRAM_BASE 0x00000000 + +/* + * Logic expansion modules + * + */ + + +/* ------------------------------------------------------------------------ + * RealView Registers + * ------------------------------------------------------------------------ + * + */ +#define REALVIEW_SYS_ID_OFFSET 0x00 +#define REALVIEW_SYS_SW_OFFSET 0x04 +#define REALVIEW_SYS_LED_OFFSET 0x08 +#define REALVIEW_SYS_OSC0_OFFSET 0x0C + +#define REALVIEW_SYS_OSC1_OFFSET 0x10 +#define REALVIEW_SYS_OSC2_OFFSET 0x14 +#define REALVIEW_SYS_OSC3_OFFSET 0x18 +#define REALVIEW_SYS_OSC4_OFFSET 0x1C /* OSC1 for RealView/AB */ + +#define REALVIEW_SYS_LOCK_OFFSET 0x20 +#define REALVIEW_SYS_100HZ_OFFSET 0x24 +#define REALVIEW_SYS_CFGDATA1_OFFSET 0x28 +#define REALVIEW_SYS_CFGDATA2_OFFSET 0x2C +#define REALVIEW_SYS_FLAGS_OFFSET 0x30 +#define REALVIEW_SYS_FLAGSSET_OFFSET 0x30 +#define REALVIEW_SYS_FLAGSCLR_OFFSET 0x34 +#define REALVIEW_SYS_NVFLAGS_OFFSET 0x38 +#define REALVIEW_SYS_NVFLAGSSET_OFFSET 0x38 +#define REALVIEW_SYS_NVFLAGSCLR_OFFSET 0x3C +#define REALVIEW_SYS_RESETCTL_OFFSET 0x40 +#define REALVIEW_SYS_PCICTL_OFFSET 0x44 +#define REALVIEW_SYS_MCI_OFFSET 0x48 +#define REALVIEW_SYS_FLASH_OFFSET 0x4C +#define REALVIEW_SYS_CLCD_OFFSET 0x50 +#define REALVIEW_SYS_CLCDSER_OFFSET 0x54 +#define REALVIEW_SYS_BOOTCS_OFFSET 0x58 +#define REALVIEW_SYS_24MHz_OFFSET 0x5C +#define REALVIEW_SYS_MISC_OFFSET 0x60 +#define REALVIEW_SYS_IOSEL_OFFSET 0x70 +#define REALVIEW_SYS_TEST_OSC0_OFFSET 0x80 +#define REALVIEW_SYS_TEST_OSC1_OFFSET 0x84 +#define REALVIEW_SYS_TEST_OSC2_OFFSET 0x88 +#define REALVIEW_SYS_TEST_OSC3_OFFSET 0x8C +#define REALVIEW_SYS_TEST_OSC4_OFFSET 0x90 + +#define REALVIEW_SYS_BASE 0x10000000 +#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET) +#define REALVIEW_SYS_SW (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET) +#define REALVIEW_SYS_LED (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET) +#define REALVIEW_SYS_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET) +#define REALVIEW_SYS_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET) + +#define REALVIEW_SYS_LOCK (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET) +#define REALVIEW_SYS_100HZ (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET) +#define REALVIEW_SYS_CFGDATA1 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET) +#define REALVIEW_SYS_CFGDATA2 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET) +#define REALVIEW_SYS_FLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET) +#define REALVIEW_SYS_FLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET) +#define REALVIEW_SYS_FLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET) +#define REALVIEW_SYS_NVFLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET) +#define REALVIEW_SYS_NVFLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET) +#define REALVIEW_SYS_NVFLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET) +#define REALVIEW_SYS_RESETCTL (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET) +#define REALVIEW_SYS_PCICTL (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET) +#define REALVIEW_SYS_MCI (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET) +#define REALVIEW_SYS_FLASH (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET) +#define REALVIEW_SYS_CLCD (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET) +#define REALVIEW_SYS_CLCDSER (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET) +#define REALVIEW_SYS_BOOTCS (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET) +#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET) +#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET) +#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET) +#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET) +#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET) +#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET) +#define REALVIEW_SYS_TEST_OSC3 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET) +#define REALVIEW_SYS_TEST_OSC4 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET) + +/* + * Values for REALVIEW_SYS_RESET_CTRL + */ +#define REALVIEW_SYS_CTRL_RESET_CONFIGCLR 0x01 +#define REALVIEW_SYS_CTRL_RESET_CONFIGINIT 0x02 +#define REALVIEW_SYS_CTRL_RESET_DLLRESET 0x03 +#define REALVIEW_SYS_CTRL_RESET_PLLRESET 0x04 +#define REALVIEW_SYS_CTRL_RESET_POR 0x05 +#define REALVIEW_SYS_CTRL_RESET_DoC 0x06 + +#define REALVIEW_SYS_CTRL_LED (1 << 0) + + +/* ------------------------------------------------------------------------ + * RealView control registers + * ------------------------------------------------------------------------ + */ + +/* + * REALVIEW_IDFIELD + * + * 31:24 = manufacturer (0x41 = ARM) + * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus) + * 15:12 = FPGA (0x3 = XVC600 or XVC600E) + * 11:4 = build value + * 3:0 = revision number (0x1 = rev B (AHB)) + */ + +/* + * REALVIEW_SYS_LOCK + * control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL, + * SYS_CLD, SYS_BOOTCS + */ +#define REALVIEW_SYS_LOCK_LOCKED (1 << 16) +#define REALVIEW_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */ + +/* + * REALVIEW_SYS_FLASH + */ +#define REALVIEW_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */ + +/* + * REALVIEW_INTREG + * - used to acknowledge and control MMCI and UART interrupts + */ +#define REALVIEW_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */ +#define REALVIEW_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */ +#define REALVIEW_INTREG_CARDIN 0x08 /* MMCI card in detect */ + /* write 1 to acknowledge and clear */ +#define REALVIEW_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */ +#define REALVIEW_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */ + +/* + * REALVIEW peripheral addresses + */ +#define REALVIEW_SCTL_BASE 0x10001000 /* System controller */ +#define REALVIEW_I2C_BASE 0x10002000 /* I2C control */ + /* Reserved 0x10003000 */ +#define REALVIEW_AACI_BASE 0x10004000 /* Audio */ +#define REALVIEW_MMCI0_BASE 0x10005000 /* MMC interface */ +#define REALVIEW_KMI0_BASE 0x10006000 /* KMI interface */ +#define REALVIEW_KMI1_BASE 0x10007000 /* KMI 2nd interface */ +#define REALVIEW_CHAR_LCD_BASE 0x10008000 /* Character LCD */ +#define REALVIEW_UART0_BASE 0x10009000 /* UART 0 */ +#define REALVIEW_UART1_BASE 0x1000A000 /* UART 1 */ +#define REALVIEW_UART2_BASE 0x1000B000 /* UART 2 */ +#define REALVIEW_UART3_BASE 0x1000C000 /* UART 3 */ +#define REALVIEW_SSP_BASE 0x1000D000 /* Synchronous Serial Port */ +#define REALVIEW_SCI_BASE 0x1000E000 /* Smart card controller */ + /* Reserved 0x1000F000 */ +#define REALVIEW_WATCHDOG_BASE 0x10010000 /* watchdog interface */ +#define REALVIEW_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */ +#define REALVIEW_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */ +#define REALVIEW_GPIO0_BASE 0x10013000 /* GPIO port 0 */ +#define REALVIEW_GPIO1_BASE 0x10014000 /* GPIO port 1 */ +#define REALVIEW_GPIO2_BASE 0x10015000 /* GPIO port 2 */ + /* Reserved 0x10016000 */ +#define REALVIEW_RTC_BASE 0x10017000 /* Real Time Clock */ +#define REALVIEW_DMC_BASE 0x10018000 /* DMC configuration */ +#define REALVIEW_PCI_CORE_BASE 0x10019000 /* PCI configuration */ + /* Reserved 0x1001A000 - 0x1001FFFF */ +#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */ +#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */ +#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */ +#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */ +#define REALVIEW_SMC_BASE 0x10080000 /* SMC */ + /* Reserved 0x10090000 - 0x100EFFFF */ + +#define REALVIEW_ETH_BASE 0x4E000000 /* Ethernet */ + +/* PCI space */ +#define REALVIEW_PCI_BASE 0x41000000 /* PCI Interface */ +#define REALVIEW_PCI_CFG_BASE 0x42000000 +#define REALVIEW_PCI_MEM_BASE0 0x44000000 +#define REALVIEW_PCI_MEM_BASE1 0x50000000 +#define REALVIEW_PCI_MEM_BASE2 0x60000000 +/* Sizes of above maps */ +#define REALVIEW_PCI_BASE_SIZE 0x01000000 +#define REALVIEW_PCI_CFG_BASE_SIZE 0x02000000 +#define REALVIEW_PCI_MEM_BASE0_SIZE 0x0c000000 /* 32Mb */ +#define REALVIEW_PCI_MEM_BASE1_SIZE 0x10000000 /* 256Mb */ +#define REALVIEW_PCI_MEM_BASE2_SIZE 0x10000000 /* 256Mb */ + +#define REALVIEW_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */ +#define REALVIEW_LT_BASE 0x80000000 /* Logic Tile expansion */ + +/* + * Disk on Chip + */ +#define REALVIEW_DOC_BASE 0x2C000000 +#define REALVIEW_DOC_SIZE (16 << 20) +#define REALVIEW_DOC_PAGE_SIZE 512 +#define REALVIEW_DOC_TOTAL_PAGES (DOC_SIZE / PAGE_SIZE) + +#define ERASE_UNIT_PAGES 32 +#define START_PAGE 0x80 + +/* + * LED settings, bits [7:0] + */ +#define REALVIEW_SYS_LED0 (1 << 0) +#define REALVIEW_SYS_LED1 (1 << 1) +#define REALVIEW_SYS_LED2 (1 << 2) +#define REALVIEW_SYS_LED3 (1 << 3) +#define REALVIEW_SYS_LED4 (1 << 4) +#define REALVIEW_SYS_LED5 (1 << 5) +#define REALVIEW_SYS_LED6 (1 << 6) +#define REALVIEW_SYS_LED7 (1 << 7) + +#define ALL_LEDS 0xFF + +#define LED_BANK REALVIEW_SYS_LED + +/* + * Control registers + */ +#define REALVIEW_IDFIELD_OFFSET 0x0 /* RealView build information */ +#define REALVIEW_FLASHPROG_OFFSET 0x4 /* Flash devices */ +#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */ +#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */ + +/* ------------------------------------------------------------------------ + * Interrupts - bit assignment (primary) + * ------------------------------------------------------------------------ + */ +#define INT_WDOGINT 0 /* Watchdog timer */ +#define INT_SOFTINT 1 /* Software interrupt */ +#define INT_COMMRx 2 /* Debug Comm Rx interrupt */ +#define INT_COMMTx 3 /* Debug Comm Tx interrupt */ +#define INT_TIMERINT0_1 4 /* Timer 0 and 1 */ +#define INT_TIMERINT2_3 5 /* Timer 2 and 3 */ +#define INT_GPIOINT0 6 /* GPIO 0 */ +#define INT_GPIOINT1 7 /* GPIO 1 */ +#define INT_GPIOINT2 8 /* GPIO 2 */ +/* 9 reserved */ +#define INT_RTCINT 10 /* Real Time Clock */ +#define INT_SSPINT 11 /* Synchronous Serial Port */ +#define INT_UARTINT0 12 /* UART 0 on development chip */ +#define INT_UARTINT1 13 /* UART 1 on development chip */ +#define INT_UARTINT2 14 /* UART 2 on development chip */ +#define INT_UARTINT3 15 /* UART 3 on development chip */ +#define INT_SCIINT 16 /* Smart Card Interface */ +#define INT_MMCI0A 17 /* Multimedia Card 0A */ +#define INT_MMCI0B 18 /* Multimedia Card 0B */ +#define INT_AACI 19 /* Audio Codec */ +#define INT_KMI0 20 /* Keyboard/Mouse port 0 */ +#define INT_KMI1 21 /* Keyboard/Mouse port 1 */ +#define INT_CHARLCD 22 /* Character LCD */ +#define INT_CLCDINT 23 /* CLCD controller */ +#define INT_DMAINT 24 /* DMA controller */ +#define INT_PWRFAILINT 25 /* Power failure */ +#define INT_PISMO 26 +#define INT_DoC 27 /* Disk on Chip memory controller */ +#define INT_ETH 28 /* Ethernet controller */ +#define INT_USB 29 /* USB controller */ +#define INT_TSPENINT 30 /* Touchscreen pen */ +#define INT_TSKPADINT 31 /* Touchscreen keypad */ + +/* + * Interrupt bit positions + * + */ +#define INTMASK_WDOGINT (1 << INT_WDOGINT) +#define INTMASK_SOFTINT (1 << INT_SOFTINT) +#define INTMASK_COMMRx (1 << INT_COMMRx) +#define INTMASK_COMMTx (1 << INT_COMMTx) +#define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1) +#define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3) +#define INTMASK_GPIOINT0 (1 << INT_GPIOINT0) +#define INTMASK_GPIOINT1 (1 << INT_GPIOINT1) +#define INTMASK_GPIOINT2 (1 << INT_GPIOINT2) +#define INTMASK_RTCINT (1 << INT_RTCINT) +#define INTMASK_SSPINT (1 << INT_SSPINT) +#define INTMASK_UARTINT0 (1 << INT_UARTINT0) +#define INTMASK_UARTINT1 (1 << INT_UARTINT1) +#define INTMASK_UARTINT2 (1 << INT_UARTINT2) +#define INTMASK_UARTINT3 (1 << INT_UARTINT3) +#define INTMASK_SCIINT (1 << INT_SCIINT) +#define INTMASK_MMCI0A (1 << INT_MMCI0A) +#define INTMASK_MMCI0B (1 << INT_MMCI0B) +#define INTMASK_AACI (1 << INT_AACI) +#define INTMASK_KMI0 (1 << INT_KMI0) +#define INTMASK_KMI1 (1 << INT_KMI1) +#define INTMASK_CHARLCD (1 << INT_CHARLCD) +#define INTMASK_CLCDINT (1 << INT_CLCDINT) +#define INTMASK_DMAINT (1 << INT_DMAINT) +#define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT) +#define INTMASK_PISMO (1 << INT_PISMO) +#define INTMASK_DoC (1 << INT_DoC) +#define INTMASK_ETH (1 << INT_ETH) +#define INTMASK_USB (1 << INT_USB) +#define INTMASK_TSPENINT (1 << INT_TSPENINT) +#define INTMASK_TSKPADINT (1 << INT_TSKPADINT) + +#define MAXIRQNUM 31 +#define MAXFIQNUM 31 +#define MAXSWINUM 31 + +/* + * Application Flash + * + */ +#define FLASH_BASE REALVIEW_FLASH_BASE +#define FLASH_SIZE REALVIEW_FLASH_SIZE +#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1) +#define FLASH_BLOCK_SIZE SZ_128K + +/* + * Boot Flash + * + */ +#define EPROM_BASE REALVIEW_BOOT_ROM_HI +#define EPROM_SIZE REALVIEW_BOOT_ROM_SIZE +#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1) + +/* + * Clean base - dummy + * + */ +#define CLEAN_BASE EPROM_BASE + +/* + * System controller bit assignment + */ +#define REALVIEW_REFCLK 0 +#define REALVIEW_TIMCLK 1 + +#define REALVIEW_TIMER1_EnSel 15 +#define REALVIEW_TIMER2_EnSel 17 +#define REALVIEW_TIMER3_EnSel 19 +#define REALVIEW_TIMER4_EnSel 21 + + +#define MAX_TIMER 2 +#define MAX_PERIOD 699050 +#define TICKS_PER_uSEC 1 + +/* + * These are useconds NOT ticks. + * + */ +#define mSEC_1 1000 +#define mSEC_5 (mSEC_1 * 5) +#define mSEC_10 (mSEC_1 * 10) +#define mSEC_25 (mSEC_1 * 25) +#define SEC_1 (mSEC_1 * 1000) + +#define REALVIEW_CSR_BASE 0x10000000 +#define REALVIEW_CSR_SIZE 0x10000000 + +#endif + +/* END */ diff --git a/include/asm-arm/arch-realview/system.h b/include/asm-arm/arch-realview/system.h new file mode 100644 index 000000000000..9f8fcbca0869 --- /dev/null +++ b/include/asm-arm/arch-realview/system.h @@ -0,0 +1,51 @@ +/* + * linux/include/asm-arm/arch-realview/system.h + * + * Copyright (C) 2003 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include <asm/hardware.h> +#include <asm/io.h> +#include <asm/arch/platform.h> + +static inline void arch_idle(void) +{ + /* + * This should do all the clock switching + * and wait for interrupt tricks + */ + cpu_do_idle(); +} + +static inline void arch_reset(char mode) +{ + unsigned int hdr_ctrl = (IO_ADDRESS(REALVIEW_SYS_BASE) + REALVIEW_SYS_RESETCTL_OFFSET); + unsigned int val; + + /* + * To reset, we hit the on-board reset register + * in the system FPGA + */ + val = __raw_readl(hdr_ctrl); + val |= REALVIEW_SYS_CTRL_RESET_CONFIGCLR; + __raw_writel(val, hdr_ctrl); +} + +#endif diff --git a/include/asm-arm/arch-realview/timex.h b/include/asm-arm/arch-realview/timex.h new file mode 100644 index 000000000000..5b9d82d0a5e0 --- /dev/null +++ b/include/asm-arm/arch-realview/timex.h @@ -0,0 +1,23 @@ +/* + * linux/include/asm-arm/arch-realview/timex.h + * + * RealView architecture timex specifications + * + * Copyright (C) 2003 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#define CLOCK_TICK_RATE (50000000 / 16) diff --git a/include/asm-arm/arch-realview/uncompress.h b/include/asm-arm/arch-realview/uncompress.h new file mode 100644 index 000000000000..b5e4d360665b --- /dev/null +++ b/include/asm-arm/arch-realview/uncompress.h @@ -0,0 +1,54 @@ +/* + * linux/include/asm-arm/arch-realview/uncompress.h + * + * Copyright (C) 2003 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <asm/hardware.h> + +#define AMBA_UART_DR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00)) +#define AMBA_UART_LCRH (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c)) +#define AMBA_UART_CR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30)) +#define AMBA_UART_FR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x18)) + +/* + * This does not append a newline + */ +static void putstr(const char *s) +{ + while (*s) { + while (AMBA_UART_FR & (1 << 5)) + barrier(); + + AMBA_UART_DR = *s; + + if (*s == '\n') { + while (AMBA_UART_FR & (1 << 5)) + barrier(); + + AMBA_UART_DR = '\r'; + } + s++; + } + while (AMBA_UART_FR & (1 << 3)) + barrier(); +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-realview/vmalloc.h b/include/asm-arm/arch-realview/vmalloc.h new file mode 100644 index 000000000000..0ad49af186af --- /dev/null +++ b/include/asm-arm/arch-realview/vmalloc.h @@ -0,0 +1,21 @@ +/* + * linux/include/asm-arm/arch-realview/vmalloc.h + * + * Copyright (C) 2003 ARM Limited + * Copyright (C) 2000 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#define VMALLOC_END (PAGE_OFFSET + 0x18000000) diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/arch-s3c2410/regs-iis.h index fdd62e8cd6cb..7fdde9b91cb4 100644 --- a/include/asm-arm/arch-s3c2410/regs-iis.h +++ b/include/asm-arm/arch-s3c2410/regs-iis.h @@ -55,6 +55,7 @@ #define S3C2410_IISMOD_16FS (0<<0) #define S3C2410_IISMOD_32FS (1<<0) #define S3C2410_IISMOD_48FS (2<<0) +#define S3C2410_IISMOD_FS_MASK (3<<0) #define S3C2410_IISPSR (0x08) #define S3C2410_IISPSR_INTMASK (31<<5) diff --git a/include/asm-arm/cpu.h b/include/asm-arm/cpu.h index fcbdd40cb667..751bc7462074 100644 --- a/include/asm-arm/cpu.h +++ b/include/asm-arm/cpu.h @@ -16,6 +16,7 @@ struct cpuinfo_arm { struct cpu cpu; #ifdef CONFIG_SMP + struct task_struct *idle; unsigned int loops_per_jiffy; #endif }; diff --git a/include/asm-arm/hardware/amba_clcd.h b/include/asm-arm/hardware/amba_clcd.h index ce4cf5c1c05d..6b8d73dc1ab0 100644 --- a/include/asm-arm/hardware/amba_clcd.h +++ b/include/asm-arm/hardware/amba_clcd.h @@ -22,7 +22,7 @@ #define CLCD_UBAS 0x00000010 #define CLCD_LBAS 0x00000014 -#ifndef CONFIG_ARCH_VERSATILE +#if !defined(CONFIG_ARCH_VERSATILE) && !defined(CONFIG_ARCH_REALVIEW) #define CLCD_IENB 0x00000018 #define CLCD_CNTL 0x0000001c #else diff --git a/include/asm-arm/irq.h b/include/asm-arm/irq.h index f97912fbb10f..59975ee43cf1 100644 --- a/include/asm-arm/irq.h +++ b/include/asm-arm/irq.h @@ -47,5 +47,6 @@ struct irqaction; struct pt_regs; int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *); +extern void migrate_irqs(void); #endif diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h index dbb4d859c586..551cd3c3093c 100644 --- a/include/asm-arm/smp.h +++ b/include/asm-arm/smp.h @@ -66,4 +66,14 @@ struct secondary_data { }; extern struct secondary_data secondary_data; +extern int __cpu_disable(void); +extern int mach_cpu_disable(unsigned int cpu); + +extern void __cpu_die(unsigned int cpu); +extern void cpu_die(void); + +extern void platform_cpu_die(unsigned int cpu); +extern int platform_cpu_kill(unsigned int cpu); +extern void platform_cpu_enable(unsigned int cpu); + #endif /* ifndef __ASM_ARM_SMP_H */ diff --git a/include/asm-arm/spinlock.h b/include/asm-arm/spinlock.h index cb4906b45555..6ed4f916b166 100644 --- a/include/asm-arm/spinlock.h +++ b/include/asm-arm/spinlock.h @@ -80,7 +80,7 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock) */ #define rwlock_is_locked(x) (*((volatile unsigned int *)(x)) != 0) -static inline void __raw_write_lock(rwlock_t *rw) +static inline void __raw_write_lock(raw_rwlock_t *rw) { unsigned long tmp; @@ -97,7 +97,7 @@ static inline void __raw_write_lock(rwlock_t *rw) smp_mb(); } -static inline int __raw_write_trylock(rwlock_t *rw) +static inline int __raw_write_trylock(raw_rwlock_t *rw) { unsigned long tmp; @@ -157,7 +157,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw) smp_mb(); } -static inline void __raw_read_unlock(rwlock_t *rw) +static inline void __raw_read_unlock(raw_rwlock_t *rw) { unsigned long tmp, tmp2; diff --git a/include/asm-m68knommu/anchor.h b/include/asm-m68knommu/anchor.h index 75390e0b40c9..871c0d5cfc3d 100644 --- a/include/asm-m68knommu/anchor.h +++ b/include/asm-m68knommu/anchor.h @@ -14,7 +14,7 @@ /* * Define basic addressing info. */ -#if defined(CONFIG_MOTOROLA) && defined(CONFIG_M5407) +#if defined(CONFIG_M5407C3) #define COMEM_BASE 0xFFFF0000 /* Base of CO-MEM address space */ #define COMEM_IRQ 25 /* IRQ of anchor part */ #else @@ -96,7 +96,7 @@ * The PCI bus will be limited in what slots will actually be used. * Define valid device numbers for different boards. */ -#if defined(CONFIG_MOTOROLA) && defined(CONFIG_M5407) +#if defined(CONFIG_M5407C3) #define COMEM_MINDEV 14 /* Minimum valid DEVICE */ #define COMEM_MAXDEV 14 /* Maximum valid DEVICE */ #define COMEM_BRIDGEDEV 15 /* Slot bridge is in */ diff --git a/include/asm-m68knommu/asm-offsets.h b/include/asm-m68knommu/asm-offsets.h deleted file mode 100644 index 825f6e210f19..000000000000 --- a/include/asm-m68knommu/asm-offsets.h +++ /dev/null @@ -1,49 +0,0 @@ -#ifndef __ASM_OFFSETS_H__ -#define __ASM_OFFSETS_H__ -/* - * DO NOT MODIFY. - * - * This file was generated by arch/m68knommu/Makefile - * - */ - -#define TASK_STATE 0 /* offsetof(struct task_struct, state) */ -#define TASK_FLAGS 12 /* offsetof(struct task_struct, flags) */ -#define TASK_PTRACE 16 /* offsetof(struct task_struct, ptrace) */ -#define TASK_BLOCKED 922 /* offsetof(struct task_struct, blocked) */ -#define TASK_THREAD 772 /* offsetof(struct task_struct, thread) */ -#define TASK_THREAD_INFO 4 /* offsetof(struct task_struct, thread_info) */ -#define TASK_MM 92 /* offsetof(struct task_struct, mm) */ -#define TASK_ACTIVE_MM 96 /* offsetof(struct task_struct, active_mm) */ -#define CPUSTAT_SOFTIRQ_PENDING 0 /* offsetof(irq_cpustat_t, __softirq_pending) */ -#define THREAD_KSP 0 /* offsetof(struct thread_struct, ksp) */ -#define THREAD_USP 4 /* offsetof(struct thread_struct, usp) */ -#define THREAD_SR 8 /* offsetof(struct thread_struct, sr) */ -#define THREAD_FS 10 /* offsetof(struct thread_struct, fs) */ -#define THREAD_CRP 12 /* offsetof(struct thread_struct, crp) */ -#define THREAD_ESP0 20 /* offsetof(struct thread_struct, esp0) */ -#define THREAD_FPREG 24 /* offsetof(struct thread_struct, fp) */ -#define THREAD_FPCNTL 120 /* offsetof(struct thread_struct, fpcntl) */ -#define THREAD_FPSTATE 132 /* offsetof(struct thread_struct, fpstate) */ -#define PT_D0 32 /* offsetof(struct pt_regs, d0) */ -#define PT_ORIG_D0 36 /* offsetof(struct pt_regs, orig_d0) */ -#define PT_D1 0 /* offsetof(struct pt_regs, d1) */ -#define PT_D2 4 /* offsetof(struct pt_regs, d2) */ -#define PT_D3 8 /* offsetof(struct pt_regs, d3) */ -#define PT_D4 12 /* offsetof(struct pt_regs, d4) */ -#define PT_D5 16 /* offsetof(struct pt_regs, d5) */ -#define PT_A0 20 /* offsetof(struct pt_regs, a0) */ -#define PT_A1 24 /* offsetof(struct pt_regs, a1) */ -#define PT_A2 28 /* offsetof(struct pt_regs, a2) */ -#define PT_PC 48 /* offsetof(struct pt_regs, pc) */ -#define PT_SR 46 /* offsetof(struct pt_regs, sr) */ -#define PT_VECTOR 52 /* offsetof(struct pt_regs, pc) + 4 */ -#define STAT_IRQ 5140 /* offsetof(struct kernel_stat, irqs) */ -#define SIGSEGV 11 /* SIGSEGV */ -#define SEGV_MAPERR 196609 /* SEGV_MAPERR */ -#define SIGTRAP 5 /* SIGTRAP */ -#define TRAP_TRACE 196610 /* TRAP_TRACE */ -#define PT_PTRACED 1 /* PT_PTRACED */ -#define PT_DTRACE 2 /* PT_DTRACE */ - -#endif diff --git a/include/asm-m68knommu/atomic.h b/include/asm-m68knommu/atomic.h index b1957fba083b..a83631ed8c8f 100644 --- a/include/asm-m68knommu/atomic.h +++ b/include/asm-m68knommu/atomic.h @@ -100,7 +100,7 @@ static __inline__ void atomic_set_mask(unsigned long mask, unsigned long *v) #define smp_mb__before_atomic_inc() barrier() #define smp_mb__after_atomic_inc() barrier() -extern __inline__ int atomic_add_return(int i, atomic_t * v) +static inline int atomic_add_return(int i, atomic_t * v) { unsigned long temp, flags; @@ -115,7 +115,7 @@ extern __inline__ int atomic_add_return(int i, atomic_t * v) #define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0) -extern __inline__ int atomic_sub_return(int i, atomic_t * v) +static inline int atomic_sub_return(int i, atomic_t * v) { unsigned long temp, flags; diff --git a/include/asm-m68knommu/coldfire.h b/include/asm-m68knommu/coldfire.h index 1df3f666a28e..6190f77b1e6c 100644 --- a/include/asm-m68knommu/coldfire.h +++ b/include/asm-m68knommu/coldfire.h @@ -20,9 +20,14 @@ */ #define MCF_MBAR 0x10000000 #define MCF_MBAR2 0x80000000 +#if defined(CONFIG_M520x) +#define MCF_IPSBAR 0xFC000000 +#else #define MCF_IPSBAR 0x40000000 +#endif -#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) +#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ + defined(CONFIG_M520x) #undef MCF_MBAR #define MCF_MBAR MCF_IPSBAR #endif @@ -78,7 +83,8 @@ * One some ColdFire family members the bus clock (used by internal * peripherals) is not the same as the CPU clock. */ -#if defined(CONFIG_M523x) || defined(CONFIG_M5249) || defined(CONFIG_M527x) +#if defined(CONFIG_M523x) || defined(CONFIG_M5249) || defined(CONFIG_M527x) || \ + defined(CONFIG_M520x) #define MCF_BUSCLK (MCF_CLK / 2) #else #define MCF_BUSCLK MCF_CLK diff --git a/include/asm-m68knommu/delay.h b/include/asm-m68knommu/delay.h index e3a976254672..04a20fd051cf 100644 --- a/include/asm-m68knommu/delay.h +++ b/include/asm-m68knommu/delay.h @@ -8,7 +8,7 @@ #include <asm/param.h> -extern __inline__ void __delay(unsigned long loops) +static inline void __delay(unsigned long loops) { #if defined(CONFIG_COLDFIRE) /* The coldfire runs this loop at significantly different speeds @@ -48,7 +48,7 @@ extern __inline__ void __delay(unsigned long loops) extern unsigned long loops_per_jiffy; -extern __inline__ void _udelay(unsigned long usecs) +static inline void _udelay(unsigned long usecs) { #if defined(CONFIG_M68328) || defined(CONFIG_M68EZ328) || \ defined(CONFIG_M68VZ328) || defined(CONFIG_M68360) || \ diff --git a/include/asm-m68knommu/ide.h b/include/asm-m68knommu/ide.h deleted file mode 100644 index 836f0721ecf9..000000000000 --- a/include/asm-m68knommu/ide.h +++ /dev/null @@ -1,437 +0,0 @@ -/****************************************************************************/ -/* - * linux/include/asm-m68knommu/ide.h - * - * Copyright (C) 1994-1996 Linus Torvalds & authors - * Copyright (C) 2001 Lineo Inc., davidm@uclinux.org - */ -/****************************************************************************/ -#ifndef _M68KNOMMU_IDE_H -#define _M68KNOMMU_IDE_H - -#ifdef __KERNEL__ -/****************************************************************************/ - -#include <linux/config.h> -#include <linux/interrupt.h> - -#include <asm/setup.h> -#include <asm/io.h> -#include <asm/irq.h> - -/****************************************************************************/ -/* - * some coldfire specifics - */ - -#ifdef CONFIG_COLDFIRE -#include <asm/coldfire.h> -#include <asm/mcfsim.h> - -/* - * Save some space, only have 1 interface - */ -#define MAX_HWIFS 1 /* we only have one interface for now */ - -#ifdef CONFIG_SECUREEDGEMP3 -#define MCFSIM_LOCALCS MCFSIM_CSCR4 -#else -#define MCFSIM_LOCALCS MCFSIM_CSCR6 -#endif - -#endif /* CONFIG_COLDFIRE */ - -/****************************************************************************/ -/* - * Fix up things that may not have been provided - */ - -#ifndef MAX_HWIFS -#define MAX_HWIFS 4 /* same as the other archs */ -#endif - -#undef SUPPORT_SLOW_DATA_PORTS -#define SUPPORT_SLOW_DATA_PORTS 0 - -#undef SUPPORT_VLB_SYNC -#define SUPPORT_VLB_SYNC 0 - -/* this definition is used only on startup .. */ -#undef HD_DATA -#define HD_DATA NULL - -#define DBGIDE(fmt,a...) -// #define DBGIDE(fmt,a...) printk(fmt, ##a) -#define IDE_INLINE __inline__ -// #define IDE_INLINE - -/****************************************************************************/ - -typedef union { - unsigned all : 8; /* all of the bits together */ - struct { - unsigned bit7 : 1; /* always 1 */ - unsigned lba : 1; /* using LBA instead of CHS */ - unsigned bit5 : 1; /* always 1 */ - unsigned unit : 1; /* drive select number, 0 or 1 */ - unsigned head : 4; /* always zeros here */ - } b; -} select_t; - -/* - * our list of ports/irq's for different boards - */ - -static struct m68k_ide_defaults { - ide_ioreg_t base; - int irq; -} m68k_ide_defaults[MAX_HWIFS] = { -#if defined(CONFIG_SECUREEDGEMP3) - { ((ide_ioreg_t)0x30800000), 29 }, -#elif defined(CONFIG_eLIA) - { ((ide_ioreg_t)0x30c00000), 29 }, -#else - { ((ide_ioreg_t)0x0), 0 } -#endif -}; - -/****************************************************************************/ - -static IDE_INLINE int ide_default_irq(ide_ioreg_t base) -{ - int i; - - for (i = 0; i < MAX_HWIFS; i++) - if (m68k_ide_defaults[i].base == base) - return(m68k_ide_defaults[i].irq); - return 0; -} - -static IDE_INLINE ide_ioreg_t ide_default_io_base(int index) -{ - if (index >= 0 && index < MAX_HWIFS) - return(m68k_ide_defaults[index].base); - return 0; -} - - -/* - * Set up a hw structure for a specified data port, control port and IRQ. - * This should follow whatever the default interface uses. - */ -static IDE_INLINE void ide_init_hwif_ports( - hw_regs_t *hw, - ide_ioreg_t data_port, - ide_ioreg_t ctrl_port, - int *irq) -{ - ide_ioreg_t reg = data_port; - int i; - - for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { - hw->io_ports[i] = reg; - reg += 1; - } - if (ctrl_port) { - hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port; - } else { - hw->io_ports[IDE_CONTROL_OFFSET] = data_port + 0xe; - } -} - -#define ide_init_default_irq(base) ide_default_irq(base) - -static IDE_INLINE int -ide_request_irq( - unsigned int irq, - void (*handler)(int, void *, struct pt_regs *), - unsigned long flags, - const char *device, - void *dev_id) -{ -#ifdef CONFIG_COLDFIRE - mcf_autovector(irq); -#endif - return(request_irq(irq, handler, flags, device, dev_id)); -} - - -static IDE_INLINE void -ide_free_irq(unsigned int irq, void *dev_id) -{ - free_irq(irq, dev_id); -} - - -static IDE_INLINE void -ide_request_region(ide_ioreg_t from, unsigned int extent, const char *name) -{ -} - - -static IDE_INLINE void -ide_release_region(ide_ioreg_t from, unsigned int extent) -{ -} - - -static IDE_INLINE void -ide_fix_driveid(struct hd_driveid *id) -{ -#ifdef CONFIG_COLDFIRE - int i, n; - unsigned short *wp = (unsigned short *) id; - int avoid[] = {49, 51, 52, 59, -1 }; /* do not swap these words */ - - /* Need to byte swap shorts, but not char fields */ - for (i = n = 0; i < sizeof(*id) / sizeof(*wp); i++, wp++) { - if (avoid[n] == i) { - n++; - continue; - } - *wp = ((*wp & 0xff) << 8) | ((*wp >> 8) & 0xff); - } - /* have to word swap the one 32 bit field */ - id->lba_capacity = ((id->lba_capacity & 0xffff) << 16) | - ((id->lba_capacity >> 16) & 0xffff); -#endif -} - - -static IDE_INLINE void -ide_release_lock (int *ide_lock) -{ -} - - -static IDE_INLINE void -ide_get_lock( - int *ide_lock, - void (*handler)(int, void *, struct pt_regs *), - void *data) -{ -} - - -#define ide_ack_intr(hwif) \ - ((hwif)->hw.ack_intr ? (hwif)->hw.ack_intr(hwif) : 1) -#define ide__sti() __sti() - -/****************************************************************************/ -/* - * System specific IO requirements - */ - -#ifdef CONFIG_COLDFIRE - -#ifdef CONFIG_SECUREEDGEMP3 - -/* Replace standard IO functions for funky mapping of MP3 board */ -#undef outb -#undef outb_p -#undef inb -#undef inb_p - -#define outb(v, a) ide_outb(v, (unsigned long) (a)) -#define outb_p(v, a) ide_outb(v, (unsigned long) (a)) -#define inb(a) ide_inb((unsigned long) (a)) -#define inb_p(a) ide_inb((unsigned long) (a)) - -#define ADDR8_PTR(addr) (((addr) & 0x1) ? (0x8000 + (addr) - 1) : (addr)) -#define ADDR16_PTR(addr) (addr) -#define ADDR32_PTR(addr) (addr) -#define SWAP8(w) ((((w) & 0xffff) << 8) | (((w) & 0xffff) >> 8)) -#define SWAP16(w) (w) -#define SWAP32(w) (w) - - -static IDE_INLINE void -ide_outb(unsigned int val, unsigned int addr) -{ - volatile unsigned short *rp; - - DBGIDE("%s(val=%x,addr=%x)\n", __FUNCTION__, val, addr); - rp = (volatile unsigned short *) ADDR8_PTR(addr); - *rp = SWAP8(val); -} - - -static IDE_INLINE int -ide_inb(unsigned int addr) -{ - volatile unsigned short *rp, val; - - DBGIDE("%s(addr=%x)\n", __FUNCTION__, addr); - rp = (volatile unsigned short *) ADDR8_PTR(addr); - val = *rp; - return(SWAP8(val)); -} - - -static IDE_INLINE void -ide_outw(unsigned int val, unsigned int addr) -{ - volatile unsigned short *rp; - - DBGIDE("%s(val=%x,addr=%x)\n", __FUNCTION__, val, addr); - rp = (volatile unsigned short *) ADDR16_PTR(addr); - *rp = SWAP16(val); -} - -static IDE_INLINE void -ide_outsw(unsigned int addr, const void *vbuf, unsigned long len) -{ - volatile unsigned short *rp, val; - unsigned short *buf; - - DBGIDE("%s(addr=%x,vbuf=%p,len=%x)\n", __FUNCTION__, addr, vbuf, len); - buf = (unsigned short *) vbuf; - rp = (volatile unsigned short *) ADDR16_PTR(addr); - for (; (len > 0); len--) { - val = *buf++; - *rp = SWAP16(val); - } -} - -static IDE_INLINE int -ide_inw(unsigned int addr) -{ - volatile unsigned short *rp, val; - - DBGIDE("%s(addr=%x)\n", __FUNCTION__, addr); - rp = (volatile unsigned short *) ADDR16_PTR(addr); - val = *rp; - return(SWAP16(val)); -} - -static IDE_INLINE void -ide_insw(unsigned int addr, void *vbuf, unsigned long len) -{ - volatile unsigned short *rp; - unsigned short w, *buf; - - DBGIDE("%s(addr=%x,vbuf=%p,len=%x)\n", __FUNCTION__, addr, vbuf, len); - buf = (unsigned short *) vbuf; - rp = (volatile unsigned short *) ADDR16_PTR(addr); - for (; (len > 0); len--) { - w = *rp; - *buf++ = SWAP16(w); - } -} - -static IDE_INLINE void -ide_insl(unsigned int addr, void *vbuf, unsigned long len) -{ - volatile unsigned long *rp; - unsigned long w, *buf; - - DBGIDE("%s(addr=%x,vbuf=%p,len=%x)\n", __FUNCTION__, addr, vbuf, len); - buf = (unsigned long *) vbuf; - rp = (volatile unsigned long *) ADDR32_PTR(addr); - for (; (len > 0); len--) { - w = *rp; - *buf++ = SWAP32(w); - } -} - -static IDE_INLINE void -ide_outsl(unsigned int addr, const void *vbuf, unsigned long len) -{ - volatile unsigned long *rp, val; - unsigned long *buf; - - DBGIDE("%s(addr=%x,vbuf=%p,len=%x)\n", __FUNCTION__, addr, vbuf, len); - buf = (unsigned long *) vbuf; - rp = (volatile unsigned long *) ADDR32_PTR(addr); - for (; (len > 0); len--) { - val = *buf++; - *rp = SWAP32(val); - } -} - -#elif CONFIG_eLIA - -/* 8/16 bit acesses are controlled by flicking bits in the CS register */ -#define ACCESS_MODE_16BIT() \ - *((volatile unsigned short *) (MCF_MBAR + MCFSIM_LOCALCS)) = 0x0080 -#define ACCESS_MODE_8BIT() \ - *((volatile unsigned short *) (MCF_MBAR + MCFSIM_LOCALCS)) = 0x0040 - - -static IDE_INLINE void -ide_outw(unsigned int val, unsigned int addr) -{ - ACCESS_MODE_16BIT(); - outw(val, addr); - ACCESS_MODE_8BIT(); -} - -static IDE_INLINE void -ide_outsw(unsigned int addr, const void *vbuf, unsigned long len) -{ - ACCESS_MODE_16BIT(); - outsw(addr, vbuf, len); - ACCESS_MODE_8BIT(); -} - -static IDE_INLINE int -ide_inw(unsigned int addr) -{ - int ret; - - ACCESS_MODE_16BIT(); - ret = inw(addr); - ACCESS_MODE_8BIT(); - return(ret); -} - -static IDE_INLINE void -ide_insw(unsigned int addr, void *vbuf, unsigned long len) -{ - ACCESS_MODE_16BIT(); - insw(addr, vbuf, len); - ACCESS_MODE_8BIT(); -} - -static IDE_INLINE void -ide_insl(unsigned int addr, void *vbuf, unsigned long len) -{ - ACCESS_MODE_16BIT(); - insl(addr, vbuf, len); - ACCESS_MODE_8BIT(); -} - -static IDE_INLINE void -ide_outsl(unsigned int addr, const void *vbuf, unsigned long len) -{ - ACCESS_MODE_16BIT(); - outsl(addr, vbuf, len); - ACCESS_MODE_8BIT(); -} - -#endif /* CONFIG_SECUREEDGEMP3 */ - -#undef outw -#undef outw_p -#undef outsw -#undef inw -#undef inw_p -#undef insw -#undef insl -#undef outsl - -#define outw(v, a) ide_outw(v, (unsigned long) (a)) -#define outw_p(v, a) ide_outw(v, (unsigned long) (a)) -#define outsw(a, b, n) ide_outsw((unsigned long) (a), b, n) -#define inw(a) ide_inw((unsigned long) (a)) -#define inw_p(a) ide_inw((unsigned long) (a)) -#define insw(a, b, n) ide_insw((unsigned long) (a), b, n) -#define insl(a, b, n) ide_insl((unsigned long) (a), b, n) -#define outsl(a, b, n) ide_outsl((unsigned long) (a), b, n) - -#endif CONFIG_COLDFIRE - -/****************************************************************************/ -#endif /* __KERNEL__ */ -#endif /* _M68KNOMMU_IDE_H */ -/****************************************************************************/ diff --git a/include/asm-m68knommu/io.h b/include/asm-m68knommu/io.h index 30fade4149b8..e08f2ee4b4a2 100644 --- a/include/asm-m68knommu/io.h +++ b/include/asm-m68knommu/io.h @@ -147,19 +147,19 @@ static inline void io_insl(unsigned int addr, void *buf, int len) extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag); extern void __iounmap(void *addr, unsigned long size); -extern inline void *ioremap(unsigned long physaddr, unsigned long size) +static inline void *ioremap(unsigned long physaddr, unsigned long size) { return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); } -extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size) +static inline void *ioremap_nocache(unsigned long physaddr, unsigned long size) { return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); } -extern inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size) +static inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size) { return __ioremap(physaddr, size, IOMAP_WRITETHROUGH); } -extern inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size) +static inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size) { return __ioremap(physaddr, size, IOMAP_FULL_CACHING); } diff --git a/include/asm-m68knommu/m520xsim.h b/include/asm-m68knommu/m520xsim.h new file mode 100644 index 000000000000..6dc62869e62b --- /dev/null +++ b/include/asm-m68knommu/m520xsim.h @@ -0,0 +1,54 @@ +/****************************************************************************/ + +/* + * m520xsim.h -- ColdFire 5207/5208 System Integration Module support. + * + * (C) Copyright 2005, Intec Automation (mike@steroidmicros.com) + */ + +/****************************************************************************/ +#ifndef m520xsim_h +#define m520xsim_h +/****************************************************************************/ + +#include <linux/config.h> + +/* + * Define the 5282 SIM register set addresses. + */ +#define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */ +#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ +#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ +#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ +#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ +#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ +#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ +#define MCFINTC_ICR0 0x40 /* Base ICR register */ + +#define MCFINT_VECBASE 64 +#define MCFINT_UART0 26 /* Interrupt number for UART0 */ +#define MCFINT_UART1 27 /* Interrupt number for UART1 */ +#define MCFINT_UART2 28 /* Interrupt number for UART2 */ +#define MCFINT_QSPI 31 /* Interrupt number for QSPI */ +#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ + + +#define MCF_GPIO_PAR_UART (0xA4036) +#define MCF_GPIO_PAR_FECI2C (0xA4033) +#define MCF_GPIO_PAR_FEC (0xA4038) + +#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) +#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002) + +#define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040) +#define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080) + +#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) +#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) + +#define ICR_INTRCONF 0x05 +#define MCFPIT_IMR MCFINTC_IMRL +#define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1) + +/****************************************************************************/ +#endif /* m520xsim_h */ diff --git a/include/asm-m68knommu/mcfcache.h b/include/asm-m68knommu/mcfcache.h index b17cd920977f..9cb401421835 100644 --- a/include/asm-m68knommu/mcfcache.h +++ b/include/asm-m68knommu/mcfcache.h @@ -117,6 +117,20 @@ .endm #endif /* CONFIG_M5407 */ +#if defined(CONFIG_M520x) +.macro CACHE_ENABLE + move.l #0x01000000,%d0 /* invalidate whole cache */ + movec %d0,%CACR + nop + move.l #0x0000c000,%d0 /* set SDRAM cached (write-thru) */ + movec %d0,%ACR0 + move.l #0x00000000,%d0 /* no other regions cached */ + movec %d0,%ACR1 + move.l #0x80400000,%d0 /* enable 8K instruction cache */ + movec %d0,%CACR + nop +.endm +#endif /* CONFIG_M520x */ /****************************************************************************/ #endif /* __M68KNOMMU_MCFCACHE_H */ diff --git a/include/asm-m68knommu/mcfne.h b/include/asm-m68knommu/mcfne.h index 045875651e4d..a71b1c8cb4f8 100644 --- a/include/asm-m68knommu/mcfne.h +++ b/include/asm-m68knommu/mcfne.h @@ -35,7 +35,7 @@ * Define the basic hardware resources of NE2000 boards. */ -#if defined(CONFIG_M5206) && defined(CONFIG_ARNEWSH) +#if defined(CONFIG_ARN5206) #define NE2000_ADDR 0x40000300 #define NE2000_ODDOFFSET 0x00010000 #define NE2000_IRQ_VECTOR 0xf0 @@ -44,7 +44,7 @@ #define NE2000_BYTE volatile unsigned short #endif -#if defined(CONFIG_M5206e) && defined(CONFIG_MOTOROLA) +#if defined(CONFIG_M5206eC3) #define NE2000_ADDR 0x40000300 #define NE2000_ODDOFFSET 0x00010000 #define NE2000_IRQ_VECTOR 0x1c @@ -61,7 +61,7 @@ #define NE2000_BYTE volatile unsigned char #endif -#if defined(CONFIG_M5206e) && defined(CONFIG_CFV240) +#if defined(CONFIG_CFV240) #define NE2000_ADDR 0x40010000 #define NE2000_ADDR1 0x40010001 #define NE2000_ODDOFFSET 0x00000000 @@ -72,7 +72,7 @@ #define NE2000_BYTE volatile unsigned char #endif -#if defined(CONFIG_M5307) && defined(CONFIG_MOTOROLA) +#if defined(CONFIG_M5307C3) #define NE2000_ADDR 0x40000300 #define NE2000_ODDOFFSET 0x00010000 #define NE2000_IRQ_VECTOR 0x1b @@ -114,7 +114,7 @@ #define RSWAP(w) (((w) << 8) | ((w) >> 8)) #endif -#if defined(CONFIG_M5307) && defined(CONFIG_ARNEWSH) +#if defined(CONFIG_ARN5307) #define NE2000_ADDR 0xfe600300 #define NE2000_ODDOFFSET 0x00010000 #define NE2000_IRQ_VECTOR 0x1b @@ -123,7 +123,7 @@ #define NE2000_BYTE volatile unsigned short #endif -#if defined(CONFIG_M5407) +#if defined(CONFIG_M5407C3) #define NE2000_ADDR 0x40000300 #define NE2000_ODDOFFSET 0x00010000 #define NE2000_IRQ_VECTOR 0x1b @@ -264,7 +264,7 @@ void ne2000_outsw(unsigned int addr, const void *vbuf, unsigned long len) * Minor differences between the different board types. */ -#if defined(CONFIG_M5206) && defined(CONFIG_ARNEWSH) +#if defined(CONFIG_ARN5206) void ne2000_irqsetup(int irq) { volatile unsigned char *icrp; @@ -275,7 +275,7 @@ void ne2000_irqsetup(int irq) } #endif -#if defined(CONFIG_M5206e) && defined(CONFIG_MOTOROLA) +#if defined(CONFIG_M5206eC3) void ne2000_irqsetup(int irq) { volatile unsigned char *icrp; @@ -286,7 +286,7 @@ void ne2000_irqsetup(int irq) } #endif -#if defined(CONFIG_M5206e) && defined(CONFIG_CFV240) +#if defined(CONFIG_CFV240) void ne2000_irqsetup(int irq) { volatile unsigned char *icrp; diff --git a/include/asm-m68knommu/mcfpit.h b/include/asm-m68knommu/mcfpit.h index 4cc2e9fd6ad0..a685f1b45401 100644 --- a/include/asm-m68knommu/mcfpit.h +++ b/include/asm-m68knommu/mcfpit.h @@ -14,13 +14,17 @@ #include <linux/config.h> /* - * Get address specific defines for the 5270/5271 and 5280/5282. + * Get address specific defines for the 5270/5271, 5280/5282, and 5208. */ +#if defined(CONFIG_M520x) +#define MCFPIT_BASE1 0x00080000 /* Base address of TIMER1 */ +#define MCFPIT_BASE2 0x00084000 /* Base address of TIMER2 */ +#else #define MCFPIT_BASE1 0x00150000 /* Base address of TIMER1 */ #define MCFPIT_BASE2 0x00160000 /* Base address of TIMER2 */ #define MCFPIT_BASE3 0x00170000 /* Base address of TIMER3 */ #define MCFPIT_BASE4 0x00180000 /* Base address of TIMER4 */ - +#endif /* * Define the PIT timer register set addresses. diff --git a/include/asm-m68knommu/mcfsim.h b/include/asm-m68knommu/mcfsim.h index b0c7736f7a99..81d74a31dc43 100644 --- a/include/asm-m68knommu/mcfsim.h +++ b/include/asm-m68knommu/mcfsim.h @@ -22,6 +22,8 @@ #include <asm/m5204sim.h> #elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) #include <asm/m5206sim.h> +#elif defined(CONFIG_M520x) +#include <asm/m520xsim.h> #elif defined(CONFIG_M523x) #include <asm/m523xsim.h> #elif defined(CONFIG_M5249) @@ -99,6 +101,19 @@ #define MCFSIM_IMR_MASKALL 0x3ffe /* All intr sources */ #endif +/* + * PIT interrupt settings, if not found in mXXXXsim.h file. + */ +#ifndef ICR_INTRCONF +#define ICR_INTRCONF 0x2b /* PIT1 level 5, priority 3 */ +#endif +#ifndef MCFPIT_IMR +#define MCFPIT_IMR MCFINTC_IMRH +#endif +#ifndef MCFPIT_IMR_IBIT +#define MCFPIT_IMR_IBIT (1 << (MCFINT_PIT1 - 32)) +#endif + #ifndef __ASSEMBLY__ /* diff --git a/include/asm-m68knommu/mcfuart.h b/include/asm-m68knommu/mcfuart.h index 9c1210613bc7..b016fad83119 100644 --- a/include/asm-m68knommu/mcfuart.h +++ b/include/asm-m68knommu/mcfuart.h @@ -41,6 +41,10 @@ #define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ #define MCFUART_BASE2 0x200 /* Base address of UART2 */ #endif +#elif defined(CONFIG_M520x) +#define MCFUART_BASE1 0x60000 /* Base address of UART1 */ +#define MCFUART_BASE2 0x64000 /* Base address of UART2 */ +#define MCFUART_BASE3 0x68000 /* Base address of UART2 */ #endif diff --git a/include/asm-m68knommu/mcfwdebug.h b/include/asm-m68knommu/mcfwdebug.h index c425dd568155..6ceae103596b 100644 --- a/include/asm-m68knommu/mcfwdebug.h +++ b/include/asm-m68knommu/mcfwdebug.h @@ -90,7 +90,7 @@ * that the debug module instructions (2 longs) must be long word aligned and * some pointer fiddling is performed to ensure this. */ -extern inline void wdebug(int reg, unsigned long data) { +static inline void wdebug(int reg, unsigned long data) { unsigned short dbg_spc[6]; unsigned short *dbg; diff --git a/include/asm-m68knommu/mmu_context.h b/include/asm-m68knommu/mmu_context.h index 9bc0fd49b8aa..1e080eca9ca8 100644 --- a/include/asm-m68knommu/mmu_context.h +++ b/include/asm-m68knommu/mmu_context.h @@ -10,7 +10,7 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) { } -extern inline int +static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm) { // mm->context = virt_to_phys(mm->pgd); @@ -25,7 +25,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, str #define deactivate_mm(tsk,mm) do { } while (0) -extern inline void activate_mm(struct mm_struct *prev_mm, +static inline void activate_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm) { } diff --git a/include/asm-m68knommu/processor.h b/include/asm-m68knommu/processor.h index 85a054e758b1..ba393b1a023b 100644 --- a/include/asm-m68knommu/processor.h +++ b/include/asm-m68knommu/processor.h @@ -21,7 +21,7 @@ #include <asm/ptrace.h> #include <asm/current.h> -extern inline unsigned long rdusp(void) +static inline unsigned long rdusp(void) { #ifdef CONFIG_COLDFIRE extern unsigned int sw_usp; @@ -33,7 +33,7 @@ extern inline unsigned long rdusp(void) #endif } -extern inline void wrusp(unsigned long usp) +static inline void wrusp(unsigned long usp) { #ifdef CONFIG_COLDFIRE extern unsigned int sw_usp; diff --git a/include/asm-m68knommu/semaphore.h b/include/asm-m68knommu/semaphore.h index 17aee15906a6..5cc1fdd86f50 100644 --- a/include/asm-m68knommu/semaphore.h +++ b/include/asm-m68knommu/semaphore.h @@ -41,7 +41,7 @@ struct semaphore { #define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name,1) #define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name,0) -extern inline void sema_init (struct semaphore *sem, int val) +static inline void sema_init (struct semaphore *sem, int val) { *sem = (struct semaphore)__SEMAPHORE_INITIALIZER(*sem, val); } @@ -73,7 +73,7 @@ extern spinlock_t semaphore_wake_lock; * "down_failed" is a special asm handler that calls the C * routine that actually waits. See arch/m68k/lib/semaphore.S */ -extern inline void down(struct semaphore * sem) +static inline void down(struct semaphore * sem) { might_sleep(); __asm__ __volatile__( @@ -88,7 +88,7 @@ extern inline void down(struct semaphore * sem) : "cc", "%a0", "%a1", "memory"); } -extern inline int down_interruptible(struct semaphore * sem) +static inline int down_interruptible(struct semaphore * sem) { int ret; @@ -107,7 +107,7 @@ extern inline int down_interruptible(struct semaphore * sem) return(ret); } -extern inline int down_trylock(struct semaphore * sem) +static inline int down_trylock(struct semaphore * sem) { register struct semaphore *sem1 __asm__ ("%a1") = sem; register int result __asm__ ("%d0"); @@ -135,7 +135,7 @@ extern inline int down_trylock(struct semaphore * sem) * The default case (no contention) will result in NO * jumps for both down() and up(). */ -extern inline void up(struct semaphore * sem) +static inline void up(struct semaphore * sem) { __asm__ __volatile__( "| atomic up operation\n\t" diff --git a/include/asm-m68knommu/system.h b/include/asm-m68knommu/system.h index 53cbbad0f130..6338afc850ba 100644 --- a/include/asm-m68knommu/system.h +++ b/include/asm-m68knommu/system.h @@ -312,6 +312,19 @@ cmpxchg(volatile int *p, int old, int new) moveb #0x80, (%a0); \ "); \ }) +#elif defined(CONFIG_M520x) + /* + * The MCF5208 has a bit (SOFTRST) in memory (Reset Control Register + * RCR), that when set, resets the MCF5208. + */ +#define HARD_RESET_NOW() \ +({ \ + unsigned char volatile *reset; \ + asm("move.w #0x2700, %sr"); \ + reset = ((volatile unsigned short *)(MCF_IPSBAR + 0xA0000)); \ + while(1) \ + *reset |= 0x80; \ +}) #else #define HARD_RESET_NOW() ({ \ asm(" \ diff --git a/include/asm-m68knommu/tlbflush.h b/include/asm-m68knommu/tlbflush.h index bf7004e1afe0..de858db28b00 100644 --- a/include/asm-m68knommu/tlbflush.h +++ b/include/asm-m68knommu/tlbflush.h @@ -47,12 +47,12 @@ static inline void flush_tlb_range(struct mm_struct *mm, BUG(); } -extern inline void flush_tlb_kernel_page(unsigned long addr) +static inline void flush_tlb_kernel_page(unsigned long addr) { BUG(); } -extern inline void flush_tlb_pgtables(struct mm_struct *mm, +static inline void flush_tlb_pgtables(struct mm_struct *mm, unsigned long start, unsigned long end) { BUG(); diff --git a/include/asm-ppc/mv64x60.h b/include/asm-ppc/mv64x60.h index ee2f9188cc64..4f2405b83612 100644 --- a/include/asm-ppc/mv64x60.h +++ b/include/asm-ppc/mv64x60.h @@ -27,6 +27,8 @@ #include <asm/pci-bridge.h> #include <asm/mv64x60_defs.h> +struct platform_device; + extern u8 mv64x60_pci_exclude_bridge; extern spinlock_t mv64x60_lock; diff --git a/include/asm-x86_64/dma-mapping.h b/include/asm-x86_64/dma-mapping.h index 54a380efed41..36d16dfbac88 100644 --- a/include/asm-x86_64/dma-mapping.h +++ b/include/asm-x86_64/dma-mapping.h @@ -85,10 +85,33 @@ static inline void dma_sync_single_for_device(struct device *hwdev, flush_write_buffers(); } -#define dma_sync_single_range_for_cpu(dev, dma_handle, offset, size, dir) \ - dma_sync_single_for_cpu(dev, dma_handle, size, dir) -#define dma_sync_single_range_for_device(dev, dma_handle, offset, size, dir) \ - dma_sync_single_for_device(dev, dma_handle, size, dir) +static inline void dma_sync_single_range_for_cpu(struct device *hwdev, + dma_addr_t dma_handle, + unsigned long offset, + size_t size, int direction) +{ + if (direction == DMA_NONE) + out_of_line_bug(); + + if (swiotlb) + return swiotlb_sync_single_range_for_cpu(hwdev,dma_handle,offset,size,direction); + + flush_write_buffers(); +} + +static inline void dma_sync_single_range_for_device(struct device *hwdev, + dma_addr_t dma_handle, + unsigned long offset, + size_t size, int direction) +{ + if (direction == DMA_NONE) + out_of_line_bug(); + + if (swiotlb) + return swiotlb_sync_single_range_for_device(hwdev,dma_handle,offset,size,direction); + + flush_write_buffers(); +} static inline void dma_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg, diff --git a/include/asm-x86_64/swiotlb.h b/include/asm-x86_64/swiotlb.h index 7cbfd10ecc3c..dddf1b218681 100644 --- a/include/asm-x86_64/swiotlb.h +++ b/include/asm-x86_64/swiotlb.h @@ -15,6 +15,14 @@ extern void swiotlb_sync_single_for_cpu(struct device *hwdev, extern void swiotlb_sync_single_for_device(struct device *hwdev, dma_addr_t dev_addr, size_t size, int dir); +extern void swiotlb_sync_single_range_for_cpu(struct device *hwdev, + dma_addr_t dev_addr, + unsigned long offset, + size_t size, int dir); +extern void swiotlb_sync_single_range_for_device(struct device *hwdev, + dma_addr_t dev_addr, + unsigned long offset, + size_t size, int dir); extern void swiotlb_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg, int nelems, int dir); diff --git a/include/linux/genhd.h b/include/linux/genhd.h index eabdb5cce357..8eeaa53a68c9 100644 --- a/include/linux/genhd.h +++ b/include/linux/genhd.h @@ -78,7 +78,7 @@ struct hd_struct { sector_t start_sect; sector_t nr_sects; struct kobject kobj; - unsigned reads, read_sectors, writes, write_sectors; + unsigned ios[2], sectors[2]; int policy, partno; }; @@ -89,10 +89,10 @@ struct hd_struct { #define GENHD_FL_SUPPRESS_PARTITION_INFO 32 struct disk_stats { - unsigned read_sectors, write_sectors; - unsigned reads, writes; - unsigned read_merges, write_merges; - unsigned read_ticks, write_ticks; + unsigned sectors[2]; + unsigned ios[2]; + unsigned merges[2]; + unsigned ticks[2]; unsigned io_ticks; unsigned time_in_queue; }; diff --git a/include/linux/netfilter_arp/arp_tables.h b/include/linux/netfilter_arp/arp_tables.h index d759a637bded..e98a870a20be 100644 --- a/include/linux/netfilter_arp/arp_tables.h +++ b/include/linux/netfilter_arp/arp_tables.h @@ -68,7 +68,8 @@ struct arpt_entry_target u_int16_t target_size; /* Used by userspace */ - char name[ARPT_FUNCTION_MAXNAMELEN]; + char name[ARPT_FUNCTION_MAXNAMELEN-1]; + u_int8_t revision; } user; struct { u_int16_t target_size; @@ -148,7 +149,9 @@ struct arpt_entry #define ARPT_SO_GET_INFO (ARPT_BASE_CTL) #define ARPT_SO_GET_ENTRIES (ARPT_BASE_CTL + 1) -#define ARPT_SO_GET_MAX ARPT_SO_GET_ENTRIES +/* #define ARPT_SO_GET_REVISION_MATCH (ARPT_BASE_CTL + 2)*/ +#define ARPT_SO_GET_REVISION_TARGET (ARPT_BASE_CTL + 3) +#define ARPT_SO_GET_MAX ARPT_SO_GET_REVISION_TARGET /* CONTINUE verdict for targets */ #define ARPT_CONTINUE 0xFFFFFFFF @@ -236,6 +239,15 @@ struct arpt_get_entries struct arpt_entry entrytable[0]; }; +/* The argument to ARPT_SO_GET_REVISION_*. Returns highest revision + * kernel supports, if >= revision. */ +struct arpt_get_revision +{ + char name[ARPT_FUNCTION_MAXNAMELEN-1]; + + u_int8_t revision; +}; + /* Standard return verdict, or do jump. */ #define ARPT_STANDARD_TARGET "" /* Error verdict. */ @@ -274,7 +286,9 @@ struct arpt_target { struct list_head list; - const char name[ARPT_FUNCTION_MAXNAMELEN]; + const char name[ARPT_FUNCTION_MAXNAMELEN-1]; + + u_int8_t revision; /* Returns verdict. */ unsigned int (*target)(struct sk_buff **pskb, diff --git a/include/linux/netfilter_ipv6/ip6_tables.h b/include/linux/netfilter_ipv6/ip6_tables.h index 59f70b34e029..2efc046d9e94 100644 --- a/include/linux/netfilter_ipv6/ip6_tables.h +++ b/include/linux/netfilter_ipv6/ip6_tables.h @@ -57,7 +57,8 @@ struct ip6t_entry_match u_int16_t match_size; /* Used by userspace */ - char name[IP6T_FUNCTION_MAXNAMELEN]; + char name[IP6T_FUNCTION_MAXNAMELEN-1]; + u_int8_t revision; } user; struct { u_int16_t match_size; @@ -80,7 +81,8 @@ struct ip6t_entry_target u_int16_t target_size; /* Used by userspace */ - char name[IP6T_FUNCTION_MAXNAMELEN]; + char name[IP6T_FUNCTION_MAXNAMELEN-1]; + u_int8_t revision; } user; struct { u_int16_t target_size; @@ -161,7 +163,9 @@ struct ip6t_entry #define IP6T_SO_GET_INFO (IP6T_BASE_CTL) #define IP6T_SO_GET_ENTRIES (IP6T_BASE_CTL + 1) -#define IP6T_SO_GET_MAX IP6T_SO_GET_ENTRIES +#define IP6T_SO_GET_REVISION_MATCH (IP6T_BASE_CTL + 2) +#define IP6T_SO_GET_REVISION_TARGET (IP6T_BASE_CTL + 3) +#define IP6T_SO_GET_MAX IP6T_SO_GET_REVISION_TARGET /* CONTINUE verdict for targets */ #define IP6T_CONTINUE 0xFFFFFFFF @@ -291,6 +295,15 @@ struct ip6t_get_entries struct ip6t_entry entrytable[0]; }; +/* The argument to IP6T_SO_GET_REVISION_*. Returns highest revision + * kernel supports, if >= revision. */ +struct ip6t_get_revision +{ + char name[IP6T_FUNCTION_MAXNAMELEN-1]; + + u_int8_t revision; +}; + /* Standard return verdict, or do jump. */ #define IP6T_STANDARD_TARGET "" /* Error verdict. */ @@ -352,7 +365,9 @@ struct ip6t_match { struct list_head list; - const char name[IP6T_FUNCTION_MAXNAMELEN]; + const char name[IP6T_FUNCTION_MAXNAMELEN-1]; + + u_int8_t revision; /* Return true or false: return FALSE and set *hotdrop = 1 to force immediate packet drop. */ @@ -387,7 +402,9 @@ struct ip6t_target { struct list_head list; - const char name[IP6T_FUNCTION_MAXNAMELEN]; + const char name[IP6T_FUNCTION_MAXNAMELEN-1]; + + u_int8_t revision; /* Returns verdict. Argument order changed since 2.6.9, as this must now handle non-linear skbs, using skb_copy_bits and diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index 2b0401b93f2b..9d2579230689 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h @@ -39,8 +39,7 @@ #define PORT_RSA 13 #define PORT_NS16550A 14 #define PORT_XSCALE 15 -#define PORT_IP3106 16 -#define PORT_MAX_8250 16 /* max port ID */ +#define PORT_MAX_8250 15 /* max port ID */ /* * ARM specific type numbers. These are not currently guaranteed @@ -118,7 +117,9 @@ #define PORT_M32R_SIO 68 /*Digi jsm */ -#define PORT_JSM 65 +#define PORT_JSM 69 + +#define PORT_IP3106 70 #ifdef __KERNEL__ |