diff options
Diffstat (limited to 'include')
431 files changed, 11567 insertions, 5812 deletions
diff --git a/include/asm-alpha/io.h b/include/asm-alpha/io.h index 21a86f1a05b3..ab5b60dcef19 100644 --- a/include/asm-alpha/io.h +++ b/include/asm-alpha/io.h @@ -4,6 +4,7 @@ #ifdef __KERNEL__ #include <linux/kernel.h> +#include <linux/mm.h> #include <asm/compiler.h> #include <asm/system.h> #include <asm/pgtable.h> @@ -90,6 +91,11 @@ static inline void * phys_to_virt(unsigned long address) #define page_to_phys(page) page_to_pa(page) +static inline dma_addr_t __deprecated isa_page_to_bus(struct page *page) +{ + return page_to_phys(page); +} + /* This depends on working iommu. */ #define BIO_VMERGE_BOUNDARY (alpha_mv.mv_pci_tbi ? PAGE_SIZE : 0) @@ -102,12 +108,12 @@ static inline void * phys_to_virt(unsigned long address) * * Note that this only works for a limited range of kernel addresses, * and very well may not span all memory. Consider this interface - * deprecated in favour of the mapping functions in <asm/pci.h>. + * deprecated in favour of the DMA-mapping API. */ extern unsigned long __direct_map_base; extern unsigned long __direct_map_size; -static inline unsigned long virt_to_bus(void *address) +static inline unsigned long __deprecated virt_to_bus(void *address) { unsigned long phys = virt_to_phys(address); unsigned long bus = phys + __direct_map_base; @@ -115,7 +121,7 @@ static inline unsigned long virt_to_bus(void *address) } #define isa_virt_to_bus virt_to_bus -static inline void *bus_to_virt(unsigned long address) +static inline void * __deprecated bus_to_virt(unsigned long address) { void *virt; @@ -126,6 +132,7 @@ static inline void *bus_to_virt(unsigned long address) virt = phys_to_virt(address); return (long)address <= 0 ? NULL : virt; } +#define isa_bus_to_virt bus_to_virt /* * There are different chipsets to interface the Alpha CPUs to the world. diff --git a/include/asm-alpha/pci.h b/include/asm-alpha/pci.h index 85aa1127c903..30ee7669b19f 100644 --- a/include/asm-alpha/pci.h +++ b/include/asm-alpha/pci.h @@ -199,30 +199,6 @@ pci_dma_sync_sg_for_device(struct pci_dev *dev, struct scatterlist *sg, extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask); -/* True if the machine supports DAC addressing, and DEV can - make use of it given MASK. */ -extern int pci_dac_dma_supported(struct pci_dev *hwdev, u64 mask); - -/* Convert to/from DAC dma address and struct page. */ -extern dma64_addr_t pci_dac_page_to_dma(struct pci_dev *, struct page *, - unsigned long, int); -extern struct page *pci_dac_dma_to_page(struct pci_dev *, dma64_addr_t); -extern unsigned long pci_dac_dma_to_offset(struct pci_dev *, dma64_addr_t); - -static inline void -pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, dma64_addr_t dma_addr, - size_t len, int direction) -{ - /* Nothing to do. */ -} - -static inline void -pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr, - size_t len, int direction) -{ - /* Nothing to do. */ -} - #ifdef CONFIG_PCI static inline void pci_dma_burst_advice(struct pci_dev *pdev, enum pci_dma_burst_strategy *strat, @@ -275,11 +251,6 @@ static inline int pci_proc_domain(struct pci_bus *bus) return hose->need_domain_info; } -static inline void -pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - struct pci_dev *alpha_gendev_to_pci(struct device *dev); #endif /* __KERNEL__ */ diff --git a/include/asm-alpha/pgtable.h b/include/asm-alpha/pgtable.h index 616d20662ff3..99037b032357 100644 --- a/include/asm-alpha/pgtable.h +++ b/include/asm-alpha/pgtable.h @@ -264,21 +264,15 @@ extern inline void pgd_clear(pgd_t * pgdp) { pgd_val(*pgdp) = 0; } * The following only work if pte_present() is true. * Undefined behaviour if not.. */ -extern inline int pte_read(pte_t pte) { return !(pte_val(pte) & _PAGE_FOR); } extern inline int pte_write(pte_t pte) { return !(pte_val(pte) & _PAGE_FOW); } -extern inline int pte_exec(pte_t pte) { return !(pte_val(pte) & _PAGE_FOE); } extern inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } extern inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } extern inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } extern inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) |= _PAGE_FOW; return pte; } -extern inline pte_t pte_rdprotect(pte_t pte) { pte_val(pte) |= _PAGE_FOR; return pte; } -extern inline pte_t pte_exprotect(pte_t pte) { pte_val(pte) |= _PAGE_FOE; return pte; } extern inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~(__DIRTY_BITS); return pte; } extern inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~(__ACCESS_BITS); return pte; } extern inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) &= ~_PAGE_FOW; return pte; } -extern inline pte_t pte_mkread(pte_t pte) { pte_val(pte) &= ~_PAGE_FOR; return pte; } -extern inline pte_t pte_mkexec(pte_t pte) { pte_val(pte) &= ~_PAGE_FOE; return pte; } extern inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= __DIRTY_BITS; return pte; } extern inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= __ACCESS_BITS; return pte; } diff --git a/include/asm-arm/Kbuild b/include/asm-arm/Kbuild index c68e1680da01..73237bd130a2 100644 --- a/include/asm-arm/Kbuild +++ b/include/asm-arm/Kbuild @@ -1 +1,3 @@ include include/asm-generic/Kbuild.asm + +unifdef-y += hwcap.h diff --git a/include/asm-arm/arch-at91/at91_dbgu.h b/include/asm-arm/arch-at91/at91_dbgu.h index b0369e176f7b..8019ffd0ad3b 100644 --- a/include/asm-arm/arch-at91/at91_dbgu.h +++ b/include/asm-arm/arch-at91/at91_dbgu.h @@ -16,6 +16,7 @@ #ifndef AT91_DBGU_H #define AT91_DBGU_H +#ifdef AT91_DBGU #define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ #define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ #define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */ @@ -30,6 +31,15 @@ #define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ #define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */ +#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */ +#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ + +#endif /* AT91_DBGU */ + +/* + * Some AT91 parts that don't have full DEBUG units still support the ID + * and extensions register. + */ #define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ #define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ #define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */ @@ -53,7 +63,4 @@ #define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ #define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ -#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */ -#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ - #endif diff --git a/include/asm-arm/arch-at91/at91x40.h b/include/asm-arm/arch-at91/at91x40.h new file mode 100644 index 000000000000..612203e0177f --- /dev/null +++ b/include/asm-arm/arch-at91/at91x40.h @@ -0,0 +1,55 @@ +/* + * include/asm-arm/arch-at91/at91x40.h + * + * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91X40_H +#define AT91X40_H + +/* + * IRQ list. + */ +#define AT91_ID_FIQ 0 /* FIQ */ +#define AT91_ID_SYS 1 /* System Peripheral */ +#define AT91X40_ID_USART0 2 /* USART port 0 */ +#define AT91X40_ID_USART1 3 /* USART port 1 */ +#define AT91X40_ID_TC0 4 /* Timer/Counter 0 */ +#define AT91X40_ID_TC1 5 /* Timer/Counter 1*/ +#define AT91X40_ID_TC2 6 /* Timer/Counter 2*/ +#define AT91X40_ID_WD 7 /* Watchdog? */ +#define AT91X40_ID_PIOA 8 /* Parallel IO Controller A */ + +#define AT91X40_ID_IRQ0 16 /* External IRQ 0 */ +#define AT91X40_ID_IRQ1 17 /* External IRQ 1 */ +#define AT91X40_ID_IRQ2 18 /* External IRQ 2 */ + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_BASE_SYS 0xffc00000 + +#define AT91_EBI (0xffe00000 - AT91_BASE_SYS) /* External Bus Interface */ +#define AT91_SF (0xfff00000 - AT91_BASE_SYS) /* Special Function */ +#define AT91_USART1 (0xfffcc000 - AT91_BASE_SYS) /* USART 1 */ +#define AT91_USART0 (0xfffd0000 - AT91_BASE_SYS) /* USART 0 */ +#define AT91_TC (0xfffe0000 - AT91_BASE_SYS) /* Timer Counter */ +#define AT91_PIOA (0xffff0000 - AT91_BASE_SYS) /* PIO Controller A */ +#define AT91_PS (0xffff4000 - AT91_BASE_SYS) /* Power Save */ +#define AT91_WD (0xffff8000 - AT91_BASE_SYS) /* Watchdog Timer */ +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */ + +/* + * The AT91x40 series doesn't have a debug unit like the other AT91 parts. + * But it does have a chip identify register and extension ID, so define at + * least these here. + */ +#define AT91_DBGU_CIDR (AT91_SF + 0) /* CIDR in PS segment */ +#define AT91_DBGU_EXID (AT91_SF + 4) /* EXID in PS segment */ + +#endif /* AT91X40_H */ diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h index ef93c30a9c5f..080cbb401a87 100644 --- a/include/asm-arm/arch-at91/cpu.h +++ b/include/asm-arm/arch-at91/cpu.h @@ -28,6 +28,11 @@ #define ARCH_ID_AT91SAM9RL64 0x019b03a0 +#define ARCH_ID_AT91M40800 0x14080044 +#define ARCH_ID_AT91R40807 0x44080746 +#define ARCH_ID_AT91M40807 0x14080745 +#define ARCH_ID_AT91R40008 0x44000840 + static inline unsigned long at91_cpu_identify(void) { return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h index 46835e945aea..8f1cdd38a969 100644 --- a/include/asm-arm/arch-at91/hardware.h +++ b/include/asm-arm/arch-at91/hardware.h @@ -26,18 +26,29 @@ #include <asm/arch/at91sam9263.h> #elif defined(CONFIG_ARCH_AT91SAM9RL) #include <asm/arch/at91sam9rl.h> +#elif defined(CONFIG_ARCH_AT91X40) +#include <asm/arch/at91x40.h> #else #error "Unsupported AT91 processor" #endif +#ifdef CONFIG_MMU /* * Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF * to 0xFEF78000 .. 0xFF000000. (544Kb) */ #define AT91_IO_PHYS_BASE 0xFFF78000 -#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1) #define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE) +#else +/* + * Identity mapping for the non MMU case. + */ +#define AT91_IO_PHYS_BASE AT91_BASE_SYS +#define AT91_IO_VIRT_BASE AT91_IO_PHYS_BASE +#endif + +#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1) /* Convert a physical IO address to virtual IO address */ #define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE) @@ -66,7 +77,11 @@ #define AT91_CHIPSELECT_7 0x80000000 /* SDRAM */ +#ifdef CONFIG_DRAM_BASE +#define AT91_SDRAM_BASE CONFIG_DRAM_BASE +#else #define AT91_SDRAM_BASE AT91_CHIPSELECT_1 +#endif /* Clocks */ #define AT91_SLOW_CLOCK 32768 /* slow clock */ diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h index 2df1ee12dfb7..a310698fb4da 100644 --- a/include/asm-arm/arch-at91/timex.h +++ b/include/asm-arm/arch-at91/timex.h @@ -42,6 +42,11 @@ #define AT91SAM9_MASTER_CLOCK 100000000 #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) +#elif defined(CONFIG_ARCH_AT91X40) + +#define AT91X40_MASTER_CLOCK 40000000 +#define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK) + #endif #endif diff --git a/include/asm-arm/arch-at91/uncompress.h b/include/asm-arm/arch-at91/uncompress.h index 30ac587b3b41..272a7e0dc6cf 100644 --- a/include/asm-arm/arch-at91/uncompress.h +++ b/include/asm-arm/arch-at91/uncompress.h @@ -33,20 +33,24 @@ */ static void putc(int c) { +#ifdef AT91_DBGU void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) barrier(); __raw_writel(c, sys + AT91_DBGU_THR); +#endif } static inline void flush(void) { +#ifdef AT91_DBGU void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ /* wait for transmission to complete */ while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) barrier(); +#endif } #define arch_decomp_setup() diff --git a/include/asm-arm/arch-davinci/clock.h b/include/asm-arm/arch-davinci/clock.h new file mode 100644 index 000000000000..cc168b7a14f2 --- /dev/null +++ b/include/asm-arm/arch-davinci/clock.h @@ -0,0 +1,22 @@ +/* + * include/asm-arm/arch-davinci/clock.h + * + * Clock control driver for DaVinci - header file + * + * Authors: Vladimir Barinov <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_DAVINCI_CLOCK_H +#define __ASM_ARCH_DAVINCI_CLOCK_H + +struct clk; + +extern int clk_register(struct clk *clk); +extern void clk_unregister(struct clk *clk); +extern int davinci_clk_init(void); + +#endif diff --git a/include/asm-arm/arch-davinci/gpio.h b/include/asm-arm/arch-davinci/gpio.h new file mode 100644 index 000000000000..ea24a0e0bfd6 --- /dev/null +++ b/include/asm-arm/arch-davinci/gpio.h @@ -0,0 +1,156 @@ +/* + * TI DaVinci GPIO Support + * + * Copyright (c) 2006 David Brownell + * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DAVINCI_GPIO_H +#define __DAVINCI_GPIO_H + +/* + * basic gpio routines + * + * board-specific init should be done by arch/.../.../board-XXX.c (maybe + * initializing banks together) rather than boot loaders; kexec() won't + * go through boot loaders. + * + * the gpio clock will be turned on when gpios are used, and you may also + * need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are + * used as gpios, not with other peripherals. + * + * GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation, and maybe + * for later updates, code should write GPIO(N) or: + * - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53) + * - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70) + * + * For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc + * for now, that's != GPIO(N) + */ +#define GPIO(X) (X) /* 0 <= X <= 70 */ +#define GPIOV18(X) (X) /* 1.8V i/o; 0 <= X <= 53 */ +#define GPIOV33(X) ((X)+54) /* 3.3V i/o; 0 <= X <= 17 */ + +struct gpio_controller { + u32 dir; + u32 out_data; + u32 set_data; + u32 clr_data; + u32 in_data; + u32 set_rising; + u32 clr_rising; + u32 set_falling; + u32 clr_falling; + u32 intstat; +}; + +/* The __gpio_to_controller() and __gpio_mask() functions inline to constants + * with constant parameters; or in outlined code they execute at runtime. + * + * You'd access the controller directly when reading or writing more than + * one gpio value at a time, and to support wired logic where the value + * being driven by the cpu need not match the value read back. + * + * These are NOT part of the cross-platform GPIO interface + */ +static inline struct gpio_controller *__iomem +__gpio_to_controller(unsigned gpio) +{ + void *__iomem ptr; + + if (gpio < 32) + ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10); + else if (gpio < 64) + ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38); + else if (gpio < DAVINCI_N_GPIO) + ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60); + else + ptr = NULL; + return ptr; +} + +static inline u32 __gpio_mask(unsigned gpio) +{ + return 1 << (gpio % 32); +} + +/* The get/set/clear functions will inline when called with constant + * parameters, for low-overhead bitbanging. Illegal constant parameters + * cause link-time errors. + * + * Otherwise, calls with variable parameters use outlined functions. + */ +extern int __error_inval_gpio(void); + +extern void __gpio_set(unsigned gpio, int value); +extern int __gpio_get(unsigned gpio); + +static inline void gpio_set_value(unsigned gpio, int value) +{ + if (__builtin_constant_p(value)) { + struct gpio_controller *__iomem g; + u32 mask; + + if (gpio >= DAVINCI_N_GPIO) + __error_inval_gpio(); + + g = __gpio_to_controller(gpio); + mask = __gpio_mask(gpio); + if (value) + __raw_writel(mask, &g->set_data); + else + __raw_writel(mask, &g->clr_data); + return; + } + + __gpio_set(gpio, value); +} + +/* Returns zero or nonzero; works for gpios configured as inputs OR + * as outputs. + * + * NOTE: changes in reported values are synchronized to the GPIO clock. + * This is most easily seen after calling gpio_set_value() and then immediatly + * gpio_get_value(), where the gpio_get_value() would return the old value + * until the GPIO clock ticks and the new value gets latched. + */ + +static inline int gpio_get_value(unsigned gpio) +{ + struct gpio_controller *__iomem g; + + if (!__builtin_constant_p(gpio)) + return __gpio_get(gpio); + + if (gpio >= DAVINCI_N_GPIO) + return __error_inval_gpio(); + + g = __gpio_to_controller(gpio); + return !!(__gpio_mask(gpio) & __raw_readl(&g->in_data)); +} + +/* powerup default direction is IN */ +extern int gpio_direction_input(unsigned gpio); +extern int gpio_direction_output(unsigned gpio, int value); + +#include <asm-generic/gpio.h> /* cansleep wrappers */ + +extern int gpio_request(unsigned gpio, const char *tag); +extern void gpio_free(unsigned gpio); + +static inline int gpio_to_irq(unsigned gpio) +{ + return DAVINCI_N_AINTC_IRQ + gpio; +} + +static inline int irq_to_gpio(unsigned irq) +{ + return irq - DAVINCI_N_AINTC_IRQ; +} + +#endif /* __DAVINCI_GPIO_H */ diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h index 60362d80229e..a2e8969afaca 100644 --- a/include/asm-arm/arch-davinci/hardware.h +++ b/include/asm-arm/arch-davinci/hardware.h @@ -11,4 +11,42 @@ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H +/* + * Base register addresses + */ +#define DAVINCI_DMA_3PCC_BASE (0x01C00000) +#define DAVINCI_DMA_3PTC0_BASE (0x01C10000) +#define DAVINCI_DMA_3PTC1_BASE (0x01C10400) +#define DAVINCI_I2C_BASE (0x01C21000) +#define DAVINCI_PWM0_BASE (0x01C22000) +#define DAVINCI_PWM1_BASE (0x01C22400) +#define DAVINCI_PWM2_BASE (0x01C22800) +#define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000) +#define DAVINCI_PLL_CNTRL0_BASE (0x01C40800) +#define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00) +#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000) +#define DAVINCI_SYSTEM_DFT_BASE (0x01C42000) +#define DAVINCI_IEEE1394_BASE (0x01C60000) +#define DAVINCI_USB_OTG_BASE (0x01C64000) +#define DAVINCI_CFC_ATA_BASE (0x01C66000) +#define DAVINCI_SPI_BASE (0x01C66800) +#define DAVINCI_GPIO_BASE (0x01C67000) +#define DAVINCI_UHPI_BASE (0x01C67800) +#define DAVINCI_VPSS_REGS_BASE (0x01C70000) +#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000) +#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000) +#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000) +#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000) +#define DAVINCI_IMCOP_BASE (0x01CC0000) +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000) +#define DAVINCI_VLYNQ_BASE (0x01E01000) +#define DAVINCI_MCBSP_BASE (0x01E02000) +#define DAVINCI_MMC_SD_BASE (0x01E10000) +#define DAVINCI_MS_BASE (0x01E20000) +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) +#define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000) + #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-davinci/mux.h b/include/asm-arm/arch-davinci/mux.h new file mode 100644 index 000000000000..c24b6782804d --- /dev/null +++ b/include/asm-arm/arch-davinci/mux.h @@ -0,0 +1,55 @@ +/* + * DaVinci pin multiplexing defines + * + * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_MUX_H +#define __ASM_ARCH_MUX_H + +#define DAVINCI_MUX_AEAW0 0 +#define DAVINCI_MUX_AEAW1 1 +#define DAVINCI_MUX_AEAW2 2 +#define DAVINCI_MUX_AEAW3 3 +#define DAVINCI_MUX_AEAW4 4 +#define DAVINCI_MUX_AECS4 10 +#define DAVINCI_MUX_AECS5 11 +#define DAVINCI_MUX_VLYNQWD0 12 +#define DAVINCI_MUX_VLYNQWD1 13 +#define DAVINCI_MUX_VLSCREN 14 +#define DAVINCI_MUX_VLYNQEN 15 +#define DAVINCI_MUX_HDIREN 16 +#define DAVINCI_MUX_ATAEN 17 +#define DAVINCI_MUX_RGB666 22 +#define DAVINCI_MUX_RGB888 23 +#define DAVINCI_MUX_LOEEN 24 +#define DAVINCI_MUX_LFLDEN 25 +#define DAVINCI_MUX_CWEN 26 +#define DAVINCI_MUX_CFLDEN 27 +#define DAVINCI_MUX_HPIEN 29 +#define DAVINCI_MUX_1394EN 30 +#define DAVINCI_MUX_EMACEN 31 + +#define DAVINCI_MUX_LEVEL2 32 +#define DAVINCI_MUX_UART0 (DAVINCI_MUX_LEVEL2 + 0) +#define DAVINCI_MUX_UART1 (DAVINCI_MUX_LEVEL2 + 1) +#define DAVINCI_MUX_UART2 (DAVINCI_MUX_LEVEL2 + 2) +#define DAVINCI_MUX_U2FLO (DAVINCI_MUX_LEVEL2 + 3) +#define DAVINCI_MUX_PWM0 (DAVINCI_MUX_LEVEL2 + 4) +#define DAVINCI_MUX_PWM1 (DAVINCI_MUX_LEVEL2 + 5) +#define DAVINCI_MUX_PWM2 (DAVINCI_MUX_LEVEL2 + 6) +#define DAVINCI_MUX_I2C (DAVINCI_MUX_LEVEL2 + 7) +#define DAVINCI_MUX_SPI (DAVINCI_MUX_LEVEL2 + 8) +#define DAVINCI_MUX_MSTK (DAVINCI_MUX_LEVEL2 + 9) +#define DAVINCI_MUX_ASP (DAVINCI_MUX_LEVEL2 + 10) +#define DAVINCI_MUX_CLK0 (DAVINCI_MUX_LEVEL2 + 16) +#define DAVINCI_MUX_CLK1 (DAVINCI_MUX_LEVEL2 + 17) +#define DAVINCI_MUX_TIMIN (DAVINCI_MUX_LEVEL2 + 18) + +extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable); + +#endif /* __ASM_ARCH_MUX_H */ diff --git a/include/asm-arm/arch-imx/gpio.h b/include/asm-arm/arch-imx/gpio.h new file mode 100644 index 000000000000..486023263f32 --- /dev/null +++ b/include/asm-arm/arch-imx/gpio.h @@ -0,0 +1,102 @@ +#ifndef _IMX_GPIO_H + +#include <asm/arch/imx-regs.h> + +#define IMX_GPIO_ALLOC_MODE_NORMAL 0 +#define IMX_GPIO_ALLOC_MODE_NO_ALLOC 1 +#define IMX_GPIO_ALLOC_MODE_TRY_ALLOC 2 +#define IMX_GPIO_ALLOC_MODE_ALLOC_ONLY 4 +#define IMX_GPIO_ALLOC_MODE_RELEASE 8 + +extern int imx_gpio_request(unsigned gpio, const char *label); + +extern void imx_gpio_free(unsigned gpio); + +extern int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count, + int alloc_mode, const char *label); + +extern int imx_gpio_direction_input(unsigned gpio); + +extern int imx_gpio_direction_output(unsigned gpio, int value); + +extern void __imx_gpio_set_value(unsigned gpio, int value); + +static inline int imx_gpio_get_value(unsigned gpio) +{ + return SSR(gpio >> GPIO_PORT_SHIFT) & (1 << (gpio & GPIO_PIN_MASK)); +} + +static inline void imx_gpio_set_value_inline(unsigned gpio, int value) +{ + unsigned long flags; + + raw_local_irq_save(flags); + if(value) + DR(gpio >> GPIO_PORT_SHIFT) |= (1 << (gpio & GPIO_PIN_MASK)); + else + DR(gpio >> GPIO_PORT_SHIFT) &= ~(1 << (gpio & GPIO_PIN_MASK)); + raw_local_irq_restore(flags); +} + +static inline void imx_gpio_set_value(unsigned gpio, int value) +{ + if(__builtin_constant_p(gpio)) + imx_gpio_set_value_inline(gpio, value); + else + __imx_gpio_set_value(gpio, value); +} + +extern int imx_gpio_to_irq(unsigned gpio); + +extern int imx_irq_to_gpio(unsigned irq); + +/*-------------------------------------------------------------------------*/ + +/* Wrappers for "new style" GPIO calls. These calls i.MX specific versions + * to allow future extension of GPIO logic. + */ + +static inline int gpio_request(unsigned gpio, const char *label) +{ + return imx_gpio_request(gpio, label); +} + +static inline void gpio_free(unsigned gpio) +{ + imx_gpio_free(gpio); +} + +static inline int gpio_direction_input(unsigned gpio) +{ + return imx_gpio_direction_input(gpio); +} + +static inline int gpio_direction_output(unsigned gpio, int value) +{ + return imx_gpio_direction_output(gpio, value); +} + +static inline int gpio_get_value(unsigned gpio) +{ + return imx_gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + imx_gpio_set_value(gpio, value); +} + +#include <asm-generic/gpio.h> /* cansleep wrappers */ + +static inline int gpio_to_irq(unsigned gpio) +{ + return imx_gpio_to_irq(gpio); +} + +static inline int irq_to_gpio(unsigned irq) +{ + return imx_irq_to_gpio(irq); +} + + +#endif diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h index 30de404c61f5..fb9de2733879 100644 --- a/include/asm-arm/arch-imx/imx-regs.h +++ b/include/asm-arm/arch-imx/imx-regs.h @@ -77,6 +77,8 @@ #define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) #define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8) +#define GPIO_PORT_MAX 3 + #define GPIO_PIN_MASK 0x1f #define GPIO_PORT_MASK (0x3 << 5) diff --git a/include/asm-arm/arch-iop13xx/adma.h b/include/asm-arm/arch-iop13xx/adma.h new file mode 100644 index 000000000000..04006c1c5fd7 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/adma.h @@ -0,0 +1,544 @@ +/* + * Copyright(c) 2006, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ +#ifndef _ADMA_H +#define _ADMA_H +#include <linux/types.h> +#include <linux/io.h> +#include <asm/hardware.h> +#include <asm/hardware/iop_adma.h> + +#define ADMA_ACCR(chan) (chan->mmr_base + 0x0) +#define ADMA_ACSR(chan) (chan->mmr_base + 0x4) +#define ADMA_ADAR(chan) (chan->mmr_base + 0x8) +#define ADMA_IIPCR(chan) (chan->mmr_base + 0x18) +#define ADMA_IIPAR(chan) (chan->mmr_base + 0x1c) +#define ADMA_IIPUAR(chan) (chan->mmr_base + 0x20) +#define ADMA_ANDAR(chan) (chan->mmr_base + 0x24) +#define ADMA_ADCR(chan) (chan->mmr_base + 0x28) +#define ADMA_CARMD(chan) (chan->mmr_base + 0x2c) +#define ADMA_ABCR(chan) (chan->mmr_base + 0x30) +#define ADMA_DLADR(chan) (chan->mmr_base + 0x34) +#define ADMA_DUADR(chan) (chan->mmr_base + 0x38) +#define ADMA_SLAR(src, chan) (chan->mmr_base + (0x3c + (src << 3))) +#define ADMA_SUAR(src, chan) (chan->mmr_base + (0x40 + (src << 3))) + +struct iop13xx_adma_src { + u32 src_addr; + union { + u32 upper_src_addr; + struct { + unsigned int pq_upper_src_addr:24; + unsigned int pq_dmlt:8; + }; + }; +}; + +struct iop13xx_adma_desc_ctrl { + unsigned int int_en:1; + unsigned int xfer_dir:2; + unsigned int src_select:4; + unsigned int zero_result:1; + unsigned int block_fill_en:1; + unsigned int crc_gen_en:1; + unsigned int crc_xfer_dis:1; + unsigned int crc_seed_fetch_dis:1; + unsigned int status_write_back_en:1; + unsigned int endian_swap_en:1; + unsigned int reserved0:2; + unsigned int pq_update_xfer_en:1; + unsigned int dual_xor_en:1; + unsigned int pq_xfer_en:1; + unsigned int p_xfer_dis:1; + unsigned int reserved1:10; + unsigned int relax_order_en:1; + unsigned int no_snoop_en:1; +}; + +struct iop13xx_adma_byte_count { + unsigned int byte_count:24; + unsigned int host_if:3; + unsigned int reserved:2; + unsigned int zero_result_err_q:1; + unsigned int zero_result_err:1; + unsigned int tx_complete:1; +}; + +struct iop13xx_adma_desc_hw { + u32 next_desc; + union { + u32 desc_ctrl; + struct iop13xx_adma_desc_ctrl desc_ctrl_field; + }; + union { + u32 crc_addr; + u32 block_fill_data; + u32 q_dest_addr; + }; + union { + u32 byte_count; + struct iop13xx_adma_byte_count byte_count_field; + }; + union { + u32 dest_addr; + u32 p_dest_addr; + }; + union { + u32 upper_dest_addr; + u32 pq_upper_dest_addr; + }; + struct iop13xx_adma_src src[1]; +}; + +struct iop13xx_adma_desc_dual_xor { + u32 next_desc; + u32 desc_ctrl; + u32 reserved; + u32 byte_count; + u32 h_dest_addr; + u32 h_upper_dest_addr; + u32 src0_addr; + u32 upper_src0_addr; + u32 src1_addr; + u32 upper_src1_addr; + u32 h_src_addr; + u32 h_upper_src_addr; + u32 d_src_addr; + u32 d_upper_src_addr; + u32 d_dest_addr; + u32 d_upper_dest_addr; +}; + +struct iop13xx_adma_desc_pq_update { + u32 next_desc; + u32 desc_ctrl; + u32 reserved; + u32 byte_count; + u32 p_dest_addr; + u32 p_upper_dest_addr; + u32 src0_addr; + u32 upper_src0_addr; + u32 src1_addr; + u32 upper_src1_addr; + u32 p_src_addr; + u32 p_upper_src_addr; + u32 q_src_addr; + struct { + unsigned int q_upper_src_addr:24; + unsigned int q_dmlt:8; + }; + u32 q_dest_addr; + u32 q_upper_dest_addr; +}; + +static inline int iop_adma_get_max_xor(void) +{ + return 16; +} + +static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan) +{ + return __raw_readl(ADMA_ADAR(chan)); +} + +static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan, + u32 next_desc_addr) +{ + __raw_writel(next_desc_addr, ADMA_ANDAR(chan)); +} + +#define ADMA_STATUS_BUSY (1 << 13) + +static inline char iop_chan_is_busy(struct iop_adma_chan *chan) +{ + if (__raw_readl(ADMA_ACSR(chan)) & + ADMA_STATUS_BUSY) + return 1; + else + return 0; +} + +static inline int +iop_chan_get_desc_align(struct iop_adma_chan *chan, int num_slots) +{ + return 1; +} +#define iop_desc_is_aligned(x, y) 1 + +static inline int +iop_chan_memcpy_slot_count(size_t len, int *slots_per_op) +{ + *slots_per_op = 1; + return 1; +} + +#define iop_chan_interrupt_slot_count(s, c) iop_chan_memcpy_slot_count(0, s) + +static inline int +iop_chan_memset_slot_count(size_t len, int *slots_per_op) +{ + *slots_per_op = 1; + return 1; +} + +static inline int +iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op) +{ + int num_slots; + /* slots_to_find = 1 for basic descriptor + 1 per 4 sources above 1 + * (1 source => 8 bytes) (1 slot => 32 bytes) + */ + num_slots = 1 + (((src_cnt - 1) << 3) >> 5); + if (((src_cnt - 1) << 3) & 0x1f) + num_slots++; + + *slots_per_op = num_slots; + + return num_slots; +} + +#define ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024) +#define IOP_ADMA_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT +#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT +#define IOP_ADMA_XOR_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT +#define iop_chan_zero_sum_slot_count(l, s, o) iop_chan_xor_slot_count(l, s, o) + +static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + return hw_desc->dest_addr; +} + +static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + return hw_desc->byte_count_field.byte_count; +} + +static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan, + int src_idx) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + return hw_desc->src[src_idx].src_addr; +} + +static inline u32 iop_desc_get_src_count(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + return hw_desc->desc_ctrl_field.src_select + 1; +} + +static inline void +iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, int int_en) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop13xx_adma_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ + u_desc_ctrl.field.int_en = int_en; + hw_desc->desc_ctrl = u_desc_ctrl.value; + hw_desc->crc_addr = 0; +} + +static inline void +iop_desc_init_memset(struct iop_adma_desc_slot *desc, int int_en) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop13xx_adma_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ + u_desc_ctrl.field.block_fill_en = 1; + u_desc_ctrl.field.int_en = int_en; + hw_desc->desc_ctrl = u_desc_ctrl.value; + hw_desc->crc_addr = 0; +} + +/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */ +static inline void +iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop13xx_adma_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + u_desc_ctrl.field.src_select = src_cnt - 1; + u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ + u_desc_ctrl.field.int_en = int_en; + hw_desc->desc_ctrl = u_desc_ctrl.value; + hw_desc->crc_addr = 0; + +} +#define iop_desc_init_null_xor(d, s, i) iop_desc_init_xor(d, s, i) + +/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */ +static inline int +iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop13xx_adma_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + u_desc_ctrl.field.src_select = src_cnt - 1; + u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ + u_desc_ctrl.field.zero_result = 1; + u_desc_ctrl.field.status_write_back_en = 1; + u_desc_ctrl.field.int_en = int_en; + hw_desc->desc_ctrl = u_desc_ctrl.value; + hw_desc->crc_addr = 0; + + return 1; +} + +static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan, + u32 byte_count) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + hw_desc->byte_count = byte_count; +} + +static inline void +iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len) +{ + int slots_per_op = desc->slots_per_op; + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter; + int i = 0; + + if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { + hw_desc->byte_count = len; + } else { + do { + iter = iop_hw_desc_slot_idx(hw_desc, i); + iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; + len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; + i += slots_per_op; + } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT); + + if (len) { + iter = iop_hw_desc_slot_idx(hw_desc, i); + iter->byte_count = len; + } + } +} + + +static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan, + dma_addr_t addr) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + hw_desc->dest_addr = addr; + hw_desc->upper_dest_addr = 0; +} + +static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc, + dma_addr_t addr) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + hw_desc->src[0].src_addr = addr; + hw_desc->src[0].upper_src_addr = 0; +} + +static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc, + int src_idx, dma_addr_t addr) +{ + int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter; + int i = 0; + + do { + iter = iop_hw_desc_slot_idx(hw_desc, i); + iter->src[src_idx].src_addr = addr; + iter->src[src_idx].upper_src_addr = 0; + slot_cnt -= slots_per_op; + if (slot_cnt) { + i += slots_per_op; + addr += IOP_ADMA_XOR_MAX_BYTE_COUNT; + } + } while (slot_cnt); +} + +static inline void +iop_desc_init_interrupt(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + iop_desc_init_memcpy(desc, 1); + iop_desc_set_byte_count(desc, chan, 0); + iop_desc_set_dest_addr(desc, chan, 0); + iop_desc_set_memcpy_src_addr(desc, 0); +} + +#define iop_desc_set_zero_sum_src_addr iop_desc_set_xor_src_addr + +static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc, + u32 next_desc_addr) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + BUG_ON(hw_desc->next_desc); + hw_desc->next_desc = next_desc_addr; +} + +static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + return hw_desc->next_desc; +} + +static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + hw_desc->next_desc = 0; +} + +static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc, + u32 val) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + hw_desc->block_fill_data = val; +} + +static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + struct iop13xx_adma_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field; + struct iop13xx_adma_byte_count byte_count = hw_desc->byte_count_field; + + BUG_ON(!(byte_count.tx_complete && desc_ctrl.zero_result)); + + if (desc_ctrl.pq_xfer_en) + return byte_count.zero_result_err_q; + else + return byte_count.zero_result_err; +} + +static inline void iop_chan_append(struct iop_adma_chan *chan) +{ + u32 adma_accr; + + adma_accr = __raw_readl(ADMA_ACCR(chan)); + adma_accr |= 0x2; + __raw_writel(adma_accr, ADMA_ACCR(chan)); +} + +static inline void iop_chan_idle(int busy, struct iop_adma_chan *chan) +{ + do { } while (0); +} + +static inline u32 iop_chan_get_status(struct iop_adma_chan *chan) +{ + return __raw_readl(ADMA_ACSR(chan)); +} + +static inline void iop_chan_disable(struct iop_adma_chan *chan) +{ + u32 adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan)); + adma_chan_ctrl &= ~0x1; + __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan)); +} + +static inline void iop_chan_enable(struct iop_adma_chan *chan) +{ + u32 adma_chan_ctrl; + + adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan)); + adma_chan_ctrl |= 0x1; + __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan)); +} + +static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan) +{ + u32 status = __raw_readl(ADMA_ACSR(chan)); + status &= (1 << 12); + __raw_writel(status, ADMA_ACSR(chan)); +} + +static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan) +{ + u32 status = __raw_readl(ADMA_ACSR(chan)); + status &= (1 << 11); + __raw_writel(status, ADMA_ACSR(chan)); +} + +static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan) +{ + u32 status = __raw_readl(ADMA_ACSR(chan)); + status &= (1 << 9) | (1 << 5) | (1 << 4) | (1 << 3); + __raw_writel(status, ADMA_ACSR(chan)); +} + +static inline int +iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan) +{ + return test_bit(9, &status); +} + +static inline int +iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan) +{ + return test_bit(5, &status); +} + +static inline int +iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan) +{ + return test_bit(4, &status); +} + +static inline int +iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan) +{ + return test_bit(3, &status); +} + +static inline int +iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan) +{ + return 0; +} + +static inline int +iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan) +{ + return 0; +} + +static inline int +iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan) +{ + return 0; +} + +#endif /* _ADMA_H */ diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h index e6736c3d1f7f..d4e4f828577c 100644 --- a/include/asm-arm/arch-iop13xx/iop13xx.h +++ b/include/asm-arm/arch-iop13xx/iop13xx.h @@ -166,12 +166,22 @@ static inline int iop13xx_cpu_id(void) #define IOP13XX_INIT_I2C_1 (1 << 1) #define IOP13XX_INIT_I2C_2 (1 << 2) -#define IQ81340_NUM_UART 2 -#define IQ81340_NUM_I2C 3 -#define IQ81340_NUM_PHYS_MAP_FLASH 1 -#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART +\ - IQ81340_NUM_I2C +\ - IQ81340_NUM_PHYS_MAP_FLASH) +/* ADMA selection flags */ +/* INIT_ADMA_DEFAULT = Rely on CONFIG_IOP13XX_ADMA* */ +#define IOP13XX_INIT_ADMA_DEFAULT (0) +#define IOP13XX_INIT_ADMA_0 (1 << 0) +#define IOP13XX_INIT_ADMA_1 (1 << 1) +#define IOP13XX_INIT_ADMA_2 (1 << 2) + +/* Platform devices */ +#define IQ81340_NUM_UART 2 +#define IQ81340_NUM_I2C 3 +#define IQ81340_NUM_PHYS_MAP_FLASH 1 +#define IQ81340_NUM_ADMA 3 +#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART + \ + IQ81340_NUM_I2C + \ + IQ81340_NUM_PHYS_MAP_FLASH + \ + IQ81340_NUM_ADMA) /*========================== PMMR offsets for key registers ============*/ #define IOP13XX_ATU0_PMMR_OFFSET 0x00048000 @@ -444,22 +454,6 @@ static inline int iop13xx_cpu_id(void) /*==============================ADMA UNITS===============================*/ #define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9)) #define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0) -#define IOP13XX_ADMA_OFFSET(chan, ofs) IOP13XX_REG_ADDR32((chan << 9) + (ofs)) - -#define IOP13XX_ADMA_ACCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x0) -#define IOP13XX_ADMA_ACSR(chan) IOP13XX_ADMA_OFFSET(chan, 0x4) -#define IOP13XX_ADMA_ADAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x8) -#define IOP13XX_ADMA_IIPCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x18) -#define IOP13XX_ADMA_IIPAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x1c) -#define IOP13XX_ADMA_IIPUAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x20) -#define IOP13XX_ADMA_ANDAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x24) -#define IOP13XX_ADMA_ADCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x28) -#define IOP13XX_ADMA_CARMD(chan) IOP13XX_ADMA_OFFSET(chan, 0x2c) -#define IOP13XX_ADMA_ABCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x30) -#define IOP13XX_ADMA_DLADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x34) -#define IOP13XX_ADMA_DUADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x38) -#define IOP13XX_ADMA_SLAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x3c + (src <<3)) -#define IOP13XX_ADMA_SUAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x40 + (src <<3)) /*==============================XSI BRIDGE===============================*/ #define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c) diff --git a/include/asm-arm/arch-iop32x/adma.h b/include/asm-arm/arch-iop32x/adma.h new file mode 100644 index 000000000000..5ed92037dd10 --- /dev/null +++ b/include/asm-arm/arch-iop32x/adma.h @@ -0,0 +1,5 @@ +#ifndef IOP32X_ADMA_H +#define IOP32X_ADMA_H +#include <asm/hardware/iop3xx-adma.h> +#endif + diff --git a/include/asm-arm/arch-iop33x/adma.h b/include/asm-arm/arch-iop33x/adma.h new file mode 100644 index 000000000000..4b92f795f90e --- /dev/null +++ b/include/asm-arm/arch-iop33x/adma.h @@ -0,0 +1,5 @@ +#ifndef IOP33X_ADMA_H +#define IOP33X_ADMA_H +#include <asm/hardware/iop3xx-adma.h> +#endif + diff --git a/include/asm-arm/arch-ixp4xx/ixdp425.h b/include/asm-arm/arch-ixp4xx/ixdp425.h index 3d3820d7ba09..e0791af3bfea 100644 --- a/include/asm-arm/arch-ixp4xx/ixdp425.h +++ b/include/asm-arm/arch-ixp4xx/ixdp425.h @@ -32,4 +32,8 @@ #define IXDP425_PCI_INTC_PIN 9 #define IXDP425_PCI_INTD_PIN 8 +/* NAND Flash pins */ +#define IXDP425_NAND_NCE_PIN 12 +#define IXDP425_NAND_CMD_BYTE 0x01 +#define IXDP425_NAND_ADDR_BYTE 0x02 diff --git a/include/asm-arm/arch-ixp4xx/udc.h b/include/asm-arm/arch-ixp4xx/udc.h index 79b850a3be47..dbdec36ff0d1 100644 --- a/include/asm-arm/arch-ixp4xx/udc.h +++ b/include/asm-arm/arch-ixp4xx/udc.h @@ -6,25 +6,3 @@ extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info); -static inline int udc_gpio_to_irq(unsigned gpio) -{ - return 0; -} - -static inline void udc_gpio_init_vbus(unsigned gpio) -{ -} - -static inline void udc_gpio_init_pullup(unsigned gpio) -{ -} - -static inline int udc_gpio_get(unsigned gpio) -{ - return 0; -} - -static inline void udc_gpio_set(unsigned gpio, int is_on) -{ -} - diff --git a/include/asm-arm/arch-ixp4xx/uncompress.h b/include/asm-arm/arch-ixp4xx/uncompress.h index 09ae6c91be60..f7a35b78823f 100644 --- a/include/asm-arm/arch-ixp4xx/uncompress.h +++ b/include/asm-arm/arch-ixp4xx/uncompress.h @@ -38,9 +38,10 @@ static void flush(void) static __inline__ void __arch_decomp_setup(unsigned long arch_id) { /* - * Coyote and gtwx5715 only have UART2 connected + * Some boards are using UART2 as console */ - if (machine_is_adi_coyote() || machine_is_gtwx5715()) + if (machine_is_adi_coyote() || machine_is_gtwx5715() || + machine_is_gateway7001() || machine_is_wg302v2()) uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; else uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; diff --git a/include/asm-arm/arch-ks8695/gpio.h b/include/asm-arm/arch-ks8695/gpio.h new file mode 100644 index 000000000000..65ceea28607b --- /dev/null +++ b/include/asm-arm/arch-ks8695/gpio.h @@ -0,0 +1,79 @@ +/* + * include/asm-arm/arch-ks8695/gpio.h + * + * Copyright (C) 2006 Andrew Victor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_GPIO_H_ +#define __ASM_ARCH_GPIO_H_ + +#define KS8695_GPIO_0 0 +#define KS8695_GPIO_1 1 +#define KS8695_GPIO_2 2 +#define KS8695_GPIO_3 3 +#define KS8695_GPIO_4 4 +#define KS8695_GPIO_5 5 +#define KS8695_GPIO_6 6 +#define KS8695_GPIO_7 7 +#define KS8695_GPIO_8 8 +#define KS8695_GPIO_9 9 +#define KS8695_GPIO_10 10 +#define KS8695_GPIO_11 11 +#define KS8695_GPIO_12 12 +#define KS8695_GPIO_13 13 +#define KS8695_GPIO_14 14 +#define KS8695_GPIO_15 15 + + +/* + * Configure GPIO pin as external interrupt source. + */ +int __init_or_module ks8695_gpio_interrupt(unsigned int pin, unsigned int type); + +/* + * Configure the GPIO line as an input. + */ +int __init_or_module gpio_direction_input(unsigned int pin); + +/* + * Configure the GPIO line as an output, with default state. + */ +int __init_or_module gpio_direction_output(unsigned int pin, unsigned int state); + +/* + * Set the state of an output GPIO line. + */ +void gpio_set_value(unsigned int pin, unsigned int state); + +/* + * Read the state of a GPIO line. + */ +int gpio_get_value(unsigned int pin); + +/* + * Map GPIO line to IRQ number. + */ +int gpio_to_irq(unsigned int pin); + +/* + * Map IRQ number to GPIO line. + */ +int irq_to_gpio(unsigned int irq); + + +#include <asm-generic/gpio.h> + +static inline int gpio_request(unsigned int pin, const char *label) +{ + return 0; +} + +static inline void gpio_free(unsigned int pin) +{ +} + +#endif diff --git a/include/asm-arm/arch-pxa/dma.h b/include/asm-arm/arch-pxa/dma.h index bed042d71d68..3280ee2ddfa5 100644 --- a/include/asm-arm/arch-pxa/dma.h +++ b/include/asm-arm/arch-pxa/dma.h @@ -30,30 +30,12 @@ typedef enum { DMA_PRIO_LOW = 2 } pxa_dma_prio; -#if defined(CONFIG_PXA27x) - -#define PXA_DMA_CHANNELS 32 - -#define pxa_for_each_dma_prio(ch, prio) \ -for ( \ - ch = prio * 4; \ - ch != (4 << prio) + 16; \ - ch = (ch + 1 == (4 << prio)) ? (prio * 4 + 16) : (ch + 1) \ -) - -#elif defined(CONFIG_PXA25x) - -#define PXA_DMA_CHANNELS 16 - -#define pxa_for_each_dma_prio(ch, prio) \ - for (ch = prio * 4; ch != (4 << prio); ch++) - -#endif - /* * DMA registration */ +int __init pxa_init_dma(int num_ch); + int pxa_request_dma (char *name, pxa_dma_prio prio, void (*irq_handler)(int, void *), diff --git a/include/asm-arm/arch-pxa/entry-macro.S b/include/asm-arm/arch-pxa/entry-macro.S index 1d5fbb9b379a..b7e730851461 100644 --- a/include/asm-arm/arch-pxa/entry-macro.S +++ b/include/asm-arm/arch-pxa/entry-macro.S @@ -20,20 +20,38 @@ .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp -#ifdef CONFIG_PXA27x - mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP - mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR -#else + mrc p15, 0, \tmp, c0, c0, 0 @ CPUID + mov \tmp, \tmp, lsr #13 + and \tmp, \tmp, #0x7 @ Core G + cmp \tmp, #1 + bhi 1004f + mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000 add \base, \base, #0x00d00000 ldr \irqstat, [\base, #0] @ ICIP ldr \irqnr, [\base, #4] @ ICMR -#endif + b 1002f + +1004: + mrc p6, 0, \irqstat, c6, c0, 0 @ ICIP2 + mrc p6, 0, \irqnr, c7, c0, 0 @ ICMR2 + ands \irqstat, \irqstat, \irqnr + beq 1003f + rsb \irqstat, \irqnr, #0 + and \irqstat, \irqstat, \irqnr + clz \irqnr, \irqstat + rsb \irqnr, \irqnr, #31 + add \irqnr, \irqnr, #32 + b 1001f +1003: + mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP + mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR +1002: ands \irqnr, \irqstat, \irqnr beq 1001f rsb \irqstat, \irqnr, #0 and \irqstat, \irqstat, \irqnr clz \irqnr, \irqstat - rsb \irqnr, \irqnr, #(31 - PXA_IRQ_SKIP) + rsb \irqnr, \irqnr, #31 1001: .endm diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h index e2bdc2fbede1..386121746417 100644 --- a/include/asm-arm/arch-pxa/hardware.h +++ b/include/asm-arm/arch-pxa/hardware.h @@ -62,6 +62,42 @@ #ifndef __ASSEMBLY__ +#define __cpu_is_pxa21x(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xf3f; \ + _id == 0x212; \ + }) + +#define __cpu_is_pxa25x(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x2d0 || _id == 0x290; \ + }) + +#define __cpu_is_pxa27x(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x411; \ + }) + +#define cpu_is_pxa21x() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa21x(id); \ + }) + +#define cpu_is_pxa25x() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa25x(id); \ + }) + +#define cpu_is_pxa27x() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa27x(id); \ + }) + /* * Handy routine to set GPIO alternate functions */ diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h index 67ed43674c63..a07fe0f928cd 100644 --- a/include/asm-arm/arch-pxa/irqs.h +++ b/include/asm-arm/arch-pxa/irqs.h @@ -11,14 +11,9 @@ */ -#ifdef CONFIG_PXA27x -#define PXA_IRQ_SKIP 0 -#else -#define PXA_IRQ_SKIP 7 -#endif - -#define PXA_IRQ(x) ((x) - PXA_IRQ_SKIP) +#define PXA_IRQ(x) (x) +#ifdef CONFIG_PXA27x #define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */ #define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */ #define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI) */ @@ -26,6 +21,8 @@ #define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */ #define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt */ #define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */ +#endif + #define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */ #define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */ #define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */ @@ -58,18 +55,15 @@ #ifdef CONFIG_PXA27x #define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */ #define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */ - -#define PXA_INTERNAL_IRQS 34 -#else -#define PXA_INTERNAL_IRQS 32 #endif -#define GPIO_2_x_TO_IRQ(x) \ - PXA_IRQ((x) - 2 + PXA_INTERNAL_IRQS) +#define PXA_GPIO_IRQ_BASE (64) +#define PXA_GPIO_IRQ_NUM (128) + +#define GPIO_2_x_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x)) #define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x)) -#define IRQ_TO_GPIO_2_x(i) \ - ((i) - IRQ_GPIO(2) + 2) +#define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE) #define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i)) #if defined(CONFIG_PXA25x) @@ -84,7 +78,7 @@ * these. If you need more, increase IRQ_BOARD_END, but keep it * within sensible limits. */ -#define IRQ_BOARD_START (IRQ_GPIO(PXA_LAST_GPIO) + 1) +#define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM) #define IRQ_BOARD_END (IRQ_BOARD_START + 16) #define IRQ_SA1111_START (IRQ_BOARD_END) diff --git a/include/asm-arm/arch-pxa/pm.h b/include/asm-arm/arch-pxa/pm.h index 7a8a1cdf430d..52243a62c4e7 100644 --- a/include/asm-arm/arch-pxa/pm.h +++ b/include/asm-arm/arch-pxa/pm.h @@ -9,4 +9,3 @@ extern int pxa_pm_prepare(suspend_state_t state); extern int pxa_pm_enter(suspend_state_t state); -extern int pxa_pm_finish(suspend_state_t state); diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index dbcc9298b0c8..e68b593d69da 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -1765,29 +1765,9 @@ #define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL)) /* - * MultiMediaCard (MMC) controller + * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h */ -#define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */ -#define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */ -#define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */ -#define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */ -#define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */ -#define MMC_RESTO __REG(0x41100014) /* Expected response time out */ -#define MMC_RDTO __REG(0x41100018) /* Expected data read time out */ -#define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */ -#define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */ -#define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */ -#define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */ -#define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */ -#define MMC_CMD __REG(0x41100030) /* Index of current command */ -#define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */ -#define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */ -#define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */ -#define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */ -#define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */ - - /* * Core Clock */ diff --git a/include/asm-arm/arch-pxa/udc.h b/include/asm-arm/arch-pxa/udc.h index 8bc6f9c3e3ea..27aa3a91012f 100644 --- a/include/asm-arm/arch-pxa/udc.h +++ b/include/asm-arm/arch-pxa/udc.h @@ -1,41 +1,8 @@ /* * linux/include/asm-arm/arch-pxa/udc.h * - * This supports machine-specific differences in how the PXA2xx - * USB Device Controller (UDC) is wired. - * */ #include <asm/mach/udc_pxa2xx.h> extern void pxa_set_udc_info(struct pxa2xx_udc_mach_info *info); -static inline int udc_gpio_to_irq(unsigned gpio) -{ - return IRQ_GPIO(gpio & GPIO_MD_MASK_NR); -} - -static inline void udc_gpio_init_vbus(unsigned gpio) -{ - pxa_gpio_mode((gpio & GPIO_MD_MASK_NR) | GPIO_IN); -} - -static inline void udc_gpio_init_pullup(unsigned gpio) -{ - pxa_gpio_mode((gpio & GPIO_MD_MASK_NR) | GPIO_OUT | GPIO_DFLT_LOW); -} - -static inline int udc_gpio_get(unsigned gpio) -{ - return (GPLR(gpio) & GPIO_bit(gpio)) != 0; -} - -static inline void udc_gpio_set(unsigned gpio, int is_on) -{ - int mask = GPIO_bit(gpio); - - if (is_on) - GPSR(gpio) = mask; - else - GPCR(gpio) = mask; -} - diff --git a/include/asm-arm/elf.h b/include/asm-arm/elf.h index 3679a8a8922e..d7a777f05088 100644 --- a/include/asm-arm/elf.h +++ b/include/asm-arm/elf.h @@ -7,6 +7,7 @@ */ #include <asm/ptrace.h> #include <asm/user.h> +#include <asm/hwcap.h> typedef unsigned long elf_greg_t; typedef unsigned long elf_freg_t[3]; @@ -39,31 +40,9 @@ typedef struct user_fp elf_fpregset_t; #endif #define ELF_ARCH EM_ARM -/* - * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP - */ -#define HWCAP_SWP 1 -#define HWCAP_HALF 2 -#define HWCAP_THUMB 4 -#define HWCAP_26BIT 8 /* Play it safe */ -#define HWCAP_FAST_MULT 16 -#define HWCAP_FPA 32 -#define HWCAP_VFP 64 -#define HWCAP_EDSP 128 -#define HWCAP_JAVA 256 -#define HWCAP_IWMMXT 512 -#define HWCAP_CRUNCH 1024 - #ifdef __KERNEL__ #ifndef __ASSEMBLY__ /* - * This yields a mask that user programs can use to figure out what - * instruction set this cpu supports. - */ -#define ELF_HWCAP (elf_hwcap) -extern unsigned int elf_hwcap; - -/* * This yields a string that ld.so will use to load implementation * specific libraries for optimization. This is more specific in * intent than poking at uname or /proc/cpuinfo. diff --git a/include/asm-arm/hardware/iop3xx-adma.h b/include/asm-arm/hardware/iop3xx-adma.h new file mode 100644 index 000000000000..10834b54f681 --- /dev/null +++ b/include/asm-arm/hardware/iop3xx-adma.h @@ -0,0 +1,892 @@ +/* + * Copyright © 2006, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ +#ifndef _ADMA_H +#define _ADMA_H +#include <linux/types.h> +#include <linux/io.h> +#include <asm/hardware.h> +#include <asm/hardware/iop_adma.h> + +/* Memory copy units */ +#define DMA_CCR(chan) (chan->mmr_base + 0x0) +#define DMA_CSR(chan) (chan->mmr_base + 0x4) +#define DMA_DAR(chan) (chan->mmr_base + 0xc) +#define DMA_NDAR(chan) (chan->mmr_base + 0x10) +#define DMA_PADR(chan) (chan->mmr_base + 0x14) +#define DMA_PUADR(chan) (chan->mmr_base + 0x18) +#define DMA_LADR(chan) (chan->mmr_base + 0x1c) +#define DMA_BCR(chan) (chan->mmr_base + 0x20) +#define DMA_DCR(chan) (chan->mmr_base + 0x24) + +/* Application accelerator unit */ +#define AAU_ACR(chan) (chan->mmr_base + 0x0) +#define AAU_ASR(chan) (chan->mmr_base + 0x4) +#define AAU_ADAR(chan) (chan->mmr_base + 0x8) +#define AAU_ANDAR(chan) (chan->mmr_base + 0xc) +#define AAU_SAR(src, chan) (chan->mmr_base + (0x10 + ((src) << 2))) +#define AAU_DAR(chan) (chan->mmr_base + 0x20) +#define AAU_ABCR(chan) (chan->mmr_base + 0x24) +#define AAU_ADCR(chan) (chan->mmr_base + 0x28) +#define AAU_SAR_EDCR(src_edc) (chan->mmr_base + (0x02c + ((src_edc-4) << 2))) +#define AAU_EDCR0_IDX 8 +#define AAU_EDCR1_IDX 17 +#define AAU_EDCR2_IDX 26 + +#define DMA0_ID 0 +#define DMA1_ID 1 +#define AAU_ID 2 + +struct iop3xx_aau_desc_ctrl { + unsigned int int_en:1; + unsigned int blk1_cmd_ctrl:3; + unsigned int blk2_cmd_ctrl:3; + unsigned int blk3_cmd_ctrl:3; + unsigned int blk4_cmd_ctrl:3; + unsigned int blk5_cmd_ctrl:3; + unsigned int blk6_cmd_ctrl:3; + unsigned int blk7_cmd_ctrl:3; + unsigned int blk8_cmd_ctrl:3; + unsigned int blk_ctrl:2; + unsigned int dual_xor_en:1; + unsigned int tx_complete:1; + unsigned int zero_result_err:1; + unsigned int zero_result_en:1; + unsigned int dest_write_en:1; +}; + +struct iop3xx_aau_e_desc_ctrl { + unsigned int reserved:1; + unsigned int blk1_cmd_ctrl:3; + unsigned int blk2_cmd_ctrl:3; + unsigned int blk3_cmd_ctrl:3; + unsigned int blk4_cmd_ctrl:3; + unsigned int blk5_cmd_ctrl:3; + unsigned int blk6_cmd_ctrl:3; + unsigned int blk7_cmd_ctrl:3; + unsigned int blk8_cmd_ctrl:3; + unsigned int reserved2:7; +}; + +struct iop3xx_dma_desc_ctrl { + unsigned int pci_transaction:4; + unsigned int int_en:1; + unsigned int dac_cycle_en:1; + unsigned int mem_to_mem_en:1; + unsigned int crc_data_tx_en:1; + unsigned int crc_gen_en:1; + unsigned int crc_seed_dis:1; + unsigned int reserved:21; + unsigned int crc_tx_complete:1; +}; + +struct iop3xx_desc_dma { + u32 next_desc; + union { + u32 pci_src_addr; + u32 pci_dest_addr; + u32 src_addr; + }; + union { + u32 upper_pci_src_addr; + u32 upper_pci_dest_addr; + }; + union { + u32 local_pci_src_addr; + u32 local_pci_dest_addr; + u32 dest_addr; + }; + u32 byte_count; + union { + u32 desc_ctrl; + struct iop3xx_dma_desc_ctrl desc_ctrl_field; + }; + u32 crc_addr; +}; + +struct iop3xx_desc_aau { + u32 next_desc; + u32 src[4]; + u32 dest_addr; + u32 byte_count; + union { + u32 desc_ctrl; + struct iop3xx_aau_desc_ctrl desc_ctrl_field; + }; + union { + u32 src_addr; + u32 e_desc_ctrl; + struct iop3xx_aau_e_desc_ctrl e_desc_ctrl_field; + } src_edc[31]; +}; + +struct iop3xx_aau_gfmr { + unsigned int gfmr1:8; + unsigned int gfmr2:8; + unsigned int gfmr3:8; + unsigned int gfmr4:8; +}; + +struct iop3xx_desc_pq_xor { + u32 next_desc; + u32 src[3]; + union { + u32 data_mult1; + struct iop3xx_aau_gfmr data_mult1_field; + }; + u32 dest_addr; + u32 byte_count; + union { + u32 desc_ctrl; + struct iop3xx_aau_desc_ctrl desc_ctrl_field; + }; + union { + u32 src_addr; + u32 e_desc_ctrl; + struct iop3xx_aau_e_desc_ctrl e_desc_ctrl_field; + u32 data_multiplier; + struct iop3xx_aau_gfmr data_mult_field; + u32 reserved; + } src_edc_gfmr[19]; +}; + +struct iop3xx_desc_dual_xor { + u32 next_desc; + u32 src0_addr; + u32 src1_addr; + u32 h_src_addr; + u32 d_src_addr; + u32 h_dest_addr; + u32 byte_count; + union { + u32 desc_ctrl; + struct iop3xx_aau_desc_ctrl desc_ctrl_field; + }; + u32 d_dest_addr; +}; + +union iop3xx_desc { + struct iop3xx_desc_aau *aau; + struct iop3xx_desc_dma *dma; + struct iop3xx_desc_pq_xor *pq_xor; + struct iop3xx_desc_dual_xor *dual_xor; + void *ptr; +}; + +static inline int iop_adma_get_max_xor(void) +{ + return 32; +} + +static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan) +{ + int id = chan->device->id; + + switch (id) { + case DMA0_ID: + case DMA1_ID: + return __raw_readl(DMA_DAR(chan)); + case AAU_ID: + return __raw_readl(AAU_ADAR(chan)); + default: + BUG(); + } + return 0; +} + +static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan, + u32 next_desc_addr) +{ + int id = chan->device->id; + + switch (id) { + case DMA0_ID: + case DMA1_ID: + __raw_writel(next_desc_addr, DMA_NDAR(chan)); + break; + case AAU_ID: + __raw_writel(next_desc_addr, AAU_ANDAR(chan)); + break; + } + +} + +#define IOP_ADMA_STATUS_BUSY (1 << 10) +#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT (1024) +#define IOP_ADMA_XOR_MAX_BYTE_COUNT (16 * 1024 * 1024) +#define IOP_ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024) + +static inline int iop_chan_is_busy(struct iop_adma_chan *chan) +{ + u32 status = __raw_readl(DMA_CSR(chan)); + return (status & IOP_ADMA_STATUS_BUSY) ? 1 : 0; +} + +static inline int iop_desc_is_aligned(struct iop_adma_desc_slot *desc, + int num_slots) +{ + /* num_slots will only ever be 1, 2, 4, or 8 */ + return (desc->idx & (num_slots - 1)) ? 0 : 1; +} + +/* to do: support large (i.e. > hw max) buffer sizes */ +static inline int iop_chan_memcpy_slot_count(size_t len, int *slots_per_op) +{ + *slots_per_op = 1; + return 1; +} + +/* to do: support large (i.e. > hw max) buffer sizes */ +static inline int iop_chan_memset_slot_count(size_t len, int *slots_per_op) +{ + *slots_per_op = 1; + return 1; +} + +static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt, + int *slots_per_op) +{ + const static int slot_count_table[] = { 0, + 1, 1, 1, 1, /* 01 - 04 */ + 2, 2, 2, 2, /* 05 - 08 */ + 4, 4, 4, 4, /* 09 - 12 */ + 4, 4, 4, 4, /* 13 - 16 */ + 8, 8, 8, 8, /* 17 - 20 */ + 8, 8, 8, 8, /* 21 - 24 */ + 8, 8, 8, 8, /* 25 - 28 */ + 8, 8, 8, 8, /* 29 - 32 */ + }; + *slots_per_op = slot_count_table[src_cnt]; + return *slots_per_op; +} + +static inline int +iop_chan_interrupt_slot_count(int *slots_per_op, struct iop_adma_chan *chan) +{ + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + return iop_chan_memcpy_slot_count(0, slots_per_op); + case AAU_ID: + return iop3xx_aau_xor_slot_count(0, 2, slots_per_op); + default: + BUG(); + } + return 0; +} + +static inline int iop_chan_xor_slot_count(size_t len, int src_cnt, + int *slots_per_op) +{ + int slot_cnt = iop3xx_aau_xor_slot_count(len, src_cnt, slots_per_op); + + if (len <= IOP_ADMA_XOR_MAX_BYTE_COUNT) + return slot_cnt; + + len -= IOP_ADMA_XOR_MAX_BYTE_COUNT; + while (len > IOP_ADMA_XOR_MAX_BYTE_COUNT) { + len -= IOP_ADMA_XOR_MAX_BYTE_COUNT; + slot_cnt += *slots_per_op; + } + + if (len) + slot_cnt += *slots_per_op; + + return slot_cnt; +} + +/* zero sum on iop3xx is limited to 1k at a time so it requires multiple + * descriptors + */ +static inline int iop_chan_zero_sum_slot_count(size_t len, int src_cnt, + int *slots_per_op) +{ + int slot_cnt = iop3xx_aau_xor_slot_count(len, src_cnt, slots_per_op); + + if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) + return slot_cnt; + + len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; + while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { + len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; + slot_cnt += *slots_per_op; + } + + if (len) + slot_cnt += *slots_per_op; + + return slot_cnt; +} + +static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + return hw_desc.dma->dest_addr; + case AAU_ID: + return hw_desc.aau->dest_addr; + default: + BUG(); + } + return 0; +} + +static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + return hw_desc.dma->byte_count; + case AAU_ID: + return hw_desc.aau->byte_count; + default: + BUG(); + } + return 0; +} + +/* translate the src_idx to a descriptor word index */ +static inline int __desc_idx(int src_idx) +{ + const static int desc_idx_table[] = { 0, 0, 0, 0, + 0, 1, 2, 3, + 5, 6, 7, 8, + 9, 10, 11, 12, + 14, 15, 16, 17, + 18, 19, 20, 21, + 23, 24, 25, 26, + 27, 28, 29, 30, + }; + + return desc_idx_table[src_idx]; +} + +static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan, + int src_idx) +{ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + return hw_desc.dma->src_addr; + case AAU_ID: + break; + default: + BUG(); + } + + if (src_idx < 4) + return hw_desc.aau->src[src_idx]; + else + return hw_desc.aau->src_edc[__desc_idx(src_idx)].src_addr; +} + +static inline void iop3xx_aau_desc_set_src_addr(struct iop3xx_desc_aau *hw_desc, + int src_idx, dma_addr_t addr) +{ + if (src_idx < 4) + hw_desc->src[src_idx] = addr; + else + hw_desc->src_edc[__desc_idx(src_idx)].src_addr = addr; +} + +static inline void +iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, int int_en) +{ + struct iop3xx_desc_dma *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop3xx_dma_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + u_desc_ctrl.field.mem_to_mem_en = 1; + u_desc_ctrl.field.pci_transaction = 0xe; /* memory read block */ + u_desc_ctrl.field.int_en = int_en; + hw_desc->desc_ctrl = u_desc_ctrl.value; + hw_desc->upper_pci_src_addr = 0; + hw_desc->crc_addr = 0; +} + +static inline void +iop_desc_init_memset(struct iop_adma_desc_slot *desc, int int_en) +{ + struct iop3xx_desc_aau *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop3xx_aau_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + u_desc_ctrl.field.blk1_cmd_ctrl = 0x2; /* memory block fill */ + u_desc_ctrl.field.dest_write_en = 1; + u_desc_ctrl.field.int_en = int_en; + hw_desc->desc_ctrl = u_desc_ctrl.value; +} + +static inline u32 +iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt, int int_en) +{ + int i, shift; + u32 edcr; + union { + u32 value; + struct iop3xx_aau_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + switch (src_cnt) { + case 25 ... 32: + u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ + edcr = 0; + shift = 1; + for (i = 24; i < src_cnt; i++) { + edcr |= (1 << shift); + shift += 3; + } + hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = edcr; + src_cnt = 24; + /* fall through */ + case 17 ... 24: + if (!u_desc_ctrl.field.blk_ctrl) { + hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0; + u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ + } + edcr = 0; + shift = 1; + for (i = 16; i < src_cnt; i++) { + edcr |= (1 << shift); + shift += 3; + } + hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = edcr; + src_cnt = 16; + /* fall through */ + case 9 ... 16: + if (!u_desc_ctrl.field.blk_ctrl) + u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */ + edcr = 0; + shift = 1; + for (i = 8; i < src_cnt; i++) { + edcr |= (1 << shift); + shift += 3; + } + hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = edcr; + src_cnt = 8; + /* fall through */ + case 2 ... 8: + shift = 1; + for (i = 0; i < src_cnt; i++) { + u_desc_ctrl.value |= (1 << shift); + shift += 3; + } + + if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4) + u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */ + } + + u_desc_ctrl.field.dest_write_en = 1; + u_desc_ctrl.field.blk1_cmd_ctrl = 0x7; /* direct fill */ + u_desc_ctrl.field.int_en = int_en; + hw_desc->desc_ctrl = u_desc_ctrl.value; + + return u_desc_ctrl.value; +} + +static inline void +iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) +{ + iop3xx_desc_init_xor(desc->hw_desc, src_cnt, int_en); +} + +/* return the number of operations */ +static inline int +iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) +{ + int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; + struct iop3xx_desc_aau *hw_desc, *prev_hw_desc, *iter; + union { + u32 value; + struct iop3xx_aau_desc_ctrl field; + } u_desc_ctrl; + int i, j; + + hw_desc = desc->hw_desc; + + for (i = 0, j = 0; (slot_cnt -= slots_per_op) >= 0; + i += slots_per_op, j++) { + iter = iop_hw_desc_slot_idx(hw_desc, i); + u_desc_ctrl.value = iop3xx_desc_init_xor(iter, src_cnt, int_en); + u_desc_ctrl.field.dest_write_en = 0; + u_desc_ctrl.field.zero_result_en = 1; + u_desc_ctrl.field.int_en = int_en; + iter->desc_ctrl = u_desc_ctrl.value; + + /* for the subsequent descriptors preserve the store queue + * and chain them together + */ + if (i) { + prev_hw_desc = + iop_hw_desc_slot_idx(hw_desc, i - slots_per_op); + prev_hw_desc->next_desc = + (u32) (desc->async_tx.phys + (i << 5)); + } + } + + return j; +} + +static inline void +iop_desc_init_null_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) +{ + struct iop3xx_desc_aau *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop3xx_aau_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + switch (src_cnt) { + case 25 ... 32: + u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ + hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0; + /* fall through */ + case 17 ... 24: + if (!u_desc_ctrl.field.blk_ctrl) { + hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0; + u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ + } + hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = 0; + /* fall through */ + case 9 ... 16: + if (!u_desc_ctrl.field.blk_ctrl) + u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */ + hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = 0; + /* fall through */ + case 1 ... 8: + if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4) + u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */ + } + + u_desc_ctrl.field.dest_write_en = 0; + u_desc_ctrl.field.int_en = int_en; + hw_desc->desc_ctrl = u_desc_ctrl.value; +} + +static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan, + u32 byte_count) +{ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + hw_desc.dma->byte_count = byte_count; + break; + case AAU_ID: + hw_desc.aau->byte_count = byte_count; + break; + default: + BUG(); + } +} + +static inline void +iop_desc_init_interrupt(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + iop_desc_init_memcpy(desc, 1); + hw_desc.dma->byte_count = 0; + hw_desc.dma->dest_addr = 0; + hw_desc.dma->src_addr = 0; + break; + case AAU_ID: + iop_desc_init_null_xor(desc, 2, 1); + hw_desc.aau->byte_count = 0; + hw_desc.aau->dest_addr = 0; + hw_desc.aau->src[0] = 0; + hw_desc.aau->src[1] = 0; + break; + default: + BUG(); + } +} + +static inline void +iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len) +{ + int slots_per_op = desc->slots_per_op; + struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter; + int i = 0; + + if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { + hw_desc->byte_count = len; + } else { + do { + iter = iop_hw_desc_slot_idx(hw_desc, i); + iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; + len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; + i += slots_per_op; + } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT); + + if (len) { + iter = iop_hw_desc_slot_idx(hw_desc, i); + iter->byte_count = len; + } + } +} + +static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan, + dma_addr_t addr) +{ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + hw_desc.dma->dest_addr = addr; + break; + case AAU_ID: + hw_desc.aau->dest_addr = addr; + break; + default: + BUG(); + } +} + +static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc, + dma_addr_t addr) +{ + struct iop3xx_desc_dma *hw_desc = desc->hw_desc; + hw_desc->src_addr = addr; +} + +static inline void +iop_desc_set_zero_sum_src_addr(struct iop_adma_desc_slot *desc, int src_idx, + dma_addr_t addr) +{ + + struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter; + int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; + int i; + + for (i = 0; (slot_cnt -= slots_per_op) >= 0; + i += slots_per_op, addr += IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { + iter = iop_hw_desc_slot_idx(hw_desc, i); + iop3xx_aau_desc_set_src_addr(iter, src_idx, addr); + } +} + +static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc, + int src_idx, dma_addr_t addr) +{ + + struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter; + int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; + int i; + + for (i = 0; (slot_cnt -= slots_per_op) >= 0; + i += slots_per_op, addr += IOP_ADMA_XOR_MAX_BYTE_COUNT) { + iter = iop_hw_desc_slot_idx(hw_desc, i); + iop3xx_aau_desc_set_src_addr(iter, src_idx, addr); + } +} + +static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc, + u32 next_desc_addr) +{ + /* hw_desc->next_desc is the same location for all channels */ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + BUG_ON(hw_desc.dma->next_desc); + hw_desc.dma->next_desc = next_desc_addr; +} + +static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc) +{ + /* hw_desc->next_desc is the same location for all channels */ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + return hw_desc.dma->next_desc; +} + +static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc) +{ + /* hw_desc->next_desc is the same location for all channels */ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + hw_desc.dma->next_desc = 0; +} + +static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc, + u32 val) +{ + struct iop3xx_desc_aau *hw_desc = desc->hw_desc; + hw_desc->src[0] = val; +} + +static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc) +{ + struct iop3xx_desc_aau *hw_desc = desc->hw_desc; + struct iop3xx_aau_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field; + + BUG_ON(!(desc_ctrl.tx_complete && desc_ctrl.zero_result_en)); + return desc_ctrl.zero_result_err; +} + +static inline void iop_chan_append(struct iop_adma_chan *chan) +{ + u32 dma_chan_ctrl; + /* workaround dropped interrupts on 3xx */ + mod_timer(&chan->cleanup_watchdog, jiffies + msecs_to_jiffies(3)); + + dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); + dma_chan_ctrl |= 0x2; + __raw_writel(dma_chan_ctrl, DMA_CCR(chan)); +} + +static inline void iop_chan_idle(int busy, struct iop_adma_chan *chan) +{ + if (!busy) + del_timer(&chan->cleanup_watchdog); +} + +static inline u32 iop_chan_get_status(struct iop_adma_chan *chan) +{ + return __raw_readl(DMA_CSR(chan)); +} + +static inline void iop_chan_disable(struct iop_adma_chan *chan) +{ + u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); + dma_chan_ctrl &= ~1; + __raw_writel(dma_chan_ctrl, DMA_CCR(chan)); +} + +static inline void iop_chan_enable(struct iop_adma_chan *chan) +{ + u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); + + dma_chan_ctrl |= 1; + __raw_writel(dma_chan_ctrl, DMA_CCR(chan)); +} + +static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan) +{ + u32 status = __raw_readl(DMA_CSR(chan)); + status &= (1 << 9); + __raw_writel(status, DMA_CSR(chan)); +} + +static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan) +{ + u32 status = __raw_readl(DMA_CSR(chan)); + status &= (1 << 8); + __raw_writel(status, DMA_CSR(chan)); +} + +static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan) +{ + u32 status = __raw_readl(DMA_CSR(chan)); + + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + status &= (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1); + break; + case AAU_ID: + status &= (1 << 5); + break; + default: + BUG(); + } + + __raw_writel(status, DMA_CSR(chan)); +} + +static inline int +iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan) +{ + return 0; +} + +static inline int +iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan) +{ + return 0; +} + +static inline int +iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan) +{ + return 0; +} + +static inline int +iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan) +{ + return test_bit(5, &status); +} + +static inline int +iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan) +{ + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + return test_bit(2, &status); + default: + return 0; + } +} + +static inline int +iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan) +{ + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + return test_bit(3, &status); + default: + return 0; + } +} + +static inline int +iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan) +{ + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + return test_bit(1, &status); + default: + return 0; + } +} +#endif /* _ADMA_H */ diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h index 63feceb7ede5..81ca5d3e2bff 100644 --- a/include/asm-arm/hardware/iop3xx.h +++ b/include/asm-arm/hardware/iop3xx.h @@ -144,24 +144,9 @@ extern int init_atu; #define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380) /* DMA Controller */ -#define IOP3XX_DMA0_CCR (volatile u32 *)IOP3XX_REG_ADDR(0x0400) -#define IOP3XX_DMA0_CSR (volatile u32 *)IOP3XX_REG_ADDR(0x0404) -#define IOP3XX_DMA0_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x040c) -#define IOP3XX_DMA0_NDAR (volatile u32 *)IOP3XX_REG_ADDR(0x0410) -#define IOP3XX_DMA0_PADR (volatile u32 *)IOP3XX_REG_ADDR(0x0414) -#define IOP3XX_DMA0_PUADR (volatile u32 *)IOP3XX_REG_ADDR(0x0418) -#define IOP3XX_DMA0_LADR (volatile u32 *)IOP3XX_REG_ADDR(0x041c) -#define IOP3XX_DMA0_BCR (volatile u32 *)IOP3XX_REG_ADDR(0x0420) -#define IOP3XX_DMA0_DCR (volatile u32 *)IOP3XX_REG_ADDR(0x0424) -#define IOP3XX_DMA1_CCR (volatile u32 *)IOP3XX_REG_ADDR(0x0440) -#define IOP3XX_DMA1_CSR (volatile u32 *)IOP3XX_REG_ADDR(0x0444) -#define IOP3XX_DMA1_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x044c) -#define IOP3XX_DMA1_NDAR (volatile u32 *)IOP3XX_REG_ADDR(0x0450) -#define IOP3XX_DMA1_PADR (volatile u32 *)IOP3XX_REG_ADDR(0x0454) -#define IOP3XX_DMA1_PUADR (volatile u32 *)IOP3XX_REG_ADDR(0x0458) -#define IOP3XX_DMA1_LADR (volatile u32 *)IOP3XX_REG_ADDR(0x045c) -#define IOP3XX_DMA1_BCR (volatile u32 *)IOP3XX_REG_ADDR(0x0460) -#define IOP3XX_DMA1_DCR (volatile u32 *)IOP3XX_REG_ADDR(0x0464) +#define IOP3XX_DMA_PHYS_BASE(chan) (IOP3XX_PERIPHERAL_PHYS_BASE + \ + (0x400 + (chan << 6))) +#define IOP3XX_DMA_UPPER_PA(chan) (IOP3XX_DMA_PHYS_BASE(chan) + 0x27) /* Peripheral bus interface */ #define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680) @@ -210,48 +195,8 @@ extern int init_atu; #define IOP_TMR_RATIO_1_1 0x00 /* Application accelerator unit */ -#define IOP3XX_AAU_ACR (volatile u32 *)IOP3XX_REG_ADDR(0x0800) -#define IOP3XX_AAU_ASR (volatile u32 *)IOP3XX_REG_ADDR(0x0804) -#define IOP3XX_AAU_ADAR (volatile u32 *)IOP3XX_REG_ADDR(0x0808) -#define IOP3XX_AAU_ANDAR (volatile u32 *)IOP3XX_REG_ADDR(0x080c) -#define IOP3XX_AAU_SAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0810) -#define IOP3XX_AAU_SAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0814) -#define IOP3XX_AAU_SAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0818) -#define IOP3XX_AAU_SAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x081c) -#define IOP3XX_AAU_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x0820) -#define IOP3XX_AAU_ABCR (volatile u32 *)IOP3XX_REG_ADDR(0x0824) -#define IOP3XX_AAU_ADCR (volatile u32 *)IOP3XX_REG_ADDR(0x0828) -#define IOP3XX_AAU_SAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x082c) -#define IOP3XX_AAU_SAR6 (volatile u32 *)IOP3XX_REG_ADDR(0x0830) -#define IOP3XX_AAU_SAR7 (volatile u32 *)IOP3XX_REG_ADDR(0x0834) -#define IOP3XX_AAU_SAR8 (volatile u32 *)IOP3XX_REG_ADDR(0x0838) -#define IOP3XX_AAU_EDCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x083c) -#define IOP3XX_AAU_SAR9 (volatile u32 *)IOP3XX_REG_ADDR(0x0840) -#define IOP3XX_AAU_SAR10 (volatile u32 *)IOP3XX_REG_ADDR(0x0844) -#define IOP3XX_AAU_SAR11 (volatile u32 *)IOP3XX_REG_ADDR(0x0848) -#define IOP3XX_AAU_SAR12 (volatile u32 *)IOP3XX_REG_ADDR(0x084c) -#define IOP3XX_AAU_SAR13 (volatile u32 *)IOP3XX_REG_ADDR(0x0850) -#define IOP3XX_AAU_SAR14 (volatile u32 *)IOP3XX_REG_ADDR(0x0854) -#define IOP3XX_AAU_SAR15 (volatile u32 *)IOP3XX_REG_ADDR(0x0858) -#define IOP3XX_AAU_SAR16 (volatile u32 *)IOP3XX_REG_ADDR(0x085c) -#define IOP3XX_AAU_EDCR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0860) -#define IOP3XX_AAU_SAR17 (volatile u32 *)IOP3XX_REG_ADDR(0x0864) -#define IOP3XX_AAU_SAR18 (volatile u32 *)IOP3XX_REG_ADDR(0x0868) -#define IOP3XX_AAU_SAR19 (volatile u32 *)IOP3XX_REG_ADDR(0x086c) -#define IOP3XX_AAU_SAR20 (volatile u32 *)IOP3XX_REG_ADDR(0x0870) -#define IOP3XX_AAU_SAR21 (volatile u32 *)IOP3XX_REG_ADDR(0x0874) -#define IOP3XX_AAU_SAR22 (volatile u32 *)IOP3XX_REG_ADDR(0x0878) -#define IOP3XX_AAU_SAR23 (volatile u32 *)IOP3XX_REG_ADDR(0x087c) -#define IOP3XX_AAU_SAR24 (volatile u32 *)IOP3XX_REG_ADDR(0x0880) -#define IOP3XX_AAU_EDCR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0884) -#define IOP3XX_AAU_SAR25 (volatile u32 *)IOP3XX_REG_ADDR(0x0888) -#define IOP3XX_AAU_SAR26 (volatile u32 *)IOP3XX_REG_ADDR(0x088c) -#define IOP3XX_AAU_SAR27 (volatile u32 *)IOP3XX_REG_ADDR(0x0890) -#define IOP3XX_AAU_SAR28 (volatile u32 *)IOP3XX_REG_ADDR(0x0894) -#define IOP3XX_AAU_SAR29 (volatile u32 *)IOP3XX_REG_ADDR(0x0898) -#define IOP3XX_AAU_SAR30 (volatile u32 *)IOP3XX_REG_ADDR(0x089c) -#define IOP3XX_AAU_SAR31 (volatile u32 *)IOP3XX_REG_ADDR(0x08a0) -#define IOP3XX_AAU_SAR32 (volatile u32 *)IOP3XX_REG_ADDR(0x08a4) +#define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800) +#define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7) /* I2C bus interface unit */ #define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680) @@ -329,6 +274,9 @@ static inline void write_tisr(u32 val) asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val)); } +extern struct platform_device iop3xx_dma_0_channel; +extern struct platform_device iop3xx_dma_1_channel; +extern struct platform_device iop3xx_aau_channel; extern struct platform_device iop3xx_i2c0_device; extern struct platform_device iop3xx_i2c1_device; diff --git a/include/asm-arm/hardware/iop_adma.h b/include/asm-arm/hardware/iop_adma.h new file mode 100644 index 000000000000..ca8e71f44346 --- /dev/null +++ b/include/asm-arm/hardware/iop_adma.h @@ -0,0 +1,118 @@ +/* + * Copyright © 2006, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ +#ifndef IOP_ADMA_H +#define IOP_ADMA_H +#include <linux/types.h> +#include <linux/dmaengine.h> +#include <linux/interrupt.h> + +#define IOP_ADMA_SLOT_SIZE 32 +#define IOP_ADMA_THRESHOLD 4 + +/** + * struct iop_adma_device - internal representation of an ADMA device + * @pdev: Platform device + * @id: HW ADMA Device selector + * @dma_desc_pool: base of DMA descriptor region (DMA address) + * @dma_desc_pool_virt: base of DMA descriptor region (CPU address) + * @common: embedded struct dma_device + */ +struct iop_adma_device { + struct platform_device *pdev; + int id; + dma_addr_t dma_desc_pool; + void *dma_desc_pool_virt; + struct dma_device common; +}; + +/** + * struct iop_adma_chan - internal representation of an ADMA device + * @pending: allows batching of hardware operations + * @completed_cookie: identifier for the most recently completed operation + * @lock: serializes enqueue/dequeue operations to the slot pool + * @mmr_base: memory mapped register base + * @chain: device chain view of the descriptors + * @device: parent device + * @common: common dmaengine channel object members + * @last_used: place holder for allocation to continue from where it left off + * @all_slots: complete domain of slots usable by the channel + * @cleanup_watchdog: workaround missed interrupts on iop3xx + * @slots_allocated: records the actual size of the descriptor slot pool + * @irq_tasklet: bottom half where iop_adma_slot_cleanup runs + */ +struct iop_adma_chan { + int pending; + dma_cookie_t completed_cookie; + spinlock_t lock; /* protects the descriptor slot pool */ + void __iomem *mmr_base; + struct list_head chain; + struct iop_adma_device *device; + struct dma_chan common; + struct iop_adma_desc_slot *last_used; + struct list_head all_slots; + struct timer_list cleanup_watchdog; + int slots_allocated; + struct tasklet_struct irq_tasklet; +}; + +/** + * struct iop_adma_desc_slot - IOP-ADMA software descriptor + * @slot_node: node on the iop_adma_chan.all_slots list + * @chain_node: node on the op_adma_chan.chain list + * @hw_desc: virtual address of the hardware descriptor chain + * @phys: hardware address of the hardware descriptor chain + * @group_head: first operation in a transaction + * @slot_cnt: total slots used in an transaction (group of operations) + * @slots_per_op: number of slots per operation + * @idx: pool index + * @unmap_src_cnt: number of xor sources + * @unmap_len: transaction bytecount + * @async_tx: support for the async_tx api + * @group_list: list of slots that make up a multi-descriptor transaction + * for example transfer lengths larger than the supported hw max + * @xor_check_result: result of zero sum + * @crc32_result: result crc calculation + */ +struct iop_adma_desc_slot { + struct list_head slot_node; + struct list_head chain_node; + void *hw_desc; + struct iop_adma_desc_slot *group_head; + u16 slot_cnt; + u16 slots_per_op; + u16 idx; + u16 unmap_src_cnt; + size_t unmap_len; + struct dma_async_tx_descriptor async_tx; + union { + u32 *xor_check_result; + u32 *crc32_result; + }; +}; + +struct iop_adma_platform_data { + int hw_id; + dma_cap_mask_t cap_mask; + size_t pool_size; +}; + +#define to_iop_sw_desc(addr_hw_desc) \ + container_of(addr_hw_desc, struct iop_adma_desc_slot, hw_desc) +#define iop_hw_desc_slot_idx(hw_desc, idx) \ + ( (void *) (((unsigned long) hw_desc) + ((idx) << 5)) ) +#endif diff --git a/include/asm-arm/hwcap.h b/include/asm-arm/hwcap.h new file mode 100644 index 000000000000..01a1391d3014 --- /dev/null +++ b/include/asm-arm/hwcap.h @@ -0,0 +1,28 @@ +#ifndef __ASMARM_HWCAP_H +#define __ASMARM_HWCAP_H + +/* + * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP + */ +#define HWCAP_SWP 1 +#define HWCAP_HALF 2 +#define HWCAP_THUMB 4 +#define HWCAP_26BIT 8 /* Play it safe */ +#define HWCAP_FAST_MULT 16 +#define HWCAP_FPA 32 +#define HWCAP_VFP 64 +#define HWCAP_EDSP 128 +#define HWCAP_JAVA 256 +#define HWCAP_IWMMXT 512 +#define HWCAP_CRUNCH 1024 + +#if defined(__KERNEL__) && !defined(__ASSEMBLY__) +/* + * This yields a mask that user programs can use to figure out what + * instruction set this cpu supports. + */ +#define ELF_HWCAP (elf_hwcap) +extern unsigned int elf_hwcap; +#endif + +#endif diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h index f21abd4ddac6..ed3f898191f4 100644 --- a/include/asm-arm/pci.h +++ b/include/asm-arm/pci.h @@ -26,11 +26,6 @@ static inline void pcibios_penalize_isa_irq(int irq, int active) #define PCI_DMA_BUS_IS_PHYS (0) /* - * We don't support DAC DMA cycles. - */ -#define pci_dac_dma_supported(pci_dev, mask) (0) - -/* * Whether pci_unmap_{single,page} is a nop depends upon the * configuration. */ @@ -76,10 +71,6 @@ pcibios_select_root(struct pci_dev *pdev, struct resource *res) return root; } -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #endif /* __KERNEL__ */ #endif diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h index 21dec9f258d8..cb4c2c9d000a 100644 --- a/include/asm-arm/pgtable.h +++ b/include/asm-arm/pgtable.h @@ -257,9 +257,7 @@ extern struct page *empty_zero_page; * Undefined behaviour if not.. */ #define pte_present(pte) (pte_val(pte) & L_PTE_PRESENT) -#define pte_read(pte) (pte_val(pte) & L_PTE_USER) #define pte_write(pte) (pte_val(pte) & L_PTE_WRITE) -#define pte_exec(pte) (pte_val(pte) & L_PTE_EXEC) #define pte_dirty(pte) (pte_val(pte) & L_PTE_DIRTY) #define pte_young(pte) (pte_val(pte) & L_PTE_YOUNG) @@ -275,12 +273,8 @@ extern struct page *empty_zero_page; #define PTE_BIT_FUNC(fn,op) \ static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; } -/*PTE_BIT_FUNC(rdprotect, &= ~L_PTE_USER);*/ -/*PTE_BIT_FUNC(mkread, |= L_PTE_USER);*/ PTE_BIT_FUNC(wrprotect, &= ~L_PTE_WRITE); PTE_BIT_FUNC(mkwrite, |= L_PTE_WRITE); -PTE_BIT_FUNC(exprotect, &= ~L_PTE_EXEC); -PTE_BIT_FUNC(mkexec, |= L_PTE_EXEC); PTE_BIT_FUNC(mkclean, &= ~L_PTE_DIRTY); PTE_BIT_FUNC(mkdirty, |= L_PTE_DIRTY); PTE_BIT_FUNC(mkold, &= ~L_PTE_YOUNG); diff --git a/include/asm-arm/ptrace.h b/include/asm-arm/ptrace.h index ee3d93c281d8..7aaa206cb54e 100644 --- a/include/asm-arm/ptrace.h +++ b/include/asm-arm/ptrace.h @@ -10,6 +10,8 @@ #ifndef __ASM_ARM_PTRACE_H #define __ASM_ARM_PTRACE_H +#include <asm/hwcap.h> + #define PTRACE_GETREGS 12 #define PTRACE_SETREGS 13 #define PTRACE_GETFPREGS 14 @@ -45,6 +47,7 @@ #define PSR_T_BIT 0x00000020 #define PSR_F_BIT 0x00000040 #define PSR_I_BIT 0x00000080 +#define PSR_A_BIT 0x00000100 #define PSR_J_BIT 0x01000000 #define PSR_Q_BIT 0x08000000 #define PSR_V_BIT 0x10000000 @@ -103,6 +106,10 @@ struct pt_regs { #define thumb_mode(regs) (0) #endif +#define isa_mode(regs) \ + ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \ + (((regs)->ARM_cpsr & PSR_T_BIT) >> 5)) + #define processor_mode(regs) \ ((regs)->ARM_cpsr & MODE_MASK) @@ -117,14 +124,17 @@ struct pt_regs { */ static inline int valid_user_regs(struct pt_regs *regs) { - if (user_mode(regs) && - (regs->ARM_cpsr & (PSR_F_BIT|PSR_I_BIT)) == 0) + if (user_mode(regs) && (regs->ARM_cpsr & PSR_I_BIT) == 0) { + regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT); return 1; + } /* * Force CPSR to something logical... */ - regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT; + regs->ARM_cpsr &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | PSR_T_BIT | MODE32_BIT; + if (!(elf_hwcap & HWCAP_26BIT)) + regs->ARM_cpsr |= USR_MODE; return 0; } diff --git a/include/asm-arm26/dma-mapping.h b/include/asm-arm26/dma-mapping.h deleted file mode 100644 index a95eae0aeb77..000000000000 --- a/include/asm-arm26/dma-mapping.h +++ /dev/null @@ -1,2 +0,0 @@ -#include <asm-generic/dma-mapping-broken.h> - diff --git a/include/asm-arm26/ioctls.h b/include/asm-arm26/ioctls.h index ba9c7d81d24e..8a3296200be1 100644 --- a/include/asm-arm26/ioctls.h +++ b/include/asm-arm26/ioctls.h @@ -47,6 +47,10 @@ #define TIOCSBRK 0x5427 /* BSD compatibility */ #define TIOCCBRK 0x5428 /* BSD compatibility */ #define TIOCGSID 0x5429 /* Return the session ID of FD */ +#define TCGETS2 _IOR('T',0x2A, struct termios2) +#define TCSETS2 _IOW('T',0x2B, struct termios2) +#define TCSETSW2 _IOW('T',0x2C, struct termios2) +#define TCSETSF2 _IOW('T',0x2D, struct termios2) #define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ diff --git a/include/asm-arm26/pgtable.h b/include/asm-arm26/pgtable.h index 2b20e9f08857..55a1a697d12b 100644 --- a/include/asm-arm26/pgtable.h +++ b/include/asm-arm26/pgtable.h @@ -218,9 +218,7 @@ extern struct page *empty_zero_page; * The following only work if pte_present() is true. * Undefined behaviour if not.. */ -#define pte_read(pte) (!(pte_val(pte) & _PAGE_NOT_USER)) #define pte_write(pte) (!(pte_val(pte) & _PAGE_READONLY)) -#define pte_exec(pte) (!(pte_val(pte) & _PAGE_NOT_USER)) #define pte_dirty(pte) (!(pte_val(pte) & _PAGE_CLEAN)) #define pte_young(pte) (!(pte_val(pte) & _PAGE_OLD)) //ONLY when !pte_present() I think. nicked from arm32 (FIXME!) @@ -231,8 +229,6 @@ static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; } PTE_BIT_FUNC(wrprotect, |= _PAGE_READONLY); PTE_BIT_FUNC(mkwrite, &= ~_PAGE_READONLY); -PTE_BIT_FUNC(exprotect, |= _PAGE_NOT_USER); -PTE_BIT_FUNC(mkexec, &= ~_PAGE_NOT_USER); PTE_BIT_FUNC(mkclean, |= _PAGE_CLEAN); PTE_BIT_FUNC(mkdirty, &= ~_PAGE_CLEAN); PTE_BIT_FUNC(mkold, |= _PAGE_OLD); diff --git a/include/asm-arm26/termbits.h b/include/asm-arm26/termbits.h index a3f4fe1742d0..48d2f5c7bcb8 100644 --- a/include/asm-arm26/termbits.h +++ b/include/asm-arm26/termbits.h @@ -15,7 +15,7 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; -struct ktermios { +struct termios2 { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ tcflag_t c_cflag; /* control mode flags */ @@ -26,6 +26,16 @@ struct ktermios { speed_t c_ospeed; /* output speed */ }; +struct ktermios { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; /* c_cc characters */ #define VINTR 0 @@ -128,6 +138,7 @@ struct ktermios { #define HUPCL 0002000 #define CLOCAL 0004000 #define CBAUDEX 0010000 +#define BOTHER 0010000 #define B57600 0010001 #define B115200 0010002 #define B230400 0010003 @@ -143,10 +154,12 @@ struct ktermios { #define B3000000 0010015 #define B3500000 0010016 #define B4000000 0010017 -#define CIBAUD 002003600000 /* input baud rate (not used) */ +#define CIBAUD 002003600000 /* input baud rate */ #define CMSPAR 010000000000 /* mark or space (stick) parity */ #define CRTSCTS 020000000000 /* flow control */ +#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ + /* c_lflag bits */ #define ISIG 0000001 #define ICANON 0000002 diff --git a/include/asm-arm26/termios.h b/include/asm-arm26/termios.h index 329c324c4040..293e3f1bc3f2 100644 --- a/include/asm-arm26/termios.h +++ b/include/asm-arm26/termios.h @@ -82,8 +82,10 @@ struct termio { copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ }) -#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) -#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) +#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) +#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) +#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) +#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) #endif /* __KERNEL__ */ diff --git a/include/asm-avr32/pgtable.h b/include/asm-avr32/pgtable.h index f6cc2b0f75c3..c07bdd10b891 100644 --- a/include/asm-avr32/pgtable.h +++ b/include/asm-avr32/pgtable.h @@ -201,18 +201,10 @@ extern struct page *empty_zero_page; * The following only work if pte_present() is true. * Undefined behaviour if not.. */ -static inline int pte_read(pte_t pte) -{ - return pte_val(pte) & _PAGE_USER; -} static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; } -static inline int pte_exec(pte_t pte) -{ - return pte_val(pte) & _PAGE_EXECUTE; -} static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; @@ -231,21 +223,11 @@ static inline int pte_file(pte_t pte) } /* Mutator functions for PTE bits */ -static inline pte_t pte_rdprotect(pte_t pte) -{ - set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); - return pte; -} static inline pte_t pte_wrprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_RW)); return pte; } -static inline pte_t pte_exprotect(pte_t pte) -{ - set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_EXECUTE)); - return pte; -} static inline pte_t pte_mkclean(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_DIRTY)); @@ -256,21 +238,11 @@ static inline pte_t pte_mkold(pte_t pte) set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_ACCESSED)); return pte; } -static inline pte_t pte_mkread(pte_t pte) -{ - set_pte(&pte, __pte(pte_val(pte) | _PAGE_USER)); - return pte; -} static inline pte_t pte_mkwrite(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_RW)); return pte; } -static inline pte_t pte_mkexec(pte_t pte) -{ - set_pte(&pte, __pte(pte_val(pte) | _PAGE_EXECUTE)); - return pte; -} static inline pte_t pte_mkdirty(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); diff --git a/include/asm-avr32/termbits.h b/include/asm-avr32/termbits.h index c215fafdae4d..db2daab31fdb 100644 --- a/include/asm-avr32/termbits.h +++ b/include/asm-avr32/termbits.h @@ -17,6 +17,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-blackfin/Kbuild b/include/asm-blackfin/Kbuild index c68e1680da01..71f8fe783258 100644 --- a/include/asm-blackfin/Kbuild +++ b/include/asm-blackfin/Kbuild @@ -1 +1,3 @@ include include/asm-generic/Kbuild.asm + +header-y += fixed_code.h diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h index 57f37ccdcdf1..c4d6cbbf96d4 100644 --- a/include/asm-blackfin/bfin-global.h +++ b/include/asm-blackfin/bfin-global.h @@ -67,6 +67,18 @@ extern void evt14_softirq(void); extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs); extern void bfin_gpio_interrupt_setup(int irq, int irq_pfx, int type); +extern asmlinkage void finish_atomic_sections (struct pt_regs *regs); +extern char fixed_code_start; +extern char fixed_code_end; +extern int atomic_xchg32(void); +extern int atomic_cas32(void); +extern int atomic_add32(void); +extern int atomic_sub32(void); +extern int atomic_ior32(void); +extern int atomic_and32(void); +extern int atomic_xor32(void); +extern void sigreturn_stub(void); + extern void *l1_data_A_sram_alloc(size_t); extern void *l1_data_B_sram_alloc(size_t); extern void *l1_inst_sram_alloc(size_t); diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h index 3bad2d1e6a8c..bec6ecdf1bdb 100644 --- a/include/asm-blackfin/cplbinit.h +++ b/include/asm-blackfin/cplbinit.h @@ -57,8 +57,8 @@ struct cplb_tab { u16 size; }; -u_long icplb_table[MAX_CPLBS+1]; -u_long dcplb_table[MAX_CPLBS+1]; +extern u_long icplb_table[MAX_CPLBS+1]; +extern u_long dcplb_table[MAX_CPLBS+1]; /* Till here we are discussing about the static memory management model. * However, the operating envoronments commonly define more CPLB @@ -70,134 +70,27 @@ u_long dcplb_table[MAX_CPLBS+1]; */ #ifdef CONFIG_CPLB_SWITCH_TAB_L1 -u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data)); -u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data)); +extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data)); +extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data)); #ifdef CONFIG_CPLB_INFO -u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data)); -u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data)); +extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data)); +extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data)); #endif /* CONFIG_CPLB_INFO */ #else -u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]; -u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]; +extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]; +extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]; #ifdef CONFIG_CPLB_INFO -u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]; -u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]; +extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]; +extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]; #endif /* CONFIG_CPLB_INFO */ #endif /*CONFIG_CPLB_SWITCH_TAB_L1*/ -struct s_cplb { - struct cplb_tab init_i; - struct cplb_tab init_d; - struct cplb_tab switch_i; - struct cplb_tab switch_d; -}; +extern unsigned long reserved_mem_dcache_on; +extern unsigned long reserved_mem_icache_on; -#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE) -static struct cplb_desc cplb_data[] = { - { - .start = 0, - .end = SIZE_4K, - .psize = SIZE_4K, - .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, - .i_conf = SDRAM_OOPS, - .d_conf = SDRAM_OOPS, -#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO) - .valid = 1, -#else - .valid = 0, -#endif - .name = "ZERO Pointer Saveguard", - }, - { - .start = L1_CODE_START, - .end = L1_CODE_START + L1_CODE_LENGTH, - .psize = SIZE_4M, - .attr = INITIAL_T | SWITCH_T | I_CPLB, - .i_conf = L1_IMEMORY, - .d_conf = 0, - .valid = 1, - .name = "L1 I-Memory", - }, - { - .start = L1_DATA_A_START, - .end = L1_DATA_B_START + L1_DATA_B_LENGTH, - .psize = SIZE_4M, - .attr = INITIAL_T | SWITCH_T | D_CPLB, - .i_conf = 0, - .d_conf = L1_DMEMORY, -#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0)) - .valid = 1, -#else - .valid = 0, -#endif - .name = "L1 D-Memory", - }, - { - .start = 0, - .end = 0, /* dynamic */ - .psize = 0, - .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, - .i_conf = SDRAM_IGENERIC, - .d_conf = SDRAM_DGENERIC, - .valid = 1, - .name = "SDRAM Kernel", - }, - { - .start = 0, /* dynamic */ - .end = 0, /* dynamic */ - .psize = 0, - .attr = INITIAL_T | SWITCH_T | D_CPLB, - .i_conf = SDRAM_IGENERIC, - .d_conf = SDRAM_DNON_CHBL, - .valid = 1, - .name = "SDRAM RAM MTD", - }, - { - .start = 0, /* dynamic */ - .end = 0, /* dynamic */ - .psize = SIZE_1M, - .attr = INITIAL_T | SWITCH_T | D_CPLB, - .d_conf = SDRAM_DNON_CHBL, - .valid = 1,//(DMA_UNCACHED_REGION > 0), - .name = "SDRAM Uncached DMA ZONE", - }, - { - .start = 0, /* dynamic */ - .end = 0, /* dynamic */ - .psize = 0, - .attr = SWITCH_T | D_CPLB, - .i_conf = 0, /* dynamic */ - .d_conf = 0, /* dynamic */ - .valid = 1, - .name = "SDRAM Reserved Memory", - }, - { - .start = ASYNC_BANK0_BASE, - .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE, - .psize = 0, - .attr = SWITCH_T | D_CPLB, - .d_conf = SDRAM_EBIU, - .valid = 1, - .name = "ASYNC Memory", - }, - { -#if defined(CONFIG_BF561) - .start = L2_SRAM, - .end = L2_SRAM_END, - .psize = SIZE_1M, - .attr = SWITCH_T | D_CPLB, - .i_conf = L2_MEMORY, - .d_conf = L2_MEMORY, - .valid = 1, -#else - .valid = 0, -#endif - .name = "L2 Memory", - } -}; -#endif +extern void generate_cpl_tables(void); diff --git a/include/asm-blackfin/fixed_code.h b/include/asm-blackfin/fixed_code.h new file mode 100644 index 000000000000..e6df84ee1557 --- /dev/null +++ b/include/asm-blackfin/fixed_code.h @@ -0,0 +1,20 @@ +/* This file defines the fixed addresses where userspace programs can find + atomic code sequences. */ + +#define FIXED_CODE_START 0x400 + +#define SIGRETURN_STUB 0x400 + +#define ATOMIC_SEQS_START 0x410 + +#define ATOMIC_XCHG32 0x410 +#define ATOMIC_CAS32 0x420 +#define ATOMIC_ADD32 0x430 +#define ATOMIC_SUB32 0x440 +#define ATOMIC_IOR32 0x450 +#define ATOMIC_AND32 0x460 +#define ATOMIC_XOR32 0x470 + +#define ATOMIC_SEQS_END 0x480 + +#define FIXED_CODE_END 0x480 diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h index d98d77ad71f7..7480cfa7e2d6 100644 --- a/include/asm-blackfin/gpio.h +++ b/include/asm-blackfin/gpio.h @@ -204,8 +204,62 @@ #endif +#ifdef BF548_FAMILY +#include <asm-blackfin/mach-bf548/gpio.h> +#endif + #ifdef BF561_FAMILY #define MAX_BLACKFIN_GPIOS 48 + +#define GPIO_PF0 0 +#define GPIO_PF1 1 +#define GPIO_PF2 2 +#define GPIO_PF3 3 +#define GPIO_PF4 4 +#define GPIO_PF5 5 +#define GPIO_PF6 6 +#define GPIO_PF7 7 +#define GPIO_PF8 8 +#define GPIO_PF9 9 +#define GPIO_PF10 10 +#define GPIO_PF11 11 +#define GPIO_PF12 12 +#define GPIO_PF13 13 +#define GPIO_PF14 14 +#define GPIO_PF15 15 +#define GPIO_PF16 16 +#define GPIO_PF17 17 +#define GPIO_PF18 18 +#define GPIO_PF19 19 +#define GPIO_PF20 20 +#define GPIO_PF21 21 +#define GPIO_PF22 22 +#define GPIO_PF23 23 +#define GPIO_PF24 24 +#define GPIO_PF25 25 +#define GPIO_PF26 26 +#define GPIO_PF27 27 +#define GPIO_PF28 28 +#define GPIO_PF29 29 +#define GPIO_PF30 30 +#define GPIO_PF31 31 +#define GPIO_PF32 32 +#define GPIO_PF33 33 +#define GPIO_PF34 34 +#define GPIO_PF35 35 +#define GPIO_PF36 36 +#define GPIO_PF37 37 +#define GPIO_PF38 38 +#define GPIO_PF39 39 +#define GPIO_PF40 40 +#define GPIO_PF41 41 +#define GPIO_PF42 42 +#define GPIO_PF43 43 +#define GPIO_PF44 44 +#define GPIO_PF45 45 +#define GPIO_PF46 46 +#define GPIO_PF47 47 + #define PORT_FIO0 GPIO_0 #define PORT_FIO1 GPIO_16 #define PORT_FIO2 GPIO_32 @@ -230,6 +284,7 @@ * MODIFICATION HISTORY : **************************************************************/ +#ifndef BF548_FAMILY void set_gpio_dir(unsigned short, unsigned short); void set_gpio_inen(unsigned short, unsigned short); void set_gpio_polar(unsigned short, unsigned short); @@ -299,6 +354,7 @@ struct gpio_port_t { unsigned short dummy16; unsigned short inen; }; +#endif #ifdef CONFIG_PM #define PM_WAKE_RISING 0x1 @@ -357,8 +413,10 @@ void gpio_free(unsigned short); void gpio_set_value(unsigned short gpio, unsigned short arg); unsigned short gpio_get_value(unsigned short gpio); +#ifndef BF548_FAMILY #define gpio_get_value(gpio) get_gpio_data(gpio) #define gpio_set_value(gpio, value) set_gpio_data(gpio, value) +#endif void gpio_direction_input(unsigned short gpio); void gpio_direction_output(unsigned short gpio); diff --git a/include/asm-blackfin/hardirq.h b/include/asm-blackfin/hardirq.h index 0cab0d35badc..b6b19f1b9dab 100644 --- a/include/asm-blackfin/hardirq.h +++ b/include/asm-blackfin/hardirq.h @@ -28,7 +28,11 @@ typedef struct { * SOFTIRQ_MASK: 0x00ff0000 */ +#if NR_IRQS > 256 +#define HARDIRQ_BITS 9 +#else #define HARDIRQ_BITS 8 +#endif #ifdef NR_IRQS # if (1 << HARDIRQ_BITS) < NR_IRQS diff --git a/include/asm-blackfin/kgdb.h b/include/asm-blackfin/kgdb.h new file mode 100644 index 000000000000..532bd9052004 --- /dev/null +++ b/include/asm-blackfin/kgdb.h @@ -0,0 +1,183 @@ +/* + * File: include/asm-blackfin/kgdb.h + * Based on: + * Author: Sonic Zhang + * + * Created: + * Description: + * + * Rev: $Id: kgdb_bfin_linux-2.6.x.patch 4934 2007-02-13 09:32:11Z sonicz $ + * + * Modified: + * Copyright 2005-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ASM_BLACKFIN_KGDB_H__ +#define __ASM_BLACKFIN_KGDB_H__ + +#include <linux/ptrace.h> + +/* gdb locks */ +#define KGDB_MAX_NO_CPUS 8 + +/************************************************************************/ +/* BUFMAX defines the maximum number of characters in inbound/outbound buffers*/ +/* at least NUMREGBYTES*2 are needed for register packets */ +/* Longer buffer is needed to list all threads */ +#define BUFMAX 2048 + +/* + * Note that this register image is different from + * the register image that Linux produces at interrupt time. + * + * Linux's register image is defined by struct pt_regs in ptrace.h. + */ +enum regnames { + /* Core Registers */ + BFIN_R0 = 0, + BFIN_R1, + BFIN_R2, + BFIN_R3, + BFIN_R4, + BFIN_R5, + BFIN_R6, + BFIN_R7, + BFIN_P0, + BFIN_P1, + BFIN_P2, + BFIN_P3, + BFIN_P4, + BFIN_P5, + BFIN_SP, + BFIN_FP, + BFIN_I0, + BFIN_I1, + BFIN_I2, + BFIN_I3, + BFIN_M0, + BFIN_M1, + BFIN_M2, + BFIN_M3, + BFIN_B0, + BFIN_B1, + BFIN_B2, + BFIN_B3, + BFIN_L0, + BFIN_L1, + BFIN_L2, + BFIN_L3, + BFIN_A0_DOT_X, + BFIN_A0_DOT_W, + BFIN_A1_DOT_X, + BFIN_A1_DOT_W, + BFIN_ASTAT, + BFIN_RETS, + BFIN_LC0, + BFIN_LT0, + BFIN_LB0, + BFIN_LC1, + BFIN_LT1, + BFIN_LB1, + BFIN_CYCLES, + BFIN_CYCLES2, + BFIN_USP, + BFIN_SEQSTAT, + BFIN_SYSCFG, + BFIN_RETI, + BFIN_RETX, + BFIN_RETN, + BFIN_RETE, + + /* Pseudo Registers */ + BFIN_PC, + BFIN_CC, + BFIN_EXTRA1, /* Address of .text section. */ + BFIN_EXTRA2, /* Address of .data section. */ + BFIN_EXTRA3, /* Address of .bss section. */ + BFIN_FDPIC_EXEC, + BFIN_FDPIC_INTERP, + + /* MMRs */ + BFIN_IPEND, + + /* LAST ENTRY SHOULD NOT BE CHANGED. */ + BFIN_NUM_REGS /* The number of all registers. */ +}; + +/* Number of bytes of registers. */ +#define NUMREGBYTES BFIN_NUM_REGS*4 + +#define BREAKPOINT() asm(" EXCPT 2;"); +#define BREAK_INSTR_SIZE 2 +#define HW_BREAKPOINT_NUM 6 + +/* Instruction watchpoint address control register bits mask */ +#define WPPWR 0x1 +#define WPIREN01 0x2 +#define WPIRINV01 0x4 +#define WPIAEN0 0x8 +#define WPIAEN1 0x10 +#define WPICNTEN0 0x20 +#define WPICNTEN1 0x40 +#define EMUSW0 0x80 +#define EMUSW1 0x100 +#define WPIREN23 0x200 +#define WPIRINV23 0x400 +#define WPIAEN2 0x800 +#define WPIAEN3 0x1000 +#define WPICNTEN2 0x2000 +#define WPICNTEN3 0x4000 +#define EMUSW2 0x8000 +#define EMUSW3 0x10000 +#define WPIREN45 0x20000 +#define WPIRINV45 0x40000 +#define WPIAEN4 0x80000 +#define WPIAEN5 0x100000 +#define WPICNTEN4 0x200000 +#define WPICNTEN5 0x400000 +#define EMUSW4 0x800000 +#define EMUSW5 0x1000000 +#define WPAND 0x2000000 + +/* Data watchpoint address control register bits mask */ +#define WPDREN01 0x1 +#define WPDRINV01 0x2 +#define WPDAEN0 0x4 +#define WPDAEN1 0x8 +#define WPDCNTEN0 0x10 +#define WPDCNTEN1 0x20 +#define WPDSRC0 0xc0 +#define WPDACC0 0x300 +#define WPDSRC1 0xc00 +#define WPDACC1 0x3000 + +/* Watchpoint status register bits mask */ +#define STATIA0 0x1 +#define STATIA1 0x2 +#define STATIA2 0x4 +#define STATIA3 0x8 +#define STATIA4 0x10 +#define STATIA5 0x20 +#define STATDA0 0x40 +#define STATDA1 0x80 + +extern void kgdb_print(const char *fmt, ...); + +#endif diff --git a/include/asm-blackfin/mach-bf533/dma.h b/include/asm-blackfin/mach-bf533/dma.h index bd9d5e94307d..16c672c01d80 100644 --- a/include/asm-blackfin/mach-bf533/dma.h +++ b/include/asm-blackfin/mach-bf533/dma.h @@ -51,4 +51,7 @@ #define CH_MEM_STREAM1_DEST 10 /* TX */ #define CH_MEM_STREAM1_SRC 11 /* RX */ +extern int channel2irq(unsigned int channel); +extern struct dma_register *base_addr[]; + #endif diff --git a/include/asm-blackfin/mach-bf533/portmux.h b/include/asm-blackfin/mach-bf533/portmux.h new file mode 100644 index 000000000000..b88d7a03ee3e --- /dev/null +++ b/include/asm-blackfin/mach-bf533/portmux.h @@ -0,0 +1,65 @@ +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define P_PPI0_CLK (P_DONTCARE) +#define P_PPI0_FS1 (P_DONTCARE) +#define P_PPI0_FS2 (P_DONTCARE) +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11)) +#define P_PPI0_D0 (P_DONTCARE) +#define P_PPI0_D1 (P_DONTCARE) +#define P_PPI0_D2 (P_DONTCARE) +#define P_PPI0_D3 (P_DONTCARE) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12)) + +#define P_SPORT1_TSCLK (P_DONTCARE) +#define P_SPORT1_RSCLK (P_DONTCARE) +#define P_SPORT0_TSCLK (P_DONTCARE) +#define P_SPORT0_RSCLK (P_DONTCARE) +#define P_UART0_RX (P_DONTCARE) +#define P_UART0_TX (P_DONTCARE) +#define P_SPORT1_DRSEC (P_DONTCARE) +#define P_SPORT1_RFS (P_DONTCARE) +#define P_SPORT1_DTPRI (P_DONTCARE) +#define P_SPORT1_DTSEC (P_DONTCARE) +#define P_SPORT1_TFS (P_DONTCARE) +#define P_SPORT1_DRPRI (P_DONTCARE) +#define P_SPORT0_DRSEC (P_DONTCARE) +#define P_SPORT0_RFS (P_DONTCARE) +#define P_SPORT0_DTPRI (P_DONTCARE) +#define P_SPORT0_DTSEC (P_DONTCARE) +#define P_SPORT0_TFS (P_DONTCARE) +#define P_SPORT0_DRPRI (P_DONTCARE) + +#define P_SPI0_MOSI (P_DONTCARE) +#define P_SPI0_MIS0 (P_DONTCARE) +#define P_SPI0_SCK (P_DONTCARE) +#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) + +#define P_TMR2 (P_DONTCARE) +#define P_TMR1 (P_DONTCARE) +#define P_TMR0 (P_DONTCARE) +#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF1)) + + + + + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/include/asm-blackfin/mach-bf537/dma.h b/include/asm-blackfin/mach-bf537/dma.h index 7a964040870a..021991984e6e 100644 --- a/include/asm-blackfin/mach-bf537/dma.h +++ b/include/asm-blackfin/mach-bf537/dma.h @@ -52,4 +52,7 @@ #define CH_MEM_STREAM1_DEST 14 /* TX */ #define CH_MEM_STREAM1_SRC 15 /* RX */ +extern int channel2irq(unsigned int channel); +extern struct dma_register *base_addr[]; + #endif diff --git a/include/asm-blackfin/mach-bf537/portmux.h b/include/asm-blackfin/mach-bf537/portmux.h new file mode 100644 index 000000000000..23e13c5abc4d --- /dev/null +++ b/include/asm-blackfin/mach-bf537/portmux.h @@ -0,0 +1,109 @@ +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) +#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) +#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0)) +#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0)) +#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0)) +#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0)) +#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) +#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) +#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0)) +#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0)) +#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0)) +#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) +#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) +#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) +#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) +#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) +#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) +#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) +#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) +#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) +#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) +#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) +#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) + +#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) +#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) +#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0)) +#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0)) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) +#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1)) +#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1)) +#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1)) +#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) +#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1)) +#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1)) +#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1)) +#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1)) + +#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0)) +#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0)) +#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0)) +#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0)) +#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0)) +#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0)) +#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0)) +#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0)) +#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0)) +#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0)) +#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0)) +#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0)) +#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0)) +#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0)) +#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0)) +#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0)) +#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1)) +#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1)) +#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1)) + +#define PORT_PJ0 (GPIO_PH15 + 1) +#define PORT_PJ1 (GPIO_PH15 + 2) +#define PORT_PJ2 (GPIO_PH15 + 3) +#define PORT_PJ3 (GPIO_PH15 + 4) +#define PORT_PJ4 (GPIO_PH15 + 5) +#define PORT_PJ5 (GPIO_PH15 + 6) +#define PORT_PJ6 (GPIO_PH15 + 7) +#define PORT_PJ7 (GPIO_PH15 + 8) +#define PORT_PJ8 (GPIO_PH15 + 9) +#define PORT_PJ9 (GPIO_PH15 + 10) +#define PORT_PJ10 (GPIO_PH15 + 11) +#define PORT_PJ11 (GPIO_PH15 + 12) + +#define P_MDC (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0)) +#define P_MDIO (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0)) +#define P_TWI0_SCL (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0)) +#define P_TWI0_SDA (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0)) +#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0)) +#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0)) +#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0)) +#define P_SPORT0_RFS (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0)) +#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0)) +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0)) +#define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0)) +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1)) +#define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1)) +#define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1)) +#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2)) + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h new file mode 100644 index 000000000000..aca1d4ba145c --- /dev/null +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -0,0 +1,74 @@ + +/* + * File: include/asm-blackfin/mach-bf548/anomaly.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _MACH_ANOMALY_H_ +#define _MACH_ANOMALY_H_ +#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in + slot1 and store of a P register in slot 2 is not + supported */ +#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive + Channel DMA stops */ +#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR + registers. */ +#define ANOMALY_05000245 /* Spurious Hardware Error from an Access in the + Shadow of a Conditional Branch */ +#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event + interrupt not functional */ +#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on + SPORT external receive and transmit clocks. */ +#define ANOMALY_05000272 /* Certain data cache write through modes fail for + VDDint <=0.9V */ +#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is + not restored */ +#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the + Boundary of Reserved Memory */ +#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and + LC Registers Are Interrupted */ +#define ANOMALY_05000324 /* TWI Slave Boot Mode Is Not Functional */ +#define ANOMALY_05000325 /* External FIFO Boot Mode Is Not Functional */ +#define ANOMALY_05000327 /* Data Lost When Core and DMA Accesses Are Made to + the USB FIFO Simultaneously */ +#define ANOMALY_05000328 /* Incorrect Access of OTP_STATUS During otp_write() + function */ +#define ANOMALY_05000329 /* Synchronous Burst Flash Boot Mode Is Not Functional + */ +#define ANOMALY_05000330 /* Host DMA Boot Mode Is Not Functional */ +#define ANOMALY_05000334 /* Inadequate Timing Margins on DDR DQS to DQ and DQM + Skew */ +#define ANOMALY_05000335 /* Inadequate Rotary Debounce Logic Duration */ +#define ANOMALY_05000336 /* Phantom Interrupt Occurs After First Configuration + of Host DMA Port */ +#define ANOMALY_05000337 /* Disallowed Configuration Prevents Subsequent + Allowed Configuration on Host DMA Port */ +#define ANOMALY_05000338 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ + +#endif /* _MACH_ANOMALY_H_ */ diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h new file mode 100644 index 000000000000..9498313a2cb7 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/bf548.h @@ -0,0 +1,271 @@ +/* + * File: include/asm-blackfin/mach-bf548/bf548.h + * Based on: + * Author: + * + * Created: + * Description: System MMR register and memory map for ADSP-BF548 + * + * Modified: + * Copyright 2004-2007 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MACH_BF548_H__ +#define __MACH_BF548_H__ + +#define SUPPORTED_REVID 0 + +#define OFFSET_(x) ((x) & 0x0000FFFF) + +/*some misc defines*/ +#define IMASK_IVG15 0x8000 +#define IMASK_IVG14 0x4000 +#define IMASK_IVG13 0x2000 +#define IMASK_IVG12 0x1000 + +#define IMASK_IVG11 0x0800 +#define IMASK_IVG10 0x0400 +#define IMASK_IVG9 0x0200 +#define IMASK_IVG8 0x0100 + +#define IMASK_IVG7 0x0080 +#define IMASK_IVGTMR 0x0040 +#define IMASK_IVGHW 0x0020 + +/***************************/ + + +#define BLKFIN_DSUBBANKS 4 +#define BLKFIN_DWAYS 2 +#define BLKFIN_DLINES 64 +#define BLKFIN_ISUBBANKS 4 +#define BLKFIN_IWAYS 4 +#define BLKFIN_ILINES 32 + +#define WAY0_L 0x1 +#define WAY1_L 0x2 +#define WAY01_L 0x3 +#define WAY2_L 0x4 +#define WAY02_L 0x5 +#define WAY12_L 0x6 +#define WAY012_L 0x7 + +#define WAY3_L 0x8 +#define WAY03_L 0x9 +#define WAY13_L 0xA +#define WAY013_L 0xB + +#define WAY32_L 0xC +#define WAY320_L 0xD +#define WAY321_L 0xE +#define WAYALL_L 0xF + +#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ + +/********************************* EBIU Settings ************************************/ +#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) +#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) + +#ifdef CONFIG_C_AMBEN_ALL +#define V_AMBEN AMBEN_ALL +#endif +#ifdef CONFIG_C_AMBEN +#define V_AMBEN 0x0 +#endif +#ifdef CONFIG_C_AMBEN_B0 +#define V_AMBEN AMBEN_B0 +#endif +#ifdef CONFIG_C_AMBEN_B0_B1 +#define V_AMBEN AMBEN_B0_B1 +#endif +#ifdef CONFIG_C_AMBEN_B0_B1_B2 +#define V_AMBEN AMBEN_B0_B1_B2 +#endif +#ifdef CONFIG_C_AMCKEN +#define V_AMCKEN AMCKEN +#else +#define V_AMCKEN 0x0 +#endif + +#define AMGCTLVAL (V_AMBEN | V_AMCKEN) + +#define MAX_VC 650000000 +#define MIN_VC 50000000 + +/********************************PLL Settings **************************************/ +#ifdef CONFIG_BFIN_KERNEL_CLOCK +#if (CONFIG_VCO_MULT < 0) +#error "VCO Multiplier is less than 0. Please select a different value" +#endif + +#if (CONFIG_VCO_MULT == 0) +#error "VCO Multiplier should be greater than 0. Please select a different value" +#endif + +#if (CONFIG_VCO_MULT > 64) +#error "VCO Multiplier is more than 64. Please select a different value" +#endif + +#ifndef CONFIG_CLKIN_HALF +#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) +#else +#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2) +#endif + +#ifndef CONFIG_PLL_BYPASS +#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV) +#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV) +#else +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#endif + +#if (CONFIG_SCLK_DIV < 1) +#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" +#endif + +#if (CONFIG_SCLK_DIV > 15) +#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" +#endif + +#if (CONFIG_CCLK_DIV != 1) +#if (CONFIG_CCLK_DIV != 2) +#if (CONFIG_CCLK_DIV != 4) +#if (CONFIG_CCLK_DIV != 8) +#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value" +#endif +#endif +#endif +#endif + +#if (CONFIG_VCO_HZ > MAX_VC) +#error "VCO selected is more than maximum value. Please change the VCO multipler" +#endif + +#if (CONFIG_SCLK_HZ > 133000000) +#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier" +#endif + +#if (CONFIG_SCLK_HZ < 27000000) +#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier" +#endif + +#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ) +#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) +#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ) +#error "Please select sclk less than cclk" +#endif +#endif +#endif + +#if (CONFIG_CCLK_DIV == 1) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 +#endif +#if (CONFIG_CCLK_DIV == 2) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 +#endif +#if (CONFIG_CCLK_DIV == 4) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 +#endif +#if (CONFIG_CCLK_DIV == 8) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 +#endif +#ifndef CONFIG_CCLK_ACT_DIV +#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly +#endif + +#endif /* CONFIG_BFIN_KERNEL_CLOCK */ + +#ifdef CONFIG_BF542 +#define CPU "BF542" +#define CPUID 0x027c8000 +#endif +#ifdef CONFIG_BF544 +#define CPU "BF544" +#define CPUID 0x027c8000 +#endif +#ifdef CONFIG_BF548 +#define CPU "BF548" +#define CPUID 0x027c6000 +#endif +#ifdef CONFIG_BF549 +#define CPU "BF549" +#endif +#ifndef CPU +#define CPU "UNKNOWN" +#define CPUID 0x0 +#endif + +#if (CONFIG_MEM_SIZE % 4) +#error "SDRAM mem size must be multible of 4MB" +#endif + +#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) +#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) +#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) + +/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ + +#define ANOMALY_05000158_WORKAROUND 0x200 +#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ +#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \ + | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#else /*Write Through */ +#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \ + | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) +#endif + + +#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY ) +#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) +#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) +#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY ) + +#define SIZE_1K 0x00000400 /* 1K */ +#define SIZE_4K 0x00001000 /* 4K */ +#define SIZE_1M 0x00100000 /* 1M */ +#define SIZE_4M 0x00400000 /* 4M */ + +#define MAX_CPLBS (16 * 2) + +/* +* Number of required data CPLB switchtable entries +* MEMSIZE / 4 (we mostly install 4M page size CPLBs +* approx 16 for smaller 1MB page size CPLBs for allignment purposes +* 1 for L1 Data Memory +* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO +* 1 for ASYNC Memory +*/ + + +#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2) + +/* +* Number of required instruction CPLB switchtable entries +* MEMSIZE / 4 (we mostly install 4M page size CPLBs +* approx 12 for smaller 1MB page size CPLBs for allignment purposes +* 1 for L1 Instruction Memory +* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO +*/ + +#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2) + +#endif /* __MACH_BF48_H__ */ diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h new file mode 100644 index 000000000000..2f4afc90db11 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h @@ -0,0 +1,193 @@ +#include <linux/serial.h> +#include <asm/dma.h> + +#define NR_PORTS 4 + +#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ +#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ +#define OFFSET_GCTL 0x08 /* Global Control Register */ +#define OFFSET_LCR 0x0C /* Line Control Register */ +#define OFFSET_MCR 0x10 /* Modem Control Register */ +#define OFFSET_LSR 0x14 /* Line Status Register */ +#define OFFSET_MSR 0x18 /* Modem Status Register */ +#define OFFSET_SCR 0x1C /* SCR Scratch Register */ +#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */ +#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */ +#define OFFSET_THR 0x28 /* Transmit Holding register */ +#define OFFSET_RBR 0x2C /* Receive Buffer register */ + +#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) +#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) +#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) +#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER_SET)) +#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) +#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR)) +#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) + +#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) +#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) +#define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v) +#define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v) +#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) +#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v) +#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) +#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) + +#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) +# define CONFIG_SERIAL_BFIN_CTSRTS + +# ifndef CONFIG_UART0_CTS_PIN +# define CONFIG_UART0_CTS_PIN -1 +# endif + +# ifndef CONFIG_UART0_RTS_PIN +# define CONFIG_UART0_RTS_PIN -1 +# endif + +# ifndef CONFIG_UART1_CTS_PIN +# define CONFIG_UART1_CTS_PIN -1 +# endif + +# ifndef CONFIG_UART1_RTS_PIN +# define CONFIG_UART1_RTS_PIN -1 +# endif +#endif +/* + * The pin configuration is different from schematic + */ +struct bfin_serial_port { + struct uart_port port; + unsigned int old_status; +#ifdef CONFIG_SERIAL_BFIN_DMA + int tx_done; + int tx_count; + struct circ_buf rx_dma_buf; + struct timer_list rx_dma_timer; + int rx_dma_nrows; + unsigned int tx_dma_channel; + unsigned int rx_dma_channel; + struct work_struct tx_dma_workqueue; +#else + struct work_struct cts_workqueue; +#endif +#ifdef CONFIG_SERIAL_BFIN_CTSRTS + int cts_pin; + int rts_pin; +#endif +}; + +struct bfin_serial_port bfin_serial_ports[NR_PORTS]; +struct bfin_serial_res { + unsigned long uart_base_addr; + int uart_irq; +#ifdef CONFIG_SERIAL_BFIN_DMA + unsigned int uart_tx_dma_channel; + unsigned int uart_rx_dma_channel; +#endif +#ifdef CONFIG_SERIAL_BFIN_CTSRTS + int uart_cts_pin; + int uart_rts_pin; +#endif +}; + +struct bfin_serial_res bfin_serial_resource[] = { +#ifdef CONFIG_SERIAL_BFIN_UART0 + { + 0xFFC00400, + IRQ_UART0_RX, +#ifdef CONFIG_SERIAL_BFIN_DMA + CH_UART0_TX, + CH_UART0_RX, +#endif +#ifdef CONFIG_BFIN_UART0_CTSRTS + CONFIG_UART0_CTS_PIN, + CONFIG_UART0_RTS_PIN, +#endif + }, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + { + 0xFFC02000, + IRQ_UART1_RX, +#ifdef CONFIG_SERIAL_BFIN_DMA + CH_UART1_TX, + CH_UART1_RX, +#endif + }, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART2 + { + 0xFFC02100, + IRQ_UART2_RX, +#ifdef CONFIG_SERIAL_BFIN_DMA + CH_UART2_TX, + CH_UART2_RX, +#endif +#ifdef CONFIG_BFIN_UART2_CTSRTS + CONFIG_UART2_CTS_PIN, + CONFIG_UART2_RTS_PIN, +#endif + }, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART3 + { + 0xFFC03100, + IRQ_UART3_RX, +#ifdef CONFIG_SERIAL_BFIN_DMA + CH_UART3_TX, + CH_UART3_RX, +#endif + }, +#endif +}; + +int nr_ports = ARRAY_SIZE(bfin_serial_resource); + +static void bfin_serial_hw_init(struct bfin_serial_port *uart) +{ +#ifdef CONFIG_SERIAL_BFIN_UART0 + /* Enable UART0 RX and TX on pin 7 & 8 of PORT E */ + bfin_write_PORTE_FER(0x180 | bfin_read_PORTE_FER()); + bfin_write_PORTE_MUX(0x3C000 | bfin_read_PORTE_MUX()); +#endif + +#ifdef CONFIG_SERIAL_BFIN_UART1 + /* Enable UART1 RX and TX on pin 0 & 1 of PORT H */ + bfin_write_PORTH_FER(0x3 | bfin_read_PORTH_FER()); + bfin_write_PORTH_MUX(~0xF & bfin_read_PORTH_MUX()); +#ifdef CONFIG_BFIN_UART1_CTSRTS + /* Enable UART1 RTS and CTS on pin 9 & 10 of PORT E */ + bfin_write_PORTE_FER(0x600 | bfin_read_PORTE_FER()); + bfin_write_PORTE_MUX(~0x3C0000 & bfin_read_PORTE_MUX()); +#endif +#endif + +#ifdef CONFIG_SERIAL_BFIN_UART2 + /* Enable UART2 RX and TX on pin 4 & 5 of PORT B */ + bfin_write_PORTB_FER(0x30 | bfin_read_PORTB_FER()); + bfin_write_PORTB_MUX(~0xF00 & bfin_read_PORTB_MUX()); +#endif + +#ifdef CONFIG_SERIAL_BFIN_UART3 + /* Enable UART3 RX and TX on pin 6 & 7 of PORT B */ + bfin_write_PORTB_FER(0xC0 | bfin_read_PORTB_FER()); + bfin_write_PORTB_MUX(~0xF000 | bfin_read_PORTB_MUX()); +#ifdef CONFIG_BFIN_UART3_CTSRTS + /* Enable UART3 RTS and CTS on pin 2 & 3 of PORT B */ + bfin_write_PORTB_FER(0xC | bfin_read_PORTB_FER()); + bfin_write_PORTB_MUX(~0xF0 | bfin_read_PORTB_MUX()); +#endif +#endif + SSYNC(); +#ifdef CONFIG_SERIAL_BFIN_CTSRTS + if (uart->cts_pin >= 0) { + gpio_request(uart->cts_pin, NULL); + gpio_direction_input(uart->cts_pin); + } + + if (uart->rts_pin >= 0) { + gpio_request(uart->rts_pin, NULL); + gpio_direction_output(uart->rts_pin); + } +#endif +} diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h new file mode 100644 index 000000000000..791218fe7d94 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/blackfin.h @@ -0,0 +1,168 @@ +/* + * File: include/asm-blackfin/mach-bf548/blackfin.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _MACH_BLACKFIN_H_ +#define _MACH_BLACKFIN_H_ + +#define BF548_FAMILY + +#include "bf548.h" +#include "mem_map.h" +#include "anomaly.h" + +#ifdef CONFIG_BF542 +#include "defBF542.h" +#endif + +#ifdef CONFIG_BF544 +#include "defBF544.h" +#endif + +#ifdef CONFIG_BF548 +#include "defBF548.h" +#endif + +#ifdef CONFIG_BF549 +#include "defBF549.h" +#endif + +#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY)) +#ifdef CONFIG_BF542 +#include "cdefBF542.h" +#endif + +#ifdef CONFIG_BF544 +#include "cdefBF544.h" +#endif +#ifdef CONFIG_BF548 +#include "cdefBF548.h" +#endif +#ifdef CONFIG_BF549 +#include "cdefBF549.h" +#endif + +/* UART 1*/ +#define bfin_read_UART_THR() bfin_read_UART1_THR() +#define bfin_write_UART_THR(val) bfin_write_UART1_THR(val) +#define bfin_read_UART_RBR() bfin_read_UART1_RBR() +#define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val) +#define bfin_read_UART_DLL() bfin_read_UART1_DLL() +#define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val) +#define bfin_read_UART_IER() bfin_read_UART1_IER() +#define bfin_write_UART_IER(val) bfin_write_UART1_IER(val) +#define bfin_read_UART_DLH() bfin_read_UART1_DLH() +#define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val) +#define bfin_read_UART_IIR() bfin_read_UART1_IIR() +#define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val) +#define bfin_read_UART_LCR() bfin_read_UART1_LCR() +#define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val) +#define bfin_read_UART_MCR() bfin_read_UART1_MCR() +#define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val) +#define bfin_read_UART_LSR() bfin_read_UART1_LSR() +#define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val) +#define bfin_read_UART_SCR() bfin_read_UART1_SCR() +#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val) +#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL() +#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val) + +#endif + +/* MAP used DEFINES from BF533 to BF54x - so we don't need to change + * them in the driver, kernel, etc. */ + +/* UART_IIR Register */ +#define STATUS(x) ((x << 1) & 0x06) +#define STATUS_P1 0x02 +#define STATUS_P0 0x01 + +/* UART 0*/ + +/* DMA Channnel */ +#define bfin_read_CH_UART_RX() bfin_read_CH_UART1_RX() +#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART1_RX(val) +#define bfin_read_CH_UART_TX() bfin_read_CH_UART1_TX() +#define bfin_write_CH_UART_TX(val) bfin_write_CH_UART1_TX(val) +#define CH_UART_RX CH_UART1_RX +#define CH_UART_TX CH_UART1_TX + +/* System Interrupt Controller */ +#define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART1_RX() +#define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART1_RX(val) +#define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART1_TX() +#define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART1_TX(val) +#define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART1_ERROR() +#define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART1_ERROR(val) +#define IRQ_UART_RX IRQ_UART1_RX +#define IRQ_UART_TX IRQ_UART1_TX +#define IRQ_UART_ERROR IRQ_UART1_ERROR + +/* MMR Registers*/ +#define bfin_read_UART_THR() bfin_read_UART1_THR() +#define bfin_write_UART_THR(val) bfin_write_UART1_THR(val) +#define bfin_read_UART_RBR() bfin_read_UART1_RBR() +#define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val) +#define bfin_read_UART_DLL() bfin_read_UART1_DLL() +#define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val) +#define bfin_read_UART_IER() bfin_read_UART1_IER() +#define bfin_write_UART_IER(val) bfin_write_UART1_IER(val) +#define bfin_read_UART_DLH() bfin_read_UART1_DLH() +#define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val) +#define bfin_read_UART_IIR() bfin_read_UART1_IIR() +#define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val) +#define bfin_read_UART_LCR() bfin_read_UART1_LCR() +#define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val) +#define bfin_read_UART_MCR() bfin_read_UART1_MCR() +#define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val) +#define bfin_read_UART_LSR() bfin_read_UART1_LSR() +#define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val) +#define bfin_read_UART_SCR() bfin_read_UART1_SCR() +#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val) +#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL() +#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val) +#define UART_THR UART1_THR +#define UART_RBR UART1_RBR +#define UART_DLL UART1_DLL +#define UART_IER UART1_IER +#define UART_DLH UART1_DLH +#define UART_IIR UART1_IIR +#define UART_LCR UART1_LCR +#define UART_MCR UART1_MCR +#define UART_LSR UART1_LSR +#define UART_SCR UART1_SCR +#define UART_GCTL UART1_GCTL + +/* PLL_DIV Masks */ +#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */ + +#endif diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h index 6bbcefeb3627..98d35a929116 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h @@ -31,7 +31,8 @@ #ifndef _CDEF_BF54X_H #define _CDEF_BF54X_H -#include <defBF54x_base.h> +#include "defBF54x_base.h" +#include <asm/system.h> /* ************************************************************** */ /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ @@ -44,7 +45,30 @@ #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) #define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) +/* Writing to VR_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_VR_CTL(unsigned int val) +{ + unsigned long flags, iwr0, iwr1, iwr2; + + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr0 = bfin_read32(SIC_IWR0); + iwr1 = bfin_read32(SIC_IWR1); + iwr2 = bfin_read32(SIC_IWR2); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR0, IWR_ENABLE(0)); + bfin_write32(SIC_IWR1, 0); + bfin_write32(SIC_IWR2, 0); + + bfin_write16(VR_CTL, val); + __builtin_bfin_ssync(); + + local_irq_save(flags); + asm("IDLE;"); + local_irq_restore(flags); + bfin_write32(SIC_IWR0, iwr0); + bfin_write32(SIC_IWR1, iwr1); + bfin_write32(SIC_IWR2, iwr2); +} #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) @@ -70,12 +94,18 @@ #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) #define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2) #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) +#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 2)) +#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val) + #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) #define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2) #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) +#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2)) +#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val) + #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) @@ -710,21 +740,21 @@ #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR) #define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR) +#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) #define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) #define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY) +#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) #define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY) +#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR) +#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) #define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR) +#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) @@ -734,23 +764,23 @@ #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR) +#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) #define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR) +#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) #define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) #define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY) +#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) #define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY) +#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR) +#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) #define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR) +#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) @@ -763,9 +793,9 @@ /* MDMA Stream 1 Registers */ #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR) +#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) #define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR) +#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) @@ -777,9 +807,9 @@ #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY) #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR) +#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) #define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR) +#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) @@ -789,9 +819,9 @@ #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR) +#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) #define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR) +#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) #define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) @@ -803,9 +833,9 @@ #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY) #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR) +#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) #define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR) +#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) diff --git a/include/asm-blackfin/mach-bf548/defBF542.h b/include/asm-blackfin/mach-bf548/defBF542.h index ac968fca5cc5..32d07130200c 100644 --- a/include/asm-blackfin/mach-bf548/defBF542.h +++ b/include/asm-blackfin/mach-bf548/defBF542.h @@ -362,7 +362,6 @@ /* Bit masks for KPAD_CTL */ #define KPAD_EN 0x1 /* Keypad Enable */ -#define nKPAD_EN 0x0 #define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ #define KPAD_ROWEN 0x1c00 /* Row Enable Width */ #define KPAD_COLEN 0xe000 /* Column Enable Width */ @@ -384,29 +383,21 @@ /* Bit masks for KPAD_STAT */ #define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ -#define nKPAD_IRQ 0x0 #define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ #define KPAD_PRESSED 0x8 /* Key press current status */ -#define nKPAD_PRESSED 0x0 /* Bit masks for KPAD_SOFTEVAL */ #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ -#define nKPAD_SOFTEVAL_E 0x0 /* Bit masks for SDH_COMMAND */ #define CMD_IDX 0x3f /* Command Index */ #define CMD_RSP 0x40 /* Response */ -#define nCMD_RSP 0x0 #define CMD_L_RSP 0x80 /* Long Response */ -#define nCMD_L_RSP 0x0 #define CMD_INT_E 0x100 /* Command Interrupt */ -#define nCMD_INT_E 0x0 #define CMD_PEND_E 0x200 /* Command Pending */ -#define nCMD_PEND_E 0x0 #define CMD_E 0x400 /* Command Enable */ -#define nCMD_E 0x0 /* Bit masks for SDH_PWR_CTL */ @@ -415,21 +406,15 @@ #define TBD 0x3c /* TBD */ #endif #define SD_CMD_OD 0x40 /* Open Drain Output */ -#define nSD_CMD_OD 0x0 #define ROD_CTL 0x80 /* Rod Control */ -#define nROD_CTL 0x0 /* Bit masks for SDH_CLK_CTL */ #define CLKDIV 0xff /* MC_CLK Divisor */ #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ -#define nCLK_E 0x0 #define PWR_SV_E 0x200 /* Power Save Enable */ -#define nPWR_SV_E 0x0 #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ -#define nCLKDIV_BYPASS 0x0 #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ -#define nWIDE_BUS 0x0 /* Bit masks for SDH_RESP_CMD */ @@ -438,133 +423,74 @@ /* Bit masks for SDH_DATA_CTL */ #define DTX_E 0x1 /* Data Transfer Enable */ -#define nDTX_E 0x0 #define DTX_DIR 0x2 /* Data Transfer Direction */ -#define nDTX_DIR 0x0 #define DTX_MODE 0x4 /* Data Transfer Mode */ -#define nDTX_MODE 0x0 #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ -#define nDTX_DMA_E 0x0 #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ /* Bit masks for SDH_STATUS */ #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ -#define nCMD_CRC_FAIL 0x0 #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ -#define nDAT_CRC_FAIL 0x0 #define CMD_TIMEOUT 0x4 /* CMD Time Out */ -#define nCMD_TIMEOUT 0x0 #define DAT_TIMEOUT 0x8 /* Data Time Out */ -#define nDAT_TIMEOUT 0x0 #define TX_UNDERRUN 0x10 /* Transmit Underrun */ -#define nTX_UNDERRUN 0x0 #define RX_OVERRUN 0x20 /* Receive Overrun */ -#define nRX_OVERRUN 0x0 #define CMD_RESP_END 0x40 /* CMD Response End */ -#define nCMD_RESP_END 0x0 #define CMD_SENT 0x80 /* CMD Sent */ -#define nCMD_SENT 0x0 #define DAT_END 0x100 /* Data End */ -#define nDAT_END 0x0 #define START_BIT_ERR 0x200 /* Start Bit Error */ -#define nSTART_BIT_ERR 0x0 #define DAT_BLK_END 0x400 /* Data Block End */ -#define nDAT_BLK_END 0x0 #define CMD_ACT 0x800 /* CMD Active */ -#define nCMD_ACT 0x0 #define TX_ACT 0x1000 /* Transmit Active */ -#define nTX_ACT 0x0 #define RX_ACT 0x2000 /* Receive Active */ -#define nRX_ACT 0x0 #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ -#define nTX_FIFO_STAT 0x0 #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ -#define nRX_FIFO_STAT 0x0 #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ -#define nTX_FIFO_FULL 0x0 #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ -#define nRX_FIFO_FULL 0x0 #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ -#define nTX_FIFO_ZERO 0x0 #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ -#define nRX_DAT_ZERO 0x0 #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ -#define nTX_DAT_RDY 0x0 #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ -#define nRX_FIFO_RDY 0x0 /* Bit masks for SDH_STATUS_CLR */ #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ -#define nCMD_CRC_FAIL_STAT 0x0 #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ -#define nDAT_CRC_FAIL_STAT 0x0 #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ -#define nCMD_TIMEOUT_STAT 0x0 #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ -#define nDAT_TIMEOUT_STAT 0x0 #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ -#define nTX_UNDERRUN_STAT 0x0 #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ -#define nRX_OVERRUN_STAT 0x0 #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ -#define nCMD_RESP_END_STAT 0x0 #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ -#define nCMD_SENT_STAT 0x0 #define DAT_END_STAT 0x100 /* Data End Status */ -#define nDAT_END_STAT 0x0 #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ -#define nSTART_BIT_ERR_STAT 0x0 #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ -#define nDAT_BLK_END_STAT 0x0 /* Bit masks for SDH_MASK0 */ #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ -#define nCMD_CRC_FAIL_MASK 0x0 #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ -#define nDAT_CRC_FAIL_MASK 0x0 #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ -#define nCMD_TIMEOUT_MASK 0x0 #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ -#define nDAT_TIMEOUT_MASK 0x0 #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ -#define nTX_UNDERRUN_MASK 0x0 #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ -#define nRX_OVERRUN_MASK 0x0 #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ -#define nCMD_RESP_END_MASK 0x0 #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ -#define nCMD_SENT_MASK 0x0 #define DAT_END_MASK 0x100 /* Data End Mask */ -#define nDAT_END_MASK 0x0 #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ -#define nSTART_BIT_ERR_MASK 0x0 #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ -#define nDAT_BLK_END_MASK 0x0 #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ -#define nCMD_ACT_MASK 0x0 #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ -#define nTX_ACT_MASK 0x0 #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ -#define nRX_ACT_MASK 0x0 #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ -#define nTX_FIFO_STAT_MASK 0x0 #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ -#define nRX_FIFO_STAT_MASK 0x0 #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ -#define nTX_FIFO_FULL_MASK 0x0 #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ -#define nRX_FIFO_FULL_MASK 0x0 #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ -#define nTX_FIFO_ZERO_MASK 0x0 #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ -#define nRX_DAT_ZERO_MASK 0x0 #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ -#define nTX_DAT_RDY_MASK 0x0 #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ -#define nRX_FIFO_RDY_MASK 0x0 /* Bit masks for SDH_FIFO_CNT */ @@ -573,73 +499,47 @@ /* Bit masks for SDH_E_STATUS */ #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ -#define nSDIO_INT_DET 0x0 #define SD_CARD_DET 0x10 /* SD Card Detect */ -#define nSD_CARD_DET 0x0 /* Bit masks for SDH_E_MASK */ #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ -#define nSDIO_MSK 0x0 #define SCD_MSK 0x40 /* Mask Card Detect */ -#define nSCD_MSK 0x0 /* Bit masks for SDH_CFG */ #define CLKS_EN 0x1 /* Clocks Enable */ -#define nCLKS_EN 0x0 #define SD4E 0x4 /* SDIO 4-Bit Enable */ -#define nSD4E 0x0 #define MWE 0x8 /* Moving Window Enable */ -#define nMWE 0x0 #define SD_RST 0x10 /* SDMMC Reset */ -#define nSD_RST 0x0 #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ -#define nPUP_SDDAT 0x0 #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ -#define nPUP_SDDAT3 0x0 #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ -#define nPD_SDDAT3 0x0 /* Bit masks for SDH_RD_WAIT_EN */ #define RWR 0x1 /* Read Wait Request */ -#define nRWR 0x0 /* Bit masks for ATAPI_CONTROL */ #define PIO_START 0x1 /* Start PIO/Reg Op */ -#define nPIO_START 0x0 #define MULTI_START 0x2 /* Start Multi-DMA Op */ -#define nMULTI_START 0x0 #define ULTRA_START 0x4 /* Start Ultra-DMA Op */ -#define nULTRA_START 0x0 #define XFER_DIR 0x8 /* Transfer Direction */ -#define nXFER_DIR 0x0 #define IORDY_EN 0x10 /* IORDY Enable */ -#define nIORDY_EN 0x0 #define FIFO_FLUSH 0x20 /* Flush FIFOs */ -#define nFIFO_FLUSH 0x0 #define SOFT_RST 0x40 /* Soft Reset */ -#define nSOFT_RST 0x0 #define DEV_RST 0x80 /* Device Reset */ -#define nDEV_RST 0x0 #define TFRCNT_RST 0x100 /* Trans Count Reset */ -#define nTFRCNT_RST 0x0 #define END_ON_TERM 0x200 /* End/Terminate Select */ -#define nEND_ON_TERM 0x0 #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ -#define nPIO_USE_DMA 0x0 #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ /* Bit masks for ATAPI_STATUS */ #define PIO_XFER_ON 0x1 /* PIO transfer in progress */ -#define nPIO_XFER_ON 0x0 #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ -#define nMULTI_XFER_ON 0x0 #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ -#define nULTRA_XFER_ON 0x0 #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ /* Bit masks for ATAPI_DEV_ADDR */ @@ -649,66 +549,39 @@ /* Bit masks for ATAPI_INT_MASK */ #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ -#define nATAPI_DEV_INT_MASK 0x0 #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ -#define nPIO_DONE_MASK 0x0 #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ -#define nMULTI_DONE_MASK 0x0 #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ -#define nUDMAIN_DONE_MASK 0x0 #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ -#define nUDMAOUT_DONE_MASK 0x0 #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ -#define nHOST_TERM_XFER_MASK 0x0 #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ -#define nMULTI_TERM_MASK 0x0 #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ -#define nUDMAIN_TERM_MASK 0x0 #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ -#define nUDMAOUT_TERM_MASK 0x0 /* Bit masks for ATAPI_INT_STATUS */ #define ATAPI_DEV_INT 0x1 /* Device interrupt status */ -#define nATAPI_DEV_INT 0x0 #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ -#define nPIO_DONE_INT 0x0 #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ -#define nMULTI_DONE_INT 0x0 #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ -#define nUDMAIN_DONE_INT 0x0 #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ -#define nUDMAOUT_DONE_INT 0x0 #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ -#define nHOST_TERM_XFER_INT 0x0 #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ -#define nMULTI_TERM_INT 0x0 #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ -#define nUDMAIN_TERM_INT 0x0 #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ -#define nUDMAOUT_TERM_INT 0x0 /* Bit masks for ATAPI_LINE_STATUS */ #define ATAPI_INTR 0x1 /* Device interrupt to host line status */ -#define nATAPI_INTR 0x0 #define ATAPI_DASP 0x2 /* Device dasp to host line status */ -#define nATAPI_DASP 0x0 #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ -#define nATAPI_CS0N 0x0 #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ -#define nATAPI_CS1N 0x0 #define ATAPI_ADDR 0x70 /* ATAPI address line status */ #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ -#define nATAPI_DMAREQ 0x0 #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ -#define nATAPI_DMAACKN 0x0 #define ATAPI_DIOWN 0x200 /* ATAPI write line status */ -#define nATAPI_DIOWN 0x0 #define ATAPI_DIORN 0x400 /* ATAPI read line status */ -#define nATAPI_DIORN 0x0 #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ -#define nATAPI_IORDY 0x0 /* Bit masks for ATAPI_SM_STATE */ @@ -720,7 +593,6 @@ /* Bit masks for ATAPI_TERMINATE */ #define ATAPI_HOST_TERM 0x1 /* Host terminationation */ -#define nATAPI_HOST_TERM 0x0 /* Bit masks for ATAPI_REG_TIM_0 */ @@ -779,131 +651,77 @@ /* Bit masks for USB_POWER */ #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ -#define nENABLE_SUSPENDM 0x0 #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ -#define nSUSPEND_MODE 0x0 #define RESUME_MODE 0x4 /* DMA Mode */ -#define nRESUME_MODE 0x0 #define RESET 0x8 /* Reset indicator */ -#define nRESET 0x0 #define HS_MODE 0x10 /* High Speed mode indicator */ -#define nHS_MODE 0x0 #define HS_ENABLE 0x20 /* high Speed Enable */ -#define nHS_ENABLE 0x0 #define SOFT_CONN 0x40 /* Soft connect */ -#define nSOFT_CONN 0x0 #define ISO_UPDATE 0x80 /* Isochronous update */ -#define nISO_UPDATE 0x0 /* Bit masks for USB_INTRTX */ #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ -#define nEP0_TX 0x0 #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ -#define nEP1_TX 0x0 #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ -#define nEP2_TX 0x0 #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ -#define nEP3_TX 0x0 #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ -#define nEP4_TX 0x0 #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ -#define nEP5_TX 0x0 #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ -#define nEP6_TX 0x0 #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ -#define nEP7_TX 0x0 /* Bit masks for USB_INTRRX */ #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ -#define nEP1_RX 0x0 #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ -#define nEP2_RX 0x0 #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ -#define nEP3_RX 0x0 #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ -#define nEP4_RX 0x0 #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ -#define nEP5_RX 0x0 #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ -#define nEP6_RX 0x0 #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ -#define nEP7_RX 0x0 /* Bit masks for USB_INTRTXE */ #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ -#define nEP0_TX_E 0x0 #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ -#define nEP1_TX_E 0x0 #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ -#define nEP2_TX_E 0x0 #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ -#define nEP3_TX_E 0x0 #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ -#define nEP4_TX_E 0x0 #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ -#define nEP5_TX_E 0x0 #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ -#define nEP6_TX_E 0x0 #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ -#define nEP7_TX_E 0x0 /* Bit masks for USB_INTRRXE */ #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ -#define nEP1_RX_E 0x0 #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ -#define nEP2_RX_E 0x0 #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ -#define nEP3_RX_E 0x0 #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ -#define nEP4_RX_E 0x0 #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ -#define nEP5_RX_E 0x0 #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ -#define nEP6_RX_E 0x0 #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ -#define nEP7_RX_E 0x0 /* Bit masks for USB_INTRUSB */ #define SUSPEND_B 0x1 /* Suspend indicator */ -#define nSUSPEND_B 0x0 #define RESUME_B 0x2 /* Resume indicator */ -#define nRESUME_B 0x0 #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ -#define nRESET_OR_BABLE_B 0x0 #define SOF_B 0x8 /* Start of frame */ -#define nSOF_B 0x0 #define CONN_B 0x10 /* Connection indicator */ -#define nCONN_B 0x0 #define DISCON_B 0x20 /* Disconnect indicator */ -#define nDISCON_B 0x0 #define SESSION_REQ_B 0x40 /* Session Request */ -#define nSESSION_REQ_B 0x0 #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ -#define nVBUS_ERROR_B 0x0 /* Bit masks for USB_INTRUSBE */ #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ -#define nSUSPEND_BE 0x0 #define RESUME_BE 0x2 /* Resume indicator int enable */ -#define nRESUME_BE 0x0 #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ -#define nRESET_OR_BABLE_BE 0x0 #define SOF_BE 0x8 /* Start of frame int enable */ -#define nSOF_BE 0x0 #define CONN_BE 0x10 /* Connection indicator int enable */ -#define nCONN_BE 0x0 #define DISCON_BE 0x20 /* Disconnect indicator int enable */ -#define nDISCON_BE 0x0 #define SESSION_REQ_BE 0x40 /* Session Request int enable */ -#define nSESSION_REQ_BE 0x0 #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ -#define nVBUS_ERROR_BE 0x0 /* Bit masks for USB_FRAME */ @@ -916,117 +734,67 @@ /* Bit masks for USB_GLOBAL_CTL */ #define GLOBAL_ENA 0x1 /* enables USB module */ -#define nGLOBAL_ENA 0x0 #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ -#define nEP1_TX_ENA 0x0 #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ -#define nEP2_TX_ENA 0x0 #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ -#define nEP3_TX_ENA 0x0 #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ -#define nEP4_TX_ENA 0x0 #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ -#define nEP5_TX_ENA 0x0 #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ -#define nEP6_TX_ENA 0x0 #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ -#define nEP7_TX_ENA 0x0 #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ -#define nEP1_RX_ENA 0x0 #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ -#define nEP2_RX_ENA 0x0 #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ -#define nEP3_RX_ENA 0x0 #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ -#define nEP4_RX_ENA 0x0 #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ -#define nEP5_RX_ENA 0x0 #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ -#define nEP6_RX_ENA 0x0 #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ -#define nEP7_RX_ENA 0x0 /* Bit masks for USB_OTG_DEV_CTL */ #define SESSION 0x1 /* session indicator */ -#define nSESSION 0x0 #define HOST_REQ 0x2 /* Host negotiation request */ -#define nHOST_REQ 0x0 #define HOST_MODE 0x4 /* indicates USBDRC is a host */ -#define nHOST_MODE 0x0 #define VBUS0 0x8 /* Vbus level indicator[0] */ -#define nVBUS0 0x0 #define VBUS1 0x10 /* Vbus level indicator[1] */ -#define nVBUS1 0x0 #define LSDEV 0x20 /* Low-speed indicator */ -#define nLSDEV 0x0 #define FSDEV 0x40 /* Full or High-speed indicator */ -#define nFSDEV 0x0 #define B_DEVICE 0x80 /* A' or 'B' device indicator */ -#define nB_DEVICE 0x0 /* Bit masks for USB_OTG_VBUS_IRQ */ #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ -#define nDRIVE_VBUS_ON 0x0 #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ -#define nDRIVE_VBUS_OFF 0x0 #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ -#define nCHRG_VBUS_START 0x0 #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ -#define nCHRG_VBUS_END 0x0 #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ -#define nDISCHRG_VBUS_START 0x0 #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ -#define nDISCHRG_VBUS_END 0x0 /* Bit masks for USB_OTG_VBUS_MASK */ #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ -#define nDRIVE_VBUS_ON_ENA 0x0 #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ -#define nDRIVE_VBUS_OFF_ENA 0x0 #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ -#define nCHRG_VBUS_START_ENA 0x0 #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ -#define nCHRG_VBUS_END_ENA 0x0 #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ -#define nDISCHRG_VBUS_START_ENA 0x0 #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ -#define nDISCHRG_VBUS_END_ENA 0x0 /* Bit masks for USB_CSR0 */ #define RXPKTRDY 0x1 /* data packet receive indicator */ -#define nRXPKTRDY 0x0 #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ -#define nTXPKTRDY 0x0 #define STALL_SENT 0x4 /* STALL handshake sent */ -#define nSTALL_SENT 0x0 #define DATAEND 0x8 /* Data end indicator */ -#define nDATAEND 0x0 #define SETUPEND 0x10 /* Setup end */ -#define nSETUPEND 0x0 #define SENDSTALL 0x20 /* Send STALL handshake */ -#define nSENDSTALL 0x0 #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ -#define nSERVICED_RXPKTRDY 0x0 #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ -#define nSERVICED_SETUPEND 0x0 #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ -#define nFLUSHFIFO 0x0 #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ -#define nSTALL_RECEIVED_H 0x0 #define SETUPPKT_H 0x8 /* send Setup token host mode */ -#define nSETUPPKT_H 0x0 #define ERROR_H 0x10 /* timeout error indicator host mode */ -#define nERROR_H 0x0 #define REQPKT_H 0x20 /* Request an IN transaction host mode */ -#define nREQPKT_H 0x0 #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ -#define nSTATUSPKT_H 0x0 #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ -#define nNAK_TIMEOUT_H 0x0 /* Bit masks for USB_COUNT0 */ @@ -1047,37 +815,21 @@ /* Bit masks for USB_TXCSR */ #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ -#define nTXPKTRDY_T 0x0 #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ -#define nFIFO_NOT_EMPTY_T 0x0 #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ -#define nUNDERRUN_T 0x0 #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ -#define nFLUSHFIFO_T 0x0 #define STALL_SEND_T 0x10 /* issue a Stall handshake */ -#define nSTALL_SEND_T 0x0 #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ -#define nSTALL_SENT_T 0x0 #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ -#define nCLEAR_DATATOGGLE_T 0x0 #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ -#define nINCOMPTX_T 0x0 #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ -#define nDMAREQMODE_T 0x0 #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ -#define nFORCE_DATATOGGLE_T 0x0 #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ -#define nDMAREQ_ENA_T 0x0 #define ISO_T 0x4000 /* enable Isochronous transfers */ -#define nISO_T 0x0 #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ -#define nAUTOSET_T 0x0 #define ERROR_TH 0x4 /* error condition host mode */ -#define nERROR_TH 0x0 #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ -#define nSTALL_RECEIVED_TH 0x0 #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ -#define nNAK_TIMEOUT_TH 0x0 /* Bit masks for USB_TXCOUNT */ @@ -1086,45 +838,25 @@ /* Bit masks for USB_RXCSR */ #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ -#define nRXPKTRDY_R 0x0 #define FIFO_FULL_R 0x2 /* FIFO not empty */ -#define nFIFO_FULL_R 0x0 #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ -#define nOVERRUN_R 0x0 #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ -#define nDATAERROR_R 0x0 #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ -#define nFLUSHFIFO_R 0x0 #define STALL_SEND_R 0x20 /* issue a Stall handshake */ -#define nSTALL_SEND_R 0x0 #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ -#define nSTALL_SENT_R 0x0 #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ -#define nCLEAR_DATATOGGLE_R 0x0 #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ -#define nINCOMPRX_R 0x0 #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ -#define nDMAREQMODE_R 0x0 #define DISNYET_R 0x1000 /* disable Nyet handshakes */ -#define nDISNYET_R 0x0 #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ -#define nDMAREQ_ENA_R 0x0 #define ISO_R 0x4000 /* enable Isochronous transfers */ -#define nISO_R 0x0 #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ -#define nAUTOCLEAR_R 0x0 #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ -#define nERROR_RH 0x0 #define REQPKT_RH 0x20 /* request an IN transaction host mode */ -#define nREQPKT_RH 0x0 #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ -#define nSTALL_RECEIVED_RH 0x0 #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ -#define nINCOMPRX_RH 0x0 #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ -#define nDMAREQMODE_RH 0x0 #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ -#define nAUTOREQ_RH 0x0 /* Bit masks for USB_RXCOUNT */ @@ -1151,35 +883,22 @@ /* Bit masks for USB_DMA_INTERRUPT */ #define DMA0_INT 0x1 /* DMA0 pending interrupt */ -#define nDMA0_INT 0x0 #define DMA1_INT 0x2 /* DMA1 pending interrupt */ -#define nDMA1_INT 0x0 #define DMA2_INT 0x4 /* DMA2 pending interrupt */ -#define nDMA2_INT 0x0 #define DMA3_INT 0x8 /* DMA3 pending interrupt */ -#define nDMA3_INT 0x0 #define DMA4_INT 0x10 /* DMA4 pending interrupt */ -#define nDMA4_INT 0x0 #define DMA5_INT 0x20 /* DMA5 pending interrupt */ -#define nDMA5_INT 0x0 #define DMA6_INT 0x40 /* DMA6 pending interrupt */ -#define nDMA6_INT 0x0 #define DMA7_INT 0x80 /* DMA7 pending interrupt */ -#define nDMA7_INT 0x0 /* Bit masks for USB_DMAxCONTROL */ #define DMA_ENA 0x1 /* DMA enable */ -#define nDMA_ENA 0x0 #define DIRECTION 0x2 /* direction of DMA transfer */ -#define nDIRECTION 0x0 #define MODE 0x4 /* DMA Bus error */ -#define nMODE 0x0 #define INT_ENA 0x8 /* Interrupt enable */ -#define nINT_ENA 0x0 #define EPNUM 0xf0 /* EP number */ #define BUSERROR 0x100 /* DMA Bus error */ -#define nBUSERROR 0x0 /* Bit masks for USB_DMAxADDRHIGH */ diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h index 8fc77ea12aa9..dd955dcd39b8 100644 --- a/include/asm-blackfin/mach-bf548/defBF544.h +++ b/include/asm-blackfin/mach-bf548/defBF544.h @@ -538,21 +538,13 @@ /* Bit masks for PIXC_CTL */ #define PIXC_EN 0x1 /* Pixel Compositor Enable */ -#define nPIXC_EN 0x0 #define OVR_A_EN 0x2 /* Overlay A Enable */ -#define nOVR_A_EN 0x0 #define OVR_B_EN 0x4 /* Overlay B Enable */ -#define nOVR_B_EN 0x0 #define IMG_FORM 0x8 /* Image Data Format */ -#define nIMG_FORM 0x0 #define OVR_FORM 0x10 /* Overlay Data Format */ -#define nOVR_FORM 0x0 #define OUT_FORM 0x20 /* Output Data Format */ -#define nOUT_FORM 0x0 #define UDS_MOD 0x40 /* Resampling Mode */ -#define nUDS_MOD 0x0 #define TC_EN 0x80 /* Transparent Color Enable */ -#define nTC_EN 0x0 #define IMG_STAT 0x300 /* Image FIFO Status */ #define OVR_STAT 0xc00 /* Overlay FIFO Status */ #define WM_LVL 0x3000 /* FIFO Watermark Level */ @@ -600,13 +592,9 @@ /* Bit masks for PIXC_INTRSTAT */ #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ -#define nOVR_INT_EN 0x0 #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ -#define nFRM_INT_EN 0x0 #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ -#define nOVR_INT_STAT 0x0 #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ -#define nFRM_INT_STAT 0x0 /* Bit masks for PIXC_RYCON */ @@ -614,7 +602,6 @@ #define A12 0xffc00 /* A12 in the Coefficient Matrix */ #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ #define RY_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nRY_MULT4 0x0 /* Bit masks for PIXC_GUCON */ @@ -622,7 +609,6 @@ #define A22 0xffc00 /* A22 in the Coefficient Matrix */ #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ #define GU_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nGU_MULT4 0x0 /* Bit masks for PIXC_BVCON */ @@ -630,7 +616,6 @@ #define A32 0xffc00 /* A32 in the Coefficient Matrix */ #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ #define BV_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nBV_MULT4 0x0 /* Bit masks for PIXC_CCBIAS */ @@ -647,48 +632,28 @@ /* Bit masks for HOST_CONTROL */ #define HOST_EN 0x1 /* Host Enable */ -#define nHOST_EN 0x0 #define HOST_END 0x2 /* Host Endianess */ -#define nHOST_END 0x0 #define DATA_SIZE 0x4 /* Data Size */ -#define nDATA_SIZE 0x0 #define HOST_RST 0x8 /* Host Reset */ -#define nHOST_RST 0x0 #define HRDY_OVR 0x20 /* Host Ready Override */ -#define nHRDY_OVR 0x0 #define INT_MODE 0x40 /* Interrupt Mode */ -#define nINT_MODE 0x0 #define BT_EN 0x80 /* Bus Timeout Enable */ -#define nBT_EN 0x0 #define EHW 0x100 /* Enable Host Write */ -#define nEHW 0x0 #define EHR 0x200 /* Enable Host Read */ -#define nEHR 0x0 #define BDR 0x400 /* Burst DMA Requests */ -#define nBDR 0x0 /* Bit masks for HOST_STATUS */ #define READY 0x1 /* DMA Ready */ -#define nREADY 0x0 #define FIFOFULL 0x2 /* FIFO Full */ -#define nFIFOFULL 0x0 #define FIFOEMPTY 0x4 /* FIFO Empty */ -#define nFIFOEMPTY 0x0 #define COMPLETE 0x8 /* DMA Complete */ -#define nCOMPLETE 0x0 #define HSHK 0x10 /* Host Handshake */ -#define nHSHK 0x0 #define TIMEOUT 0x20 /* Host Timeout */ -#define nTIMEOUT 0x0 #define HIRQ 0x40 /* Host Interrupt Request */ -#define nHIRQ 0x0 #define ALLOW_CNFG 0x80 /* Allow New Configuration */ -#define nALLOW_CNFG 0x0 #define DMA_DIR 0x100 /* DMA Direction */ -#define nDMA_DIR 0x0 #define BTE 0x200 /* Bus Timeout Enabled */ -#define nBTE 0x0 /* Bit masks for HOST_TIMEOUT */ @@ -697,67 +662,42 @@ /* Bit masks for TIMER_ENABLE1 */ #define TIMEN8 0x1 /* Timer 8 Enable */ -#define nTIMEN8 0x0 #define TIMEN9 0x2 /* Timer 9 Enable */ -#define nTIMEN9 0x0 #define TIMEN10 0x4 /* Timer 10 Enable */ -#define nTIMEN10 0x0 /* Bit masks for TIMER_DISABLE1 */ #define TIMDIS8 0x1 /* Timer 8 Disable */ -#define nTIMDIS8 0x0 #define TIMDIS9 0x2 /* Timer 9 Disable */ -#define nTIMDIS9 0x0 #define TIMDIS10 0x4 /* Timer 10 Disable */ -#define nTIMDIS10 0x0 /* Bit masks for TIMER_STATUS1 */ #define TIMIL8 0x1 /* Timer 8 Interrupt */ -#define nTIMIL8 0x0 #define TIMIL9 0x2 /* Timer 9 Interrupt */ -#define nTIMIL9 0x0 #define TIMIL10 0x4 /* Timer 10 Interrupt */ -#define nTIMIL10 0x0 #define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ -#define nTOVF_ERR8 0x0 #define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ -#define nTOVF_ERR9 0x0 #define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ -#define nTOVF_ERR10 0x0 #define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ -#define nTRUN8 0x0 #define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ -#define nTRUN9 0x0 #define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ -#define nTRUN10 0x0 /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ /* Bit masks for HMDMAx_CONTROL */ #define HMDMAEN 0x1 /* Handshake MDMA Enable */ -#define nHMDMAEN 0x0 #define REP 0x2 /* Handshake MDMA Request Polarity */ -#define nREP 0x0 #define UTE 0x8 /* Urgency Threshold Enable */ -#define nUTE 0x0 #define OIE 0x10 /* Overflow Interrupt Enable */ -#define nOIE 0x0 #define BDIE 0x20 /* Block Done Interrupt Enable */ -#define nBDIE 0x0 #define MBDI 0x40 /* Mask Block Done Interrupt */ -#define nMBDI 0x0 #define DRQ 0x300 /* Handshake MDMA Request Type */ #define RBC 0x1000 /* Force Reload of BCOUNT */ -#define nRBC 0x0 #define PS 0x2000 /* Pin Status */ -#define nPS 0x0 #define OI 0x4000 /* Overflow Interrupt Generated */ -#define nOI 0x0 #define BDI 0x8000 /* Block Done Interrupt Generated */ -#define nBDI 0x0 /* ******************************************* */ /* MULTI BIT MACRO ENUMERATIONS */ diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h index d9e3062a9117..8d4214e0807c 100644 --- a/include/asm-blackfin/mach-bf548/defBF548.h +++ b/include/asm-blackfin/mach-bf548/defBF548.h @@ -899,21 +899,13 @@ /* Bit masks for PIXC_CTL */ #define PIXC_EN 0x1 /* Pixel Compositor Enable */ -#define nPIXC_EN 0x0 #define OVR_A_EN 0x2 /* Overlay A Enable */ -#define nOVR_A_EN 0x0 #define OVR_B_EN 0x4 /* Overlay B Enable */ -#define nOVR_B_EN 0x0 #define IMG_FORM 0x8 /* Image Data Format */ -#define nIMG_FORM 0x0 #define OVR_FORM 0x10 /* Overlay Data Format */ -#define nOVR_FORM 0x0 #define OUT_FORM 0x20 /* Output Data Format */ -#define nOUT_FORM 0x0 #define UDS_MOD 0x40 /* Resampling Mode */ -#define nUDS_MOD 0x0 #define TC_EN 0x80 /* Transparent Color Enable */ -#define nTC_EN 0x0 #define IMG_STAT 0x300 /* Image FIFO Status */ #define OVR_STAT 0xc00 /* Overlay FIFO Status */ #define WM_LVL 0x3000 /* FIFO Watermark Level */ @@ -961,13 +953,9 @@ /* Bit masks for PIXC_INTRSTAT */ #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ -#define nOVR_INT_EN 0x0 #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ -#define nFRM_INT_EN 0x0 #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ -#define nOVR_INT_STAT 0x0 #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ -#define nFRM_INT_STAT 0x0 /* Bit masks for PIXC_RYCON */ @@ -975,7 +963,6 @@ #define A12 0xffc00 /* A12 in the Coefficient Matrix */ #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ #define RY_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nRY_MULT4 0x0 /* Bit masks for PIXC_GUCON */ @@ -983,7 +970,6 @@ #define A22 0xffc00 /* A22 in the Coefficient Matrix */ #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ #define GU_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nGU_MULT4 0x0 /* Bit masks for PIXC_BVCON */ @@ -991,7 +977,6 @@ #define A32 0xffc00 /* A32 in the Coefficient Matrix */ #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ #define BV_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nBV_MULT4 0x0 /* Bit masks for PIXC_CCBIAS */ @@ -1008,48 +993,28 @@ /* Bit masks for HOST_CONTROL */ #define HOST_EN 0x1 /* Host Enable */ -#define nHOST_EN 0x0 #define HOST_END 0x2 /* Host Endianess */ -#define nHOST_END 0x0 #define DATA_SIZE 0x4 /* Data Size */ -#define nDATA_SIZE 0x0 #define HOST_RST 0x8 /* Host Reset */ -#define nHOST_RST 0x0 #define HRDY_OVR 0x20 /* Host Ready Override */ -#define nHRDY_OVR 0x0 #define INT_MODE 0x40 /* Interrupt Mode */ -#define nINT_MODE 0x0 #define BT_EN 0x80 /* Bus Timeout Enable */ -#define nBT_EN 0x0 #define EHW 0x100 /* Enable Host Write */ -#define nEHW 0x0 #define EHR 0x200 /* Enable Host Read */ -#define nEHR 0x0 #define BDR 0x400 /* Burst DMA Requests */ -#define nBDR 0x0 /* Bit masks for HOST_STATUS */ #define READY 0x1 /* DMA Ready */ -#define nREADY 0x0 #define FIFOFULL 0x2 /* FIFO Full */ -#define nFIFOFULL 0x0 #define FIFOEMPTY 0x4 /* FIFO Empty */ -#define nFIFOEMPTY 0x0 #define COMPLETE 0x8 /* DMA Complete */ -#define nCOMPLETE 0x0 #define HSHK 0x10 /* Host Handshake */ -#define nHSHK 0x0 #define TIMEOUT 0x20 /* Host Timeout */ -#define nTIMEOUT 0x0 #define HIRQ 0x40 /* Host Interrupt Request */ -#define nHIRQ 0x0 #define ALLOW_CNFG 0x80 /* Allow New Configuration */ -#define nALLOW_CNFG 0x0 #define DMA_DIR 0x100 /* DMA Direction */ -#define nDMA_DIR 0x0 #define BTE 0x200 /* Bus Timeout Enabled */ -#define nBTE 0x0 /* Bit masks for HOST_TIMEOUT */ @@ -1058,7 +1023,6 @@ /* Bit masks for KPAD_CTL */ #define KPAD_EN 0x1 /* Keypad Enable */ -#define nKPAD_EN 0x0 #define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ #define KPAD_ROWEN 0x1c00 /* Row Enable Width */ #define KPAD_COLEN 0xe000 /* Column Enable Width */ @@ -1080,29 +1044,21 @@ /* Bit masks for KPAD_STAT */ #define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ -#define nKPAD_IRQ 0x0 #define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ #define KPAD_PRESSED 0x8 /* Key press current status */ -#define nKPAD_PRESSED 0x0 /* Bit masks for KPAD_SOFTEVAL */ #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ -#define nKPAD_SOFTEVAL_E 0x0 /* Bit masks for SDH_COMMAND */ #define CMD_IDX 0x3f /* Command Index */ #define CMD_RSP 0x40 /* Response */ -#define nCMD_RSP 0x0 #define CMD_L_RSP 0x80 /* Long Response */ -#define nCMD_L_RSP 0x0 #define CMD_INT_E 0x100 /* Command Interrupt */ -#define nCMD_INT_E 0x0 #define CMD_PEND_E 0x200 /* Command Pending */ -#define nCMD_PEND_E 0x0 #define CMD_E 0x400 /* Command Enable */ -#define nCMD_E 0x0 /* Bit masks for SDH_PWR_CTL */ @@ -1111,21 +1067,15 @@ #define TBD 0x3c /* TBD */ #endif #define SD_CMD_OD 0x40 /* Open Drain Output */ -#define nSD_CMD_OD 0x0 #define ROD_CTL 0x80 /* Rod Control */ -#define nROD_CTL 0x0 /* Bit masks for SDH_CLK_CTL */ #define CLKDIV 0xff /* MC_CLK Divisor */ #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ -#define nCLK_E 0x0 #define PWR_SV_E 0x200 /* Power Save Enable */ -#define nPWR_SV_E 0x0 #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ -#define nCLKDIV_BYPASS 0x0 #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ -#define nWIDE_BUS 0x0 /* Bit masks for SDH_RESP_CMD */ @@ -1134,133 +1084,74 @@ /* Bit masks for SDH_DATA_CTL */ #define DTX_E 0x1 /* Data Transfer Enable */ -#define nDTX_E 0x0 #define DTX_DIR 0x2 /* Data Transfer Direction */ -#define nDTX_DIR 0x0 #define DTX_MODE 0x4 /* Data Transfer Mode */ -#define nDTX_MODE 0x0 #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ -#define nDTX_DMA_E 0x0 #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ /* Bit masks for SDH_STATUS */ #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ -#define nCMD_CRC_FAIL 0x0 #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ -#define nDAT_CRC_FAIL 0x0 #define CMD_TIMEOUT 0x4 /* CMD Time Out */ -#define nCMD_TIMEOUT 0x0 #define DAT_TIMEOUT 0x8 /* Data Time Out */ -#define nDAT_TIMEOUT 0x0 #define TX_UNDERRUN 0x10 /* Transmit Underrun */ -#define nTX_UNDERRUN 0x0 #define RX_OVERRUN 0x20 /* Receive Overrun */ -#define nRX_OVERRUN 0x0 #define CMD_RESP_END 0x40 /* CMD Response End */ -#define nCMD_RESP_END 0x0 #define CMD_SENT 0x80 /* CMD Sent */ -#define nCMD_SENT 0x0 #define DAT_END 0x100 /* Data End */ -#define nDAT_END 0x0 #define START_BIT_ERR 0x200 /* Start Bit Error */ -#define nSTART_BIT_ERR 0x0 #define DAT_BLK_END 0x400 /* Data Block End */ -#define nDAT_BLK_END 0x0 #define CMD_ACT 0x800 /* CMD Active */ -#define nCMD_ACT 0x0 #define TX_ACT 0x1000 /* Transmit Active */ -#define nTX_ACT 0x0 #define RX_ACT 0x2000 /* Receive Active */ -#define nRX_ACT 0x0 #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ -#define nTX_FIFO_STAT 0x0 #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ -#define nRX_FIFO_STAT 0x0 #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ -#define nTX_FIFO_FULL 0x0 #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ -#define nRX_FIFO_FULL 0x0 #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ -#define nTX_FIFO_ZERO 0x0 #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ -#define nRX_DAT_ZERO 0x0 #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ -#define nTX_DAT_RDY 0x0 #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ -#define nRX_FIFO_RDY 0x0 /* Bit masks for SDH_STATUS_CLR */ #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ -#define nCMD_CRC_FAIL_STAT 0x0 #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ -#define nDAT_CRC_FAIL_STAT 0x0 #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ -#define nCMD_TIMEOUT_STAT 0x0 #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ -#define nDAT_TIMEOUT_STAT 0x0 #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ -#define nTX_UNDERRUN_STAT 0x0 #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ -#define nRX_OVERRUN_STAT 0x0 #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ -#define nCMD_RESP_END_STAT 0x0 #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ -#define nCMD_SENT_STAT 0x0 #define DAT_END_STAT 0x100 /* Data End Status */ -#define nDAT_END_STAT 0x0 #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ -#define nSTART_BIT_ERR_STAT 0x0 #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ -#define nDAT_BLK_END_STAT 0x0 /* Bit masks for SDH_MASK0 */ #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ -#define nCMD_CRC_FAIL_MASK 0x0 #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ -#define nDAT_CRC_FAIL_MASK 0x0 #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ -#define nCMD_TIMEOUT_MASK 0x0 #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ -#define nDAT_TIMEOUT_MASK 0x0 #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ -#define nTX_UNDERRUN_MASK 0x0 #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ -#define nRX_OVERRUN_MASK 0x0 #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ -#define nCMD_RESP_END_MASK 0x0 #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ -#define nCMD_SENT_MASK 0x0 #define DAT_END_MASK 0x100 /* Data End Mask */ -#define nDAT_END_MASK 0x0 #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ -#define nSTART_BIT_ERR_MASK 0x0 #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ -#define nDAT_BLK_END_MASK 0x0 #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ -#define nCMD_ACT_MASK 0x0 #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ -#define nTX_ACT_MASK 0x0 #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ -#define nRX_ACT_MASK 0x0 #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ -#define nTX_FIFO_STAT_MASK 0x0 #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ -#define nRX_FIFO_STAT_MASK 0x0 #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ -#define nTX_FIFO_FULL_MASK 0x0 #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ -#define nRX_FIFO_FULL_MASK 0x0 #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ -#define nTX_FIFO_ZERO_MASK 0x0 #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ -#define nRX_DAT_ZERO_MASK 0x0 #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ -#define nTX_DAT_RDY_MASK 0x0 #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ -#define nRX_FIFO_RDY_MASK 0x0 /* Bit masks for SDH_FIFO_CNT */ @@ -1269,73 +1160,47 @@ /* Bit masks for SDH_E_STATUS */ #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ -#define nSDIO_INT_DET 0x0 #define SD_CARD_DET 0x10 /* SD Card Detect */ -#define nSD_CARD_DET 0x0 /* Bit masks for SDH_E_MASK */ #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ -#define nSDIO_MSK 0x0 #define SCD_MSK 0x40 /* Mask Card Detect */ -#define nSCD_MSK 0x0 /* Bit masks for SDH_CFG */ #define CLKS_EN 0x1 /* Clocks Enable */ -#define nCLKS_EN 0x0 #define SD4E 0x4 /* SDIO 4-Bit Enable */ -#define nSD4E 0x0 #define MWE 0x8 /* Moving Window Enable */ -#define nMWE 0x0 #define SD_RST 0x10 /* SDMMC Reset */ -#define nSD_RST 0x0 #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ -#define nPUP_SDDAT 0x0 #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ -#define nPUP_SDDAT3 0x0 #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ -#define nPD_SDDAT3 0x0 /* Bit masks for SDH_RD_WAIT_EN */ #define RWR 0x1 /* Read Wait Request */ -#define nRWR 0x0 /* Bit masks for ATAPI_CONTROL */ #define PIO_START 0x1 /* Start PIO/Reg Op */ -#define nPIO_START 0x0 #define MULTI_START 0x2 /* Start Multi-DMA Op */ -#define nMULTI_START 0x0 #define ULTRA_START 0x4 /* Start Ultra-DMA Op */ -#define nULTRA_START 0x0 #define XFER_DIR 0x8 /* Transfer Direction */ -#define nXFER_DIR 0x0 #define IORDY_EN 0x10 /* IORDY Enable */ -#define nIORDY_EN 0x0 #define FIFO_FLUSH 0x20 /* Flush FIFOs */ -#define nFIFO_FLUSH 0x0 #define SOFT_RST 0x40 /* Soft Reset */ -#define nSOFT_RST 0x0 #define DEV_RST 0x80 /* Device Reset */ -#define nDEV_RST 0x0 #define TFRCNT_RST 0x100 /* Trans Count Reset */ -#define nTFRCNT_RST 0x0 #define END_ON_TERM 0x200 /* End/Terminate Select */ -#define nEND_ON_TERM 0x0 #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ -#define nPIO_USE_DMA 0x0 #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ /* Bit masks for ATAPI_STATUS */ #define PIO_XFER_ON 0x1 /* PIO transfer in progress */ -#define nPIO_XFER_ON 0x0 #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ -#define nMULTI_XFER_ON 0x0 #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ -#define nULTRA_XFER_ON 0x0 #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ /* Bit masks for ATAPI_DEV_ADDR */ @@ -1345,66 +1210,39 @@ /* Bit masks for ATAPI_INT_MASK */ #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ -#define nATAPI_DEV_INT_MASK 0x0 #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ -#define nPIO_DONE_MASK 0x0 #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ -#define nMULTI_DONE_MASK 0x0 #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ -#define nUDMAIN_DONE_MASK 0x0 #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ -#define nUDMAOUT_DONE_MASK 0x0 #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ -#define nHOST_TERM_XFER_MASK 0x0 #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ -#define nMULTI_TERM_MASK 0x0 #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ -#define nUDMAIN_TERM_MASK 0x0 #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ -#define nUDMAOUT_TERM_MASK 0x0 /* Bit masks for ATAPI_INT_STATUS */ #define ATAPI_DEV_INT 0x1 /* Device interrupt status */ -#define nATAPI_DEV_INT 0x0 #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ -#define nPIO_DONE_INT 0x0 #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ -#define nMULTI_DONE_INT 0x0 #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ -#define nUDMAIN_DONE_INT 0x0 #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ -#define nUDMAOUT_DONE_INT 0x0 #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ -#define nHOST_TERM_XFER_INT 0x0 #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ -#define nMULTI_TERM_INT 0x0 #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ -#define nUDMAIN_TERM_INT 0x0 #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ -#define nUDMAOUT_TERM_INT 0x0 /* Bit masks for ATAPI_LINE_STATUS */ #define ATAPI_INTR 0x1 /* Device interrupt to host line status */ -#define nATAPI_INTR 0x0 #define ATAPI_DASP 0x2 /* Device dasp to host line status */ -#define nATAPI_DASP 0x0 #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ -#define nATAPI_CS0N 0x0 #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ -#define nATAPI_CS1N 0x0 #define ATAPI_ADDR 0x70 /* ATAPI address line status */ #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ -#define nATAPI_DMAREQ 0x0 #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ -#define nATAPI_DMAACKN 0x0 #define ATAPI_DIOWN 0x200 /* ATAPI write line status */ -#define nATAPI_DIOWN 0x0 #define ATAPI_DIORN 0x400 /* ATAPI read line status */ -#define nATAPI_DIORN 0x0 #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ -#define nATAPI_IORDY 0x0 /* Bit masks for ATAPI_SM_STATE */ @@ -1416,7 +1254,6 @@ /* Bit masks for ATAPI_TERMINATE */ #define ATAPI_HOST_TERM 0x1 /* Host terminationation */ -#define nATAPI_HOST_TERM 0x0 /* Bit masks for ATAPI_REG_TIM_0 */ @@ -1471,41 +1308,26 @@ /* Bit masks for TIMER_ENABLE1 */ #define TIMEN8 0x1 /* Timer 8 Enable */ -#define nTIMEN8 0x0 #define TIMEN9 0x2 /* Timer 9 Enable */ -#define nTIMEN9 0x0 #define TIMEN10 0x4 /* Timer 10 Enable */ -#define nTIMEN10 0x0 /* Bit masks for TIMER_DISABLE1 */ #define TIMDIS8 0x1 /* Timer 8 Disable */ -#define nTIMDIS8 0x0 #define TIMDIS9 0x2 /* Timer 9 Disable */ -#define nTIMDIS9 0x0 #define TIMDIS10 0x4 /* Timer 10 Disable */ -#define nTIMDIS10 0x0 /* Bit masks for TIMER_STATUS1 */ #define TIMIL8 0x1 /* Timer 8 Interrupt */ -#define nTIMIL8 0x0 #define TIMIL9 0x2 /* Timer 9 Interrupt */ -#define nTIMIL9 0x0 #define TIMIL10 0x4 /* Timer 10 Interrupt */ -#define nTIMIL10 0x0 #define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ -#define nTOVF_ERR8 0x0 #define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ -#define nTOVF_ERR9 0x0 #define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ -#define nTOVF_ERR10 0x0 #define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ -#define nTRUN8 0x0 #define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ -#define nTRUN9 0x0 #define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ -#define nTRUN10 0x0 /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ @@ -1516,131 +1338,77 @@ /* Bit masks for USB_POWER */ #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ -#define nENABLE_SUSPENDM 0x0 #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ -#define nSUSPEND_MODE 0x0 #define RESUME_MODE 0x4 /* DMA Mode */ -#define nRESUME_MODE 0x0 #define RESET 0x8 /* Reset indicator */ -#define nRESET 0x0 #define HS_MODE 0x10 /* High Speed mode indicator */ -#define nHS_MODE 0x0 #define HS_ENABLE 0x20 /* high Speed Enable */ -#define nHS_ENABLE 0x0 #define SOFT_CONN 0x40 /* Soft connect */ -#define nSOFT_CONN 0x0 #define ISO_UPDATE 0x80 /* Isochronous update */ -#define nISO_UPDATE 0x0 /* Bit masks for USB_INTRTX */ #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ -#define nEP0_TX 0x0 #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ -#define nEP1_TX 0x0 #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ -#define nEP2_TX 0x0 #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ -#define nEP3_TX 0x0 #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ -#define nEP4_TX 0x0 #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ -#define nEP5_TX 0x0 #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ -#define nEP6_TX 0x0 #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ -#define nEP7_TX 0x0 /* Bit masks for USB_INTRRX */ #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ -#define nEP1_RX 0x0 #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ -#define nEP2_RX 0x0 #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ -#define nEP3_RX 0x0 #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ -#define nEP4_RX 0x0 #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ -#define nEP5_RX 0x0 #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ -#define nEP6_RX 0x0 #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ -#define nEP7_RX 0x0 /* Bit masks for USB_INTRTXE */ #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ -#define nEP0_TX_E 0x0 #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ -#define nEP1_TX_E 0x0 #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ -#define nEP2_TX_E 0x0 #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ -#define nEP3_TX_E 0x0 #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ -#define nEP4_TX_E 0x0 #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ -#define nEP5_TX_E 0x0 #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ -#define nEP6_TX_E 0x0 #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ -#define nEP7_TX_E 0x0 /* Bit masks for USB_INTRRXE */ #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ -#define nEP1_RX_E 0x0 #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ -#define nEP2_RX_E 0x0 #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ -#define nEP3_RX_E 0x0 #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ -#define nEP4_RX_E 0x0 #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ -#define nEP5_RX_E 0x0 #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ -#define nEP6_RX_E 0x0 #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ -#define nEP7_RX_E 0x0 /* Bit masks for USB_INTRUSB */ #define SUSPEND_B 0x1 /* Suspend indicator */ -#define nSUSPEND_B 0x0 #define RESUME_B 0x2 /* Resume indicator */ -#define nRESUME_B 0x0 #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ -#define nRESET_OR_BABLE_B 0x0 #define SOF_B 0x8 /* Start of frame */ -#define nSOF_B 0x0 #define CONN_B 0x10 /* Connection indicator */ -#define nCONN_B 0x0 #define DISCON_B 0x20 /* Disconnect indicator */ -#define nDISCON_B 0x0 #define SESSION_REQ_B 0x40 /* Session Request */ -#define nSESSION_REQ_B 0x0 #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ -#define nVBUS_ERROR_B 0x0 /* Bit masks for USB_INTRUSBE */ #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ -#define nSUSPEND_BE 0x0 #define RESUME_BE 0x2 /* Resume indicator int enable */ -#define nRESUME_BE 0x0 #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ -#define nRESET_OR_BABLE_BE 0x0 #define SOF_BE 0x8 /* Start of frame int enable */ -#define nSOF_BE 0x0 #define CONN_BE 0x10 /* Connection indicator int enable */ -#define nCONN_BE 0x0 #define DISCON_BE 0x20 /* Disconnect indicator int enable */ -#define nDISCON_BE 0x0 #define SESSION_REQ_BE 0x40 /* Session Request int enable */ -#define nSESSION_REQ_BE 0x0 #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ -#define nVBUS_ERROR_BE 0x0 /* Bit masks for USB_FRAME */ @@ -1653,117 +1421,67 @@ /* Bit masks for USB_GLOBAL_CTL */ #define GLOBAL_ENA 0x1 /* enables USB module */ -#define nGLOBAL_ENA 0x0 #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ -#define nEP1_TX_ENA 0x0 #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ -#define nEP2_TX_ENA 0x0 #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ -#define nEP3_TX_ENA 0x0 #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ -#define nEP4_TX_ENA 0x0 #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ -#define nEP5_TX_ENA 0x0 #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ -#define nEP6_TX_ENA 0x0 #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ -#define nEP7_TX_ENA 0x0 #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ -#define nEP1_RX_ENA 0x0 #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ -#define nEP2_RX_ENA 0x0 #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ -#define nEP3_RX_ENA 0x0 #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ -#define nEP4_RX_ENA 0x0 #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ -#define nEP5_RX_ENA 0x0 #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ -#define nEP6_RX_ENA 0x0 #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ -#define nEP7_RX_ENA 0x0 /* Bit masks for USB_OTG_DEV_CTL */ #define SESSION 0x1 /* session indicator */ -#define nSESSION 0x0 #define HOST_REQ 0x2 /* Host negotiation request */ -#define nHOST_REQ 0x0 #define HOST_MODE 0x4 /* indicates USBDRC is a host */ -#define nHOST_MODE 0x0 #define VBUS0 0x8 /* Vbus level indicator[0] */ -#define nVBUS0 0x0 #define VBUS1 0x10 /* Vbus level indicator[1] */ -#define nVBUS1 0x0 #define LSDEV 0x20 /* Low-speed indicator */ -#define nLSDEV 0x0 #define FSDEV 0x40 /* Full or High-speed indicator */ -#define nFSDEV 0x0 #define B_DEVICE 0x80 /* A' or 'B' device indicator */ -#define nB_DEVICE 0x0 /* Bit masks for USB_OTG_VBUS_IRQ */ #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ -#define nDRIVE_VBUS_ON 0x0 #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ -#define nDRIVE_VBUS_OFF 0x0 #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ -#define nCHRG_VBUS_START 0x0 #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ -#define nCHRG_VBUS_END 0x0 #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ -#define nDISCHRG_VBUS_START 0x0 #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ -#define nDISCHRG_VBUS_END 0x0 /* Bit masks for USB_OTG_VBUS_MASK */ #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ -#define nDRIVE_VBUS_ON_ENA 0x0 #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ -#define nDRIVE_VBUS_OFF_ENA 0x0 #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ -#define nCHRG_VBUS_START_ENA 0x0 #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ -#define nCHRG_VBUS_END_ENA 0x0 #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ -#define nDISCHRG_VBUS_START_ENA 0x0 #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ -#define nDISCHRG_VBUS_END_ENA 0x0 /* Bit masks for USB_CSR0 */ #define RXPKTRDY 0x1 /* data packet receive indicator */ -#define nRXPKTRDY 0x0 #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ -#define nTXPKTRDY 0x0 #define STALL_SENT 0x4 /* STALL handshake sent */ -#define nSTALL_SENT 0x0 #define DATAEND 0x8 /* Data end indicator */ -#define nDATAEND 0x0 #define SETUPEND 0x10 /* Setup end */ -#define nSETUPEND 0x0 #define SENDSTALL 0x20 /* Send STALL handshake */ -#define nSENDSTALL 0x0 #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ -#define nSERVICED_RXPKTRDY 0x0 #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ -#define nSERVICED_SETUPEND 0x0 #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ -#define nFLUSHFIFO 0x0 #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ -#define nSTALL_RECEIVED_H 0x0 #define SETUPPKT_H 0x8 /* send Setup token host mode */ -#define nSETUPPKT_H 0x0 #define ERROR_H 0x10 /* timeout error indicator host mode */ -#define nERROR_H 0x0 #define REQPKT_H 0x20 /* Request an IN transaction host mode */ -#define nREQPKT_H 0x0 #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ -#define nSTATUSPKT_H 0x0 #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ -#define nNAK_TIMEOUT_H 0x0 /* Bit masks for USB_COUNT0 */ @@ -1784,37 +1502,21 @@ /* Bit masks for USB_TXCSR */ #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ -#define nTXPKTRDY_T 0x0 #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ -#define nFIFO_NOT_EMPTY_T 0x0 #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ -#define nUNDERRUN_T 0x0 #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ -#define nFLUSHFIFO_T 0x0 #define STALL_SEND_T 0x10 /* issue a Stall handshake */ -#define nSTALL_SEND_T 0x0 #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ -#define nSTALL_SENT_T 0x0 #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ -#define nCLEAR_DATATOGGLE_T 0x0 #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ -#define nINCOMPTX_T 0x0 #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ -#define nDMAREQMODE_T 0x0 #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ -#define nFORCE_DATATOGGLE_T 0x0 #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ -#define nDMAREQ_ENA_T 0x0 #define ISO_T 0x4000 /* enable Isochronous transfers */ -#define nISO_T 0x0 #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ -#define nAUTOSET_T 0x0 #define ERROR_TH 0x4 /* error condition host mode */ -#define nERROR_TH 0x0 #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ -#define nSTALL_RECEIVED_TH 0x0 #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ -#define nNAK_TIMEOUT_TH 0x0 /* Bit masks for USB_TXCOUNT */ @@ -1823,45 +1525,25 @@ /* Bit masks for USB_RXCSR */ #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ -#define nRXPKTRDY_R 0x0 #define FIFO_FULL_R 0x2 /* FIFO not empty */ -#define nFIFO_FULL_R 0x0 #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ -#define nOVERRUN_R 0x0 #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ -#define nDATAERROR_R 0x0 #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ -#define nFLUSHFIFO_R 0x0 #define STALL_SEND_R 0x20 /* issue a Stall handshake */ -#define nSTALL_SEND_R 0x0 #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ -#define nSTALL_SENT_R 0x0 #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ -#define nCLEAR_DATATOGGLE_R 0x0 #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ -#define nINCOMPRX_R 0x0 #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ -#define nDMAREQMODE_R 0x0 #define DISNYET_R 0x1000 /* disable Nyet handshakes */ -#define nDISNYET_R 0x0 #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ -#define nDMAREQ_ENA_R 0x0 #define ISO_R 0x4000 /* enable Isochronous transfers */ -#define nISO_R 0x0 #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ -#define nAUTOCLEAR_R 0x0 #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ -#define nERROR_RH 0x0 #define REQPKT_RH 0x20 /* request an IN transaction host mode */ -#define nREQPKT_RH 0x0 #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ -#define nSTALL_RECEIVED_RH 0x0 #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ -#define nINCOMPRX_RH 0x0 #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ -#define nDMAREQMODE_RH 0x0 #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ -#define nAUTOREQ_RH 0x0 /* Bit masks for USB_RXCOUNT */ @@ -1888,35 +1570,22 @@ /* Bit masks for USB_DMA_INTERRUPT */ #define DMA0_INT 0x1 /* DMA0 pending interrupt */ -#define nDMA0_INT 0x0 #define DMA1_INT 0x2 /* DMA1 pending interrupt */ -#define nDMA1_INT 0x0 #define DMA2_INT 0x4 /* DMA2 pending interrupt */ -#define nDMA2_INT 0x0 #define DMA3_INT 0x8 /* DMA3 pending interrupt */ -#define nDMA3_INT 0x0 #define DMA4_INT 0x10 /* DMA4 pending interrupt */ -#define nDMA4_INT 0x0 #define DMA5_INT 0x20 /* DMA5 pending interrupt */ -#define nDMA5_INT 0x0 #define DMA6_INT 0x40 /* DMA6 pending interrupt */ -#define nDMA6_INT 0x0 #define DMA7_INT 0x80 /* DMA7 pending interrupt */ -#define nDMA7_INT 0x0 /* Bit masks for USB_DMAxCONTROL */ #define DMA_ENA 0x1 /* DMA enable */ -#define nDMA_ENA 0x0 #define DIRECTION 0x2 /* direction of DMA transfer */ -#define nDIRECTION 0x0 #define MODE 0x4 /* DMA Bus error */ -#define nMODE 0x0 #define INT_ENA 0x8 /* Interrupt enable */ -#define nINT_ENA 0x0 #define EPNUM 0xf0 /* EP number */ #define BUSERROR 0x100 /* DMA Bus error */ -#define nBUSERROR 0x0 /* Bit masks for USB_DMAxADDRHIGH */ @@ -1937,26 +1606,16 @@ /* Bit masks for HMDMAx_CONTROL */ #define HMDMAEN 0x1 /* Handshake MDMA Enable */ -#define nHMDMAEN 0x0 #define REP 0x2 /* Handshake MDMA Request Polarity */ -#define nREP 0x0 #define UTE 0x8 /* Urgency Threshold Enable */ -#define nUTE 0x0 #define OIE 0x10 /* Overflow Interrupt Enable */ -#define nOIE 0x0 #define BDIE 0x20 /* Block Done Interrupt Enable */ -#define nBDIE 0x0 #define MBDI 0x40 /* Mask Block Done Interrupt */ -#define nMBDI 0x0 #define DRQ 0x300 /* Handshake MDMA Request Type */ #define RBC 0x1000 /* Force Reload of BCOUNT */ -#define nRBC 0x0 #define PS 0x2000 /* Pin Status */ -#define nPS 0x0 #define OI 0x4000 /* Overflow Interrupt Generated */ -#define nOI 0x0 #define BDI 0x8000 /* Block Done Interrupt Generated */ -#define nBDI 0x0 /* ******************************************* */ /* MULTI BIT MACRO ENUMERATIONS */ diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h index b1cc1c073b41..c2f4734da48d 100644 --- a/include/asm-blackfin/mach-bf548/defBF549.h +++ b/include/asm-blackfin/mach-bf548/defBF549.h @@ -1070,21 +1070,13 @@ /* Bit masks for PIXC_CTL */ #define PIXC_EN 0x1 /* Pixel Compositor Enable */ -#define nPIXC_EN 0x0 #define OVR_A_EN 0x2 /* Overlay A Enable */ -#define nOVR_A_EN 0x0 #define OVR_B_EN 0x4 /* Overlay B Enable */ -#define nOVR_B_EN 0x0 #define IMG_FORM 0x8 /* Image Data Format */ -#define nIMG_FORM 0x0 #define OVR_FORM 0x10 /* Overlay Data Format */ -#define nOVR_FORM 0x0 #define OUT_FORM 0x20 /* Output Data Format */ -#define nOUT_FORM 0x0 #define UDS_MOD 0x40 /* Resampling Mode */ -#define nUDS_MOD 0x0 #define TC_EN 0x80 /* Transparent Color Enable */ -#define nTC_EN 0x0 #define IMG_STAT 0x300 /* Image FIFO Status */ #define OVR_STAT 0xc00 /* Overlay FIFO Status */ #define WM_LVL 0x3000 /* FIFO Watermark Level */ @@ -1132,13 +1124,9 @@ /* Bit masks for PIXC_INTRSTAT */ #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ -#define nOVR_INT_EN 0x0 #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ -#define nFRM_INT_EN 0x0 #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ -#define nOVR_INT_STAT 0x0 #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ -#define nFRM_INT_STAT 0x0 /* Bit masks for PIXC_RYCON */ @@ -1146,7 +1134,6 @@ #define A12 0xffc00 /* A12 in the Coefficient Matrix */ #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ #define RY_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nRY_MULT4 0x0 /* Bit masks for PIXC_GUCON */ @@ -1154,7 +1141,6 @@ #define A22 0xffc00 /* A22 in the Coefficient Matrix */ #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ #define GU_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nGU_MULT4 0x0 /* Bit masks for PIXC_BVCON */ @@ -1162,7 +1148,6 @@ #define A32 0xffc00 /* A32 in the Coefficient Matrix */ #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ #define BV_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nBV_MULT4 0x0 /* Bit masks for PIXC_CCBIAS */ @@ -1179,48 +1164,28 @@ /* Bit masks for HOST_CONTROL */ #define HOST_EN 0x1 /* Host Enable */ -#define nHOST_EN 0x0 #define HOST_END 0x2 /* Host Endianess */ -#define nHOST_END 0x0 #define DATA_SIZE 0x4 /* Data Size */ -#define nDATA_SIZE 0x0 #define HOST_RST 0x8 /* Host Reset */ -#define nHOST_RST 0x0 #define HRDY_OVR 0x20 /* Host Ready Override */ -#define nHRDY_OVR 0x0 #define INT_MODE 0x40 /* Interrupt Mode */ -#define nINT_MODE 0x0 #define BT_EN 0x80 /* Bus Timeout Enable */ -#define nBT_EN 0x0 #define EHW 0x100 /* Enable Host Write */ -#define nEHW 0x0 #define EHR 0x200 /* Enable Host Read */ -#define nEHR 0x0 #define BDR 0x400 /* Burst DMA Requests */ -#define nBDR 0x0 /* Bit masks for HOST_STATUS */ #define READY 0x1 /* DMA Ready */ -#define nREADY 0x0 #define FIFOFULL 0x2 /* FIFO Full */ -#define nFIFOFULL 0x0 #define FIFOEMPTY 0x4 /* FIFO Empty */ -#define nFIFOEMPTY 0x0 -#define COMPLETE 0x8 /* DMA Complete */ -#define nCOMPLETE 0x0 +#define DMA_COMPLETE 0x8 /* DMA Complete */ #define HSHK 0x10 /* Host Handshake */ -#define nHSHK 0x0 #define TIMEOUT 0x20 /* Host Timeout */ -#define nTIMEOUT 0x0 #define HIRQ 0x40 /* Host Interrupt Request */ -#define nHIRQ 0x0 #define ALLOW_CNFG 0x80 /* Allow New Configuration */ -#define nALLOW_CNFG 0x0 #define DMA_DIR 0x100 /* DMA Direction */ -#define nDMA_DIR 0x0 #define BTE 0x200 /* Bus Timeout Enabled */ -#define nBTE 0x0 /* Bit masks for HOST_TIMEOUT */ @@ -1229,71 +1194,41 @@ /* Bit masks for MXVR_CONFIG */ #define MXVREN 0x1 /* MXVR Enable */ -#define nMXVREN 0x0 #define MMSM 0x2 /* MXVR Master/Slave Mode Select */ -#define nMMSM 0x0 #define ACTIVE 0x4 /* Active Mode */ -#define nACTIVE 0x0 #define SDELAY 0x8 /* Synchronous Data Delay */ -#define nSDELAY 0x0 #define NCMRXEN 0x10 /* Normal Control Message Receive Enable */ -#define nNCMRXEN 0x0 #define RWRRXEN 0x20 /* Remote Write Receive Enable */ -#define nRWRRXEN 0x0 #define MTXEN 0x40 /* MXVR Transmit Data Enable */ -#define nMTXEN 0x0 #define MTXONB 0x80 /* MXVR Phy Transmitter On */ -#define nMTXONB 0x0 #define EPARITY 0x100 /* Even Parity Select */ -#define nEPARITY 0x0 #define MSB 0x1e00 /* Master Synchronous Boundary */ #define APRXEN 0x2000 /* Asynchronous Packet Receive Enable */ -#define nAPRXEN 0x0 #define WAKEUP 0x4000 /* Wake-Up */ -#define nWAKEUP 0x0 #define LMECH 0x8000 /* Lock Mechanism Select */ -#define nLMECH 0x0 /* Bit masks for MXVR_STATE_0 */ #define NACT 0x1 /* Network Activity */ -#define nNACT 0x0 #define SBLOCK 0x2 /* Super Block Lock */ -#define nSBLOCK 0x0 #define FMPLLST 0xc /* Frequency Multiply PLL SM State */ #define CDRPLLST 0xe0 /* Clock/Data Recovery PLL SM State */ #define APBSY 0x100 /* Asynchronous Packet Transmit Buffer Busy */ -#define nAPBSY 0x0 #define APARB 0x200 /* Asynchronous Packet Arbitrating */ -#define nAPARB 0x0 #define APTX 0x400 /* Asynchronous Packet Transmitting */ -#define nAPTX 0x0 #define APRX 0x800 /* Receiving Asynchronous Packet */ -#define nAPRX 0x0 #define CMBSY 0x1000 /* Control Message Transmit Buffer Busy */ -#define nCMBSY 0x0 #define CMARB 0x2000 /* Control Message Arbitrating */ -#define nCMARB 0x0 #define CMTX 0x4000 /* Control Message Transmitting */ -#define nCMTX 0x0 #define CMRX 0x8000 /* Receiving Control Message */ -#define nCMRX 0x0 #define MRXONB 0x10000 /* MRXONB Pin State */ -#define nMRXONB 0x0 #define RGSIP 0x20000 /* Remote Get Source In Progress */ -#define nRGSIP 0x0 #define DALIP 0x40000 /* Resource Deallocate In Progress */ -#define nDALIP 0x0 #define ALIP 0x80000 /* Resource Allocate In Progress */ -#define nALIP 0x0 #define RRDIP 0x100000 /* Remote Read In Progress */ -#define nRRDIP 0x0 #define RWRIP 0x200000 /* Remote Write In Progress */ -#define nRWRIP 0x0 #define FLOCK 0x400000 /* Frame Lock */ -#define nFLOCK 0x0 #define BLOCK 0x800000 /* Block Lock */ -#define nBLOCK 0x0 #define RSB 0xf000000 /* Received Synchronous Boundary */ #define DERRNUM 0xf0000000 /* DMA Error Channel Number */ @@ -1302,535 +1237,343 @@ #define SRXNUMB 0xf /* Synchronous Receive FIFO Number of Bytes */ #define STXNUMB 0xf0 /* Synchronous Transmit FIFO Number of Bytes */ #define APCONT 0x100 /* Asynchronous Packet Continuation */ -#define nAPCONT 0x0 #define OBERRNUM 0xe00 /* DMA Out of Bounds Error Channel Number */ #define DMAACTIVE0 0x10000 /* DMA0 Active */ -#define nDMAACTIVE0 0x0 #define DMAACTIVE1 0x20000 /* DMA1 Active */ -#define nDMAACTIVE1 0x0 #define DMAACTIVE2 0x40000 /* DMA2 Active */ -#define nDMAACTIVE2 0x0 #define DMAACTIVE3 0x80000 /* DMA3 Active */ -#define nDMAACTIVE3 0x0 #define DMAACTIVE4 0x100000 /* DMA4 Active */ -#define nDMAACTIVE4 0x0 #define DMAACTIVE5 0x200000 /* DMA5 Active */ -#define nDMAACTIVE5 0x0 #define DMAACTIVE6 0x400000 /* DMA6 Active */ -#define nDMAACTIVE6 0x0 #define DMAACTIVE7 0x800000 /* DMA7 Active */ -#define nDMAACTIVE7 0x0 #define DMAPMEN0 0x1000000 /* DMA0 Pattern Matching Enabled */ -#define nDMAPMEN0 0x0 #define DMAPMEN1 0x2000000 /* DMA1 Pattern Matching Enabled */ -#define nDMAPMEN1 0x0 #define DMAPMEN2 0x4000000 /* DMA2 Pattern Matching Enabled */ -#define nDMAPMEN2 0x0 #define DMAPMEN3 0x8000000 /* DMA3 Pattern Matching Enabled */ -#define nDMAPMEN3 0x0 #define DMAPMEN4 0x10000000 /* DMA4 Pattern Matching Enabled */ -#define nDMAPMEN4 0x0 #define DMAPMEN5 0x20000000 /* DMA5 Pattern Matching Enabled */ -#define nDMAPMEN5 0x0 #define DMAPMEN6 0x40000000 /* DMA6 Pattern Matching Enabled */ -#define nDMAPMEN6 0x0 #define DMAPMEN7 0x80000000 /* DMA7 Pattern Matching Enabled */ -#define nDMAPMEN7 0x0 /* Bit masks for MXVR_INT_STAT_0 */ #define NI2A 0x1 /* Network Inactive to Active */ -#define nNI2A 0x0 #define NA2I 0x2 /* Network Active to Inactive */ -#define nNA2I 0x0 #define SBU2L 0x4 /* Super Block Unlock to Lock */ -#define nSBU2L 0x0 #define SBL2U 0x8 /* Super Block Lock to Unlock */ -#define nSBL2U 0x0 #define PRU 0x10 /* Position Register Updated */ -#define nPRU 0x0 #define MPRU 0x20 /* Maximum Position Register Updated */ -#define nMPRU 0x0 #define DRU 0x40 /* Delay Register Updated */ -#define nDRU 0x0 #define MDRU 0x80 /* Maximum Delay Register Updated */ -#define nMDRU 0x0 #define SBU 0x100 /* Synchronous Boundary Updated */ -#define nSBU 0x0 #define ATU 0x200 /* Allocation Table Updated */ -#define nATU 0x0 #define FCZ0 0x400 /* Frame Counter 0 Zero */ -#define nFCZ0 0x0 #define FCZ1 0x800 /* Frame Counter 1 Zero */ -#define nFCZ1 0x0 #define PERR 0x1000 /* Parity Error */ -#define nPERR 0x0 #define MH2L 0x2000 /* MRXONB High to Low */ -#define nMH2L 0x0 #define ML2H 0x4000 /* MRXONB Low to High */ -#define nML2H 0x0 #define WUP 0x8000 /* Wake-Up Preamble Received */ -#define nWUP 0x0 #define FU2L 0x10000 /* Frame Unlock to Lock */ -#define nFU2L 0x0 #define FL2U 0x20000 /* Frame Lock to Unlock */ -#define nFL2U 0x0 #define BU2L 0x40000 /* Block Unlock to Lock */ -#define nBU2L 0x0 #define BL2U 0x80000 /* Block Lock to Unlock */ -#define nBL2U 0x0 #define OBERR 0x100000 /* DMA Out of Bounds Error */ -#define nOBERR 0x0 #define PFL 0x200000 /* PLL Frequency Locked */ -#define nPFL 0x0 #define SCZ 0x400000 /* System Clock Counter Zero */ -#define nSCZ 0x0 #define FERR 0x800000 /* FIFO Error */ -#define nFERR 0x0 #define CMR 0x1000000 /* Control Message Received */ -#define nCMR 0x0 #define CMROF 0x2000000 /* Control Message Receive Buffer Overflow */ -#define nCMROF 0x0 #define CMTS 0x4000000 /* Control Message Transmit Buffer Successfully Sent */ -#define nCMTS 0x0 #define CMTC 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled */ -#define nCMTC 0x0 #define RWRC 0x10000000 /* Remote Write Control Message Completed */ -#define nRWRC 0x0 #define BCZ 0x20000000 /* Block Counter Zero */ -#define nBCZ 0x0 #define BMERR 0x40000000 /* Biphase Mark Coding Error */ -#define nBMERR 0x0 #define DERR 0x80000000 /* DMA Error */ -#define nDERR 0x0 /* Bit masks for MXVR_INT_STAT_1 */ #define HDONE0 0x1 /* DMA0 Half Done */ -#define nHDONE0 0x0 #define DONE0 0x2 /* DMA0 Done */ -#define nDONE0 0x0 #define APR 0x4 /* Asynchronous Packet Received */ -#define nAPR 0x0 #define APROF 0x8 /* Asynchronous Packet Receive Buffer Overflow */ -#define nAPROF 0x0 #define HDONE1 0x10 /* DMA1 Half Done */ -#define nHDONE1 0x0 #define DONE1 0x20 /* DMA1 Done */ -#define nDONE1 0x0 #define APTS 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent */ -#define nAPTS 0x0 #define APTC 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled */ -#define nAPTC 0x0 #define HDONE2 0x100 /* DMA2 Half Done */ -#define nHDONE2 0x0 #define DONE2 0x200 /* DMA2 Done */ -#define nDONE2 0x0 #define APRCE 0x400 /* Asynchronous Packet Receive CRC Error */ -#define nAPRCE 0x0 #define APRPE 0x800 /* Asynchronous Packet Receive Packet Error */ -#define nAPRPE 0x0 #define HDONE3 0x1000 /* DMA3 Half Done */ -#define nHDONE3 0x0 #define DONE3 0x2000 /* DMA3 Done */ -#define nDONE3 0x0 #define HDONE4 0x10000 /* DMA4 Half Done */ -#define nHDONE4 0x0 #define DONE4 0x20000 /* DMA4 Done */ -#define nDONE4 0x0 #define HDONE5 0x100000 /* DMA5 Half Done */ -#define nHDONE5 0x0 #define DONE5 0x200000 /* DMA5 Done */ -#define nDONE5 0x0 #define HDONE6 0x1000000 /* DMA6 Half Done */ -#define nHDONE6 0x0 #define DONE6 0x2000000 /* DMA6 Done */ -#define nDONE6 0x0 #define HDONE7 0x10000000 /* DMA7 Half Done */ -#define nHDONE7 0x0 #define DONE7 0x20000000 /* DMA7 Done */ -#define nDONE7 0x0 /* Bit masks for MXVR_INT_EN_0 */ #define NI2AEN 0x1 /* Network Inactive to Active Interrupt Enable */ -#define nNI2AEN 0x0 #define NA2IEN 0x2 /* Network Active to Inactive Interrupt Enable */ -#define nNA2IEN 0x0 #define SBU2LEN 0x4 /* Super Block Unlock to Lock Interrupt Enable */ -#define nSBU2LEN 0x0 #define SBL2UEN 0x8 /* Super Block Lock to Unlock Interrupt Enable */ -#define nSBL2UEN 0x0 #define PRUEN 0x10 /* Position Register Updated Interrupt Enable */ -#define nPRUEN 0x0 #define MPRUEN 0x20 /* Maximum Position Register Updated Interrupt Enable */ -#define nMPRUEN 0x0 #define DRUEN 0x40 /* Delay Register Updated Interrupt Enable */ -#define nDRUEN 0x0 #define MDRUEN 0x80 /* Maximum Delay Register Updated Interrupt Enable */ -#define nMDRUEN 0x0 #define SBUEN 0x100 /* Synchronous Boundary Updated Interrupt Enable */ -#define nSBUEN 0x0 #define ATUEN 0x200 /* Allocation Table Updated Interrupt Enable */ -#define nATUEN 0x0 #define FCZ0EN 0x400 /* Frame Counter 0 Zero Interrupt Enable */ -#define nFCZ0EN 0x0 #define FCZ1EN 0x800 /* Frame Counter 1 Zero Interrupt Enable */ -#define nFCZ1EN 0x0 #define PERREN 0x1000 /* Parity Error Interrupt Enable */ -#define nPERREN 0x0 #define MH2LEN 0x2000 /* MRXONB High to Low Interrupt Enable */ -#define nMH2LEN 0x0 #define ML2HEN 0x4000 /* MRXONB Low to High Interrupt Enable */ -#define nML2HEN 0x0 #define WUPEN 0x8000 /* Wake-Up Preamble Received Interrupt Enable */ -#define nWUPEN 0x0 #define FU2LEN 0x10000 /* Frame Unlock to Lock Interrupt Enable */ -#define nFU2LEN 0x0 #define FL2UEN 0x20000 /* Frame Lock to Unlock Interrupt Enable */ -#define nFL2UEN 0x0 #define BU2LEN 0x40000 /* Block Unlock to Lock Interrupt Enable */ -#define nBU2LEN 0x0 #define BL2UEN 0x80000 /* Block Lock to Unlock Interrupt Enable */ -#define nBL2UEN 0x0 #define OBERREN 0x100000 /* DMA Out of Bounds Error Interrupt Enable */ -#define nOBERREN 0x0 #define PFLEN 0x200000 /* PLL Frequency Locked Interrupt Enable */ -#define nPFLEN 0x0 #define SCZEN 0x400000 /* System Clock Counter Zero Interrupt Enable */ -#define nSCZEN 0x0 #define FERREN 0x800000 /* FIFO Error Interrupt Enable */ -#define nFERREN 0x0 #define CMREN 0x1000000 /* Control Message Received Interrupt Enable */ -#define nCMREN 0x0 #define CMROFEN 0x2000000 /* Control Message Receive Buffer Overflow Interrupt Enable */ -#define nCMROFEN 0x0 #define CMTSEN 0x4000000 /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */ -#define nCMTSEN 0x0 #define CMTCEN 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */ -#define nCMTCEN 0x0 #define RWRCEN 0x10000000 /* Remote Write Control Message Completed Interrupt Enable */ -#define nRWRCEN 0x0 #define BCZEN 0x20000000 /* Block Counter Zero Interrupt Enable */ -#define nBCZEN 0x0 #define BMERREN 0x40000000 /* Biphase Mark Coding Error Interrupt Enable */ -#define nBMERREN 0x0 #define DERREN 0x80000000 /* DMA Error Interrupt Enable */ -#define nDERREN 0x0 /* Bit masks for MXVR_INT_EN_1 */ #define HDONEEN0 0x1 /* DMA0 Half Done Interrupt Enable */ -#define nHDONEEN0 0x0 #define DONEEN0 0x2 /* DMA0 Done Interrupt Enable */ -#define nDONEEN0 0x0 #define APREN 0x4 /* Asynchronous Packet Received Interrupt Enable */ -#define nAPREN 0x0 #define APROFEN 0x8 /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */ -#define nAPROFEN 0x0 #define HDONEEN1 0x10 /* DMA1 Half Done Interrupt Enable */ -#define nHDONEEN1 0x0 #define DONEEN1 0x20 /* DMA1 Done Interrupt Enable */ -#define nDONEEN1 0x0 #define APTSEN 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */ -#define nAPTSEN 0x0 #define APTCEN 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */ -#define nAPTCEN 0x0 #define HDONEEN2 0x100 /* DMA2 Half Done Interrupt Enable */ -#define nHDONEEN2 0x0 #define DONEEN2 0x200 /* DMA2 Done Interrupt Enable */ -#define nDONEEN2 0x0 #define APRCEEN 0x400 /* Asynchronous Packet Receive CRC Error Interrupt Enable */ -#define nAPRCEEN 0x0 #define APRPEEN 0x800 /* Asynchronous Packet Receive Packet Error Interrupt Enable */ -#define nAPRPEEN 0x0 #define HDONEEN3 0x1000 /* DMA3 Half Done Interrupt Enable */ -#define nHDONEEN3 0x0 #define DONEEN3 0x2000 /* DMA3 Done Interrupt Enable */ -#define nDONEEN3 0x0 #define HDONEEN4 0x10000 /* DMA4 Half Done Interrupt Enable */ -#define nHDONEEN4 0x0 #define DONEEN4 0x20000 /* DMA4 Done Interrupt Enable */ -#define nDONEEN4 0x0 #define HDONEEN5 0x100000 /* DMA5 Half Done Interrupt Enable */ -#define nHDONEEN5 0x0 #define DONEEN5 0x200000 /* DMA5 Done Interrupt Enable */ -#define nDONEEN5 0x0 #define HDONEEN6 0x1000000 /* DMA6 Half Done Interrupt Enable */ -#define nHDONEEN6 0x0 #define DONEEN6 0x2000000 /* DMA6 Done Interrupt Enable */ -#define nDONEEN6 0x0 #define HDONEEN7 0x10000000 /* DMA7 Half Done Interrupt Enable */ -#define nHDONEEN7 0x0 #define DONEEN7 0x20000000 /* DMA7 Done Interrupt Enable */ -#define nDONEEN7 0x0 /* Bit masks for MXVR_POSITION */ #define POSITION 0x3f /* Node Position */ #define PVALID 0x8000 /* Node Position Valid */ -#define nPVALID 0x0 /* Bit masks for MXVR_MAX_POSITION */ #define MPOSITION 0x3f /* Maximum Node Position */ #define MPVALID 0x8000 /* Maximum Node Position Valid */ -#define nMPVALID 0x0 /* Bit masks for MXVR_DELAY */ #define DELAY 0x3f /* Node Frame Delay */ #define DVALID 0x8000 /* Node Frame Delay Valid */ -#define nDVALID 0x0 /* Bit masks for MXVR_MAX_DELAY */ #define MDELAY 0x3f /* Maximum Node Frame Delay */ #define MDVALID 0x8000 /* Maximum Node Frame Delay Valid */ -#define nMDVALID 0x0 /* Bit masks for MXVR_LADDR */ #define LADDR 0xffff /* Logical Address */ #define LVALID 0x80000000 /* Logical Address Valid */ -#define nLVALID 0x0 /* Bit masks for MXVR_GADDR */ #define GADDRL 0xff /* Group Address Lower Byte */ #define GVALID 0x8000 /* Group Address Valid */ -#define nGVALID 0x0 /* Bit masks for MXVR_AADDR */ #define AADDR 0xffff /* Alternate Address */ #define AVALID 0x80000000 /* Alternate Address Valid */ -#define nAVALID 0x0 /* Bit masks for MXVR_ALLOC_0 */ #define CL0 0x7f /* Channel 0 Connection Label */ #define CIU0 0x80 /* Channel 0 In Use */ -#define nCIU0 0x0 #define CL1 0x7f00 /* Channel 0 Connection Label */ #define CIU1 0x8000 /* Channel 0 In Use */ -#define nCIU1 0x0 #define CL2 0x7f0000 /* Channel 0 Connection Label */ #define CIU2 0x800000 /* Channel 0 In Use */ -#define nCIU2 0x0 #define CL3 0x7f000000 /* Channel 0 Connection Label */ #define CIU3 0x80000000 /* Channel 0 In Use */ -#define nCIU3 0x0 /* Bit masks for MXVR_ALLOC_1 */ #define CL4 0x7f /* Channel 4 Connection Label */ #define CIU4 0x80 /* Channel 4 In Use */ -#define nCIU4 0x0 #define CL5 0x7f00 /* Channel 5 Connection Label */ #define CIU5 0x8000 /* Channel 5 In Use */ -#define nCIU5 0x0 #define CL6 0x7f0000 /* Channel 6 Connection Label */ #define CIU6 0x800000 /* Channel 6 In Use */ -#define nCIU6 0x0 #define CL7 0x7f000000 /* Channel 7 Connection Label */ #define CIU7 0x80000000 /* Channel 7 In Use */ -#define nCIU7 0x0 /* Bit masks for MXVR_ALLOC_2 */ #define CL8 0x7f /* Channel 8 Connection Label */ #define CIU8 0x80 /* Channel 8 In Use */ -#define nCIU8 0x0 #define CL9 0x7f00 /* Channel 9 Connection Label */ #define CIU9 0x8000 /* Channel 9 In Use */ -#define nCIU9 0x0 #define CL10 0x7f0000 /* Channel 10 Connection Label */ #define CIU10 0x800000 /* Channel 10 In Use */ -#define nCIU10 0x0 #define CL11 0x7f000000 /* Channel 11 Connection Label */ #define CIU11 0x80000000 /* Channel 11 In Use */ -#define nCIU11 0x0 /* Bit masks for MXVR_ALLOC_3 */ #define CL12 0x7f /* Channel 12 Connection Label */ #define CIU12 0x80 /* Channel 12 In Use */ -#define nCIU12 0x0 #define CL13 0x7f00 /* Channel 13 Connection Label */ #define CIU13 0x8000 /* Channel 13 In Use */ -#define nCIU13 0x0 #define CL14 0x7f0000 /* Channel 14 Connection Label */ #define CIU14 0x800000 /* Channel 14 In Use */ -#define nCIU14 0x0 #define CL15 0x7f000000 /* Channel 15 Connection Label */ #define CIU15 0x80000000 /* Channel 15 In Use */ -#define nCIU15 0x0 /* Bit masks for MXVR_ALLOC_4 */ #define CL16 0x7f /* Channel 16 Connection Label */ #define CIU16 0x80 /* Channel 16 In Use */ -#define nCIU16 0x0 #define CL17 0x7f00 /* Channel 17 Connection Label */ #define CIU17 0x8000 /* Channel 17 In Use */ -#define nCIU17 0x0 #define CL18 0x7f0000 /* Channel 18 Connection Label */ #define CIU18 0x800000 /* Channel 18 In Use */ -#define nCIU18 0x0 #define CL19 0x7f000000 /* Channel 19 Connection Label */ #define CIU19 0x80000000 /* Channel 19 In Use */ -#define nCIU19 0x0 /* Bit masks for MXVR_ALLOC_5 */ #define CL20 0x7f /* Channel 20 Connection Label */ #define CIU20 0x80 /* Channel 20 In Use */ -#define nCIU20 0x0 #define CL21 0x7f00 /* Channel 21 Connection Label */ #define CIU21 0x8000 /* Channel 21 In Use */ -#define nCIU21 0x0 #define CL22 0x7f0000 /* Channel 22 Connection Label */ #define CIU22 0x800000 /* Channel 22 In Use */ -#define nCIU22 0x0 #define CL23 0x7f000000 /* Channel 23 Connection Label */ #define CIU23 0x80000000 /* Channel 23 In Use */ -#define nCIU23 0x0 /* Bit masks for MXVR_ALLOC_6 */ #define CL24 0x7f /* Channel 24 Connection Label */ #define CIU24 0x80 /* Channel 24 In Use */ -#define nCIU24 0x0 #define CL25 0x7f00 /* Channel 25 Connection Label */ #define CIU25 0x8000 /* Channel 25 In Use */ -#define nCIU25 0x0 #define CL26 0x7f0000 /* Channel 26 Connection Label */ #define CIU26 0x800000 /* Channel 26 In Use */ -#define nCIU26 0x0 #define CL27 0x7f000000 /* Channel 27 Connection Label */ #define CIU27 0x80000000 /* Channel 27 In Use */ -#define nCIU27 0x0 /* Bit masks for MXVR_ALLOC_7 */ #define CL28 0x7f /* Channel 28 Connection Label */ #define CIU28 0x80 /* Channel 28 In Use */ -#define nCIU28 0x0 #define CL29 0x7f00 /* Channel 29 Connection Label */ #define CIU29 0x8000 /* Channel 29 In Use */ -#define nCIU29 0x0 #define CL30 0x7f0000 /* Channel 30 Connection Label */ #define CIU30 0x800000 /* Channel 30 In Use */ -#define nCIU30 0x0 #define CL31 0x7f000000 /* Channel 31 Connection Label */ #define CIU31 0x80000000 /* Channel 31 In Use */ -#define nCIU31 0x0 /* Bit masks for MXVR_ALLOC_8 */ #define CL32 0x7f /* Channel 32 Connection Label */ #define CIU32 0x80 /* Channel 32 In Use */ -#define nCIU32 0x0 #define CL33 0x7f00 /* Channel 33 Connection Label */ #define CIU33 0x8000 /* Channel 33 In Use */ -#define nCIU33 0x0 #define CL34 0x7f0000 /* Channel 34 Connection Label */ #define CIU34 0x800000 /* Channel 34 In Use */ -#define nCIU34 0x0 #define CL35 0x7f000000 /* Channel 35 Connection Label */ #define CIU35 0x80000000 /* Channel 35 In Use */ -#define nCIU35 0x0 /* Bit masks for MXVR_ALLOC_9 */ #define CL36 0x7f /* Channel 36 Connection Label */ #define CIU36 0x80 /* Channel 36 In Use */ -#define nCIU36 0x0 #define CL37 0x7f00 /* Channel 37 Connection Label */ #define CIU37 0x8000 /* Channel 37 In Use */ -#define nCIU37 0x0 #define CL38 0x7f0000 /* Channel 38 Connection Label */ #define CIU38 0x800000 /* Channel 38 In Use */ -#define nCIU38 0x0 #define CL39 0x7f000000 /* Channel 39 Connection Label */ #define CIU39 0x80000000 /* Channel 39 In Use */ -#define nCIU39 0x0 /* Bit masks for MXVR_ALLOC_10 */ #define CL40 0x7f /* Channel 40 Connection Label */ #define CIU40 0x80 /* Channel 40 In Use */ -#define nCIU40 0x0 #define CL41 0x7f00 /* Channel 41 Connection Label */ #define CIU41 0x8000 /* Channel 41 In Use */ -#define nCIU41 0x0 #define CL42 0x7f0000 /* Channel 42 Connection Label */ #define CIU42 0x800000 /* Channel 42 In Use */ -#define nCIU42 0x0 #define CL43 0x7f000000 /* Channel 43 Connection Label */ #define CIU43 0x80000000 /* Channel 43 In Use */ -#define nCIU43 0x0 /* Bit masks for MXVR_ALLOC_11 */ #define CL44 0x7f /* Channel 44 Connection Label */ #define CIU44 0x80 /* Channel 44 In Use */ -#define nCIU44 0x0 #define CL45 0x7f00 /* Channel 45 Connection Label */ #define CIU45 0x8000 /* Channel 45 In Use */ -#define nCIU45 0x0 #define CL46 0x7f0000 /* Channel 46 Connection Label */ #define CIU46 0x800000 /* Channel 46 In Use */ -#define nCIU46 0x0 #define CL47 0x7f000000 /* Channel 47 Connection Label */ #define CIU47 0x80000000 /* Channel 47 In Use */ -#define nCIU47 0x0 /* Bit masks for MXVR_ALLOC_12 */ #define CL48 0x7f /* Channel 48 Connection Label */ #define CIU48 0x80 /* Channel 48 In Use */ -#define nCIU48 0x0 #define CL49 0x7f00 /* Channel 49 Connection Label */ #define CIU49 0x8000 /* Channel 49 In Use */ -#define nCIU49 0x0 #define CL50 0x7f0000 /* Channel 50 Connection Label */ #define CIU50 0x800000 /* Channel 50 In Use */ -#define nCIU50 0x0 #define CL51 0x7f000000 /* Channel 51 Connection Label */ #define CIU51 0x80000000 /* Channel 51 In Use */ -#define nCIU51 0x0 /* Bit masks for MXVR_ALLOC_13 */ #define CL52 0x7f /* Channel 52 Connection Label */ #define CIU52 0x80 /* Channel 52 In Use */ -#define nCIU52 0x0 #define CL53 0x7f00 /* Channel 53 Connection Label */ #define CIU53 0x8000 /* Channel 53 In Use */ -#define nCIU53 0x0 #define CL54 0x7f0000 /* Channel 54 Connection Label */ #define CIU54 0x800000 /* Channel 54 In Use */ -#define nCIU54 0x0 #define CL55 0x7f000000 /* Channel 55 Connection Label */ #define CIU55 0x80000000 /* Channel 55 In Use */ -#define nCIU55 0x0 /* Bit masks for MXVR_ALLOC_14 */ #define CL56 0x7f /* Channel 56 Connection Label */ #define CIU56 0x80 /* Channel 56 In Use */ -#define nCIU56 0x0 #define CL57 0x7f00 /* Channel 57 Connection Label */ #define CIU57 0x8000 /* Channel 57 In Use */ -#define nCIU57 0x0 #define CL58 0x7f0000 /* Channel 58 Connection Label */ #define CIU58 0x800000 /* Channel 58 In Use */ -#define nCIU58 0x0 #define CL59 0x7f000000 /* Channel 59 Connection Label */ #define CIU59 0x80000000 /* Channel 59 In Use */ -#define nCIU59 0x0 /* MXVR_SYNC_LCHAN_0 Masks */ @@ -1926,19 +1669,13 @@ /* Bit masks for MXVR_DMAx_CONFIG */ #define MDMAEN 0x1 /* DMA Channel Enable */ -#define nMDMAEN 0x0 #define DD 0x2 /* DMA Channel Direction */ -#define nDD 0x0 #define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */ -#define nBY4SWAPEN 0x0 #define LCHAN 0x3c0 /* DMA Channel Logical Channel */ #define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */ -#define nBITSWAPEN 0x0 #define BY2SWAPEN 0x800 /* DMA Channel Two Byte Swap Enable */ -#define nBY2SWAPEN 0x0 #define MFLOW 0x7000 /* DMA Channel Operation Flow */ #define FIXEDPM 0x80000 /* DMA Channel Fixed Pattern Matching Select */ -#define nFIXEDPM 0x0 #define STARTPAT 0x300000 /* DMA Channel Start Pattern Select */ #define STOPPAT 0xc00000 /* DMA Channel Stop Pattern Select */ #define COUNTPOS 0x1c000000 /* DMA Channel Count Position */ @@ -1946,94 +1683,71 @@ /* Bit masks for MXVR_AP_CTL */ #define STARTAP 0x1 /* Start Asynchronous Packet Transmission */ -#define nSTARTAP 0x0 #define CANCELAP 0x2 /* Cancel Asynchronous Packet Transmission */ -#define nCANCELAP 0x0 #define RESETAP 0x4 /* Reset Asynchronous Packet Arbitration */ -#define nRESETAP 0x0 #define APRBE0 0x4000 /* Asynchronous Packet Receive Buffer Entry 0 */ -#define nAPRBE0 0x0 #define APRBE1 0x8000 /* Asynchronous Packet Receive Buffer Entry 1 */ -#define nAPRBE1 0x0 /* Bit masks for MXVR_APRB_START_ADDR */ -#define MXVR_APRB_START_ADDR 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */ +#define MXVR_APRB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */ /* Bit masks for MXVR_APRB_CURR_ADDR */ -#define MXVR_APRB_CURR_ADDR 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */ +#define MXVR_APRB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */ /* Bit masks for MXVR_APTB_START_ADDR */ -#define MXVR_APTB_START_ADDR 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */ +#define MXVR_APTB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */ /* Bit masks for MXVR_APTB_CURR_ADDR */ -#define MXVR_APTB_CURR_ADDR 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */ +#define MXVR_APTB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */ /* Bit masks for MXVR_CM_CTL */ #define STARTCM 0x1 /* Start Control Message Transmission */ -#define nSTARTCM 0x0 #define CANCELCM 0x2 /* Cancel Control Message Transmission */ -#define nCANCELCM 0x0 #define CMRBE0 0x10000 /* Control Message Receive Buffer Entry 0 */ -#define nCMRBE0 0x0 #define CMRBE1 0x20000 /* Control Message Receive Buffer Entry 1 */ -#define nCMRBE1 0x0 #define CMRBE2 0x40000 /* Control Message Receive Buffer Entry 2 */ -#define nCMRBE2 0x0 #define CMRBE3 0x80000 /* Control Message Receive Buffer Entry 3 */ -#define nCMRBE3 0x0 #define CMRBE4 0x100000 /* Control Message Receive Buffer Entry 4 */ -#define nCMRBE4 0x0 #define CMRBE5 0x200000 /* Control Message Receive Buffer Entry 5 */ -#define nCMRBE5 0x0 #define CMRBE6 0x400000 /* Control Message Receive Buffer Entry 6 */ -#define nCMRBE6 0x0 #define CMRBE7 0x800000 /* Control Message Receive Buffer Entry 7 */ -#define nCMRBE7 0x0 #define CMRBE8 0x1000000 /* Control Message Receive Buffer Entry 8 */ -#define nCMRBE8 0x0 #define CMRBE9 0x2000000 /* Control Message Receive Buffer Entry 9 */ -#define nCMRBE9 0x0 #define CMRBE10 0x4000000 /* Control Message Receive Buffer Entry 10 */ -#define nCMRBE10 0x0 #define CMRBE11 0x8000000 /* Control Message Receive Buffer Entry 11 */ -#define nCMRBE11 0x0 #define CMRBE12 0x10000000 /* Control Message Receive Buffer Entry 12 */ -#define nCMRBE12 0x0 #define CMRBE13 0x20000000 /* Control Message Receive Buffer Entry 13 */ -#define nCMRBE13 0x0 #define CMRBE14 0x40000000 /* Control Message Receive Buffer Entry 14 */ -#define nCMRBE14 0x0 #define CMRBE15 0x80000000 /* Control Message Receive Buffer Entry 15 */ -#define nCMRBE15 0x0 /* Bit masks for MXVR_CMRB_START_ADDR */ -#define MXVR_CMRB_START_ADDR 0x1fffffe /* Control Message Receive Buffer Start Address */ +#define MXVR_CMRB_START_ADDR_MASK 0x1fffffe /* Control Message Receive Buffer Start Address */ /* Bit masks for MXVR_CMRB_CURR_ADDR */ -#define MXVR_CMRB_CURR_ADDR 0xffffffff /* Control Message Receive Buffer Current Address */ +#define MXVR_CMRB_CURR_ADDR_MASK 0xffffffff /* Control Message Receive Buffer Current Address */ /* Bit masks for MXVR_CMTB_START_ADDR */ -#define MXVR_CMTB_START_ADDR 0x1fffffe /* Control Message Transmit Buffer Start Address */ +#define MXVR_CMTB_START_ADDR_MASK 0x1fffffe /* Control Message Transmit Buffer Start Address */ /* Bit masks for MXVR_CMTB_CURR_ADDR */ -#define MXVR_CMTB_CURR_ADDR 0xffffffff /* Control Message Transmit Buffer Current Address */ +#define MXVR_CMTB_CURR_ADDR_MASK 0xffffffff /* Control Message Transmit Buffer Current Address */ /* Bit masks for MXVR_RRDB_START_ADDR */ -#define MXVR_RRDB_START_ADDR 0x1fffffe /* Remote Read Buffer Start Address */ +#define MXVR_RRDB_START_ADDR_MASK 0x1fffffe /* Remote Read Buffer Start Address */ /* Bit masks for MXVR_RRDB_CURR_ADDR */ -#define MXVR_RRDB_CURR_ADDR 0xffffffff /* Remote Read Buffer Current Address */ +#define MXVR_RRDB_CURR_ADDR_MASK 0xffffffff /* Remote Read Buffer Current Address */ /* Bit masks for MXVR_PAT_DATAx */ @@ -2045,136 +1759,72 @@ /* Bit masks for MXVR_PAT_EN_0 */ #define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ -#define nMATCH_EN_0_0 0x0 #define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ -#define nMATCH_EN_0_1 0x0 #define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ -#define nMATCH_EN_0_2 0x0 #define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ -#define nMATCH_EN_0_3 0x0 #define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ -#define nMATCH_EN_0_4 0x0 #define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ -#define nMATCH_EN_0_5 0x0 #define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ -#define nMATCH_EN_0_6 0x0 #define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ -#define nMATCH_EN_0_7 0x0 #define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ -#define nMATCH_EN_1_0 0x0 #define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ -#define nMATCH_EN_1_1 0x0 #define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ -#define nMATCH_EN_1_2 0x0 #define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ -#define nMATCH_EN_1_3 0x0 #define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ -#define nMATCH_EN_1_4 0x0 #define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ -#define nMATCH_EN_1_5 0x0 #define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ -#define nMATCH_EN_1_6 0x0 #define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ -#define nMATCH_EN_1_7 0x0 #define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ -#define nMATCH_EN_2_0 0x0 #define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ -#define nMATCH_EN_2_1 0x0 #define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ -#define nMATCH_EN_2_2 0x0 #define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ -#define nMATCH_EN_2_3 0x0 #define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ -#define nMATCH_EN_2_4 0x0 #define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ -#define nMATCH_EN_2_5 0x0 #define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ -#define nMATCH_EN_2_6 0x0 #define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ -#define nMATCH_EN_2_7 0x0 #define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ -#define nMATCH_EN_3_0 0x0 #define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ -#define nMATCH_EN_3_1 0x0 #define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ -#define nMATCH_EN_3_2 0x0 #define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ -#define nMATCH_EN_3_3 0x0 #define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ -#define nMATCH_EN_3_4 0x0 #define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ -#define nMATCH_EN_3_5 0x0 #define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ -#define nMATCH_EN_3_6 0x0 #define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ -#define nMATCH_EN_3_7 0x0 /* Bit masks for MXVR_PAT_EN_1 */ #define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ -#define nMATCH_EN_0_0 0x0 #define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ -#define nMATCH_EN_0_1 0x0 #define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ -#define nMATCH_EN_0_2 0x0 #define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ -#define nMATCH_EN_0_3 0x0 #define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ -#define nMATCH_EN_0_4 0x0 #define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ -#define nMATCH_EN_0_5 0x0 #define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ -#define nMATCH_EN_0_6 0x0 #define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ -#define nMATCH_EN_0_7 0x0 #define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ -#define nMATCH_EN_1_0 0x0 #define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ -#define nMATCH_EN_1_1 0x0 #define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ -#define nMATCH_EN_1_2 0x0 #define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ -#define nMATCH_EN_1_3 0x0 #define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ -#define nMATCH_EN_1_4 0x0 #define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ -#define nMATCH_EN_1_5 0x0 #define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ -#define nMATCH_EN_1_6 0x0 #define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ -#define nMATCH_EN_1_7 0x0 #define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ -#define nMATCH_EN_2_0 0x0 #define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ -#define nMATCH_EN_2_1 0x0 #define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ -#define nMATCH_EN_2_2 0x0 #define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ -#define nMATCH_EN_2_3 0x0 #define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ -#define nMATCH_EN_2_4 0x0 #define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ -#define nMATCH_EN_2_5 0x0 #define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ -#define nMATCH_EN_2_6 0x0 #define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ -#define nMATCH_EN_2_7 0x0 #define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ -#define nMATCH_EN_3_0 0x0 #define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ -#define nMATCH_EN_3_1 0x0 #define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ -#define nMATCH_EN_3_2 0x0 #define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ -#define nMATCH_EN_3_3 0x0 #define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ -#define nMATCH_EN_3_4 0x0 #define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ -#define nMATCH_EN_3_5 0x0 #define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ -#define nMATCH_EN_3_6 0x0 #define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ -#define nMATCH_EN_3_7 0x0 /* Bit masks for MXVR_FRAME_CNT_0 */ @@ -2188,226 +1838,166 @@ #define TX_CH0 0x3f /* Transmit Channel 0 */ #define MUTE_CH0 0x80 /* Mute Channel 0 */ -#define nMUTE_CH0 0x0 #define TX_CH1 0x3f00 /* Transmit Channel 0 */ #define MUTE_CH1 0x8000 /* Mute Channel 0 */ -#define nMUTE_CH1 0x0 #define TX_CH2 0x3f0000 /* Transmit Channel 0 */ #define MUTE_CH2 0x800000 /* Mute Channel 0 */ -#define nMUTE_CH2 0x0 #define TX_CH3 0x3f000000 /* Transmit Channel 0 */ #define MUTE_CH3 0x80000000 /* Mute Channel 0 */ -#define nMUTE_CH3 0x0 /* Bit masks for MXVR_ROUTING_1 */ #define TX_CH4 0x3f /* Transmit Channel 4 */ #define MUTE_CH4 0x80 /* Mute Channel 4 */ -#define nMUTE_CH4 0x0 #define TX_CH5 0x3f00 /* Transmit Channel 5 */ #define MUTE_CH5 0x8000 /* Mute Channel 5 */ -#define nMUTE_CH5 0x0 #define TX_CH6 0x3f0000 /* Transmit Channel 6 */ #define MUTE_CH6 0x800000 /* Mute Channel 6 */ -#define nMUTE_CH6 0x0 #define TX_CH7 0x3f000000 /* Transmit Channel 7 */ #define MUTE_CH7 0x80000000 /* Mute Channel 7 */ -#define nMUTE_CH7 0x0 /* Bit masks for MXVR_ROUTING_2 */ #define TX_CH8 0x3f /* Transmit Channel 8 */ #define MUTE_CH8 0x80 /* Mute Channel 8 */ -#define nMUTE_CH8 0x0 #define TX_CH9 0x3f00 /* Transmit Channel 9 */ #define MUTE_CH9 0x8000 /* Mute Channel 9 */ -#define nMUTE_CH9 0x0 #define TX_CH10 0x3f0000 /* Transmit Channel 10 */ #define MUTE_CH10 0x800000 /* Mute Channel 10 */ -#define nMUTE_CH10 0x0 #define TX_CH11 0x3f000000 /* Transmit Channel 11 */ #define MUTE_CH11 0x80000000 /* Mute Channel 11 */ -#define nMUTE_CH11 0x0 /* Bit masks for MXVR_ROUTING_3 */ #define TX_CH12 0x3f /* Transmit Channel 12 */ #define MUTE_CH12 0x80 /* Mute Channel 12 */ -#define nMUTE_CH12 0x0 #define TX_CH13 0x3f00 /* Transmit Channel 13 */ #define MUTE_CH13 0x8000 /* Mute Channel 13 */ -#define nMUTE_CH13 0x0 #define TX_CH14 0x3f0000 /* Transmit Channel 14 */ #define MUTE_CH14 0x800000 /* Mute Channel 14 */ -#define nMUTE_CH14 0x0 #define TX_CH15 0x3f000000 /* Transmit Channel 15 */ #define MUTE_CH15 0x80000000 /* Mute Channel 15 */ -#define nMUTE_CH15 0x0 /* Bit masks for MXVR_ROUTING_4 */ #define TX_CH16 0x3f /* Transmit Channel 16 */ #define MUTE_CH16 0x80 /* Mute Channel 16 */ -#define nMUTE_CH16 0x0 #define TX_CH17 0x3f00 /* Transmit Channel 17 */ #define MUTE_CH17 0x8000 /* Mute Channel 17 */ -#define nMUTE_CH17 0x0 #define TX_CH18 0x3f0000 /* Transmit Channel 18 */ #define MUTE_CH18 0x800000 /* Mute Channel 18 */ -#define nMUTE_CH18 0x0 #define TX_CH19 0x3f000000 /* Transmit Channel 19 */ #define MUTE_CH19 0x80000000 /* Mute Channel 19 */ -#define nMUTE_CH19 0x0 /* Bit masks for MXVR_ROUTING_5 */ #define TX_CH20 0x3f /* Transmit Channel 20 */ #define MUTE_CH20 0x80 /* Mute Channel 20 */ -#define nMUTE_CH20 0x0 #define TX_CH21 0x3f00 /* Transmit Channel 21 */ #define MUTE_CH21 0x8000 /* Mute Channel 21 */ -#define nMUTE_CH21 0x0 #define TX_CH22 0x3f0000 /* Transmit Channel 22 */ #define MUTE_CH22 0x800000 /* Mute Channel 22 */ -#define nMUTE_CH22 0x0 #define TX_CH23 0x3f000000 /* Transmit Channel 23 */ #define MUTE_CH23 0x80000000 /* Mute Channel 23 */ -#define nMUTE_CH23 0x0 /* Bit masks for MXVR_ROUTING_6 */ #define TX_CH24 0x3f /* Transmit Channel 24 */ #define MUTE_CH24 0x80 /* Mute Channel 24 */ -#define nMUTE_CH24 0x0 #define TX_CH25 0x3f00 /* Transmit Channel 25 */ #define MUTE_CH25 0x8000 /* Mute Channel 25 */ -#define nMUTE_CH25 0x0 #define TX_CH26 0x3f0000 /* Transmit Channel 26 */ #define MUTE_CH26 0x800000 /* Mute Channel 26 */ -#define nMUTE_CH26 0x0 #define TX_CH27 0x3f000000 /* Transmit Channel 27 */ #define MUTE_CH27 0x80000000 /* Mute Channel 27 */ -#define nMUTE_CH27 0x0 /* Bit masks for MXVR_ROUTING_7 */ #define TX_CH28 0x3f /* Transmit Channel 28 */ #define MUTE_CH28 0x80 /* Mute Channel 28 */ -#define nMUTE_CH28 0x0 #define TX_CH29 0x3f00 /* Transmit Channel 29 */ #define MUTE_CH29 0x8000 /* Mute Channel 29 */ -#define nMUTE_CH29 0x0 #define TX_CH30 0x3f0000 /* Transmit Channel 30 */ #define MUTE_CH30 0x800000 /* Mute Channel 30 */ -#define nMUTE_CH30 0x0 #define TX_CH31 0x3f000000 /* Transmit Channel 31 */ #define MUTE_CH31 0x80000000 /* Mute Channel 31 */ -#define nMUTE_CH31 0x0 /* Bit masks for MXVR_ROUTING_8 */ #define TX_CH32 0x3f /* Transmit Channel 32 */ #define MUTE_CH32 0x80 /* Mute Channel 32 */ -#define nMUTE_CH32 0x0 #define TX_CH33 0x3f00 /* Transmit Channel 33 */ #define MUTE_CH33 0x8000 /* Mute Channel 33 */ -#define nMUTE_CH33 0x0 #define TX_CH34 0x3f0000 /* Transmit Channel 34 */ #define MUTE_CH34 0x800000 /* Mute Channel 34 */ -#define nMUTE_CH34 0x0 #define TX_CH35 0x3f000000 /* Transmit Channel 35 */ #define MUTE_CH35 0x80000000 /* Mute Channel 35 */ -#define nMUTE_CH35 0x0 /* Bit masks for MXVR_ROUTING_9 */ #define TX_CH36 0x3f /* Transmit Channel 36 */ #define MUTE_CH36 0x80 /* Mute Channel 36 */ -#define nMUTE_CH36 0x0 #define TX_CH37 0x3f00 /* Transmit Channel 37 */ #define MUTE_CH37 0x8000 /* Mute Channel 37 */ -#define nMUTE_CH37 0x0 #define TX_CH38 0x3f0000 /* Transmit Channel 38 */ #define MUTE_CH38 0x800000 /* Mute Channel 38 */ -#define nMUTE_CH38 0x0 #define TX_CH39 0x3f000000 /* Transmit Channel 39 */ #define MUTE_CH39 0x80000000 /* Mute Channel 39 */ -#define nMUTE_CH39 0x0 /* Bit masks for MXVR_ROUTING_10 */ #define TX_CH40 0x3f /* Transmit Channel 40 */ #define MUTE_CH40 0x80 /* Mute Channel 40 */ -#define nMUTE_CH40 0x0 #define TX_CH41 0x3f00 /* Transmit Channel 41 */ #define MUTE_CH41 0x8000 /* Mute Channel 41 */ -#define nMUTE_CH41 0x0 #define TX_CH42 0x3f0000 /* Transmit Channel 42 */ #define MUTE_CH42 0x800000 /* Mute Channel 42 */ -#define nMUTE_CH42 0x0 #define TX_CH43 0x3f000000 /* Transmit Channel 43 */ #define MUTE_CH43 0x80000000 /* Mute Channel 43 */ -#define nMUTE_CH43 0x0 /* Bit masks for MXVR_ROUTING_11 */ #define TX_CH44 0x3f /* Transmit Channel 44 */ #define MUTE_CH44 0x80 /* Mute Channel 44 */ -#define nMUTE_CH44 0x0 #define TX_CH45 0x3f00 /* Transmit Channel 45 */ #define MUTE_CH45 0x8000 /* Mute Channel 45 */ -#define nMUTE_CH45 0x0 #define TX_CH46 0x3f0000 /* Transmit Channel 46 */ #define MUTE_CH46 0x800000 /* Mute Channel 46 */ -#define nMUTE_CH46 0x0 #define TX_CH47 0x3f000000 /* Transmit Channel 47 */ #define MUTE_CH47 0x80000000 /* Mute Channel 47 */ -#define nMUTE_CH47 0x0 /* Bit masks for MXVR_ROUTING_12 */ #define TX_CH48 0x3f /* Transmit Channel 48 */ #define MUTE_CH48 0x80 /* Mute Channel 48 */ -#define nMUTE_CH48 0x0 #define TX_CH49 0x3f00 /* Transmit Channel 49 */ #define MUTE_CH49 0x8000 /* Mute Channel 49 */ -#define nMUTE_CH49 0x0 #define TX_CH50 0x3f0000 /* Transmit Channel 50 */ #define MUTE_CH50 0x800000 /* Mute Channel 50 */ -#define nMUTE_CH50 0x0 #define TX_CH51 0x3f000000 /* Transmit Channel 51 */ #define MUTE_CH51 0x80000000 /* Mute Channel 51 */ -#define nMUTE_CH51 0x0 /* Bit masks for MXVR_ROUTING_13 */ #define TX_CH52 0x3f /* Transmit Channel 52 */ #define MUTE_CH52 0x80 /* Mute Channel 52 */ -#define nMUTE_CH52 0x0 #define TX_CH53 0x3f00 /* Transmit Channel 53 */ #define MUTE_CH53 0x8000 /* Mute Channel 53 */ -#define nMUTE_CH53 0x0 #define TX_CH54 0x3f0000 /* Transmit Channel 54 */ #define MUTE_CH54 0x800000 /* Mute Channel 54 */ -#define nMUTE_CH54 0x0 #define TX_CH55 0x3f000000 /* Transmit Channel 55 */ #define MUTE_CH55 0x80000000 /* Mute Channel 55 */ -#define nMUTE_CH55 0x0 /* Bit masks for MXVR_ROUTING_14 */ #define TX_CH56 0x3f /* Transmit Channel 56 */ #define MUTE_CH56 0x80 /* Mute Channel 56 */ -#define nMUTE_CH56 0x0 #define TX_CH57 0x3f00 /* Transmit Channel 57 */ #define MUTE_CH57 0x8000 /* Mute Channel 57 */ -#define nMUTE_CH57 0x0 #define TX_CH58 0x3f0000 /* Transmit Channel 58 */ #define MUTE_CH58 0x800000 /* Mute Channel 58 */ -#define nMUTE_CH58 0x0 #define TX_CH59 0x3f000000 /* Transmit Channel 59 */ #define MUTE_CH59 0x80000000 /* Mute Channel 59 */ -#define nMUTE_CH59 0x0 /* Bit masks for MXVR_BLOCK_CNT */ @@ -2416,53 +2006,37 @@ /* Bit masks for MXVR_CLK_CTL */ #define MXTALCEN 0x1 /* MXVR Crystal Oscillator Clock Enable */ -#define nMXTALCEN 0x0 #define MXTALFEN 0x2 /* MXVR Crystal Oscillator Feedback Enable */ -#define nMXTALFEN 0x0 #define MXTALMUL 0x30 /* MXVR Crystal Multiplier */ #define CLKX3SEL 0x80 /* Clock Generation Source Select */ -#define nCLKX3SEL 0x0 #define MMCLKEN 0x100 /* Master Clock Enable */ -#define nMMCLKEN 0x0 #define MMCLKMUL 0x1e00 /* Master Clock Multiplication Factor */ #define PLLSMPS 0xe000 /* MXVR PLL State Machine Prescaler */ #define MBCLKEN 0x10000 /* Bit Clock Enable */ -#define nMBCLKEN 0x0 #define MBCLKDIV 0x1e0000 /* Bit Clock Divide Factor */ #define INVRX 0x800000 /* Invert Receive Data */ -#define nINVRX 0x0 #define MFSEN 0x1000000 /* Frame Sync Enable */ -#define nMFSEN 0x0 #define MFSDIV 0x1e000000 /* Frame Sync Divide Factor */ #define MFSSEL 0x60000000 /* Frame Sync Select */ #define MFSSYNC 0x80000000 /* Frame Sync Synchronization Select */ -#define nMFSSYNC 0x0 /* Bit masks for MXVR_CDRPLL_CTL */ #define CDRSMEN 0x1 /* MXVR CDRPLL State Machine Enable */ -#define nCDRSMEN 0x0 #define CDRRSTB 0x2 /* MXVR CDRPLL Reset */ -#define nCDRRSTB 0x0 #define CDRSVCO 0x4 /* MXVR CDRPLL Start VCO */ -#define nCDRSVCO 0x0 #define CDRMODE 0x8 /* MXVR CDRPLL CDR Mode Select */ -#define nCDRMODE 0x0 #define CDRSCNT 0x3f0 /* MXVR CDRPLL Start Counter */ #define CDRLCNT 0xfc00 /* MXVR CDRPLL Lock Counter */ #define CDRSHPSEL 0x3f0000 /* MXVR CDRPLL Shaper Select */ #define CDRSHPEN 0x800000 /* MXVR CDRPLL Shaper Enable */ -#define nCDRSHPEN 0x0 #define CDRCPSEL 0xff000000 /* MXVR CDRPLL Charge Pump Current Select */ /* Bit masks for MXVR_FMPLL_CTL */ #define FMSMEN 0x1 /* MXVR FMPLL State Machine Enable */ -#define nFMSMEN 0x0 #define FMRSTB 0x2 /* MXVR FMPLL Reset */ -#define nFMRSTB 0x0 #define FMSVCO 0x4 /* MXVR FMPLL Start VCO */ -#define nFMSVCO 0x0 #define FMSCNT 0x3f0 /* MXVR FMPLL Start Counter */ #define FMLCNT 0xfc00 /* MXVR FMPLL Lock Counter */ #define FMCPSEL 0xff000000 /* MXVR FMPLL Charge Pump Current Select */ @@ -2470,15 +2044,10 @@ /* Bit masks for MXVR_PIN_CTL */ #define MTXONBOD 0x1 /* MTXONB Open Drain Select */ -#define nMTXONBOD 0x0 #define MTXONBG 0x2 /* MTXONB Gates MTX Select */ -#define nMTXONBG 0x0 #define MFSOE 0x10 /* MFS Output Enable */ -#define nMFSOE 0x0 #define MFSGPSEL 0x20 /* MFS General Purpose Output Select */ -#define nMFSGPSEL 0x0 #define MFSGPDAT 0x40 /* MFS General Purpose Output Data */ -#define nMFSGPDAT 0x0 /* Bit masks for MXVR_SCLK_CNT */ @@ -2487,7 +2056,6 @@ /* Bit masks for KPAD_CTL */ #define KPAD_EN 0x1 /* Keypad Enable */ -#define nKPAD_EN 0x0 #define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ #define KPAD_ROWEN 0x1c00 /* Row Enable Width */ #define KPAD_COLEN 0xe000 /* Column Enable Width */ @@ -2509,29 +2077,21 @@ /* Bit masks for KPAD_STAT */ #define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ -#define nKPAD_IRQ 0x0 #define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ #define KPAD_PRESSED 0x8 /* Key press current status */ -#define nKPAD_PRESSED 0x0 /* Bit masks for KPAD_SOFTEVAL */ #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ -#define nKPAD_SOFTEVAL_E 0x0 /* Bit masks for SDH_COMMAND */ #define CMD_IDX 0x3f /* Command Index */ #define CMD_RSP 0x40 /* Response */ -#define nCMD_RSP 0x0 #define CMD_L_RSP 0x80 /* Long Response */ -#define nCMD_L_RSP 0x0 #define CMD_INT_E 0x100 /* Command Interrupt */ -#define nCMD_INT_E 0x0 #define CMD_PEND_E 0x200 /* Command Pending */ -#define nCMD_PEND_E 0x0 #define CMD_E 0x400 /* Command Enable */ -#define nCMD_E 0x0 /* Bit masks for SDH_PWR_CTL */ @@ -2540,21 +2100,15 @@ #define TBD 0x3c /* TBD */ #endif #define SD_CMD_OD 0x40 /* Open Drain Output */ -#define nSD_CMD_OD 0x0 #define ROD_CTL 0x80 /* Rod Control */ -#define nROD_CTL 0x0 /* Bit masks for SDH_CLK_CTL */ #define CLKDIV 0xff /* MC_CLK Divisor */ #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ -#define nCLK_E 0x0 #define PWR_SV_E 0x200 /* Power Save Enable */ -#define nPWR_SV_E 0x0 #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ -#define nCLKDIV_BYPASS 0x0 #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ -#define nWIDE_BUS 0x0 /* Bit masks for SDH_RESP_CMD */ @@ -2563,133 +2117,74 @@ /* Bit masks for SDH_DATA_CTL */ #define DTX_E 0x1 /* Data Transfer Enable */ -#define nDTX_E 0x0 #define DTX_DIR 0x2 /* Data Transfer Direction */ -#define nDTX_DIR 0x0 #define DTX_MODE 0x4 /* Data Transfer Mode */ -#define nDTX_MODE 0x0 #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ -#define nDTX_DMA_E 0x0 #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ /* Bit masks for SDH_STATUS */ #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ -#define nCMD_CRC_FAIL 0x0 #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ -#define nDAT_CRC_FAIL 0x0 -#define CMD_TIMEOUT 0x4 /* CMD Time Out */ -#define nCMD_TIMEOUT 0x0 -#define DAT_TIMEOUT 0x8 /* Data Time Out */ -#define nDAT_TIMEOUT 0x0 +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ #define TX_UNDERRUN 0x10 /* Transmit Underrun */ -#define nTX_UNDERRUN 0x0 #define RX_OVERRUN 0x20 /* Receive Overrun */ -#define nRX_OVERRUN 0x0 #define CMD_RESP_END 0x40 /* CMD Response End */ -#define nCMD_RESP_END 0x0 #define CMD_SENT 0x80 /* CMD Sent */ -#define nCMD_SENT 0x0 #define DAT_END 0x100 /* Data End */ -#define nDAT_END 0x0 #define START_BIT_ERR 0x200 /* Start Bit Error */ -#define nSTART_BIT_ERR 0x0 #define DAT_BLK_END 0x400 /* Data Block End */ -#define nDAT_BLK_END 0x0 #define CMD_ACT 0x800 /* CMD Active */ -#define nCMD_ACT 0x0 #define TX_ACT 0x1000 /* Transmit Active */ -#define nTX_ACT 0x0 #define RX_ACT 0x2000 /* Receive Active */ -#define nRX_ACT 0x0 #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ -#define nTX_FIFO_STAT 0x0 #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ -#define nRX_FIFO_STAT 0x0 #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ -#define nTX_FIFO_FULL 0x0 #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ -#define nRX_FIFO_FULL 0x0 #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ -#define nTX_FIFO_ZERO 0x0 #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ -#define nRX_DAT_ZERO 0x0 #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ -#define nTX_DAT_RDY 0x0 #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ -#define nRX_FIFO_RDY 0x0 /* Bit masks for SDH_STATUS_CLR */ #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ -#define nCMD_CRC_FAIL_STAT 0x0 #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ -#define nDAT_CRC_FAIL_STAT 0x0 #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ -#define nCMD_TIMEOUT_STAT 0x0 #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ -#define nDAT_TIMEOUT_STAT 0x0 #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ -#define nTX_UNDERRUN_STAT 0x0 #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ -#define nRX_OVERRUN_STAT 0x0 #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ -#define nCMD_RESP_END_STAT 0x0 #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ -#define nCMD_SENT_STAT 0x0 #define DAT_END_STAT 0x100 /* Data End Status */ -#define nDAT_END_STAT 0x0 #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ -#define nSTART_BIT_ERR_STAT 0x0 #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ -#define nDAT_BLK_END_STAT 0x0 /* Bit masks for SDH_MASK0 */ #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ -#define nCMD_CRC_FAIL_MASK 0x0 #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ -#define nDAT_CRC_FAIL_MASK 0x0 #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ -#define nCMD_TIMEOUT_MASK 0x0 #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ -#define nDAT_TIMEOUT_MASK 0x0 #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ -#define nTX_UNDERRUN_MASK 0x0 #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ -#define nRX_OVERRUN_MASK 0x0 #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ -#define nCMD_RESP_END_MASK 0x0 #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ -#define nCMD_SENT_MASK 0x0 #define DAT_END_MASK 0x100 /* Data End Mask */ -#define nDAT_END_MASK 0x0 #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ -#define nSTART_BIT_ERR_MASK 0x0 #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ -#define nDAT_BLK_END_MASK 0x0 #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ -#define nCMD_ACT_MASK 0x0 #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ -#define nTX_ACT_MASK 0x0 #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ -#define nRX_ACT_MASK 0x0 #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ -#define nTX_FIFO_STAT_MASK 0x0 #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ -#define nRX_FIFO_STAT_MASK 0x0 #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ -#define nTX_FIFO_FULL_MASK 0x0 #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ -#define nRX_FIFO_FULL_MASK 0x0 #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ -#define nTX_FIFO_ZERO_MASK 0x0 #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ -#define nRX_DAT_ZERO_MASK 0x0 #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ -#define nTX_DAT_RDY_MASK 0x0 #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ -#define nRX_FIFO_RDY_MASK 0x0 /* Bit masks for SDH_FIFO_CNT */ @@ -2698,73 +2193,47 @@ /* Bit masks for SDH_E_STATUS */ #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ -#define nSDIO_INT_DET 0x0 #define SD_CARD_DET 0x10 /* SD Card Detect */ -#define nSD_CARD_DET 0x0 /* Bit masks for SDH_E_MASK */ #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ -#define nSDIO_MSK 0x0 #define SCD_MSK 0x40 /* Mask Card Detect */ -#define nSCD_MSK 0x0 /* Bit masks for SDH_CFG */ #define CLKS_EN 0x1 /* Clocks Enable */ -#define nCLKS_EN 0x0 #define SD4E 0x4 /* SDIO 4-Bit Enable */ -#define nSD4E 0x0 #define MWE 0x8 /* Moving Window Enable */ -#define nMWE 0x0 #define SD_RST 0x10 /* SDMMC Reset */ -#define nSD_RST 0x0 #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ -#define nPUP_SDDAT 0x0 #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ -#define nPUP_SDDAT3 0x0 #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ -#define nPD_SDDAT3 0x0 /* Bit masks for SDH_RD_WAIT_EN */ #define RWR 0x1 /* Read Wait Request */ -#define nRWR 0x0 /* Bit masks for ATAPI_CONTROL */ #define PIO_START 0x1 /* Start PIO/Reg Op */ -#define nPIO_START 0x0 #define MULTI_START 0x2 /* Start Multi-DMA Op */ -#define nMULTI_START 0x0 #define ULTRA_START 0x4 /* Start Ultra-DMA Op */ -#define nULTRA_START 0x0 #define XFER_DIR 0x8 /* Transfer Direction */ -#define nXFER_DIR 0x0 #define IORDY_EN 0x10 /* IORDY Enable */ -#define nIORDY_EN 0x0 #define FIFO_FLUSH 0x20 /* Flush FIFOs */ -#define nFIFO_FLUSH 0x0 #define SOFT_RST 0x40 /* Soft Reset */ -#define nSOFT_RST 0x0 #define DEV_RST 0x80 /* Device Reset */ -#define nDEV_RST 0x0 #define TFRCNT_RST 0x100 /* Trans Count Reset */ -#define nTFRCNT_RST 0x0 #define END_ON_TERM 0x200 /* End/Terminate Select */ -#define nEND_ON_TERM 0x0 #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ -#define nPIO_USE_DMA 0x0 #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ /* Bit masks for ATAPI_STATUS */ #define PIO_XFER_ON 0x1 /* PIO transfer in progress */ -#define nPIO_XFER_ON 0x0 #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ -#define nMULTI_XFER_ON 0x0 #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ -#define nULTRA_XFER_ON 0x0 #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ /* Bit masks for ATAPI_DEV_ADDR */ @@ -2774,66 +2243,39 @@ /* Bit masks for ATAPI_INT_MASK */ #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ -#define nATAPI_DEV_INT_MASK 0x0 #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ -#define nPIO_DONE_MASK 0x0 #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ -#define nMULTI_DONE_MASK 0x0 #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ -#define nUDMAIN_DONE_MASK 0x0 #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ -#define nUDMAOUT_DONE_MASK 0x0 #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ -#define nHOST_TERM_XFER_MASK 0x0 #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ -#define nMULTI_TERM_MASK 0x0 #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ -#define nUDMAIN_TERM_MASK 0x0 #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ -#define nUDMAOUT_TERM_MASK 0x0 /* Bit masks for ATAPI_INT_STATUS */ #define ATAPI_DEV_INT 0x1 /* Device interrupt status */ -#define nATAPI_DEV_INT 0x0 #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ -#define nPIO_DONE_INT 0x0 #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ -#define nMULTI_DONE_INT 0x0 #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ -#define nUDMAIN_DONE_INT 0x0 #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ -#define nUDMAOUT_DONE_INT 0x0 #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ -#define nHOST_TERM_XFER_INT 0x0 #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ -#define nMULTI_TERM_INT 0x0 #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ -#define nUDMAIN_TERM_INT 0x0 #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ -#define nUDMAOUT_TERM_INT 0x0 /* Bit masks for ATAPI_LINE_STATUS */ #define ATAPI_INTR 0x1 /* Device interrupt to host line status */ -#define nATAPI_INTR 0x0 #define ATAPI_DASP 0x2 /* Device dasp to host line status */ -#define nATAPI_DASP 0x0 #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ -#define nATAPI_CS0N 0x0 #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ -#define nATAPI_CS1N 0x0 #define ATAPI_ADDR 0x70 /* ATAPI address line status */ #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ -#define nATAPI_DMAREQ 0x0 #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ -#define nATAPI_DMAACKN 0x0 #define ATAPI_DIOWN 0x200 /* ATAPI write line status */ -#define nATAPI_DIOWN 0x0 #define ATAPI_DIORN 0x400 /* ATAPI read line status */ -#define nATAPI_DIORN 0x0 #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ -#define nATAPI_IORDY 0x0 /* Bit masks for ATAPI_SM_STATE */ @@ -2845,7 +2287,6 @@ /* Bit masks for ATAPI_TERMINATE */ #define ATAPI_HOST_TERM 0x1 /* Host terminationation */ -#define nATAPI_HOST_TERM 0x0 /* Bit masks for ATAPI_REG_TIM_0 */ @@ -2900,41 +2341,26 @@ /* Bit masks for TIMER_ENABLE1 */ #define TIMEN8 0x1 /* Timer 8 Enable */ -#define nTIMEN8 0x0 #define TIMEN9 0x2 /* Timer 9 Enable */ -#define nTIMEN9 0x0 #define TIMEN10 0x4 /* Timer 10 Enable */ -#define nTIMEN10 0x0 /* Bit masks for TIMER_DISABLE1 */ #define TIMDIS8 0x1 /* Timer 8 Disable */ -#define nTIMDIS8 0x0 #define TIMDIS9 0x2 /* Timer 9 Disable */ -#define nTIMDIS9 0x0 #define TIMDIS10 0x4 /* Timer 10 Disable */ -#define nTIMDIS10 0x0 /* Bit masks for TIMER_STATUS1 */ #define TIMIL8 0x1 /* Timer 8 Interrupt */ -#define nTIMIL8 0x0 #define TIMIL9 0x2 /* Timer 9 Interrupt */ -#define nTIMIL9 0x0 #define TIMIL10 0x4 /* Timer 10 Interrupt */ -#define nTIMIL10 0x0 #define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ -#define nTOVF_ERR8 0x0 #define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ -#define nTOVF_ERR9 0x0 #define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ -#define nTOVF_ERR10 0x0 #define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ -#define nTRUN8 0x0 #define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ -#define nTRUN9 0x0 #define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ -#define nTRUN10 0x0 /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ @@ -2945,131 +2371,77 @@ /* Bit masks for USB_POWER */ #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ -#define nENABLE_SUSPENDM 0x0 #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ -#define nSUSPEND_MODE 0x0 #define RESUME_MODE 0x4 /* DMA Mode */ -#define nRESUME_MODE 0x0 #define RESET 0x8 /* Reset indicator */ -#define nRESET 0x0 #define HS_MODE 0x10 /* High Speed mode indicator */ -#define nHS_MODE 0x0 #define HS_ENABLE 0x20 /* high Speed Enable */ -#define nHS_ENABLE 0x0 #define SOFT_CONN 0x40 /* Soft connect */ -#define nSOFT_CONN 0x0 #define ISO_UPDATE 0x80 /* Isochronous update */ -#define nISO_UPDATE 0x0 /* Bit masks for USB_INTRTX */ #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ -#define nEP0_TX 0x0 #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ -#define nEP1_TX 0x0 #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ -#define nEP2_TX 0x0 #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ -#define nEP3_TX 0x0 #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ -#define nEP4_TX 0x0 #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ -#define nEP5_TX 0x0 #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ -#define nEP6_TX 0x0 #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ -#define nEP7_TX 0x0 /* Bit masks for USB_INTRRX */ #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ -#define nEP1_RX 0x0 #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ -#define nEP2_RX 0x0 #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ -#define nEP3_RX 0x0 #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ -#define nEP4_RX 0x0 #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ -#define nEP5_RX 0x0 #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ -#define nEP6_RX 0x0 #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ -#define nEP7_RX 0x0 /* Bit masks for USB_INTRTXE */ #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ -#define nEP0_TX_E 0x0 #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ -#define nEP1_TX_E 0x0 #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ -#define nEP2_TX_E 0x0 #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ -#define nEP3_TX_E 0x0 #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ -#define nEP4_TX_E 0x0 #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ -#define nEP5_TX_E 0x0 #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ -#define nEP6_TX_E 0x0 #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ -#define nEP7_TX_E 0x0 /* Bit masks for USB_INTRRXE */ #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ -#define nEP1_RX_E 0x0 #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ -#define nEP2_RX_E 0x0 #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ -#define nEP3_RX_E 0x0 #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ -#define nEP4_RX_E 0x0 #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ -#define nEP5_RX_E 0x0 #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ -#define nEP6_RX_E 0x0 #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ -#define nEP7_RX_E 0x0 /* Bit masks for USB_INTRUSB */ #define SUSPEND_B 0x1 /* Suspend indicator */ -#define nSUSPEND_B 0x0 #define RESUME_B 0x2 /* Resume indicator */ -#define nRESUME_B 0x0 #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ -#define nRESET_OR_BABLE_B 0x0 #define SOF_B 0x8 /* Start of frame */ -#define nSOF_B 0x0 #define CONN_B 0x10 /* Connection indicator */ -#define nCONN_B 0x0 #define DISCON_B 0x20 /* Disconnect indicator */ -#define nDISCON_B 0x0 #define SESSION_REQ_B 0x40 /* Session Request */ -#define nSESSION_REQ_B 0x0 #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ -#define nVBUS_ERROR_B 0x0 /* Bit masks for USB_INTRUSBE */ #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ -#define nSUSPEND_BE 0x0 #define RESUME_BE 0x2 /* Resume indicator int enable */ -#define nRESUME_BE 0x0 #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ -#define nRESET_OR_BABLE_BE 0x0 #define SOF_BE 0x8 /* Start of frame int enable */ -#define nSOF_BE 0x0 #define CONN_BE 0x10 /* Connection indicator int enable */ -#define nCONN_BE 0x0 #define DISCON_BE 0x20 /* Disconnect indicator int enable */ -#define nDISCON_BE 0x0 #define SESSION_REQ_BE 0x40 /* Session Request int enable */ -#define nSESSION_REQ_BE 0x0 #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ -#define nVBUS_ERROR_BE 0x0 /* Bit masks for USB_FRAME */ @@ -3082,117 +2454,67 @@ /* Bit masks for USB_GLOBAL_CTL */ #define GLOBAL_ENA 0x1 /* enables USB module */ -#define nGLOBAL_ENA 0x0 #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ -#define nEP1_TX_ENA 0x0 #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ -#define nEP2_TX_ENA 0x0 #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ -#define nEP3_TX_ENA 0x0 #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ -#define nEP4_TX_ENA 0x0 #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ -#define nEP5_TX_ENA 0x0 #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ -#define nEP6_TX_ENA 0x0 #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ -#define nEP7_TX_ENA 0x0 #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ -#define nEP1_RX_ENA 0x0 #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ -#define nEP2_RX_ENA 0x0 #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ -#define nEP3_RX_ENA 0x0 #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ -#define nEP4_RX_ENA 0x0 #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ -#define nEP5_RX_ENA 0x0 #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ -#define nEP6_RX_ENA 0x0 #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ -#define nEP7_RX_ENA 0x0 /* Bit masks for USB_OTG_DEV_CTL */ #define SESSION 0x1 /* session indicator */ -#define nSESSION 0x0 #define HOST_REQ 0x2 /* Host negotiation request */ -#define nHOST_REQ 0x0 #define HOST_MODE 0x4 /* indicates USBDRC is a host */ -#define nHOST_MODE 0x0 #define VBUS0 0x8 /* Vbus level indicator[0] */ -#define nVBUS0 0x0 #define VBUS1 0x10 /* Vbus level indicator[1] */ -#define nVBUS1 0x0 #define LSDEV 0x20 /* Low-speed indicator */ -#define nLSDEV 0x0 #define FSDEV 0x40 /* Full or High-speed indicator */ -#define nFSDEV 0x0 #define B_DEVICE 0x80 /* A' or 'B' device indicator */ -#define nB_DEVICE 0x0 /* Bit masks for USB_OTG_VBUS_IRQ */ #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ -#define nDRIVE_VBUS_ON 0x0 #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ -#define nDRIVE_VBUS_OFF 0x0 #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ -#define nCHRG_VBUS_START 0x0 #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ -#define nCHRG_VBUS_END 0x0 #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ -#define nDISCHRG_VBUS_START 0x0 #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ -#define nDISCHRG_VBUS_END 0x0 /* Bit masks for USB_OTG_VBUS_MASK */ #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ -#define nDRIVE_VBUS_ON_ENA 0x0 #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ -#define nDRIVE_VBUS_OFF_ENA 0x0 #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ -#define nCHRG_VBUS_START_ENA 0x0 #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ -#define nCHRG_VBUS_END_ENA 0x0 #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ -#define nDISCHRG_VBUS_START_ENA 0x0 #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ -#define nDISCHRG_VBUS_END_ENA 0x0 /* Bit masks for USB_CSR0 */ #define RXPKTRDY 0x1 /* data packet receive indicator */ -#define nRXPKTRDY 0x0 #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ -#define nTXPKTRDY 0x0 #define STALL_SENT 0x4 /* STALL handshake sent */ -#define nSTALL_SENT 0x0 #define DATAEND 0x8 /* Data end indicator */ -#define nDATAEND 0x0 #define SETUPEND 0x10 /* Setup end */ -#define nSETUPEND 0x0 #define SENDSTALL 0x20 /* Send STALL handshake */ -#define nSENDSTALL 0x0 #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ -#define nSERVICED_RXPKTRDY 0x0 #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ -#define nSERVICED_SETUPEND 0x0 #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ -#define nFLUSHFIFO 0x0 #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ -#define nSTALL_RECEIVED_H 0x0 #define SETUPPKT_H 0x8 /* send Setup token host mode */ -#define nSETUPPKT_H 0x0 #define ERROR_H 0x10 /* timeout error indicator host mode */ -#define nERROR_H 0x0 #define REQPKT_H 0x20 /* Request an IN transaction host mode */ -#define nREQPKT_H 0x0 #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ -#define nSTATUSPKT_H 0x0 #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ -#define nNAK_TIMEOUT_H 0x0 /* Bit masks for USB_COUNT0 */ @@ -3213,37 +2535,21 @@ /* Bit masks for USB_TXCSR */ #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ -#define nTXPKTRDY_T 0x0 #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ -#define nFIFO_NOT_EMPTY_T 0x0 #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ -#define nUNDERRUN_T 0x0 #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ -#define nFLUSHFIFO_T 0x0 #define STALL_SEND_T 0x10 /* issue a Stall handshake */ -#define nSTALL_SEND_T 0x0 #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ -#define nSTALL_SENT_T 0x0 #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ -#define nCLEAR_DATATOGGLE_T 0x0 #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ -#define nINCOMPTX_T 0x0 #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ -#define nDMAREQMODE_T 0x0 #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ -#define nFORCE_DATATOGGLE_T 0x0 #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ -#define nDMAREQ_ENA_T 0x0 #define ISO_T 0x4000 /* enable Isochronous transfers */ -#define nISO_T 0x0 #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ -#define nAUTOSET_T 0x0 #define ERROR_TH 0x4 /* error condition host mode */ -#define nERROR_TH 0x0 #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ -#define nSTALL_RECEIVED_TH 0x0 #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ -#define nNAK_TIMEOUT_TH 0x0 /* Bit masks for USB_TXCOUNT */ @@ -3252,45 +2558,25 @@ /* Bit masks for USB_RXCSR */ #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ -#define nRXPKTRDY_R 0x0 #define FIFO_FULL_R 0x2 /* FIFO not empty */ -#define nFIFO_FULL_R 0x0 #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ -#define nOVERRUN_R 0x0 #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ -#define nDATAERROR_R 0x0 #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ -#define nFLUSHFIFO_R 0x0 #define STALL_SEND_R 0x20 /* issue a Stall handshake */ -#define nSTALL_SEND_R 0x0 #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ -#define nSTALL_SENT_R 0x0 #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ -#define nCLEAR_DATATOGGLE_R 0x0 #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ -#define nINCOMPRX_R 0x0 #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ -#define nDMAREQMODE_R 0x0 #define DISNYET_R 0x1000 /* disable Nyet handshakes */ -#define nDISNYET_R 0x0 #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ -#define nDMAREQ_ENA_R 0x0 #define ISO_R 0x4000 /* enable Isochronous transfers */ -#define nISO_R 0x0 #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ -#define nAUTOCLEAR_R 0x0 #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ -#define nERROR_RH 0x0 #define REQPKT_RH 0x20 /* request an IN transaction host mode */ -#define nREQPKT_RH 0x0 #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ -#define nSTALL_RECEIVED_RH 0x0 #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ -#define nINCOMPRX_RH 0x0 #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ -#define nDMAREQMODE_RH 0x0 #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ -#define nAUTOREQ_RH 0x0 /* Bit masks for USB_RXCOUNT */ @@ -3317,35 +2603,22 @@ /* Bit masks for USB_DMA_INTERRUPT */ #define DMA0_INT 0x1 /* DMA0 pending interrupt */ -#define nDMA0_INT 0x0 #define DMA1_INT 0x2 /* DMA1 pending interrupt */ -#define nDMA1_INT 0x0 #define DMA2_INT 0x4 /* DMA2 pending interrupt */ -#define nDMA2_INT 0x0 #define DMA3_INT 0x8 /* DMA3 pending interrupt */ -#define nDMA3_INT 0x0 #define DMA4_INT 0x10 /* DMA4 pending interrupt */ -#define nDMA4_INT 0x0 #define DMA5_INT 0x20 /* DMA5 pending interrupt */ -#define nDMA5_INT 0x0 #define DMA6_INT 0x40 /* DMA6 pending interrupt */ -#define nDMA6_INT 0x0 #define DMA7_INT 0x80 /* DMA7 pending interrupt */ -#define nDMA7_INT 0x0 /* Bit masks for USB_DMAxCONTROL */ #define DMA_ENA 0x1 /* DMA enable */ -#define nDMA_ENA 0x0 #define DIRECTION 0x2 /* direction of DMA transfer */ -#define nDIRECTION 0x0 #define MODE 0x4 /* DMA Bus error */ -#define nMODE 0x0 #define INT_ENA 0x8 /* Interrupt enable */ -#define nINT_ENA 0x0 #define EPNUM 0xf0 /* EP number */ #define BUSERROR 0x100 /* DMA Bus error */ -#define nBUSERROR 0x0 /* Bit masks for USB_DMAxADDRHIGH */ @@ -3366,26 +2639,16 @@ /* Bit masks for HMDMAx_CONTROL */ #define HMDMAEN 0x1 /* Handshake MDMA Enable */ -#define nHMDMAEN 0x0 #define REP 0x2 /* Handshake MDMA Request Polarity */ -#define nREP 0x0 #define UTE 0x8 /* Urgency Threshold Enable */ -#define nUTE 0x0 #define OIE 0x10 /* Overflow Interrupt Enable */ -#define nOIE 0x0 #define BDIE 0x20 /* Block Done Interrupt Enable */ -#define nBDIE 0x0 #define MBDI 0x40 /* Mask Block Done Interrupt */ -#define nMBDI 0x0 #define DRQ 0x300 /* Handshake MDMA Request Type */ #define RBC 0x1000 /* Force Reload of BCOUNT */ -#define nRBC 0x0 #define PS 0x2000 /* Pin Status */ -#define nPS 0x0 #define OI 0x4000 /* Overflow Interrupt Generated */ -#define nOI 0x0 #define BDI 0x8000 /* Block Done Interrupt Generated */ -#define nBDI 0x0 /* ******************************************* */ /* MULTI BIT MACRO ENUMERATIONS */ diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h index a1b200fe6a1f..895ddd40a838 100644 --- a/include/asm-blackfin/mach-bf548/defBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h @@ -46,7 +46,7 @@ /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ -#define CHIPID 0xffc00014 +#define CHIPID 0xffc00014 /* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */ @@ -1512,231 +1512,144 @@ /* and MULTI BIT READ MACROS */ /* ********************************************************** */ +/* SIC_IMASK Masks */ +#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ +#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ +#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ +#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ + +/* SIC_IWR Masks */ +#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ +#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ +#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ +#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ + /* Bit masks for SIC_IAR0 */ -#define IRQ_PLL_WAKEUP 0x1 /* PLL Wakeup */ -#define nIRQ_PLL_WAKEUP 0x0 +#define PLL_WAKEUP 0x1 /* PLL Wakeup */ /* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */ -#define IRQ_DMA0_ERR 0x2 /* DMA Controller 0 Error */ -#define nIRQ_DMA0_ERR 0x0 -#define IRQ_EPPI0_ERR 0x4 /* EPPI0 Error */ -#define nIRQ_EPPI0_ERR 0x0 -#define IRQ_SPORT0_ERR 0x8 /* SPORT0 Error */ -#define nIRQ_SPORT0_ERR 0x0 -#define IRQ_SPORT1_ERR 0x10 /* SPORT1 Error */ -#define nIRQ_SPORT1_ERR 0x0 -#define IRQ_SPI0_ERR 0x20 /* SPI0 Error */ -#define nIRQ_SPI0_ERR 0x0 -#define IRQ_UART0_ERR 0x40 /* UART0 Error */ -#define nIRQ_UART0_ERR 0x0 -#define IRQ_RTC 0x80 /* Real-Time Clock */ -#define nIRQ_RTC 0x0 -#define IRQ_DMA12 0x100 /* DMA Channel 12 */ -#define nIRQ_DMA12 0x0 -#define IRQ_DMA0 0x200 /* DMA Channel 0 */ -#define nIRQ_DMA0 0x0 -#define IRQ_DMA1 0x400 /* DMA Channel 1 */ -#define nIRQ_DMA1 0x0 -#define IRQ_DMA2 0x800 /* DMA Channel 2 */ -#define nIRQ_DMA2 0x0 -#define IRQ_DMA3 0x1000 /* DMA Channel 3 */ -#define nIRQ_DMA3 0x0 -#define IRQ_DMA4 0x2000 /* DMA Channel 4 */ -#define nIRQ_DMA4 0x0 -#define IRQ_DMA6 0x4000 /* DMA Channel 6 */ -#define nIRQ_DMA6 0x0 -#define IRQ_DMA7 0x8000 /* DMA Channel 7 */ -#define nIRQ_DMA7 0x0 -#define IRQ_PINT0 0x80000 /* Pin Interrupt 0 */ -#define nIRQ_PINT0 0x0 -#define IRQ_PINT1 0x100000 /* Pin Interrupt 1 */ -#define nIRQ_PINT1 0x0 -#define IRQ_MDMA0 0x200000 /* Memory DMA Stream 0 */ -#define nIRQ_MDMA0 0x0 -#define IRQ_MDMA1 0x400000 /* Memory DMA Stream 1 */ -#define nIRQ_MDMA1 0x0 -#define IRQ_WDOG 0x800000 /* Watchdog Timer */ -#define nIRQ_WDOG 0x0 -#define IRQ_DMA1_ERR 0x1000000 /* DMA Controller 1 Error */ -#define nIRQ_DMA1_ERR 0x0 -#define IRQ_SPORT2_ERR 0x2000000 /* SPORT2 Error */ -#define nIRQ_SPORT2_ERR 0x0 -#define IRQ_SPORT3_ERR 0x4000000 /* SPORT3 Error */ -#define nIRQ_SPORT3_ERR 0x0 -#define IRQ_MXVR_SD 0x8000000 /* MXVR Synchronous Data */ -#define nIRQ_MXVR_SD 0x0 -#define IRQ_SPI1_ERR 0x10000000 /* SPI1 Error */ -#define nIRQ_SPI1_ERR 0x0 -#define IRQ_SPI2_ERR 0x20000000 /* SPI2 Error */ -#define nIRQ_SPI2_ERR 0x0 -#define IRQ_UART1_ERR 0x40000000 /* UART1 Error */ -#define nIRQ_UART1_ERR 0x0 -#define IRQ_UART2_ERR 0x80000000 /* UART2 Error */ -#define nIRQ_UART2_ERR 0x0 +#define DMA0_ERR 0x2 /* DMA Controller 0 Error */ +#define EPPI0_ERR 0x4 /* EPPI0 Error */ +#define SPORT0_ERR 0x8 /* SPORT0 Error */ +#define SPORT1_ERR 0x10 /* SPORT1 Error */ +#define SPI0_ERR 0x20 /* SPI0 Error */ +#define UART0_ERR 0x40 /* UART0 Error */ +#define RTC 0x80 /* Real-Time Clock */ +#define DMA12 0x100 /* DMA Channel 12 */ +#define DMA0 0x200 /* DMA Channel 0 */ +#define DMA1 0x400 /* DMA Channel 1 */ +#define DMA2 0x800 /* DMA Channel 2 */ +#define DMA3 0x1000 /* DMA Channel 3 */ +#define DMA4 0x2000 /* DMA Channel 4 */ +#define DMA6 0x4000 /* DMA Channel 6 */ +#define DMA7 0x8000 /* DMA Channel 7 */ +#define PINT0 0x80000 /* Pin Interrupt 0 */ +#define PINT1 0x100000 /* Pin Interrupt 1 */ +#define MDMA0 0x200000 /* Memory DMA Stream 0 */ +#define MDMA1 0x400000 /* Memory DMA Stream 1 */ +#define WDOG 0x800000 /* Watchdog Timer */ +#define DMA1_ERR 0x1000000 /* DMA Controller 1 Error */ +#define SPORT2_ERR 0x2000000 /* SPORT2 Error */ +#define SPORT3_ERR 0x4000000 /* SPORT3 Error */ +#define MXVR_SD 0x8000000 /* MXVR Synchronous Data */ +#define SPI1_ERR 0x10000000 /* SPI1 Error */ +#define SPI2_ERR 0x20000000 /* SPI2 Error */ +#define UART1_ERR 0x40000000 /* UART1 Error */ +#define UART2_ERR 0x80000000 /* UART2 Error */ /* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */ -#define IRQ_CAN0_ERR 0x1 /* CAN0 Error */ -#define nIRQ_CAN0_ERR 0x0 -#define IRQ_DMA18 0x2 /* DMA Channel 18 */ -#define nIRQ_DMA18 0x0 -#define IRQ_DMA19 0x4 /* DMA Channel 19 */ -#define nIRQ_DMA19 0x0 -#define IRQ_DMA20 0x8 /* DMA Channel 20 */ -#define nIRQ_DMA20 0x0 -#define IRQ_DMA21 0x10 /* DMA Channel 21 */ -#define nIRQ_DMA21 0x0 -#define IRQ_DMA13 0x20 /* DMA Channel 13 */ -#define nIRQ_DMA13 0x0 -#define IRQ_DMA14 0x40 /* DMA Channel 14 */ -#define nIRQ_DMA14 0x0 -#define IRQ_DMA5 0x80 /* DMA Channel 5 */ -#define nIRQ_DMA5 0x0 -#define IRQ_DMA23 0x100 /* DMA Channel 23 */ -#define nIRQ_DMA23 0x0 -#define IRQ_DMA8 0x200 /* DMA Channel 8 */ -#define nIRQ_DMA8 0x0 -#define IRQ_DMA9 0x400 /* DMA Channel 9 */ -#define nIRQ_DMA9 0x0 -#define IRQ_DMA10 0x800 /* DMA Channel 10 */ -#define nIRQ_DMA10 0x0 -#define IRQ_DMA11 0x1000 /* DMA Channel 11 */ -#define nIRQ_DMA11 0x0 -#define IRQ_TWI0 0x2000 /* TWI0 */ -#define nIRQ_TWI0 0x0 -#define IRQ_TWI1 0x4000 /* TWI1 */ -#define nIRQ_TWI1 0x0 -#define IRQ_CAN0_RX 0x8000 /* CAN0 Receive */ -#define nIRQ_CAN0_RX 0x0 -#define IRQ_CAN0_TX 0x10000 /* CAN0 Transmit */ -#define nIRQ_CAN0_TX 0x0 -#define IRQ_MDMA2 0x20000 /* Memory DMA Stream 0 */ -#define nIRQ_MDMA2 0x0 -#define IRQ_MDMA3 0x40000 /* Memory DMA Stream 1 */ -#define nIRQ_MDMA3 0x0 -#define IRQ_MXVR_STAT 0x80000 /* MXVR Status */ -#define nIRQ_MXVR_STAT 0x0 -#define IRQ_MXVR_CM 0x100000 /* MXVR Control Message */ -#define nIRQ_MXVR_CM 0x0 -#define IRQ_MXVR_AP 0x200000 /* MXVR Asynchronous Packet */ -#define nIRQ_MXVR_AP 0x0 -#define IRQ_EPPI1_ERR 0x400000 /* EPPI1 Error */ -#define nIRQ_EPPI1_ERR 0x0 -#define IRQ_EPPI2_ERR 0x800000 /* EPPI2 Error */ -#define nIRQ_EPPI2_ERR 0x0 -#define IRQ_UART3_ERR 0x1000000 /* UART3 Error */ -#define nIRQ_UART3_ERR 0x0 -#define IRQ_HOST_ERR 0x2000000 /* Host DMA Port Error */ -#define nIRQ_HOST_ERR 0x0 -#define IRQ_USB_ERR 0x4000000 /* USB Error */ -#define nIRQ_USB_ERR 0x0 -#define IRQ_PIXC_ERR 0x8000000 /* Pixel Compositor Error */ -#define nIRQ_PIXC_ERR 0x0 -#define IRQ_NFC_ERR 0x10000000 /* Nand Flash Controller Error */ -#define nIRQ_NFC_ERR 0x0 -#define IRQ_ATAPI_ERR 0x20000000 /* ATAPI Error */ -#define nIRQ_ATAPI_ERR 0x0 -#define IRQ_CAN1_ERR 0x40000000 /* CAN1 Error */ -#define nIRQ_CAN1_ERR 0x0 -#define IRQ_DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */ -#define nIRQ_DMAR0_ERR 0x0 -#define IRQ_DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */ -#define nIRQ_DMAR1_ERR 0x0 -#define IRQ_DMAR0 0x80000000 /* DMAR0 Block */ -#define nIRQ_DMAR0 0x0 -#define IRQ_DMAR1 0x80000000 /* DMAR1 Block */ -#define nIRQ_DMAR1 0x0 +#define CAN0_ERR 0x1 /* CAN0 Error */ +#define DMA18 0x2 /* DMA Channel 18 */ +#define DMA19 0x4 /* DMA Channel 19 */ +#define DMA20 0x8 /* DMA Channel 20 */ +#define DMA21 0x10 /* DMA Channel 21 */ +#define DMA13 0x20 /* DMA Channel 13 */ +#define DMA14 0x40 /* DMA Channel 14 */ +#define DMA5 0x80 /* DMA Channel 5 */ +#define DMA23 0x100 /* DMA Channel 23 */ +#define DMA8 0x200 /* DMA Channel 8 */ +#define DMA9 0x400 /* DMA Channel 9 */ +#define DMA10 0x800 /* DMA Channel 10 */ +#define DMA11 0x1000 /* DMA Channel 11 */ +#define TWI0 0x2000 /* TWI0 */ +#define TWI1 0x4000 /* TWI1 */ +#define CAN0_RX 0x8000 /* CAN0 Receive */ +#define CAN0_TX 0x10000 /* CAN0 Transmit */ +#define MDMA2 0x20000 /* Memory DMA Stream 0 */ +#define MDMA3 0x40000 /* Memory DMA Stream 1 */ +#define MXVR_STAT 0x80000 /* MXVR Status */ +#define MXVR_CM 0x100000 /* MXVR Control Message */ +#define MXVR_AP 0x200000 /* MXVR Asynchronous Packet */ +#define EPPI1_ERR 0x400000 /* EPPI1 Error */ +#define EPPI2_ERR 0x800000 /* EPPI2 Error */ +#define UART3_ERR 0x1000000 /* UART3 Error */ +#define HOST_ERR 0x2000000 /* Host DMA Port Error */ +#define USB_ERR 0x4000000 /* USB Error */ +#define PIXC_ERR 0x8000000 /* Pixel Compositor Error */ +#define NFC_ERR 0x10000000 /* Nand Flash Controller Error */ +#define ATAPI_ERR 0x20000000 /* ATAPI Error */ +#define CAN1_ERR 0x40000000 /* CAN1 Error */ +#define DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */ +#define DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */ +#define DMAR0 0x80000000 /* DMAR0 Block */ +#define DMAR1 0x80000000 /* DMAR1 Block */ /* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */ -#define IRQ_DMA15 0x1 /* DMA Channel 15 */ -#define nIRQ_DMA15 0x0 -#define IRQ_DMA16 0x2 /* DMA Channel 16 */ -#define nIRQ_DMA16 0x0 -#define IRQ_DMA17 0x4 /* DMA Channel 17 */ -#define nIRQ_DMA17 0x0 -#define IRQ_DMA22 0x8 /* DMA Channel 22 */ -#define nIRQ_DMA22 0x0 -#define IRQ_CNT 0x10 /* Counter */ -#define nIRQ_CNT 0x0 -#define IRQ_KEY 0x20 /* Keypad */ -#define nIRQ_KEY 0x0 -#define IRQ_CAN1_RX 0x40 /* CAN1 Receive */ -#define nIRQ_CAN1_RX 0x0 -#define IRQ_CAN1_TX 0x80 /* CAN1 Transmit */ -#define nIRQ_CAN1_TX 0x0 -#define IRQ_SDH_MASK0 0x100 /* SDH Mask 0 */ -#define nIRQ_SDH_MASK0 0x0 -#define IRQ_SDH_MASK1 0x200 /* SDH Mask 1 */ -#define nIRQ_SDH_MASK1 0x0 -#define IRQ_USB_EINT 0x400 /* USB Exception */ -#define nIRQ_USB_EINT 0x0 -#define IRQ_USB_INT0 0x800 /* USB Interrupt 0 */ -#define nIRQ_USB_INT0 0x0 -#define IRQ_USB_INT1 0x1000 /* USB Interrupt 1 */ -#define nIRQ_USB_INT1 0x0 -#define IRQ_USB_INT2 0x2000 /* USB Interrupt 2 */ -#define nIRQ_USB_INT2 0x0 -#define IRQ_USB_DMAINT 0x4000 /* USB DMA */ -#define nIRQ_USB_DMAINT 0x0 -#define IRQ_OTPSEC 0x8000 /* OTP Access Complete */ -#define nIRQ_OTPSEC 0x0 -#define IRQ_TIMER0 0x400000 /* Timer 0 */ -#define nIRQ_TIMER0 0x0 -#define IRQ_TIMER1 0x800000 /* Timer 1 */ -#define nIRQ_TIMER1 0x0 -#define IRQ_TIMER2 0x1000000 /* Timer 2 */ -#define nIRQ_TIMER2 0x0 -#define IRQ_TIMER3 0x2000000 /* Timer 3 */ -#define nIRQ_TIMER3 0x0 -#define IRQ_TIMER4 0x4000000 /* Timer 4 */ -#define nIRQ_TIMER4 0x0 -#define IRQ_TIMER5 0x8000000 /* Timer 5 */ -#define nIRQ_TIMER5 0x0 -#define IRQ_TIMER6 0x10000000 /* Timer 6 */ -#define nIRQ_TIMER6 0x0 -#define IRQ_TIMER7 0x20000000 /* Timer 7 */ -#define nIRQ_TIMER7 0x0 -#define IRQ_PINT2 0x40000000 /* Pin Interrupt 2 */ -#define nIRQ_PINT2 0x0 -#define IRQ_PINT3 0x80000000 /* Pin Interrupt 3 */ -#define nIRQ_PINT3 0x0 +#define DMA15 0x1 /* DMA Channel 15 */ +#define DMA16 0x2 /* DMA Channel 16 */ +#define DMA17 0x4 /* DMA Channel 17 */ +#define DMA22 0x8 /* DMA Channel 22 */ +#define CNT 0x10 /* Counter */ +#define KEY 0x20 /* Keypad */ +#define CAN1_RX 0x40 /* CAN1 Receive */ +#define CAN1_TX 0x80 /* CAN1 Transmit */ +#define SDH_INT_MASK0 0x100 /* SDH Mask 0 */ +#define SDH_INT_MASK1 0x200 /* SDH Mask 1 */ +#define USB_EINT 0x400 /* USB Exception */ +#define USB_INT0 0x800 /* USB Interrupt 0 */ +#define USB_INT1 0x1000 /* USB Interrupt 1 */ +#define USB_INT2 0x2000 /* USB Interrupt 2 */ +#define USB_DMAINT 0x4000 /* USB DMA */ +#define OTPSEC 0x8000 /* OTP Access Complete */ +#define TIMER0 0x400000 /* Timer 0 */ +#define TIMER1 0x800000 /* Timer 1 */ +#define TIMER2 0x1000000 /* Timer 2 */ +#define TIMER3 0x2000000 /* Timer 3 */ +#define TIMER4 0x4000000 /* Timer 4 */ +#define TIMER5 0x8000000 /* Timer 5 */ +#define TIMER6 0x10000000 /* Timer 6 */ +#define TIMER7 0x20000000 /* Timer 7 */ +#define PINT2 0x40000000 /* Pin Interrupt 2 */ +#define PINT3 0x80000000 /* Pin Interrupt 3 */ /* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */ #define DMAEN 0x1 /* DMA Channel Enable */ -#define nDMAEN 0x0 #define WNR 0x2 /* DMA Direction */ -#define nWNR 0x0 -#define WDSIZE 0xc /* Transfer Word Size */ +#define WDSIZE_8 0x0 /* Transfer Word Size = 8 */ +#define WDSIZE_16 0x4 /* Transfer Word Size = 16 */ +#define WDSIZE_32 0x8 /* Transfer Word Size = 32 */ #define DMA2D 0x10 /* DMA Mode */ -#define nDMA2D 0x0 #define RESTART 0x20 /* Work Unit Transitions */ -#define nRESTART 0x0 #define DI_SEL 0x40 /* Data Interrupt Timing Select */ -#define nDI_SEL 0x0 #define DI_EN 0x80 /* Data Interrupt Enable */ -#define nDI_EN 0x0 #define NDSIZE 0xf00 /* Flex Descriptor Size */ #define DMAFLOW 0xf000 /* Next Operation */ /* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ #define DMA_DONE 0x1 /* DMA Completion Interrupt Status */ -#define nDMA_DONE 0x0 #define DMA_ERR 0x2 /* DMA Error Interrupt Status */ -#define nDMA_ERR 0x0 #define DFETCH 0x4 /* DMA Descriptor Fetch */ -#define nDFETCH 0x0 #define DMA_RUN 0x8 /* DMA Channel Running */ -#define nDMA_RUN 0x0 /* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ #define CTYPE 0x40 /* DMA Channel Type */ -#define nCTYPE 0x0 #define PMAP 0xf000 /* Peripheral Mapped To This Channel */ /* Bit masks for DMACx_TCPER */ @@ -1756,29 +1669,28 @@ /* Bit masks for DMAC1_PERIMUX */ #define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */ -#define nPMUXSDH 0x0 -/* Bit masks for EBIU_AMGCTL */ +/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ +/* EBIU_AMGCTL Masks */ +#define AMCKEN 0x0001 /* Enable CLKOUT */ +#define AMBEN_NONE 0x0000 /* All Banks Disabled */ +#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ +#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ +#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ +#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ -#define AMCKEN 0x1 /* Async Memory Enable */ -#define nAMCKEN 0x0 -#define AMBEN 0xe /* Async bank enable */ /* Bit masks for EBIU_AMBCTL0 */ #define B0RDYEN 0x1 /* Bank 0 ARDY Enable */ -#define nB0RDYEN 0x0 #define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */ -#define nB0RDYPOL 0x0 #define B0TT 0xc /* Bank 0 transition time */ #define B0ST 0x30 /* Bank 0 Setup time */ #define B0HT 0xc0 /* Bank 0 Hold time */ #define B0RAT 0xf00 /* Bank 0 Read access time */ #define B0WAT 0xf000 /* Bank 0 write access time */ #define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */ -#define nB1RDYEN 0x0 #define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */ -#define nB1RDYPOL 0x0 #define B1TT 0xc0000 /* Bank 1 transition time */ #define B1ST 0x300000 /* Bank 1 Setup time */ #define B1HT 0xc00000 /* Bank 1 Hold time */ @@ -1788,18 +1700,14 @@ /* Bit masks for EBIU_AMBCTL1 */ #define B2RDYEN 0x1 /* Bank 2 ARDY Enable */ -#define nB2RDYEN 0x0 #define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */ -#define nB2RDYPOL 0x0 #define B2TT 0xc /* Bank 2 transition time */ #define B2ST 0x30 /* Bank 2 Setup time */ #define B2HT 0xc0 /* Bank 2 Hold time */ #define B2RAT 0xf00 /* Bank 2 Read access time */ #define B2WAT 0xf000 /* Bank 2 write access time */ #define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */ -#define nB3RDYEN 0x0 #define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */ -#define nB3RDYPOL 0x0 #define B3TT 0xc0000 /* Bank 3 transition time */ #define B3ST 0x300000 /* Bank 3 Setup time */ #define B3HT 0xc00000 /* Bank 3 Hold time */ @@ -1823,19 +1731,15 @@ /* Bit masks for EBIU_FCTL */ #define TESTSETLOCK 0x1 /* Test set lock */ -#define nTESTSETLOCK 0x0 #define BCLK 0x6 /* Burst clock frequency */ #define PGWS 0x38 /* Page wait states */ #define PGSZ 0x40 /* Page size */ -#define nPGSZ 0x0 #define RDDL 0x380 /* Read data delay */ /* Bit masks for EBIU_ARBSTAT */ #define ARBSTAT 0x1 /* Arbitration status */ -#define nARBSTAT 0x0 #define BGSTAT 0x2 /* Bus grant status */ -#define nBGSTAT 0x0 /* Bit masks for EBIU_DDRCTL0 */ @@ -1861,9 +1765,7 @@ #define BURSTLENGTH 0x7 /* Burst length */ #define CASLATENCY 0x70 /* CAS latency */ #define DLLRESET 0x100 /* DLL Reset */ -#define nDLLRESET 0x0 #define REGE 0x1000 /* Register mode enable */ -#define nREGE 0x0 /* Bit masks for EBIU_DDRCTL3 */ @@ -1876,30 +1778,19 @@ #define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */ #define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */ #define DEB1_URGENT 0x1000 /* DEB1 Urgent */ -#define nDEB1_URGENT 0x0 #define DEB2_URGENT 0x2000 /* DEB2 Urgent */ -#define nDEB2_URGENT 0x0 #define DEB3_URGENT 0x4000 /* DEB3 Urgent */ -#define nDEB3_URGENT 0x0 /* Bit masks for EBIU_ERRMST */ #define DEB1_ERROR 0x1 /* DEB1 Error */ -#define nDEB1_ERROR 0x0 #define DEB2_ERROR 0x2 /* DEB2 Error */ -#define nDEB2_ERROR 0x0 #define DEB3_ERROR 0x4 /* DEB3 Error */ -#define nDEB3_ERROR 0x0 #define CORE_ERROR 0x8 /* Core error */ -#define nCORE_ERROR 0x0 #define DEB_MERROR 0x10 /* DEB1 Error (2nd) */ -#define nDEB_MERROR 0x0 #define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */ -#define nDEB2_MERROR 0x0 #define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */ -#define nDEB3_MERROR 0x0 #define CORE_MERROR 0x80 /* Core Error (2nd) */ -#define nCORE_MERROR 0x0 /* Bit masks for EBIU_ERRADD */ @@ -1908,15 +1799,10 @@ /* Bit masks for EBIU_RSTCTL */ #define DDRSRESET 0x1 /* DDR soft reset */ -#define nDDRSRESET 0x0 #define PFTCHSRESET 0x4 /* DDR prefetch reset */ -#define nPFTCHSRESET 0x0 #define SRREQ 0x8 /* Self-refresh request */ -#define nSRREQ 0x0 #define SRACK 0x10 /* Self-refresh acknowledge */ -#define nSRACK 0x0 #define MDDRENABLE 0x20 /* Mobile DDR enable */ -#define nMDDRENABLE 0x0 /* Bit masks for EBIU_DDRBRC0 */ @@ -2013,136 +1899,74 @@ /* Bit masks for EBIU_DDRMCEN */ #define B0WCENABLE 0x1 /* Bank 0 write count enable */ -#define nB0WCENABLE 0x0 #define B1WCENABLE 0x2 /* Bank 1 write count enable */ -#define nB1WCENABLE 0x0 #define B2WCENABLE 0x4 /* Bank 2 write count enable */ -#define nB2WCENABLE 0x0 #define B3WCENABLE 0x8 /* Bank 3 write count enable */ -#define nB3WCENABLE 0x0 #define B4WCENABLE 0x10 /* Bank 4 write count enable */ -#define nB4WCENABLE 0x0 #define B5WCENABLE 0x20 /* Bank 5 write count enable */ -#define nB5WCENABLE 0x0 #define B6WCENABLE 0x40 /* Bank 6 write count enable */ -#define nB6WCENABLE 0x0 #define B7WCENABLE 0x80 /* Bank 7 write count enable */ -#define nB7WCENABLE 0x0 #define B0RCENABLE 0x100 /* Bank 0 read count enable */ -#define nB0RCENABLE 0x0 #define B1RCENABLE 0x200 /* Bank 1 read count enable */ -#define nB1RCENABLE 0x0 #define B2RCENABLE 0x400 /* Bank 2 read count enable */ -#define nB2RCENABLE 0x0 #define B3RCENABLE 0x800 /* Bank 3 read count enable */ -#define nB3RCENABLE 0x0 #define B4RCENABLE 0x1000 /* Bank 4 read count enable */ -#define nB4RCENABLE 0x0 #define B5RCENABLE 0x2000 /* Bank 5 read count enable */ -#define nB5RCENABLE 0x0 #define B6RCENABLE 0x4000 /* Bank 6 read count enable */ -#define nB6RCENABLE 0x0 #define B7RCENABLE 0x8000 /* Bank 7 read count enable */ -#define nB7RCENABLE 0x0 #define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */ -#define nROWACTCENABLE 0x0 #define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */ -#define nRWTCENABLE 0x0 #define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */ -#define nARCENABLE 0x0 #define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */ -#define nGC0ENABLE 0x0 #define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */ -#define nGC1ENABLE 0x0 #define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */ -#define nGC2ENABLE 0x0 #define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */ -#define nGC3ENABLE 0x0 #define GCCONTROL 0x3000000 /* DDR Grant Count Control */ /* Bit masks for EBIU_DDRMCCL */ #define CB0WCOUNT 0x1 /* Clear write count 0 */ -#define nCB0WCOUNT 0x0 #define CB1WCOUNT 0x2 /* Clear write count 1 */ -#define nCB1WCOUNT 0x0 #define CB2WCOUNT 0x4 /* Clear write count 2 */ -#define nCB2WCOUNT 0x0 #define CB3WCOUNT 0x8 /* Clear write count 3 */ -#define nCB3WCOUNT 0x0 #define CB4WCOUNT 0x10 /* Clear write count 4 */ -#define nCB4WCOUNT 0x0 #define CB5WCOUNT 0x20 /* Clear write count 5 */ -#define nCB5WCOUNT 0x0 #define CB6WCOUNT 0x40 /* Clear write count 6 */ -#define nCB6WCOUNT 0x0 #define CB7WCOUNT 0x80 /* Clear write count 7 */ -#define nCB7WCOUNT 0x0 #define CBRCOUNT 0x100 /* Clear read count 0 */ -#define nCBRCOUNT 0x0 #define CB1RCOUNT 0x200 /* Clear read count 1 */ -#define nCB1RCOUNT 0x0 #define CB2RCOUNT 0x400 /* Clear read count 2 */ -#define nCB2RCOUNT 0x0 #define CB3RCOUNT 0x800 /* Clear read count 3 */ -#define nCB3RCOUNT 0x0 #define CB4RCOUNT 0x1000 /* Clear read count 4 */ -#define nCB4RCOUNT 0x0 #define CB5RCOUNT 0x2000 /* Clear read count 5 */ -#define nCB5RCOUNT 0x0 #define CB6RCOUNT 0x4000 /* Clear read count 6 */ -#define nCB6RCOUNT 0x0 #define CB7RCOUNT 0x8000 /* Clear read count 7 */ -#define nCB7RCOUNT 0x0 #define CRACOUNT 0x10000 /* Clear row activation count */ -#define nCRACOUNT 0x0 #define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */ -#define nCRWTACOUNT 0x0 #define CARCOUNT 0x40000 /* Clear auto-refresh count */ -#define nCARCOUNT 0x0 #define CG0COUNT 0x100000 /* Clear grant count 0 */ -#define nCG0COUNT 0x0 #define CG1COUNT 0x200000 /* Clear grant count 1 */ -#define nCG1COUNT 0x0 #define CG2COUNT 0x400000 /* Clear grant count 2 */ -#define nCG2COUNT 0x0 #define CG3COUNT 0x800000 /* Clear grant count 3 */ -#define nCG3COUNT 0x0 /* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */ #define Px0 0x1 /* GPIO 0 */ -#define nPx0 0x0 #define Px1 0x2 /* GPIO 1 */ -#define nPx1 0x0 #define Px2 0x4 /* GPIO 2 */ -#define nPx2 0x0 #define Px3 0x8 /* GPIO 3 */ -#define nPx3 0x0 #define Px4 0x10 /* GPIO 4 */ -#define nPx4 0x0 #define Px5 0x20 /* GPIO 5 */ -#define nPx5 0x0 #define Px6 0x40 /* GPIO 6 */ -#define nPx6 0x0 #define Px7 0x80 /* GPIO 7 */ -#define nPx7 0x0 #define Px8 0x100 /* GPIO 8 */ -#define nPx8 0x0 #define Px9 0x200 /* GPIO 9 */ -#define nPx9 0x0 #define Px10 0x400 /* GPIO 10 */ -#define nPx10 0x0 #define Px11 0x800 /* GPIO 11 */ -#define nPx11 0x0 #define Px12 0x1000 /* GPIO 12 */ -#define nPx12 0x0 #define Px13 0x2000 /* GPIO 13 */ -#define nPx13 0x0 #define Px14 0x4000 /* GPIO 14 */ -#define nPx14 0x0 #define Px15 0x8000 /* GPIO 15 */ -#define nPx15 0x0 /* Bit masks for PORTA_MUX - PORTJ_MUX */ @@ -2167,223 +1991,129 @@ /* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */ #define IB0 0x1 /* Interrupt Bit 0 */ -#define nIB0 0x0 #define IB1 0x2 /* Interrupt Bit 1 */ -#define nIB1 0x0 #define IB2 0x4 /* Interrupt Bit 2 */ -#define nIB2 0x0 #define IB3 0x8 /* Interrupt Bit 3 */ -#define nIB3 0x0 #define IB4 0x10 /* Interrupt Bit 4 */ -#define nIB4 0x0 #define IB5 0x20 /* Interrupt Bit 5 */ -#define nIB5 0x0 #define IB6 0x40 /* Interrupt Bit 6 */ -#define nIB6 0x0 #define IB7 0x80 /* Interrupt Bit 7 */ -#define nIB7 0x0 #define IB8 0x100 /* Interrupt Bit 8 */ -#define nIB8 0x0 #define IB9 0x200 /* Interrupt Bit 9 */ -#define nIB9 0x0 #define IB10 0x400 /* Interrupt Bit 10 */ -#define nIB10 0x0 #define IB11 0x800 /* Interrupt Bit 11 */ -#define nIB11 0x0 #define IB12 0x1000 /* Interrupt Bit 12 */ -#define nIB12 0x0 #define IB13 0x2000 /* Interrupt Bit 13 */ -#define nIB13 0x0 #define IB14 0x4000 /* Interrupt Bit 14 */ -#define nIB14 0x0 #define IB15 0x8000 /* Interrupt Bit 15 */ -#define nIB15 0x0 /* Bit masks for TIMERx_CONFIG */ #define TMODE 0x3 /* Timer Mode */ #define PULSE_HI 0x4 /* Pulse Polarity */ -#define nPULSE_HI 0x0 #define PERIOD_CNT 0x8 /* Period Count */ -#define nPERIOD_CNT 0x0 #define IRQ_ENA 0x10 /* Interrupt Request Enable */ -#define nIRQ_ENA 0x0 #define TIN_SEL 0x20 /* Timer Input Select */ -#define nTIN_SEL 0x0 #define OUT_DIS 0x40 /* Output Pad Disable */ -#define nOUT_DIS 0x0 #define CLK_SEL 0x80 /* Timer Clock Select */ -#define nCLK_SEL 0x0 #define TOGGLE_HI 0x100 /* Toggle Mode */ -#define nTOGGLE_HI 0x0 #define EMU_RUN 0x200 /* Emulation Behavior Select */ -#define nEMU_RUN 0x0 #define ERR_TYP 0xc000 /* Error Type */ /* Bit masks for TIMER_ENABLE0 */ #define TIMEN0 0x1 /* Timer 0 Enable */ -#define nTIMEN0 0x0 #define TIMEN1 0x2 /* Timer 1 Enable */ -#define nTIMEN1 0x0 #define TIMEN2 0x4 /* Timer 2 Enable */ -#define nTIMEN2 0x0 #define TIMEN3 0x8 /* Timer 3 Enable */ -#define nTIMEN3 0x0 #define TIMEN4 0x10 /* Timer 4 Enable */ -#define nTIMEN4 0x0 #define TIMEN5 0x20 /* Timer 5 Enable */ -#define nTIMEN5 0x0 #define TIMEN6 0x40 /* Timer 6 Enable */ -#define nTIMEN6 0x0 #define TIMEN7 0x80 /* Timer 7 Enable */ -#define nTIMEN7 0x0 /* Bit masks for TIMER_DISABLE0 */ #define TIMDIS0 0x1 /* Timer 0 Disable */ -#define nTIMDIS0 0x0 #define TIMDIS1 0x2 /* Timer 1 Disable */ -#define nTIMDIS1 0x0 #define TIMDIS2 0x4 /* Timer 2 Disable */ -#define nTIMDIS2 0x0 #define TIMDIS3 0x8 /* Timer 3 Disable */ -#define nTIMDIS3 0x0 #define TIMDIS4 0x10 /* Timer 4 Disable */ -#define nTIMDIS4 0x0 #define TIMDIS5 0x20 /* Timer 5 Disable */ -#define nTIMDIS5 0x0 #define TIMDIS6 0x40 /* Timer 6 Disable */ -#define nTIMDIS6 0x0 #define TIMDIS7 0x80 /* Timer 7 Disable */ -#define nTIMDIS7 0x0 /* Bit masks for TIMER_STATUS0 */ #define TIMIL0 0x1 /* Timer 0 Interrupt */ -#define nTIMIL0 0x0 #define TIMIL1 0x2 /* Timer 1 Interrupt */ -#define nTIMIL1 0x0 #define TIMIL2 0x4 /* Timer 2 Interrupt */ -#define nTIMIL2 0x0 #define TIMIL3 0x8 /* Timer 3 Interrupt */ -#define nTIMIL3 0x0 #define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */ -#define nTOVF_ERR0 0x0 #define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */ -#define nTOVF_ERR1 0x0 #define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */ -#define nTOVF_ERR2 0x0 #define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */ -#define nTOVF_ERR3 0x0 #define TRUN0 0x1000 /* Timer 0 Slave Enable Status */ -#define nTRUN0 0x0 #define TRUN1 0x2000 /* Timer 1 Slave Enable Status */ -#define nTRUN1 0x0 #define TRUN2 0x4000 /* Timer 2 Slave Enable Status */ -#define nTRUN2 0x0 #define TRUN3 0x8000 /* Timer 3 Slave Enable Status */ -#define nTRUN3 0x0 #define TIMIL4 0x10000 /* Timer 4 Interrupt */ -#define nTIMIL4 0x0 #define TIMIL5 0x20000 /* Timer 5 Interrupt */ -#define nTIMIL5 0x0 #define TIMIL6 0x40000 /* Timer 6 Interrupt */ -#define nTIMIL6 0x0 #define TIMIL7 0x80000 /* Timer 7 Interrupt */ -#define nTIMIL7 0x0 #define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */ -#define nTOVF_ERR4 0x0 #define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */ -#define nTOVF_ERR5 0x0 #define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */ -#define nTOVF_ERR6 0x0 #define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */ -#define nTOVF_ERR7 0x0 #define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ -#define nTRUN4 0x0 #define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ -#define nTRUN5 0x0 #define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ -#define nTRUN6 0x0 #define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ -#define nTRUN7 0x0 /* Bit masks for WDOG_CTL */ #define WDEV 0x6 /* Watchdog Event */ #define WDEN 0xff0 /* Watchdog Enable */ #define WDRO 0x8000 /* Watchdog Rolled Over */ -#define nWDRO 0x0 /* Bit masks for CNT_CONFIG */ #define CNTE 0x1 /* Counter Enable */ -#define nCNTE 0x0 #define DEBE 0x2 /* Debounce Enable */ -#define nDEBE 0x0 #define CDGINV 0x10 /* CDG Pin Polarity Invert */ -#define nCDGINV 0x0 #define CUDINV 0x20 /* CUD Pin Polarity Invert */ -#define nCUDINV 0x0 #define CZMINV 0x40 /* CZM Pin Polarity Invert */ -#define nCZMINV 0x0 #define CNTMODE 0x700 /* Counter Operating Mode */ #define ZMZC 0x800 /* CZM Zeroes Counter Enable */ -#define nZMZC 0x0 #define BNDMODE 0x3000 /* Boundary register Mode */ #define INPDIS 0x8000 /* CUG and CDG Input Disable */ -#define nINPDIS 0x0 /* Bit masks for CNT_IMASK */ #define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */ -#define nICIE 0x0 #define UCIE 0x2 /* Up count Interrupt Enable */ -#define nUCIE 0x0 #define DCIE 0x4 /* Down count Interrupt Enable */ -#define nDCIE 0x0 #define MINCIE 0x8 /* Min Count Interrupt Enable */ -#define nMINCIE 0x0 #define MAXCIE 0x10 /* Max Count Interrupt Enable */ -#define nMAXCIE 0x0 #define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */ -#define nCOV31IE 0x0 #define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */ -#define nCOV15IE 0x0 #define CZEROIE 0x80 /* Count to Zero Interrupt Enable */ -#define nCZEROIE 0x0 #define CZMIE 0x100 /* CZM Pin Interrupt Enable */ -#define nCZMIE 0x0 #define CZMEIE 0x200 /* CZM Error Interrupt Enable */ -#define nCZMEIE 0x0 #define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */ -#define nCZMZIE 0x0 /* Bit masks for CNT_STATUS */ #define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */ -#define nICII 0x0 #define UCII 0x2 /* Up count Interrupt Identifier */ -#define nUCII 0x0 #define DCII 0x4 /* Down count Interrupt Identifier */ -#define nDCII 0x0 #define MINCII 0x8 /* Min Count Interrupt Identifier */ -#define nMINCII 0x0 #define MAXCII 0x10 /* Max Count Interrupt Identifier */ -#define nMAXCII 0x0 #define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */ -#define nCOV31II 0x0 #define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */ -#define nCOV15II 0x0 #define CZEROII 0x80 /* Count to Zero Interrupt Identifier */ -#define nCZEROII 0x0 #define CZMII 0x100 /* CZM Pin Interrupt Identifier */ -#define nCZMII 0x0 #define CZMEII 0x200 /* CZM Error Interrupt Identifier */ -#define nCZMEII 0x0 #define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */ -#define nCZMZII 0x0 /* Bit masks for CNT_COMMAND */ @@ -2391,7 +2121,6 @@ #define W1LMIN 0xf0 /* Load Min Register */ #define W1LMAX 0xf00 /* Load Max Register */ #define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */ -#define nW1ZMONCE 0x0 /* Bit masks for CNT_DEBOUNCE */ @@ -2407,42 +2136,25 @@ /* Bit masks for RTC_ICTL */ #define STOPWATCH_INTERRUPT_ENABLE 0x1 /* Stopwatch Interrupt Enable */ -#define nSTOPWATCH_INTERRUPT_ENABLE 0x0 #define ALARM_INTERRUPT_ENABLE 0x2 /* Alarm Interrupt Enable */ -#define nALARM_INTERRUPT_ENABLE 0x0 #define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */ -#define nSECONDS_INTERRUPT_ENABLE 0x0 #define MINUTES_INTERRUPT_ENABLE 0x8 /* Minutes Interrupt Enable */ -#define nMINUTES_INTERRUPT_ENABLE 0x0 #define HOURS_INTERRUPT_ENABLE 0x10 /* Hours Interrupt Enable */ -#define nHOURS_INTERRUPT_ENABLE 0x0 #define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x20 /* 24 Hours Interrupt Enable */ -#define nTWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x0 #define DAY_ALARM_INTERRUPT_ENABLE 0x40 /* Day Alarm Interrupt Enable */ -#define nDAY_ALARM_INTERRUPT_ENABLE 0x0 #define WRITE_COMPLETE_INTERRUPT_ENABLE 0x8000 /* Write Complete Interrupt Enable */ -#define nWRITE_COMPLETE_INTERRUPT_ENABLE 0x0 /* Bit masks for RTC_ISTAT */ #define STOPWATCH_EVENT_FLAG 0x1 /* Stopwatch Event Flag */ -#define nSTOPWATCH_EVENT_FLAG 0x0 #define ALARM_EVENT_FLAG 0x2 /* Alarm Event Flag */ -#define nALARM_EVENT_FLAG 0x0 #define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */ -#define nSECONDS_EVENT_FLAG 0x0 #define MINUTES_EVENT_FLAG 0x8 /* Minutes Event Flag */ -#define nMINUTES_EVENT_FLAG 0x0 #define HOURS_EVENT_FLAG 0x10 /* Hours Event Flag */ -#define nHOURS_EVENT_FLAG 0x0 #define TWENTY_FOUR_HOURS_EVENT_FLAG 0x20 /* 24 Hours Event Flag */ -#define nTWENTY_FOUR_HOURS_EVENT_FLAG 0x0 #define DAY_ALARM_EVENT_FLAG 0x40 /* Day Alarm Event Flag */ -#define nDAY_ALARM_EVENT_FLAG 0x0 #define WRITE_PENDING__STATUS 0x4000 /* Write Pending Status */ -#define nWRITE_PENDING__STATUS 0x0 #define WRITE_COMPLETE 0x8000 /* Write Complete */ -#define nWRITE_COMPLETE 0x0 /* Bit masks for RTC_SWCNT */ @@ -2458,21 +2170,15 @@ /* Bit masks for RTC_PREN */ #define PREN 0x1 /* Prescaler Enable */ -#define nPREN 0x0 /* Bit masks for OTP_CONTROL */ #define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ #define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ -#define nFIEN 0x0 #define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ -#define nFTESTDEC 0x0 #define FWRTEST 0x2000 /* OTP/Fuse Write Test */ -#define nFWRTEST 0x0 #define FRDEN 0x4000 /* OTP/Fuse Read Enable */ -#define nFRDEN 0x0 #define FWREN 0x8000 /* OTP/Fuse Write Enable */ -#define nFWREN 0x0 /* Bit masks for OTP_BEN */ @@ -2481,15 +2187,10 @@ /* Bit masks for OTP_STATUS */ #define FCOMP 0x1 /* OTP/Fuse Access Complete */ -#define nFCOMP 0x0 #define FERROR 0x2 /* OTP/Fuse Access Error */ -#define nFERROR 0x0 #define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ -#define nMMRGLOAD 0x0 #define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ -#define nMMRGLOCK 0x0 #define FPGMEN 0x40 /* OTP/Fuse Program Enable */ -#define nFPGMEN 0x0 /* Bit masks for OTP_TIMING */ @@ -2503,42 +2204,29 @@ /* Bit masks for SECURE_SYSSWT */ #define EMUDABL 0x1 /* Emulation Disable. */ -#define nEMUDABL 0x0 #define RSTDABL 0x2 /* Reset Disable */ -#define nRSTDABL 0x0 #define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ #define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ #define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ #define DMA0OVR 0x800 /* DMA0 Memory Access Override */ -#define nDMA0OVR 0x0 #define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ -#define nDMA1OVR 0x0 #define EMUOVR 0x4000 /* Emulation Override */ -#define nEMUOVR 0x0 #define OTPSEN 0x8000 /* OTP Secrets Enable. */ -#define nOTPSEN 0x0 #define L2DABL 0x70000 /* L2 Memory Disable. */ /* Bit masks for SECURE_CONTROL */ #define SECURE0 0x1 /* SECURE 0 */ -#define nSECURE0 0x0 #define SECURE1 0x2 /* SECURE 1 */ -#define nSECURE1 0x0 #define SECURE2 0x4 /* SECURE 2 */ -#define nSECURE2 0x0 #define SECURE3 0x8 /* SECURE 3 */ -#define nSECURE3 0x0 /* Bit masks for SECURE_STATUS */ #define SECMODE 0x3 /* Secured Mode Control State */ #define NMI 0x4 /* Non Maskable Interrupt */ -#define nNMI 0x0 #define AFVALID 0x8 /* Authentication Firmware Valid */ -#define nAFVALID 0x0 #define AFEXIT 0x10 /* Authentication Firmware Exit */ -#define nAFEXIT 0x0 #define SECSTAT 0xe0 /* Secure Status */ /* Bit masks for PLL_DIV */ @@ -2550,42 +2238,25 @@ #define MSEL 0x7e00 /* Multiplier Select */ #define BYPASS 0x100 /* PLL Bypass Enable */ -#define nBYPASS 0x0 #define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */ -#define nOUTPUT_DELAY 0x0 #define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */ -#define nINPUT_DELAY 0x0 #define PDWN 0x20 /* Power Down */ -#define nPDWN 0x0 #define STOPCK 0x8 /* Stop Clock */ -#define nSTOPCK 0x0 #define PLL_OFF 0x2 /* Disable PLL */ -#define nPLL_OFF 0x0 #define DF 0x1 /* Divide Frequency */ -#define nDF 0x0 /* Bit masks for PLL_STAT */ #define PLL_LOCKED 0x20 /* PLL Locked Status */ -#define nPLL_LOCKED 0x0 #define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */ -#define nACTIVE_PLLDISABLED 0x0 #define FULL_ON 0x2 /* Full-On Mode */ -#define nFULL_ON 0x0 #define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */ -#define nACTIVE_PLLENABLED 0x0 #define RTCWS 0x400 /* RTC/Reset Wake-Up Status */ -#define nRTCWS 0x0 #define CANWS 0x800 /* CAN Wake-Up Status */ -#define nCANWS 0x0 #define USBWS 0x2000 /* USB Wake-Up Status */ -#define nUSBWS 0x0 #define KPADWS 0x4000 /* Keypad Wake-Up Status */ -#define nKPADWS 0x0 #define ROTWS 0x8000 /* Rotary Wake-Up Status */ -#define nROTWS 0x0 #define GPWS 0x1000 /* General-Purpose Wake-Up Status */ -#define nGPWS 0x0 /* Bit masks for VR_CTL */ @@ -2593,79 +2264,52 @@ #define GAIN 0xc /* Voltage Output Level Gain */ #define VLEV 0xf0 /* Internal Voltage Level */ #define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */ -#define nSCKELOW 0x0 #define WAKE 0x100 /* RTC/Reset Wake-Up Enable */ -#define nWAKE 0x0 #define CANWE 0x200 /* CAN0/1 Wake-Up Enable */ -#define nCANWE 0x0 #define GPWE 0x400 /* General-Purpose Wake-Up Enable */ -#define nGPWE 0x0 #define USBWE 0x800 /* USB Wake-Up Enable */ -#define nUSBWE 0x0 #define KPADWE 0x1000 /* Keypad Wake-Up Enable */ -#define nKPADWE 0x0 #define ROTWE 0x2000 /* Rotary Wake-Up Enable */ -#define nROTWE 0x0 /* Bit masks for NFC_CTL */ #define WR_DLY 0xf /* Write Strobe Delay */ #define RD_DLY 0xf0 /* Read Strobe Delay */ #define NWIDTH 0x100 /* NAND Data Width */ -#define nNWIDTH 0x0 #define PG_SIZE 0x200 /* Page Size */ -#define nPG_SIZE 0x0 /* Bit masks for NFC_STAT */ #define NBUSY 0x1 /* Not Busy */ -#define nNBUSY 0x0 #define WB_FULL 0x2 /* Write Buffer Full */ -#define nWB_FULL 0x0 #define PG_WR_STAT 0x4 /* Page Write Pending */ -#define nPG_WR_STAT 0x0 #define PG_RD_STAT 0x8 /* Page Read Pending */ -#define nPG_RD_STAT 0x0 #define WB_EMPTY 0x10 /* Write Buffer Empty */ -#define nWB_EMPTY 0x0 /* Bit masks for NFC_IRQSTAT */ #define NBUSYIRQ 0x1 /* Not Busy IRQ */ -#define nNBUSYIRQ 0x0 #define WB_OVF 0x2 /* Write Buffer Overflow */ -#define nWB_OVF 0x0 #define WB_EDGE 0x4 /* Write Buffer Edge Detect */ -#define nWB_EDGE 0x0 #define RD_RDY 0x8 /* Read Data Ready */ -#define nRD_RDY 0x0 #define WR_DONE 0x10 /* Page Write Done */ -#define nWR_DONE 0x0 /* Bit masks for NFC_IRQMASK */ #define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */ -#define nMASK_BUSYIRQ 0x0 #define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */ -#define nMASK_WBOVF 0x0 #define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */ -#define nMASK_WBEMPTY 0x0 #define MASK_RDRDY 0x8 /* Mask Read Data Ready */ -#define nMASK_RDRDY 0x0 #define MASK_WRDONE 0x10 /* Mask Write Done */ -#define nMASK_WRDONE 0x0 /* Bit masks for NFC_RST */ #define ECC_RST 0x1 /* ECC (and NFC counters) Reset */ -#define nECC_RST 0x0 /* Bit masks for NFC_PGCTL */ #define PG_RD_START 0x1 /* Page Read Start */ -#define nPG_RD_START 0x0 #define PG_WR_START 0x2 /* Page Write Start */ -#define nPG_WR_START 0x0 /* Bit masks for NFC_ECC0 */ @@ -2690,56 +2334,34 @@ /* Bit masks for CAN0_CONTROL */ #define SRS 0x1 /* Software Reset */ -#define nSRS 0x0 #define DNM 0x2 /* DeviceNet Mode */ -#define nDNM 0x0 #define ABO 0x4 /* Auto Bus On */ -#define nABO 0x0 #define WBA 0x10 /* Wakeup On CAN Bus Activity */ -#define nWBA 0x0 #define SMR 0x20 /* Sleep Mode Request */ -#define nSMR 0x0 #define CSR 0x40 /* CAN Suspend Mode Request */ -#define nCSR 0x0 #define CCR 0x80 /* CAN Configuration Mode Request */ -#define nCCR 0x0 /* Bit masks for CAN0_STATUS */ #define WT 0x1 /* CAN Transmit Warning Flag */ -#define nWT 0x0 #define WR 0x2 /* CAN Receive Warning Flag */ -#define nWR 0x0 #define EP 0x4 /* CAN Error Passive Mode */ -#define nEP 0x0 #define EBO 0x8 /* CAN Error Bus Off Mode */ -#define nEBO 0x0 #define CSA 0x40 /* CAN Suspend Mode Acknowledge */ -#define nCSA 0x0 #define CCA 0x80 /* CAN Configuration Mode Acknowledge */ -#define nCCA 0x0 #define MBPTR 0x1f00 /* Mailbox Pointer */ #define TRM 0x4000 /* Transmit Mode Status */ -#define nTRM 0x0 #define REC 0x8000 /* Receive Mode Status */ -#define nREC 0x0 /* Bit masks for CAN0_DEBUG */ #define DEC 0x1 /* Disable Transmit/Receive Error Counters */ -#define nDEC 0x0 #define DRI 0x2 /* Disable CANRX Input Pin */ -#define nDRI 0x0 #define DTO 0x4 /* Disable CANTX Output Pin */ -#define nDTO 0x0 #define DIL 0x8 /* Disable Internal Loop */ -#define nDIL 0x0 #define MAA 0x10 /* Mode Auto-Acknowledge */ -#define nMAA 0x0 #define MRB 0x20 /* Mode Read Back */ -#define nMRB 0x0 #define CDE 0x8000 /* CAN Debug Mode Enable */ -#define nCDE 0x0 /* Bit masks for CAN0_CLOCK */ @@ -2749,111 +2371,69 @@ #define SJW 0x300 /* Synchronization Jump Width */ #define SAM 0x80 /* Sampling */ -#define nSAM 0x0 #define TSEG2 0x70 /* Time Segment 2 */ #define TSEG1 0xf /* Time Segment 1 */ /* Bit masks for CAN0_INTR */ #define CANRX 0x80 /* Serial Input From Transceiver */ -#define nCANRX 0x0 #define CANTX 0x40 /* Serial Output To Transceiver */ -#define nCANTX 0x0 #define SMACK 0x8 /* Sleep Mode Acknowledge */ -#define nSMACK 0x0 #define GIRQ 0x4 /* Global Interrupt Request Status */ -#define nGIRQ 0x0 #define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */ -#define nMBTIRQ 0x0 #define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */ -#define nMBRIRQ 0x0 /* Bit masks for CAN0_GIM */ #define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */ -#define nEWTIM 0x0 #define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */ -#define nEWRIM 0x0 #define EPIM 0x4 /* Error Passive Interrupt Mask */ -#define nEPIM 0x0 #define BOIM 0x8 /* Bus Off Interrupt Mask */ -#define nBOIM 0x0 #define WUIM 0x10 /* Wakeup Interrupt Mask */ -#define nWUIM 0x0 #define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */ -#define nUIAIM 0x0 #define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */ -#define nAAIM 0x0 #define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */ -#define nRMLIM 0x0 #define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */ -#define nUCEIM 0x0 #define ADIM 0x400 /* Access Denied Interrupt Mask */ -#define nADIM 0x0 /* Bit masks for CAN0_GIS */ #define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */ -#define nEWTIS 0x0 #define EWRIS 0x2 /* Error Warning Receive Interrupt Status */ -#define nEWRIS 0x0 #define EPIS 0x4 /* Error Passive Interrupt Status */ -#define nEPIS 0x0 #define BOIS 0x8 /* Bus Off Interrupt Status */ -#define nBOIS 0x0 #define WUIS 0x10 /* Wakeup Interrupt Status */ -#define nWUIS 0x0 #define UIAIS 0x20 /* Unimplemented Address Interrupt Status */ -#define nUIAIS 0x0 #define AAIS 0x40 /* Abort Acknowledge Interrupt Status */ -#define nAAIS 0x0 #define RMLIS 0x80 /* Receive Message Lost Interrupt Status */ -#define nRMLIS 0x0 #define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */ -#define nUCEIS 0x0 #define ADIS 0x400 /* Access Denied Interrupt Status */ -#define nADIS 0x0 /* Bit masks for CAN0_GIF */ #define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */ -#define nEWTIF 0x0 #define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */ -#define nEWRIF 0x0 #define EPIF 0x4 /* Error Passive Interrupt Flag */ -#define nEPIF 0x0 #define BOIF 0x8 /* Bus Off Interrupt Flag */ -#define nBOIF 0x0 #define WUIF 0x10 /* Wakeup Interrupt Flag */ -#define nWUIF 0x0 #define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */ -#define nUIAIF 0x0 #define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */ -#define nAAIF 0x0 #define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */ -#define nRMLIF 0x0 #define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */ -#define nUCEIF 0x0 #define ADIF 0x400 /* Access Denied Interrupt Flag */ -#define nADIF 0x0 /* Bit masks for CAN0_MBTD */ #define TDR 0x80 /* Temporary Disable Request */ -#define nTDR 0x0 #define TDA 0x40 /* Temporary Disable Acknowledge */ -#define nTDA 0x0 #define TDPTR 0x1f /* Temporary Disable Pointer */ /* Bit masks for CAN0_UCCNF */ #define UCCNF 0xf /* Universal Counter Configuration */ #define UCRC 0x20 /* Universal Counter Reload/Clear */ -#define nUCRC 0x0 #define UCCT 0x40 /* Universal Counter CAN Trigger */ -#define nUCCT 0x0 #define UCE 0x80 /* Universal Counter Enable */ -#define nUCE 0x0 /* Bit masks for CAN0_UCCNT */ @@ -2871,17 +2451,11 @@ /* Bit masks for CAN0_ESR */ #define FER 0x80 /* Form Error */ -#define nFER 0x0 #define BEF 0x40 /* Bit Error Flag */ -#define nBEF 0x0 #define SA0 0x20 /* Stuck At Dominant */ -#define nSA0 0x0 #define CRCE 0x10 /* CRC Error */ -#define nCRCE 0x0 #define SER 0x8 /* Stuff Bit Error */ -#define nSER 0x0 #define ACKE 0x4 /* Acknowledge Error */ -#define nACKE 0x0 /* Bit masks for CAN0_EWR */ @@ -2891,11 +2465,8 @@ /* Bit masks for CAN0_AMxx_H */ #define FDF 0x8000 /* Filter On Data Field */ -#define nFDF 0x0 #define FMD 0x4000 /* Full Mask Data */ -#define nFMD 0x0 #define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */ -#define nAMIDE 0x0 #define BASEID 0x1ffc /* Base Identifier */ #define EXTID_HI 0x3 /* Extended Identifier High Bits */ @@ -2907,11 +2478,8 @@ /* Bit masks for CAN0_MBxx_ID1 */ #define AME 0x8000 /* Acceptance Mask Enable */ -#define nAME 0x0 #define RTR 0x4000 /* Remote Transmission Request */ -#define nRTR 0x0 #define IDE 0x2000 /* Identifier Extension */ -#define nIDE 0x0 #define BASEID 0x1ffc /* Base Identifier */ #define EXTID_HI 0x3 /* Extended Identifier High Bits */ @@ -2951,980 +2519,546 @@ /* Bit masks for CAN0_MC1 */ #define MC0 0x1 /* Mailbox 0 Enable */ -#define nMC0 0x0 #define MC1 0x2 /* Mailbox 1 Enable */ -#define nMC1 0x0 #define MC2 0x4 /* Mailbox 2 Enable */ -#define nMC2 0x0 #define MC3 0x8 /* Mailbox 3 Enable */ -#define nMC3 0x0 #define MC4 0x10 /* Mailbox 4 Enable */ -#define nMC4 0x0 #define MC5 0x20 /* Mailbox 5 Enable */ -#define nMC5 0x0 #define MC6 0x40 /* Mailbox 6 Enable */ -#define nMC6 0x0 #define MC7 0x80 /* Mailbox 7 Enable */ -#define nMC7 0x0 #define MC8 0x100 /* Mailbox 8 Enable */ -#define nMC8 0x0 #define MC9 0x200 /* Mailbox 9 Enable */ -#define nMC9 0x0 #define MC10 0x400 /* Mailbox 10 Enable */ -#define nMC10 0x0 #define MC11 0x800 /* Mailbox 11 Enable */ -#define nMC11 0x0 #define MC12 0x1000 /* Mailbox 12 Enable */ -#define nMC12 0x0 #define MC13 0x2000 /* Mailbox 13 Enable */ -#define nMC13 0x0 #define MC14 0x4000 /* Mailbox 14 Enable */ -#define nMC14 0x0 #define MC15 0x8000 /* Mailbox 15 Enable */ -#define nMC15 0x0 /* Bit masks for CAN0_MC2 */ #define MC16 0x1 /* Mailbox 16 Enable */ -#define nMC16 0x0 #define MC17 0x2 /* Mailbox 17 Enable */ -#define nMC17 0x0 #define MC18 0x4 /* Mailbox 18 Enable */ -#define nMC18 0x0 #define MC19 0x8 /* Mailbox 19 Enable */ -#define nMC19 0x0 #define MC20 0x10 /* Mailbox 20 Enable */ -#define nMC20 0x0 #define MC21 0x20 /* Mailbox 21 Enable */ -#define nMC21 0x0 #define MC22 0x40 /* Mailbox 22 Enable */ -#define nMC22 0x0 #define MC23 0x80 /* Mailbox 23 Enable */ -#define nMC23 0x0 #define MC24 0x100 /* Mailbox 24 Enable */ -#define nMC24 0x0 #define MC25 0x200 /* Mailbox 25 Enable */ -#define nMC25 0x0 #define MC26 0x400 /* Mailbox 26 Enable */ -#define nMC26 0x0 #define MC27 0x800 /* Mailbox 27 Enable */ -#define nMC27 0x0 #define MC28 0x1000 /* Mailbox 28 Enable */ -#define nMC28 0x0 #define MC29 0x2000 /* Mailbox 29 Enable */ -#define nMC29 0x0 #define MC30 0x4000 /* Mailbox 30 Enable */ -#define nMC30 0x0 #define MC31 0x8000 /* Mailbox 31 Enable */ -#define nMC31 0x0 /* Bit masks for CAN0_MD1 */ #define MD0 0x1 /* Mailbox 0 Receive Enable */ -#define nMD0 0x0 #define MD1 0x2 /* Mailbox 1 Receive Enable */ -#define nMD1 0x0 #define MD2 0x4 /* Mailbox 2 Receive Enable */ -#define nMD2 0x0 #define MD3 0x8 /* Mailbox 3 Receive Enable */ -#define nMD3 0x0 #define MD4 0x10 /* Mailbox 4 Receive Enable */ -#define nMD4 0x0 #define MD5 0x20 /* Mailbox 5 Receive Enable */ -#define nMD5 0x0 #define MD6 0x40 /* Mailbox 6 Receive Enable */ -#define nMD6 0x0 #define MD7 0x80 /* Mailbox 7 Receive Enable */ -#define nMD7 0x0 #define MD8 0x100 /* Mailbox 8 Receive Enable */ -#define nMD8 0x0 #define MD9 0x200 /* Mailbox 9 Receive Enable */ -#define nMD9 0x0 #define MD10 0x400 /* Mailbox 10 Receive Enable */ -#define nMD10 0x0 #define MD11 0x800 /* Mailbox 11 Receive Enable */ -#define nMD11 0x0 #define MD12 0x1000 /* Mailbox 12 Receive Enable */ -#define nMD12 0x0 #define MD13 0x2000 /* Mailbox 13 Receive Enable */ -#define nMD13 0x0 #define MD14 0x4000 /* Mailbox 14 Receive Enable */ -#define nMD14 0x0 #define MD15 0x8000 /* Mailbox 15 Receive Enable */ -#define nMD15 0x0 /* Bit masks for CAN0_MD2 */ #define MD16 0x1 /* Mailbox 16 Receive Enable */ -#define nMD16 0x0 #define MD17 0x2 /* Mailbox 17 Receive Enable */ -#define nMD17 0x0 #define MD18 0x4 /* Mailbox 18 Receive Enable */ -#define nMD18 0x0 #define MD19 0x8 /* Mailbox 19 Receive Enable */ -#define nMD19 0x0 #define MD20 0x10 /* Mailbox 20 Receive Enable */ -#define nMD20 0x0 #define MD21 0x20 /* Mailbox 21 Receive Enable */ -#define nMD21 0x0 #define MD22 0x40 /* Mailbox 22 Receive Enable */ -#define nMD22 0x0 #define MD23 0x80 /* Mailbox 23 Receive Enable */ -#define nMD23 0x0 #define MD24 0x100 /* Mailbox 24 Receive Enable */ -#define nMD24 0x0 #define MD25 0x200 /* Mailbox 25 Receive Enable */ -#define nMD25 0x0 #define MD26 0x400 /* Mailbox 26 Receive Enable */ -#define nMD26 0x0 #define MD27 0x800 /* Mailbox 27 Receive Enable */ -#define nMD27 0x0 #define MD28 0x1000 /* Mailbox 28 Receive Enable */ -#define nMD28 0x0 #define MD29 0x2000 /* Mailbox 29 Receive Enable */ -#define nMD29 0x0 #define MD30 0x4000 /* Mailbox 30 Receive Enable */ -#define nMD30 0x0 #define MD31 0x8000 /* Mailbox 31 Receive Enable */ -#define nMD31 0x0 /* Bit masks for CAN0_RMP1 */ #define RMP0 0x1 /* Mailbox 0 Receive Message Pending */ -#define nRMP0 0x0 #define RMP1 0x2 /* Mailbox 1 Receive Message Pending */ -#define nRMP1 0x0 #define RMP2 0x4 /* Mailbox 2 Receive Message Pending */ -#define nRMP2 0x0 #define RMP3 0x8 /* Mailbox 3 Receive Message Pending */ -#define nRMP3 0x0 #define RMP4 0x10 /* Mailbox 4 Receive Message Pending */ -#define nRMP4 0x0 #define RMP5 0x20 /* Mailbox 5 Receive Message Pending */ -#define nRMP5 0x0 #define RMP6 0x40 /* Mailbox 6 Receive Message Pending */ -#define nRMP6 0x0 #define RMP7 0x80 /* Mailbox 7 Receive Message Pending */ -#define nRMP7 0x0 #define RMP8 0x100 /* Mailbox 8 Receive Message Pending */ -#define nRMP8 0x0 #define RMP9 0x200 /* Mailbox 9 Receive Message Pending */ -#define nRMP9 0x0 #define RMP10 0x400 /* Mailbox 10 Receive Message Pending */ -#define nRMP10 0x0 #define RMP11 0x800 /* Mailbox 11 Receive Message Pending */ -#define nRMP11 0x0 #define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */ -#define nRMP12 0x0 #define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */ -#define nRMP13 0x0 #define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */ -#define nRMP14 0x0 #define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */ -#define nRMP15 0x0 /* Bit masks for CAN0_RMP2 */ #define RMP16 0x1 /* Mailbox 16 Receive Message Pending */ -#define nRMP16 0x0 #define RMP17 0x2 /* Mailbox 17 Receive Message Pending */ -#define nRMP17 0x0 #define RMP18 0x4 /* Mailbox 18 Receive Message Pending */ -#define nRMP18 0x0 #define RMP19 0x8 /* Mailbox 19 Receive Message Pending */ -#define nRMP19 0x0 #define RMP20 0x10 /* Mailbox 20 Receive Message Pending */ -#define nRMP20 0x0 #define RMP21 0x20 /* Mailbox 21 Receive Message Pending */ -#define nRMP21 0x0 #define RMP22 0x40 /* Mailbox 22 Receive Message Pending */ -#define nRMP22 0x0 #define RMP23 0x80 /* Mailbox 23 Receive Message Pending */ -#define nRMP23 0x0 #define RMP24 0x100 /* Mailbox 24 Receive Message Pending */ -#define nRMP24 0x0 #define RMP25 0x200 /* Mailbox 25 Receive Message Pending */ -#define nRMP25 0x0 #define RMP26 0x400 /* Mailbox 26 Receive Message Pending */ -#define nRMP26 0x0 #define RMP27 0x800 /* Mailbox 27 Receive Message Pending */ -#define nRMP27 0x0 #define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */ -#define nRMP28 0x0 #define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */ -#define nRMP29 0x0 #define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */ -#define nRMP30 0x0 #define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */ -#define nRMP31 0x0 /* Bit masks for CAN0_RML1 */ #define RML0 0x1 /* Mailbox 0 Receive Message Lost */ -#define nRML0 0x0 #define RML1 0x2 /* Mailbox 1 Receive Message Lost */ -#define nRML1 0x0 #define RML2 0x4 /* Mailbox 2 Receive Message Lost */ -#define nRML2 0x0 #define RML3 0x8 /* Mailbox 3 Receive Message Lost */ -#define nRML3 0x0 #define RML4 0x10 /* Mailbox 4 Receive Message Lost */ -#define nRML4 0x0 #define RML5 0x20 /* Mailbox 5 Receive Message Lost */ -#define nRML5 0x0 #define RML6 0x40 /* Mailbox 6 Receive Message Lost */ -#define nRML6 0x0 #define RML7 0x80 /* Mailbox 7 Receive Message Lost */ -#define nRML7 0x0 #define RML8 0x100 /* Mailbox 8 Receive Message Lost */ -#define nRML8 0x0 #define RML9 0x200 /* Mailbox 9 Receive Message Lost */ -#define nRML9 0x0 #define RML10 0x400 /* Mailbox 10 Receive Message Lost */ -#define nRML10 0x0 #define RML11 0x800 /* Mailbox 11 Receive Message Lost */ -#define nRML11 0x0 #define RML12 0x1000 /* Mailbox 12 Receive Message Lost */ -#define nRML12 0x0 #define RML13 0x2000 /* Mailbox 13 Receive Message Lost */ -#define nRML13 0x0 #define RML14 0x4000 /* Mailbox 14 Receive Message Lost */ -#define nRML14 0x0 #define RML15 0x8000 /* Mailbox 15 Receive Message Lost */ -#define nRML15 0x0 /* Bit masks for CAN0_RML2 */ #define RML16 0x1 /* Mailbox 16 Receive Message Lost */ -#define nRML16 0x0 #define RML17 0x2 /* Mailbox 17 Receive Message Lost */ -#define nRML17 0x0 #define RML18 0x4 /* Mailbox 18 Receive Message Lost */ -#define nRML18 0x0 #define RML19 0x8 /* Mailbox 19 Receive Message Lost */ -#define nRML19 0x0 #define RML20 0x10 /* Mailbox 20 Receive Message Lost */ -#define nRML20 0x0 #define RML21 0x20 /* Mailbox 21 Receive Message Lost */ -#define nRML21 0x0 #define RML22 0x40 /* Mailbox 22 Receive Message Lost */ -#define nRML22 0x0 #define RML23 0x80 /* Mailbox 23 Receive Message Lost */ -#define nRML23 0x0 #define RML24 0x100 /* Mailbox 24 Receive Message Lost */ -#define nRML24 0x0 #define RML25 0x200 /* Mailbox 25 Receive Message Lost */ -#define nRML25 0x0 #define RML26 0x400 /* Mailbox 26 Receive Message Lost */ -#define nRML26 0x0 #define RML27 0x800 /* Mailbox 27 Receive Message Lost */ -#define nRML27 0x0 #define RML28 0x1000 /* Mailbox 28 Receive Message Lost */ -#define nRML28 0x0 #define RML29 0x2000 /* Mailbox 29 Receive Message Lost */ -#define nRML29 0x0 #define RML30 0x4000 /* Mailbox 30 Receive Message Lost */ -#define nRML30 0x0 #define RML31 0x8000 /* Mailbox 31 Receive Message Lost */ -#define nRML31 0x0 /* Bit masks for CAN0_OPSS1 */ #define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS0 0x0 #define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS1 0x0 #define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS2 0x0 #define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS3 0x0 #define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS4 0x0 #define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS5 0x0 #define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS6 0x0 #define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS7 0x0 #define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS8 0x0 #define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS9 0x0 #define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS10 0x0 #define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS11 0x0 #define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS12 0x0 #define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS13 0x0 #define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS14 0x0 #define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS15 0x0 /* Bit masks for CAN0_OPSS2 */ #define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS16 0x0 #define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS17 0x0 #define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS18 0x0 #define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS19 0x0 #define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS20 0x0 #define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS21 0x0 #define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS22 0x0 #define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS23 0x0 #define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS24 0x0 #define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS25 0x0 #define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS26 0x0 #define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS27 0x0 #define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS28 0x0 #define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS29 0x0 #define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS30 0x0 #define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS31 0x0 /* Bit masks for CAN0_TRS1 */ #define TRS0 0x1 /* Mailbox 0 Transmit Request Set */ -#define nTRS0 0x0 #define TRS1 0x2 /* Mailbox 1 Transmit Request Set */ -#define nTRS1 0x0 #define TRS2 0x4 /* Mailbox 2 Transmit Request Set */ -#define nTRS2 0x0 #define TRS3 0x8 /* Mailbox 3 Transmit Request Set */ -#define nTRS3 0x0 #define TRS4 0x10 /* Mailbox 4 Transmit Request Set */ -#define nTRS4 0x0 #define TRS5 0x20 /* Mailbox 5 Transmit Request Set */ -#define nTRS5 0x0 #define TRS6 0x40 /* Mailbox 6 Transmit Request Set */ -#define nTRS6 0x0 #define TRS7 0x80 /* Mailbox 7 Transmit Request Set */ -#define nTRS7 0x0 #define TRS8 0x100 /* Mailbox 8 Transmit Request Set */ -#define nTRS8 0x0 #define TRS9 0x200 /* Mailbox 9 Transmit Request Set */ -#define nTRS9 0x0 #define TRS10 0x400 /* Mailbox 10 Transmit Request Set */ -#define nTRS10 0x0 #define TRS11 0x800 /* Mailbox 11 Transmit Request Set */ -#define nTRS11 0x0 #define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */ -#define nTRS12 0x0 #define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */ -#define nTRS13 0x0 #define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */ -#define nTRS14 0x0 #define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */ -#define nTRS15 0x0 /* Bit masks for CAN0_TRS2 */ #define TRS16 0x1 /* Mailbox 16 Transmit Request Set */ -#define nTRS16 0x0 #define TRS17 0x2 /* Mailbox 17 Transmit Request Set */ -#define nTRS17 0x0 #define TRS18 0x4 /* Mailbox 18 Transmit Request Set */ -#define nTRS18 0x0 #define TRS19 0x8 /* Mailbox 19 Transmit Request Set */ -#define nTRS19 0x0 #define TRS20 0x10 /* Mailbox 20 Transmit Request Set */ -#define nTRS20 0x0 #define TRS21 0x20 /* Mailbox 21 Transmit Request Set */ -#define nTRS21 0x0 #define TRS22 0x40 /* Mailbox 22 Transmit Request Set */ -#define nTRS22 0x0 #define TRS23 0x80 /* Mailbox 23 Transmit Request Set */ -#define nTRS23 0x0 #define TRS24 0x100 /* Mailbox 24 Transmit Request Set */ -#define nTRS24 0x0 #define TRS25 0x200 /* Mailbox 25 Transmit Request Set */ -#define nTRS25 0x0 #define TRS26 0x400 /* Mailbox 26 Transmit Request Set */ -#define nTRS26 0x0 #define TRS27 0x800 /* Mailbox 27 Transmit Request Set */ -#define nTRS27 0x0 #define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */ -#define nTRS28 0x0 #define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */ -#define nTRS29 0x0 #define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */ -#define nTRS30 0x0 #define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */ -#define nTRS31 0x0 /* Bit masks for CAN0_TRR1 */ #define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */ -#define nTRR0 0x0 #define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */ -#define nTRR1 0x0 #define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */ -#define nTRR2 0x0 #define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */ -#define nTRR3 0x0 #define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */ -#define nTRR4 0x0 #define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */ -#define nTRR5 0x0 #define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */ -#define nTRR6 0x0 #define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */ -#define nTRR7 0x0 #define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */ -#define nTRR8 0x0 #define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */ -#define nTRR9 0x0 #define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */ -#define nTRR10 0x0 #define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */ -#define nTRR11 0x0 #define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */ -#define nTRR12 0x0 #define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */ -#define nTRR13 0x0 #define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */ -#define nTRR14 0x0 #define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */ -#define nTRR15 0x0 /* Bit masks for CAN0_TRR2 */ #define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */ -#define nTRR16 0x0 #define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */ -#define nTRR17 0x0 #define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */ -#define nTRR18 0x0 #define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */ -#define nTRR19 0x0 #define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */ -#define nTRR20 0x0 #define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */ -#define nTRR21 0x0 #define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */ -#define nTRR22 0x0 #define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */ -#define nTRR23 0x0 #define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */ -#define nTRR24 0x0 #define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */ -#define nTRR25 0x0 #define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */ -#define nTRR26 0x0 #define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */ -#define nTRR27 0x0 #define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */ -#define nTRR28 0x0 #define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */ -#define nTRR29 0x0 #define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */ -#define nTRR30 0x0 #define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */ -#define nTRR31 0x0 /* Bit masks for CAN0_AA1 */ #define AA0 0x1 /* Mailbox 0 Abort Acknowledge */ -#define nAA0 0x0 #define AA1 0x2 /* Mailbox 1 Abort Acknowledge */ -#define nAA1 0x0 #define AA2 0x4 /* Mailbox 2 Abort Acknowledge */ -#define nAA2 0x0 #define AA3 0x8 /* Mailbox 3 Abort Acknowledge */ -#define nAA3 0x0 #define AA4 0x10 /* Mailbox 4 Abort Acknowledge */ -#define nAA4 0x0 #define AA5 0x20 /* Mailbox 5 Abort Acknowledge */ -#define nAA5 0x0 #define AA6 0x40 /* Mailbox 6 Abort Acknowledge */ -#define nAA6 0x0 #define AA7 0x80 /* Mailbox 7 Abort Acknowledge */ -#define nAA7 0x0 #define AA8 0x100 /* Mailbox 8 Abort Acknowledge */ -#define nAA8 0x0 #define AA9 0x200 /* Mailbox 9 Abort Acknowledge */ -#define nAA9 0x0 #define AA10 0x400 /* Mailbox 10 Abort Acknowledge */ -#define nAA10 0x0 #define AA11 0x800 /* Mailbox 11 Abort Acknowledge */ -#define nAA11 0x0 #define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */ -#define nAA12 0x0 #define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */ -#define nAA13 0x0 #define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */ -#define nAA14 0x0 #define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */ -#define nAA15 0x0 /* Bit masks for CAN0_AA2 */ #define AA16 0x1 /* Mailbox 16 Abort Acknowledge */ -#define nAA16 0x0 #define AA17 0x2 /* Mailbox 17 Abort Acknowledge */ -#define nAA17 0x0 #define AA18 0x4 /* Mailbox 18 Abort Acknowledge */ -#define nAA18 0x0 #define AA19 0x8 /* Mailbox 19 Abort Acknowledge */ -#define nAA19 0x0 #define AA20 0x10 /* Mailbox 20 Abort Acknowledge */ -#define nAA20 0x0 #define AA21 0x20 /* Mailbox 21 Abort Acknowledge */ -#define nAA21 0x0 #define AA22 0x40 /* Mailbox 22 Abort Acknowledge */ -#define nAA22 0x0 #define AA23 0x80 /* Mailbox 23 Abort Acknowledge */ -#define nAA23 0x0 #define AA24 0x100 /* Mailbox 24 Abort Acknowledge */ -#define nAA24 0x0 #define AA25 0x200 /* Mailbox 25 Abort Acknowledge */ -#define nAA25 0x0 #define AA26 0x400 /* Mailbox 26 Abort Acknowledge */ -#define nAA26 0x0 #define AA27 0x800 /* Mailbox 27 Abort Acknowledge */ -#define nAA27 0x0 #define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */ -#define nAA28 0x0 #define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */ -#define nAA29 0x0 #define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */ -#define nAA30 0x0 #define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */ -#define nAA31 0x0 /* Bit masks for CAN0_TA1 */ #define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */ -#define nTA0 0x0 #define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */ -#define nTA1 0x0 #define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */ -#define nTA2 0x0 #define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */ -#define nTA3 0x0 #define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */ -#define nTA4 0x0 #define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */ -#define nTA5 0x0 #define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */ -#define nTA6 0x0 #define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */ -#define nTA7 0x0 #define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */ -#define nTA8 0x0 #define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */ -#define nTA9 0x0 #define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */ -#define nTA10 0x0 #define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */ -#define nTA11 0x0 #define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */ -#define nTA12 0x0 #define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */ -#define nTA13 0x0 #define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */ -#define nTA14 0x0 #define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */ -#define nTA15 0x0 /* Bit masks for CAN0_TA2 */ #define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */ -#define nTA16 0x0 #define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */ -#define nTA17 0x0 #define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */ -#define nTA18 0x0 #define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */ -#define nTA19 0x0 #define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */ -#define nTA20 0x0 #define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */ -#define nTA21 0x0 #define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */ -#define nTA22 0x0 #define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */ -#define nTA23 0x0 #define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */ -#define nTA24 0x0 #define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */ -#define nTA25 0x0 #define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */ -#define nTA26 0x0 #define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */ -#define nTA27 0x0 #define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */ -#define nTA28 0x0 #define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */ -#define nTA29 0x0 #define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */ -#define nTA30 0x0 #define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */ -#define nTA31 0x0 /* Bit masks for CAN0_RFH1 */ #define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */ -#define nRFH0 0x0 #define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */ -#define nRFH1 0x0 #define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */ -#define nRFH2 0x0 #define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */ -#define nRFH3 0x0 #define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */ -#define nRFH4 0x0 #define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */ -#define nRFH5 0x0 #define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */ -#define nRFH6 0x0 #define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */ -#define nRFH7 0x0 #define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */ -#define nRFH8 0x0 #define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */ -#define nRFH9 0x0 #define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */ -#define nRFH10 0x0 #define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */ -#define nRFH11 0x0 #define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */ -#define nRFH12 0x0 #define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */ -#define nRFH13 0x0 #define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */ -#define nRFH14 0x0 #define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */ -#define nRFH15 0x0 /* Bit masks for CAN0_RFH2 */ #define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */ -#define nRFH16 0x0 #define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */ -#define nRFH17 0x0 #define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */ -#define nRFH18 0x0 #define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */ -#define nRFH19 0x0 #define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */ -#define nRFH20 0x0 #define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */ -#define nRFH21 0x0 #define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */ -#define nRFH22 0x0 #define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */ -#define nRFH23 0x0 #define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */ -#define nRFH24 0x0 #define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */ -#define nRFH25 0x0 #define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */ -#define nRFH26 0x0 #define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */ -#define nRFH27 0x0 #define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */ -#define nRFH28 0x0 #define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */ -#define nRFH29 0x0 #define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */ -#define nRFH30 0x0 #define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */ -#define nRFH31 0x0 /* Bit masks for CAN0_MBIM1 */ #define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */ -#define nMBIM0 0x0 #define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */ -#define nMBIM1 0x0 #define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */ -#define nMBIM2 0x0 #define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */ -#define nMBIM3 0x0 #define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */ -#define nMBIM4 0x0 #define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */ -#define nMBIM5 0x0 #define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */ -#define nMBIM6 0x0 #define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */ -#define nMBIM7 0x0 #define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */ -#define nMBIM8 0x0 #define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */ -#define nMBIM9 0x0 #define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */ -#define nMBIM10 0x0 #define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */ -#define nMBIM11 0x0 #define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */ -#define nMBIM12 0x0 #define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */ -#define nMBIM13 0x0 #define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */ -#define nMBIM14 0x0 #define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */ -#define nMBIM15 0x0 /* Bit masks for CAN0_MBIM2 */ #define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */ -#define nMBIM16 0x0 #define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */ -#define nMBIM17 0x0 #define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */ -#define nMBIM18 0x0 #define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */ -#define nMBIM19 0x0 #define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */ -#define nMBIM20 0x0 #define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */ -#define nMBIM21 0x0 #define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */ -#define nMBIM22 0x0 #define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */ -#define nMBIM23 0x0 #define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */ -#define nMBIM24 0x0 #define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */ -#define nMBIM25 0x0 #define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */ -#define nMBIM26 0x0 #define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */ -#define nMBIM27 0x0 #define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */ -#define nMBIM28 0x0 #define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */ -#define nMBIM29 0x0 #define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */ -#define nMBIM30 0x0 #define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */ -#define nMBIM31 0x0 /* Bit masks for CAN0_MBTIF1 */ #define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */ -#define nMBTIF0 0x0 #define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */ -#define nMBTIF1 0x0 #define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */ -#define nMBTIF2 0x0 #define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */ -#define nMBTIF3 0x0 #define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */ -#define nMBTIF4 0x0 #define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */ -#define nMBTIF5 0x0 #define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */ -#define nMBTIF6 0x0 #define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */ -#define nMBTIF7 0x0 #define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */ -#define nMBTIF8 0x0 #define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */ -#define nMBTIF9 0x0 #define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */ -#define nMBTIF10 0x0 #define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */ -#define nMBTIF11 0x0 #define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */ -#define nMBTIF12 0x0 #define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */ -#define nMBTIF13 0x0 #define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */ -#define nMBTIF14 0x0 #define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */ -#define nMBTIF15 0x0 /* Bit masks for CAN0_MBTIF2 */ #define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */ -#define nMBTIF16 0x0 #define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */ -#define nMBTIF17 0x0 #define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */ -#define nMBTIF18 0x0 #define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */ -#define nMBTIF19 0x0 #define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */ -#define nMBTIF20 0x0 #define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */ -#define nMBTIF21 0x0 #define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */ -#define nMBTIF22 0x0 #define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */ -#define nMBTIF23 0x0 #define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */ -#define nMBTIF24 0x0 #define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */ -#define nMBTIF25 0x0 #define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */ -#define nMBTIF26 0x0 #define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */ -#define nMBTIF27 0x0 #define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */ -#define nMBTIF28 0x0 #define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */ -#define nMBTIF29 0x0 #define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */ -#define nMBTIF30 0x0 #define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */ -#define nMBTIF31 0x0 /* Bit masks for CAN0_MBRIF1 */ #define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */ -#define nMBRIF0 0x0 #define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */ -#define nMBRIF1 0x0 #define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */ -#define nMBRIF2 0x0 #define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */ -#define nMBRIF3 0x0 #define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */ -#define nMBRIF4 0x0 #define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */ -#define nMBRIF5 0x0 #define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */ -#define nMBRIF6 0x0 #define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */ -#define nMBRIF7 0x0 #define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */ -#define nMBRIF8 0x0 #define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */ -#define nMBRIF9 0x0 #define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */ -#define nMBRIF10 0x0 #define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */ -#define nMBRIF11 0x0 #define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */ -#define nMBRIF12 0x0 #define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */ -#define nMBRIF13 0x0 #define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */ -#define nMBRIF14 0x0 #define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */ -#define nMBRIF15 0x0 /* Bit masks for CAN0_MBRIF2 */ #define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */ -#define nMBRIF16 0x0 #define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */ -#define nMBRIF17 0x0 #define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */ -#define nMBRIF18 0x0 #define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */ -#define nMBRIF19 0x0 #define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */ -#define nMBRIF20 0x0 #define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */ -#define nMBRIF21 0x0 #define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */ -#define nMBRIF22 0x0 #define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */ -#define nMBRIF23 0x0 #define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */ -#define nMBRIF24 0x0 #define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */ -#define nMBRIF25 0x0 #define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */ -#define nMBRIF26 0x0 #define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */ -#define nMBRIF27 0x0 #define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */ -#define nMBRIF28 0x0 #define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */ -#define nMBRIF29 0x0 #define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */ -#define nMBRIF30 0x0 #define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */ -#define nMBRIF31 0x0 /* Bit masks for EPPIx_STATUS */ #define CFIFO_ERR 0x1 /* Chroma FIFO Error */ -#define nCFIFO_ERR 0x0 #define YFIFO_ERR 0x2 /* Luma FIFO Error */ -#define nYFIFO_ERR 0x0 #define LTERR_OVR 0x4 /* Line Track Overflow */ -#define nLTERR_OVR 0x0 #define LTERR_UNDR 0x8 /* Line Track Underflow */ -#define nLTERR_UNDR 0x0 #define FTERR_OVR 0x10 /* Frame Track Overflow */ -#define nFTERR_OVR 0x0 #define FTERR_UNDR 0x20 /* Frame Track Underflow */ -#define nFTERR_UNDR 0x0 #define ERR_NCOR 0x40 /* Preamble Error Not Corrected */ -#define nERR_NCOR 0x0 #define DMA1URQ 0x80 /* DMA1 Urgent Request */ -#define nDMA1URQ 0x0 #define DMA0URQ 0x100 /* DMA0 Urgent Request */ -#define nDMA0URQ 0x0 #define ERR_DET 0x4000 /* Preamble Error Detected */ -#define nERR_DET 0x0 #define FLD 0x8000 /* Field */ -#define nFLD 0x0 /* Bit masks for EPPIx_CONTROL */ #define EPPI_EN 0x1 /* Enable */ -#define nEPPI_EN 0x0 #define EPPI_DIR 0x2 /* Direction */ -#define nEPPI_DIR 0x0 #define XFR_TYPE 0xc /* Operating Mode */ #define FS_CFG 0x30 /* Frame Sync Configuration */ #define FLD_SEL 0x40 /* Field Select/Trigger */ -#define nFLD_SEL 0x0 #define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */ -#define nITU_TYPE 0x0 #define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */ -#define nBLANKGEN 0x0 #define ICLKGEN 0x200 /* Internal Clock Generation */ -#define nICLKGEN 0x0 #define IFSGEN 0x400 /* Internal Frame Sync Generation */ -#define nIFSGEN 0x0 #define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */ #define POLS 0x6000 /* Frame Sync Polarity */ #define DLENGTH 0x38000 /* Data Length */ #define SKIP_EN 0x40000 /* Skip Enable */ -#define nSKIP_EN 0x0 #define SKIP_EO 0x80000 /* Skip Even or Odd */ -#define nSKIP_EO 0x0 #define PACKEN 0x100000 /* Packing/Unpacking Enable */ -#define nPACKEN 0x0 #define SWAPEN 0x200000 /* Swap Enable */ -#define nSWAPEN 0x0 #define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */ -#define nSIGN_EXT 0x0 #define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */ -#define nSPLT_EVEN_ODD 0x0 #define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */ -#define nSUBSPLT_ODD 0x0 #define DMACFG 0x2000000 /* One or Two DMA Channels Mode */ -#define nDMACFG 0x0 #define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */ -#define nRGB_FMT_EN 0x0 #define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */ #define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */ +#define DLEN_8 (0 << 15) /* 000 - 8 bits */ +#define DLEN_10 (1 << 15) /* 001 - 10 bits */ +#define DLEN_12 (2 << 15) /* 010 - 12 bits */ +#define DLEN_14 (3 << 15) /* 011 - 14 bits */ +#define DLEN_16 (4 << 15) /* 100 - 16 bits */ +#define DLEN_18 (5 << 15) /* 101 - 18 bits */ +#define DLEN_24 (6 << 15) /* 110 - 24 bits */ + + /* Bit masks for EPPIx_FS2W_LVB */ #define F1VB_BD 0xff /* Vertical Blanking before Field 1 Active Data */ @@ -3951,60 +3085,36 @@ /* Bit masks for SPIx_CTL */ #define SPE 0x4000 /* SPI Enable */ -#define nSPE 0x0 #define WOM 0x2000 /* Write Open Drain Master */ -#define nWOM 0x0 #define MSTR 0x1000 /* Master Mode */ -#define nMSTR 0x0 #define CPOL 0x800 /* Clock Polarity */ -#define nCPOL 0x0 #define CPHA 0x400 /* Clock Phase */ -#define nCPHA 0x0 #define LSBF 0x200 /* LSB First */ -#define nLSBF 0x0 #define SIZE 0x100 /* Size of Words */ -#define nSIZE 0x0 #define EMISO 0x20 /* Enable MISO Output */ -#define nEMISO 0x0 #define PSSE 0x10 /* Slave-Select Enable */ -#define nPSSE 0x0 #define GM 0x8 /* Get More Data */ -#define nGM 0x0 #define SZ 0x4 /* Send Zero */ -#define nSZ 0x0 #define TIMOD 0x3 /* Transfer Initiation Mode */ /* Bit masks for SPIx_FLG */ #define FLS1 0x2 /* Slave Select Enable 1 */ -#define nFLS1 0x0 #define FLS2 0x4 /* Slave Select Enable 2 */ -#define nFLS2 0x0 #define FLS3 0x8 /* Slave Select Enable 3 */ -#define nFLS3 0x0 #define FLG1 0x200 /* Slave Select Value 1 */ -#define nFLG1 0x0 #define FLG2 0x400 /* Slave Select Value 2 */ -#define nFLG2 0x0 #define FLG3 0x800 /* Slave Select Value 3 */ -#define nFLG3 0x0 /* Bit masks for SPIx_STAT */ #define TXCOL 0x40 /* Transmit Collision Error */ -#define nTXCOL 0x0 #define RXS 0x20 /* RDBR Data Buffer Status */ -#define nRXS 0x0 #define RBSY 0x10 /* Receive Error */ -#define nRBSY 0x0 #define TXS 0x8 /* TDBR Data Buffer Status */ -#define nTXS 0x0 #define TXE 0x4 /* Transmission Error */ -#define nTXE 0x0 #define MODF 0x2 /* Mode Fault Error */ -#define nMODF 0x0 #define SPIF 0x1 /* SPI Finished */ -#define nSPIF 0x0 /* Bit masks for SPIx_TDBR */ @@ -4028,9 +3138,7 @@ #define PRESCALE 0x7f /* Prescale Value */ #define TWI_ENA 0x80 /* TWI Enable */ -#define nTWI_ENA 0x0 #define SCCB 0x200 /* Serial Camera Control Bus */ -#define nSCCB 0x0 /* Bit maskes for TWIx_CLKDIV */ @@ -4040,13 +3148,9 @@ /* Bit maskes for TWIx_SLAVE_CTL */ #define SEN 0x1 /* Slave Enable */ -#define nSEN 0x0 #define STDVAL 0x4 /* Slave Transmit Data Valid */ -#define nSTDVAL 0x0 #define NAK 0x8 /* Not Acknowledge */ -#define nNAK 0x0 #define GEN 0x10 /* General Call Enable */ -#define nGEN 0x0 /* Bit maskes for TWIx_SLAVE_ADDR */ @@ -4055,27 +3159,18 @@ /* Bit maskes for TWIx_SLAVE_STAT */ #define SDIR 0x1 /* Slave Transfer Direction */ -#define nSDIR 0x0 #define GCALL 0x2 /* General Call */ -#define nGCALL 0x0 /* Bit maskes for TWIx_MASTER_CTL */ #define MEN 0x1 /* Master Mode Enable */ -#define nMEN 0x0 #define MDIR 0x4 /* Master Transfer Direction */ -#define nMDIR 0x0 #define FAST 0x8 /* Fast Mode */ -#define nFAST 0x0 #define STOP 0x10 /* Issue Stop Condition */ -#define nSTOP 0x0 #define RSTART 0x20 /* Repeat Start */ -#define nRSTART 0x0 #define DCNT 0x3fc0 /* Data Transfer Count */ #define SDAOVR 0x4000 /* Serial Data Override */ -#define nSDAOVR 0x0 #define SCLOVR 0x8000 /* Serial Clock Override */ -#define nSCLOVR 0x0 /* Bit maskes for TWIx_MASTER_ADDR */ @@ -4084,34 +3179,21 @@ /* Bit maskes for TWIx_MASTER_STAT */ #define MPROG 0x1 /* Master Transfer in Progress */ -#define nMPROG 0x0 #define LOSTARB 0x2 /* Lost Arbitration */ -#define nLOSTARB 0x0 #define ANAK 0x4 /* Address Not Acknowledged */ -#define nANAK 0x0 #define DNAK 0x8 /* Data Not Acknowledged */ -#define nDNAK 0x0 #define BUFRDERR 0x10 /* Buffer Read Error */ -#define nBUFRDERR 0x0 #define BUFWRERR 0x20 /* Buffer Write Error */ -#define nBUFWRERR 0x0 #define SDASEN 0x40 /* Serial Data Sense */ -#define nSDASEN 0x0 #define SCLSEN 0x80 /* Serial Clock Sense */ -#define nSCLSEN 0x0 #define BUSBUSY 0x100 /* Bus Busy */ -#define nBUSBUSY 0x0 /* Bit maskes for TWIx_FIFO_CTL */ #define XMTFLUSH 0x1 /* Transmit Buffer Flush */ -#define nXMTFLUSH 0x0 #define RCVFLUSH 0x2 /* Receive Buffer Flush */ -#define nRCVFLUSH 0x0 #define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */ -#define nXMTINTLEN 0x0 #define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */ -#define nRCVINTLEN 0x0 /* Bit maskes for TWIx_FIFO_STAT */ @@ -4121,40 +3203,24 @@ /* Bit maskes for TWIx_INT_MASK */ #define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */ -#define nSINITM 0x0 #define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */ -#define nSCOMPM 0x0 #define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */ -#define nSERRM 0x0 #define SOVFM 0x8 /* Slave Overflow Interrupt Mask */ -#define nSOVFM 0x0 #define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */ -#define nMCOMPM 0x0 #define MERRM 0x20 /* Master Transfer Error Interrupt Mask */ -#define nMERRM 0x0 #define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */ -#define nXMTSERVM 0x0 #define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */ -#define nRCVSERVM 0x0 /* Bit maskes for TWIx_INT_STAT */ #define SINIT 0x1 /* Slave Transfer Initiated */ -#define nSINIT 0x0 #define SCOMP 0x2 /* Slave Transfer Complete */ -#define nSCOMP 0x0 #define SERR 0x4 /* Slave Transfer Error */ -#define nSERR 0x0 #define SOVF 0x8 /* Slave Overflow */ -#define nSOVF 0x0 #define MCOMP 0x10 /* Master Transfer Complete */ -#define nMCOMP 0x0 #define MERR 0x20 /* Master Transfer Error */ -#define nMERR 0x0 #define XMTSERV 0x40 /* Transmit FIFO Service */ -#define nXMTSERV 0x0 #define RCVSERV 0x80 /* Receive FIFO Service */ -#define nRCVSERV 0x0 /* Bit maskes for TWIx_XMT_DATA8 */ @@ -4175,81 +3241,51 @@ /* Bit masks for SPORTx_TCR1 */ #define TCKFE 0x4000 /* Clock Falling Edge Select */ -#define nTCKFE 0x0 #define LATFS 0x2000 /* Late Transmit Frame Sync */ -#define nLATFS 0x0 #define LTFS 0x1000 /* Low Transmit Frame Sync Select */ -#define nLTFS 0x0 #define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */ -#define nDITFS 0x0 #define TFSR 0x400 /* Transmit Frame Sync Required Select */ -#define nTFSR 0x0 #define ITFS 0x200 /* Internal Transmit Frame Sync Select */ -#define nITFS 0x0 #define TLSBIT 0x10 /* Transmit Bit Order */ -#define nTLSBIT 0x0 #define TDTYPE 0xc /* Data Formatting Type Select */ #define ITCLK 0x2 /* Internal Transmit Clock Select */ -#define nITCLK 0x0 #define TSPEN 0x1 /* Transmit Enable */ -#define nTSPEN 0x0 /* Bit masks for SPORTx_TCR2 */ #define TRFST 0x400 /* Left/Right Order */ -#define nTRFST 0x0 #define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */ -#define nTSFSE 0x0 #define TXSE 0x100 /* TxSEC Enable */ -#define nTXSE 0x0 #define SLEN_T 0x1f /* SPORT Word Length */ /* Bit masks for SPORTx_RCR1 */ #define RCKFE 0x4000 /* Clock Falling Edge Select */ -#define nRCKFE 0x0 #define LARFS 0x2000 /* Late Receive Frame Sync */ -#define nLARFS 0x0 #define LRFS 0x1000 /* Low Receive Frame Sync Select */ -#define nLRFS 0x0 #define RFSR 0x400 /* Receive Frame Sync Required Select */ -#define nRFSR 0x0 #define IRFS 0x200 /* Internal Receive Frame Sync Select */ -#define nIRFS 0x0 #define RLSBIT 0x10 /* Receive Bit Order */ -#define nRLSBIT 0x0 #define RDTYPE 0xc /* Data Formatting Type Select */ #define IRCLK 0x2 /* Internal Receive Clock Select */ -#define nIRCLK 0x0 #define RSPEN 0x1 /* Receive Enable */ -#define nRSPEN 0x0 /* Bit masks for SPORTx_RCR2 */ #define RRFST 0x400 /* Left/Right Order */ -#define nRRFST 0x0 #define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */ -#define nRSFSE 0x0 #define RXSE 0x100 /* RxSEC Enable */ -#define nRXSE 0x0 #define SLEN_R 0x1f /* SPORT Word Length */ /* Bit masks for SPORTx_STAT */ #define TXHRE 0x40 /* Transmit Hold Register Empty */ -#define nTXHRE 0x0 #define TOVF 0x20 /* Sticky Transmit Overflow Status */ -#define nTOVF 0x0 #define TUVF 0x10 /* Sticky Transmit Underflow Status */ -#define nTUVF 0x0 #define TXF 0x8 /* Transmit FIFO Full Status */ -#define nTXF 0x0 #define ROVF 0x4 /* Sticky Receive Overflow Status */ -#define nROVF 0x0 #define RUVF 0x2 /* Sticky Receive Underflow Status */ -#define nRUVF 0x0 #define RXNE 0x1 /* Receive FIFO Not Empty Status */ -#define nRXNE 0x0 /* Bit masks for SPORTx_MCMC1 */ @@ -4260,13 +3296,9 @@ #define MFD 0xf000 /* Multi channel Frame Delay */ #define FSDR 0x80 /* Frame Sync to Data Relationship */ -#define nFSDR 0x0 #define MCMEM 0x10 /* Multi channel Frame Mode Enable */ -#define nMCMEM 0x0 #define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */ -#define nMCDRXPE 0x0 #define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */ -#define nMCDTXPE 0x0 #define MCCRM 0x3 /* 2X Clock Recovery Mode */ /* Bit masks for SPORTx_CHNL */ @@ -4280,115 +3312,59 @@ #define WLS 0x3 /* Word Length Select */ #endif #define STB 0x4 /* Stop Bits */ -#define nSTB 0x0 #define PEN 0x8 /* Parity Enable */ -#define nPEN 0x0 #define EPS 0x10 /* Even Parity Select */ -#define nEPS 0x0 #define STP 0x20 /* Sticky Parity */ -#define nSTP 0x0 #define SB 0x40 /* Set Break */ -#define nSB 0x0 /* Bit masks for UARTx_MCR */ #define XOFF 0x1 /* Transmitter Off */ -#define nXOFF 0x0 #define MRTS 0x2 /* Manual Request To Send */ -#define nMRTS 0x0 #define RFIT 0x4 /* Receive FIFO IRQ Threshold */ -#define nRFIT 0x0 #define RFRT 0x8 /* Receive FIFO RTS Threshold */ -#define nRFRT 0x0 #define LOOP_ENA 0x10 /* Loopback Mode Enable */ -#define nLOOP_ENA 0x0 #define FCPOL 0x20 /* Flow Control Pin Polarity */ -#define nFCPOL 0x0 #define ARTS 0x40 /* Automatic Request To Send */ -#define nARTS 0x0 #define ACTS 0x80 /* Automatic Clear To Send */ -#define nACTS 0x0 /* Bit masks for UARTx_LSR */ #define DR 0x1 /* Data Ready */ -#define nDR 0x0 #define OE 0x2 /* Overrun Error */ -#define nOE 0x0 #define PE 0x4 /* Parity Error */ -#define nPE 0x0 #define FE 0x8 /* Framing Error */ -#define nFE 0x0 #define BI 0x10 /* Break Interrupt */ -#define nBI 0x0 #define THRE 0x20 /* THR Empty */ -#define nTHRE 0x0 #define TEMT 0x40 /* Transmitter Empty */ -#define nTEMT 0x0 #define TFI 0x80 /* Transmission Finished Indicator */ -#define nTFI 0x0 /* Bit masks for UARTx_MSR */ #define SCTS 0x1 /* Sticky CTS */ -#define nSCTS 0x0 #define CTS 0x10 /* Clear To Send */ -#define nCTS 0x0 #define RFCS 0x20 /* Receive FIFO Count Status */ -#define nRFCS 0x0 - -/* Bit masks for UARTx_IER_SET */ - -#define ERBFI_S 0x1 /* Enable Receive Buffer Full Interrupt */ -#define nERBFI_S 0x0 -#define ETBEI_S 0x2 /* Enable Transmit Buffer Empty Interrupt */ -#define nETBEI_S 0x0 -#define ELSI_S 0x4 /* Enable Receive Status Interrupt */ -#define nELSI_S 0x0 -#define EDSSI_S 0x8 /* Enable Modem Status Interrupt */ -#define nEDSSI_S 0x0 -#define EDTPTI_S 0x10 /* Enable DMA Transmit PIRQ Interrupt */ -#define nEDTPTI_S 0x0 -#define ETFI_S 0x20 /* Enable Transmission Finished Interrupt */ -#define nETFI_S 0x0 -#define ERFCI_S 0x40 /* Enable Receive FIFO Count Interrupt */ -#define nERFCI_S 0x0 - -/* Bit masks for UARTx_IER_CLEAR */ - -#define ERBFI_C 0x1 /* Enable Receive Buffer Full Interrupt */ -#define nERBFI_C 0x0 -#define ETBEI_C 0x2 /* Enable Transmit Buffer Empty Interrupt */ -#define nETBEI_C 0x0 -#define ELSI_C 0x4 /* Enable Receive Status Interrupt */ -#define nELSI_C 0x0 -#define EDSSI_C 0x8 /* Enable Modem Status Interrupt */ -#define nEDSSI_C 0x0 -#define EDTPTI_C 0x10 /* Enable DMA Transmit PIRQ Interrupt */ -#define nEDTPTI_C 0x0 -#define ETFI_C 0x20 /* Enable Transmission Finished Interrupt */ -#define nETFI_C 0x0 -#define ERFCI_C 0x40 /* Enable Receive FIFO Count Interrupt */ -#define nERFCI_C 0x0 + +/* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */ + +#define ERBFI 0x1 /* Enable Receive Buffer Full Interrupt */ +#define ETBEI 0x2 /* Enable Transmit Buffer Empty Interrupt */ +#define ELSI 0x4 /* Enable Receive Status Interrupt */ +#define EDSSI 0x8 /* Enable Modem Status Interrupt */ +#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */ +#define ETFI 0x20 /* Enable Transmission Finished Interrupt */ +#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */ /* Bit masks for UARTx_GCTL */ #define UCEN 0x1 /* UART Enable */ -#define nUCEN 0x0 #define IREN 0x2 /* IrDA Mode Enable */ -#define nIREN 0x0 #define TPOLC 0x4 /* IrDA TX Polarity Change */ -#define nTPOLC 0x0 #define RPOLC 0x8 /* IrDA RX Polarity Change */ -#define nRPOLC 0x0 #define FPE 0x10 /* Force Parity Error */ -#define nFPE 0x0 #define FFE 0x20 /* Force Framing Error */ -#define nFFE 0x0 #define EDBO 0x40 /* Enable Divide-by-One */ -#define nEDBO 0x0 #define EGLSI 0x80 /* Enable Global LS Interrupt */ -#define nEGLSI 0x0 /* ******************************************* */ @@ -4398,32 +3374,32 @@ /* BCODE bit field options (SYSCFG register) */ #define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */ -#define BCODE_FULLBOOT 0x0010 /* always perform full boot */ +#define BCODE_FULLBOOT 0x0010 /* always perform full boot */ #define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */ #define BCODE_NOBOOT 0x0030 /* always perform full boot */ /* CNT_COMMAND bit field options */ - + #define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */ #define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */ #define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */ - + #define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */ #define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */ #define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */ - + #define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */ #define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */ #define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */ - + /* CNT_CONFIG bit field options */ - + #define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */ #define CNTMODE_BINENC 0x0100 /* binary encoder mode */ #define CNTMODE_UDCNT 0x0200 /* up/down counter mode */ #define CNTMODE_DIRCNT 0x0400 /* direction counter mode */ #define CNTMODE_DIRTMR 0x0500 /* direction timer mode */ - + #define BNDMODE_COMP 0x0000 /* boundary compare mode */ #define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */ #define BNDMODE_CAPT 0x2000 /* boundary capture mode */ @@ -4436,7 +3412,7 @@ #define EXT_CLK 0x0003 /* UARTx_LCR bit field options */ - + #define WLS_5 0x0000 /* 5 data bits */ #define WLS_6 0x0001 /* 6 data bits */ #define WLS_7 0x0002 /* 7 data bits */ @@ -4484,7 +3460,7 @@ #define PIQ30 0x40000000 #define PIQ31 0x80000000 -/* PORT A Bit Definitions for the registers +/* PORT A Bit Definitions for the registers PORTA, PORTA_SET, PORTA_CLEAR, PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN, PORTA_FER registers @@ -4507,7 +3483,7 @@ PORTA_FER registers #define PA14 0x4000 #define PA15 0x8000 -/* PORT B Bit Definitions for the registers +/* PORT B Bit Definitions for the registers PORTB, PORTB_SET, PORTB_CLEAR, PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN, PORTB_FER registers @@ -4530,7 +3506,7 @@ PORTB_FER registers #define PB14 0x4000 -/* PORT C Bit Definitions for the registers +/* PORT C Bit Definitions for the registers PORTC, PORTC_SET, PORTC_CLEAR, PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN, PORTC_FER registers @@ -4553,7 +3529,7 @@ PORTC_FER registers #define PC13 0x2000 -/* PORT D Bit Definitions for the registers +/* PORT D Bit Definitions for the registers PORTD, PORTD_SET, PORTD_CLEAR, PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN, PORTD_FER registers @@ -4576,7 +3552,7 @@ PORTD_FER registers #define PD14 0x4000 #define PD15 0x8000 -/* PORT E Bit Definitions for the registers +/* PORT E Bit Definitions for the registers PORTE, PORTE_SET, PORTE_CLEAR, PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN, PORTE_FER registers @@ -4600,7 +3576,7 @@ PORTE_FER registers #define PE14 0x4000 #define PE15 0x8000 -/* PORT F Bit Definitions for the registers +/* PORT F Bit Definitions for the registers PORTF, PORTF_SET, PORTF_CLEAR, PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN, PORTF_FER registers @@ -4624,7 +3600,7 @@ PORTF_FER registers #define PF14 0x4000 #define PF15 0x8000 -/* PORT G Bit Definitions for the registers +/* PORT G Bit Definitions for the registers PORTG, PORTG_SET, PORTG_CLEAR, PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN, PORTG_FER registers @@ -4648,7 +3624,7 @@ PORTG_FER registers #define PG14 0x4000 #define PG15 0x8000 -/* PORT H Bit Definitions for the registers +/* PORT H Bit Definitions for the registers PORTH, PORTH_SET, PORTH_CLEAR, PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN, PORTH_FER registers @@ -4671,7 +3647,7 @@ PORTH_FER registers #define PH13 0x2000 -/* PORT I Bit Definitions for the registers +/* PORT I Bit Definitions for the registers PORTI, PORTI_SET, PORTI_CLEAR, PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN, PORTI_FER registers @@ -4695,7 +3671,7 @@ PORTI_FER registers #define PI14 0x4000 #define PI15 0x8000 -/* PORT J Bit Definitions for the registers +/* PORT J Bit Definitions for the registers PORTJ, PORTJ_SET, PORTJ_CLEAR, PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN, PORTJ_FER registers @@ -4716,7 +3692,7 @@ PORTJ_FER registers #define PJ11 0x0800 #define PJ12 0x1000 #define PJ13 0x2000 - + /* Port Muxing Bit Fields for PORTx_MUX Registers */ @@ -4860,7 +3836,7 @@ PORTJ_FER registers #define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */ #define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */ -#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */ +#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */ #define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */ #define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */ #define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */ @@ -4869,27 +3845,27 @@ PORTJ_FER registers #define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */ #define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */ -#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */ -#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */ -#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */ -#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */ -#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */ -#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */ -#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */ -#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */ - -#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */ -#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */ -#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */ -#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */ -#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */ -#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */ -#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */ -#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */ +#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */ +#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */ +#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */ +#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */ +#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */ +#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */ +#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */ +#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */ + +#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */ +#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */ +#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */ +#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */ +#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */ +#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */ +#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */ +#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */ /* for legacy compatibility */ - + #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ #define W1LMAX_MAX W1LMAX_MIN #define EBIU_AMCBCTL0 EBIU_AMBCTL0 diff --git a/include/asm-blackfin/mach-bf548/dma.h b/include/asm-blackfin/mach-bf548/dma.h new file mode 100644 index 000000000000..fcc8b4c34c6a --- /dev/null +++ b/include/asm-blackfin/mach-bf548/dma.h @@ -0,0 +1,73 @@ +/* + * file: include/asm-blackfin/mach-bf548/dma.h + * based on: + * author: + * + * created: + * description: + * system mmr register map + * rev: + * + * modified: + * + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + +#ifndef _MACH_DMA_H_ +#define _MACH_DMA_H_ + +#define CH_SPORT0_RX 0 +#define CH_SPORT0_TX 1 +#define CH_SPORT1_RX 2 +#define CH_SPORT1_TX 3 +#define CH_SPI0 4 +#define CH_SPI1 5 +#define CH_UART0_RX 6 +#define CH_UART0_TX 7 +#define CH_UART1_RX 8 +#define CH_UART1_TX 9 +#define CH_ATAPI_RX 10 +#define CH_ATAPI_TX 11 +#define CH_EPPI0 12 +#define CH_EPPI1 13 +#define CH_EPPI2 14 +#define CH_PIXC_IMAGE 15 +#define CH_PIXC_OVERLAY 16 +#define CH_PIXC_OUTPUT 17 +#define CH_SPORT2_RX 18 +#define CH_SPORT2_TX 19 +#define CH_SPORT3_RX 20 +#define CH_SPORT3_TX 21 +#define CH_SDH 22 +#define CH_SPI2 23 + +#define CH_MEM_STREAM0_DEST 24 +#define CH_MEM_STREAM0_SRC 25 +#define CH_MEM_STREAM1_DEST 26 +#define CH_MEM_STREAM1_SRC 27 +#define CH_MEM_STREAM2_DEST 28 +#define CH_MEM_STREAM2_SRC 29 +#define CH_MEM_STREAM3_DEST 30 +#define CH_MEM_STREAM3_SRC 31 + +#define MAX_BLACKFIN_DMA_CHANNEL 32 + +extern int channel2irq(unsigned int channel); +extern struct dma_register *base_addr[]; +#endif diff --git a/include/asm-blackfin/mach-bf548/gpio.h b/include/asm-blackfin/mach-bf548/gpio.h new file mode 100644 index 000000000000..dbf66bcabe35 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/gpio.h @@ -0,0 +1,216 @@ +/* + * File: include/asm-blackfin/mach-bf548/gpio.h + * Based on: + * Author: Michael Hennerich (hennerich@blackfin.uclinux.org) + * + * Created: + * Description: + * + * Modified: + * Copyright 2004-2007 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + + +#define GPIO_PA0 0 +#define GPIO_PA1 1 +#define GPIO_PA2 2 +#define GPIO_PA3 3 +#define GPIO_PA4 4 +#define GPIO_PA5 5 +#define GPIO_PA6 6 +#define GPIO_PA7 7 +#define GPIO_PA8 8 +#define GPIO_PA9 9 +#define GPIO_PA10 10 +#define GPIO_PA11 11 +#define GPIO_PA12 12 +#define GPIO_PA13 13 +#define GPIO_PA14 14 +#define GPIO_PA15 15 +#define GPIO_PB0 16 +#define GPIO_PB1 17 +#define GPIO_PB2 18 +#define GPIO_PB3 19 +#define GPIO_PB4 20 +#define GPIO_PB5 21 +#define GPIO_PB6 22 +#define GPIO_PB7 23 +#define GPIO_PB8 24 +#define GPIO_PB9 25 +#define GPIO_PB10 26 +#define GPIO_PB11 27 +#define GPIO_PB12 28 +#define GPIO_PB13 29 +#define GPIO_PB14 30 +#define GPIO_PB15 31 /* N/A */ +#define GPIO_PC0 32 +#define GPIO_PC1 33 +#define GPIO_PC2 34 +#define GPIO_PC3 35 +#define GPIO_PC4 36 +#define GPIO_PC5 37 +#define GPIO_PC6 38 +#define GPIO_PC7 39 +#define GPIO_PC8 40 +#define GPIO_PC9 41 +#define GPIO_PC10 42 +#define GPIO_PC11 43 +#define GPIO_PC12 44 +#define GPIO_PC13 45 +#define GPIO_PC14 46 /* N/A */ +#define GPIO_PC15 47 /* N/A */ +#define GPIO_PD0 48 +#define GPIO_PD1 49 +#define GPIO_PD2 50 +#define GPIO_PD3 51 +#define GPIO_PD4 52 +#define GPIO_PD5 53 +#define GPIO_PD6 54 +#define GPIO_PD7 55 +#define GPIO_PD8 56 +#define GPIO_PD9 57 +#define GPIO_PD10 58 +#define GPIO_PD11 59 +#define GPIO_PD12 60 +#define GPIO_PD13 61 +#define GPIO_PD14 62 +#define GPIO_PD15 63 +#define GPIO_PE0 64 +#define GPIO_PE1 65 +#define GPIO_PE2 66 +#define GPIO_PE3 67 +#define GPIO_PE4 68 +#define GPIO_PE5 69 +#define GPIO_PE6 70 +#define GPIO_PE7 71 +#define GPIO_PE8 72 +#define GPIO_PE9 73 +#define GPIO_PE10 74 +#define GPIO_PE11 75 +#define GPIO_PE12 76 +#define GPIO_PE13 77 +#define GPIO_PE14 78 +#define GPIO_PE15 79 +#define GPIO_PF0 80 +#define GPIO_PF1 81 +#define GPIO_PF2 82 +#define GPIO_PF3 83 +#define GPIO_PF4 84 +#define GPIO_PF5 85 +#define GPIO_PF6 86 +#define GPIO_PF7 87 +#define GPIO_PF8 88 +#define GPIO_PF9 89 +#define GPIO_PF10 90 +#define GPIO_PF11 91 +#define GPIO_PF12 92 +#define GPIO_PF13 93 +#define GPIO_PF14 94 +#define GPIO_PF15 95 +#define GPIO_PG0 96 +#define GPIO_PG1 97 +#define GPIO_PG2 98 +#define GPIO_PG3 99 +#define GPIO_PG4 100 +#define GPIO_PG5 101 +#define GPIO_PG6 102 +#define GPIO_PG7 103 +#define GPIO_PG8 104 +#define GPIO_PG9 105 +#define GPIO_PG10 106 +#define GPIO_PG11 107 +#define GPIO_PG12 108 +#define GPIO_PG13 109 +#define GPIO_PG14 110 +#define GPIO_PG15 111 +#define GPIO_PH0 112 +#define GPIO_PH1 113 +#define GPIO_PH2 114 +#define GPIO_PH3 115 +#define GPIO_PH4 116 +#define GPIO_PH5 117 +#define GPIO_PH6 118 +#define GPIO_PH7 119 +#define GPIO_PH8 120 +#define GPIO_PH9 121 +#define GPIO_PH10 122 +#define GPIO_PH11 123 +#define GPIO_PH12 124 +#define GPIO_PH13 125 +#define GPIO_PH14 126 /* N/A */ +#define GPIO_PH15 127 /* N/A */ +#define GPIO_PI0 128 +#define GPIO_PI1 129 +#define GPIO_PI2 130 +#define GPIO_PI3 131 +#define GPIO_PI4 132 +#define GPIO_PI5 133 +#define GPIO_PI6 134 +#define GPIO_PI7 135 +#define GPIO_PI8 136 +#define GPIO_PI9 137 +#define GPIO_PI10 138 +#define GPIO_PI11 139 +#define GPIO_PI12 140 +#define GPIO_PI13 141 +#define GPIO_PI14 142 +#define GPIO_PI15 143 +#define GPIO_PJ0 144 +#define GPIO_PJ1 145 +#define GPIO_PJ2 146 +#define GPIO_PJ3 147 +#define GPIO_PJ4 148 +#define GPIO_PJ5 149 +#define GPIO_PJ6 150 +#define GPIO_PJ7 151 +#define GPIO_PJ8 152 +#define GPIO_PJ9 153 +#define GPIO_PJ10 154 +#define GPIO_PJ11 155 +#define GPIO_PJ12 156 +#define GPIO_PJ13 157 +#define GPIO_PJ14 158 /* N/A */ +#define GPIO_PJ15 159 /* N/A */ + +#define MAX_BLACKFIN_GPIOS 160 + +struct gpio_port_t { + unsigned short port_fer; + unsigned short dummy1; + unsigned short port_data; + unsigned short dummy2; + unsigned short port_set; + unsigned short dummy3; + unsigned short port_clear; + unsigned short dummy4; + unsigned short port_dir_set; + unsigned short dummy5; + unsigned short port_dir_clear; + unsigned short dummy6; + unsigned short port_inen; + unsigned short dummy7; + unsigned int port_mux; +}; + +int gpio_request(unsigned short gpio, const char *label); +void peripheral_free(unsigned short per); +int peripheral_request_list(unsigned short per[], const char *label); +void peripheral_free_list(unsigned short per[]); diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h new file mode 100644 index 000000000000..0b3325bb1fff --- /dev/null +++ b/include/asm-blackfin/mach-bf548/irq.h @@ -0,0 +1,467 @@ +/* + * file: include/asm-blackfin/mach-bf548/irq.h + * based on: include/asm-blackfin/mach-bf537/irq.h + * author: Roy Huang (roy.huang@analog.com) + * + * created: + * description: + * system mmr register map + * rev: + * + * modified: + * + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + +#ifndef _BF548_IRQ_H_ +#define _BF548_IRQ_H_ + +/* + * Interrupt source definitions + Event Source Core Event Name +Core Emulation ** +Events (highest priority) EMU 0 + Reset RST 1 + NMI NMI 2 + Exception EVX 3 + Reserved -- 4 + Hardware Error IVHW 5 + Core Timer IVTMR 6 * + +..... + + Software Interrupt 1 IVG14 31 + Software Interrupt 2 -- + (lowest priority) IVG15 32 * + */ + +#define NR_PERI_INTS (32 * 3) + +/* The ABSTRACT IRQ definitions */ +/** the first seven of the following are fixed, the rest you change if you need to **/ +#define IRQ_EMU 0 /* Emulation */ +#define IRQ_RST 1 /* reset */ +#define IRQ_NMI 2 /* Non Maskable */ +#define IRQ_EVX 3 /* Exception */ +#define IRQ_UNUSED 4 /* - unused interrupt*/ +#define IRQ_HWERR 5 /* Hardware Error */ +#define IRQ_CORETMR 6 /* Core timer */ + +#define BFIN_IRQ(x) ((x) + 7) + +#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ +#define IRQ_DMAC0_ERR BFIN_IRQ(1) /* DMAC0 Status Interrupt */ +#define IRQ_EPPI0_ERR BFIN_IRQ(2) /* EPPI0 Error Interrupt */ +#define IRQ_SPORT0_ERR BFIN_IRQ(3) /* SPORT0 Error Interrupt */ +#define IRQ_SPORT1_ERR BFIN_IRQ(4) /* SPORT1 Error Interrupt */ +#define IRQ_SPI0_ERR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */ +#define IRQ_UART0_ERR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */ +#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */ +#define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */ +#define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */ +#define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */ +#define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */ +#define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */ +#define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */ +#define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */ +#define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */ +#define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */ +#define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */ +#define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */ +#define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */ +#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */ +#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */ +#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */ +#define IRQ_WATCHDOG BFIN_IRQ(23) /* Watchdog Interrupt */ +#define IRQ_DMAC1_ERR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ +#define IRQ_SPORT2_ERR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ +#define IRQ_SPORT3_ERR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ +#define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */ +#define IRQ_SPI1_ERR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */ +#define IRQ_SPI2_ERR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */ +#define IRQ_UART1_ERR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */ +#define IRQ_UART2_ERR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ +#define IRQ_CAN0_ERR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ +#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ +#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ +#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ +#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ +#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ +#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ +#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ +#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */ +#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */ +#define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */ +#define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */ +#define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */ +#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */ +#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */ +#define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */ +#define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */ +#define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */ +#define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */ +#define IRQ_MXVR_ERR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */ +#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */ +#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */ +#define IRQ_EPP1_ERR BFIN_IRQ(54) /* EPPI1 Error Interrupt */ +#define IRQ_EPP2_ERR BFIN_IRQ(55) /* EPPI2 Error Interrupt */ +#define IRQ_UART3_ERR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */ +#define IRQ_HOST_ERR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */ +#define IRQ_PIXC_ERR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */ +#define IRQ_NFC_ERR BFIN_IRQ(60) /* NFC Error Interrupt */ +#define IRQ_ATAPI_ERR BFIN_IRQ(61) /* ATAPI Error Interrupt */ +#define IRQ_CAN1_ERR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */ +#define IRQ_HS_DMA_ERR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */ +#define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */ +#define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */ +#define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */ +#define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */ +#define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */ +#define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */ +#define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */ +#define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */ +#define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */ +#define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */ +#define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */ +#define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */ +#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */ +#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */ +#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */ +#define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */ +#define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */ +#define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */ +#define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */ +#define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */ +#define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */ +#define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */ +#define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */ +#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ +#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ + +#define SYS_IRQS IRQ_PINT3 + +#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1) +#define IRQ_PA0 BFIN_PA_IRQ(0) +#define IRQ_PA1 BFIN_PA_IRQ(1) +#define IRQ_PA2 BFIN_PA_IRQ(2) +#define IRQ_PA3 BFIN_PA_IRQ(3) +#define IRQ_PA4 BFIN_PA_IRQ(4) +#define IRQ_PA5 BFIN_PA_IRQ(5) +#define IRQ_PA6 BFIN_PA_IRQ(6) +#define IRQ_PA7 BFIN_PA_IRQ(7) +#define IRQ_PA8 BFIN_PA_IRQ(8) +#define IRQ_PA9 BFIN_PA_IRQ(9) +#define IRQ_PA10 BFIN_PA_IRQ(10) +#define IRQ_PA11 BFIN_PA_IRQ(11) +#define IRQ_PA12 BFIN_PA_IRQ(12) +#define IRQ_PA13 BFIN_PA_IRQ(13) +#define IRQ_PA14 BFIN_PA_IRQ(14) +#define IRQ_PA15 BFIN_PA_IRQ(15) + +#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1) +#define IRQ_PB0 BFIN_PB_IRQ(0) +#define IRQ_PB1 BFIN_PB_IRQ(1) +#define IRQ_PB2 BFIN_PB_IRQ(2) +#define IRQ_PB3 BFIN_PB_IRQ(3) +#define IRQ_PB4 BFIN_PB_IRQ(4) +#define IRQ_PB5 BFIN_PB_IRQ(5) +#define IRQ_PB6 BFIN_PB_IRQ(6) +#define IRQ_PB7 BFIN_PB_IRQ(7) +#define IRQ_PB8 BFIN_PB_IRQ(8) +#define IRQ_PB9 BFIN_PB_IRQ(9) +#define IRQ_PB10 BFIN_PB_IRQ(10) +#define IRQ_PB11 BFIN_PB_IRQ(11) +#define IRQ_PB12 BFIN_PB_IRQ(12) +#define IRQ_PB13 BFIN_PB_IRQ(13) +#define IRQ_PB14 BFIN_PB_IRQ(14) +#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */ + +#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1) +#define IRQ_PC0 BFIN_PC_IRQ(0) +#define IRQ_PC1 BFIN_PC_IRQ(1) +#define IRQ_PC2 BFIN_PC_IRQ(2) +#define IRQ_PC3 BFIN_PC_IRQ(3) +#define IRQ_PC4 BFIN_PC_IRQ(4) +#define IRQ_PC5 BFIN_PC_IRQ(5) +#define IRQ_PC6 BFIN_PC_IRQ(6) +#define IRQ_PC7 BFIN_PC_IRQ(7) +#define IRQ_PC8 BFIN_PC_IRQ(8) +#define IRQ_PC9 BFIN_PC_IRQ(9) +#define IRQ_PC10 BFIN_PC_IRQ(10) +#define IRQ_PC11 BFIN_PC_IRQ(11) +#define IRQ_PC12 BFIN_PC_IRQ(12) +#define IRQ_PC13 BFIN_PC_IRQ(13) +#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */ +#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */ + +#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1) +#define IRQ_PD0 BFIN_PD_IRQ(0) +#define IRQ_PD1 BFIN_PD_IRQ(1) +#define IRQ_PD2 BFIN_PD_IRQ(2) +#define IRQ_PD3 BFIN_PD_IRQ(3) +#define IRQ_PD4 BFIN_PD_IRQ(4) +#define IRQ_PD5 BFIN_PD_IRQ(5) +#define IRQ_PD6 BFIN_PD_IRQ(6) +#define IRQ_PD7 BFIN_PD_IRQ(7) +#define IRQ_PD8 BFIN_PD_IRQ(8) +#define IRQ_PD9 BFIN_PD_IRQ(9) +#define IRQ_PD10 BFIN_PD_IRQ(10) +#define IRQ_PD11 BFIN_PD_IRQ(11) +#define IRQ_PD12 BFIN_PD_IRQ(12) +#define IRQ_PD13 BFIN_PD_IRQ(13) +#define IRQ_PD14 BFIN_PD_IRQ(14) +#define IRQ_PD15 BFIN_PD_IRQ(15) + +#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1) +#define IRQ_PE0 BFIN_PE_IRQ(0) +#define IRQ_PE1 BFIN_PE_IRQ(1) +#define IRQ_PE2 BFIN_PE_IRQ(2) +#define IRQ_PE3 BFIN_PE_IRQ(3) +#define IRQ_PE4 BFIN_PE_IRQ(4) +#define IRQ_PE5 BFIN_PE_IRQ(5) +#define IRQ_PE6 BFIN_PE_IRQ(6) +#define IRQ_PE7 BFIN_PE_IRQ(7) +#define IRQ_PE8 BFIN_PE_IRQ(8) +#define IRQ_PE9 BFIN_PE_IRQ(9) +#define IRQ_PE10 BFIN_PE_IRQ(10) +#define IRQ_PE11 BFIN_PE_IRQ(11) +#define IRQ_PE12 BFIN_PE_IRQ(12) +#define IRQ_PE13 BFIN_PE_IRQ(13) +#define IRQ_PE14 BFIN_PE_IRQ(14) +#define IRQ_PE15 BFIN_PE_IRQ(15) + +#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1) +#define IRQ_PF0 BFIN_PF_IRQ(0) +#define IRQ_PF1 BFIN_PF_IRQ(1) +#define IRQ_PF2 BFIN_PF_IRQ(2) +#define IRQ_PF3 BFIN_PF_IRQ(3) +#define IRQ_PF4 BFIN_PF_IRQ(4) +#define IRQ_PF5 BFIN_PF_IRQ(5) +#define IRQ_PF6 BFIN_PF_IRQ(6) +#define IRQ_PF7 BFIN_PF_IRQ(7) +#define IRQ_PF8 BFIN_PF_IRQ(8) +#define IRQ_PF9 BFIN_PF_IRQ(9) +#define IRQ_PF10 BFIN_PF_IRQ(10) +#define IRQ_PF11 BFIN_PF_IRQ(11) +#define IRQ_PF12 BFIN_PF_IRQ(12) +#define IRQ_PF13 BFIN_PF_IRQ(13) +#define IRQ_PF14 BFIN_PF_IRQ(14) +#define IRQ_PF15 BFIN_PF_IRQ(15) + +#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1) +#define IRQ_PG0 BFIN_PG_IRQ(0) +#define IRQ_PG1 BFIN_PG_IRQ(1) +#define IRQ_PG2 BFIN_PG_IRQ(2) +#define IRQ_PG3 BFIN_PG_IRQ(3) +#define IRQ_PG4 BFIN_PG_IRQ(4) +#define IRQ_PG5 BFIN_PG_IRQ(5) +#define IRQ_PG6 BFIN_PG_IRQ(6) +#define IRQ_PG7 BFIN_PG_IRQ(7) +#define IRQ_PG8 BFIN_PG_IRQ(8) +#define IRQ_PG9 BFIN_PG_IRQ(9) +#define IRQ_PG10 BFIN_PG_IRQ(10) +#define IRQ_PG11 BFIN_PG_IRQ(11) +#define IRQ_PG12 BFIN_PG_IRQ(12) +#define IRQ_PG13 BFIN_PG_IRQ(13) +#define IRQ_PG14 BFIN_PG_IRQ(14) +#define IRQ_PG15 BFIN_PG_IRQ(15) + +#define BFIN_PH_IRQ(x) ((x) + IRQ_PG15 + 1) +#define IRQ_PH0 BFIN_PH_IRQ(0) +#define IRQ_PH1 BFIN_PH_IRQ(1) +#define IRQ_PH2 BFIN_PH_IRQ(2) +#define IRQ_PH3 BFIN_PH_IRQ(3) +#define IRQ_PH4 BFIN_PH_IRQ(4) +#define IRQ_PH5 BFIN_PH_IRQ(5) +#define IRQ_PH6 BFIN_PH_IRQ(6) +#define IRQ_PH7 BFIN_PH_IRQ(7) +#define IRQ_PH8 BFIN_PH_IRQ(8) +#define IRQ_PH9 BFIN_PH_IRQ(9) +#define IRQ_PH10 BFIN_PH_IRQ(10) +#define IRQ_PH11 BFIN_PH_IRQ(11) +#define IRQ_PH12 BFIN_PH_IRQ(12) +#define IRQ_PH13 BFIN_PH_IRQ(13) +#define IRQ_PH14 BFIN_PH_IRQ(14) /* N/A */ +#define IRQ_PH15 BFIN_PH_IRQ(15) /* N/A */ + +#define BFIN_PI_IRQ(x) ((x) + IRQ_PH15 + 1) +#define IRQ_PI0 BFIN_PI_IRQ(0) +#define IRQ_PI1 BFIN_PI_IRQ(1) +#define IRQ_PI2 BFIN_PI_IRQ(2) +#define IRQ_PI3 BFIN_PI_IRQ(3) +#define IRQ_PI4 BFIN_PI_IRQ(4) +#define IRQ_PI5 BFIN_PI_IRQ(5) +#define IRQ_PI6 BFIN_PI_IRQ(6) +#define IRQ_PI7 BFIN_PI_IRQ(7) +#define IRQ_PI8 BFIN_PI_IRQ(8) +#define IRQ_PI9 BFIN_PI_IRQ(9) +#define IRQ_PI10 BFIN_PI_IRQ(10) +#define IRQ_PI11 BFIN_PI_IRQ(11) +#define IRQ_PI12 BFIN_PI_IRQ(12) +#define IRQ_PI13 BFIN_PI_IRQ(13) +#define IRQ_PI14 BFIN_PI_IRQ(14) +#define IRQ_PI15 BFIN_PI_IRQ(15) + +#define BFIN_PJ_IRQ(x) ((x) + IRQ_PI15 + 1) +#define IRQ_PJ0 BFIN_PJ_IRQ(0) +#define IRQ_PJ1 BFIN_PJ_IRQ(1) +#define IRQ_PJ2 BFIN_PJ_IRQ(2) +#define IRQ_PJ3 BFIN_PJ_IRQ(3) +#define IRQ_PJ4 BFIN_PJ_IRQ(4) +#define IRQ_PJ5 BFIN_PJ_IRQ(5) +#define IRQ_PJ6 BFIN_PJ_IRQ(6) +#define IRQ_PJ7 BFIN_PJ_IRQ(7) +#define IRQ_PJ8 BFIN_PJ_IRQ(8) +#define IRQ_PJ9 BFIN_PJ_IRQ(9) +#define IRQ_PJ10 BFIN_PJ_IRQ(10) +#define IRQ_PJ11 BFIN_PJ_IRQ(11) +#define IRQ_PJ12 BFIN_PJ_IRQ(12) +#define IRQ_PJ13 BFIN_PJ_IRQ(13) +#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */ +#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */ + +#ifdef CONFIG_IRQCHIP_DEMUX_GPIO +#define NR_IRQS (IRQ_PJ15+1) +#else +#define NR_IRQS (SYS_IRQS+1) +#endif + +#define IVG7 7 +#define IVG8 8 +#define IVG9 9 +#define IVG10 10 +#define IVG11 11 +#define IVG12 12 +#define IVG13 13 +#define IVG14 14 +#define IVG15 15 + +/* IAR0 BIT FIELDS */ +#define IRQ_PLL_WAKEUP_POS 0 +#define IRQ_DMAC0_ERR_POS 4 +#define IRQ_EPPI0_ERR_POS 8 +#define IRQ_SPORT0_ERR_POS 12 +#define IRQ_SPORT1_ERR_POS 16 +#define IRQ_SPI0_ERR_POS 20 +#define IRQ_UART0_ERR_POS 24 +#define IRQ_RTC_POS 28 + +/* IAR1 BIT FIELDS */ +#define IRQ_EPPI0_POS 0 +#define IRQ_SPORT0_RX_POS 4 +#define IRQ_SPORT0_TX_POS 8 +#define IRQ_SPORT1_RX_POS 12 +#define IRQ_SPORT1_TX_POS 16 +#define IRQ_SPI0_POS 20 +#define IRQ_UART0_RX_POS 24 +#define IRQ_UART0_TX_POS 28 + +/* IAR2 BIT FIELDS */ +#define IRQ_TIMER8_POS 0 +#define IRQ_TIMER9_POS 4 +#define IRQ_TIMER10_POS 8 +#define IRQ_PINT0_POS 12 +#define IRQ_PINT1_POS 16 +#define IRQ_MDMAS0_POS 20 +#define IRQ_MDMAS1_POS 24 +#define IRQ_WATCHDOG_POS 28 + +/* IAR3 BIT FIELDS */ +#define IRQ_DMAC1_ERR_POS 0 +#define IRQ_SPORT2_ERR_POS 4 +#define IRQ_SPORT3_ERR_POS 8 +#define IRQ_MXVR_DATA_POS 12 +#define IRQ_SPI1_ERR_POS 16 +#define IRQ_SPI2_ERR_POS 20 +#define IRQ_UART1_ERR_POS 24 +#define IRQ_UART2_ERR_POS 28 + +/* IAR4 BIT FILEDS */ +#define IRQ_CAN0_ERR_POS 0 +#define IRQ_SPORT2_RX_POS 4 +#define IRQ_SPORT2_TX_POS 8 +#define IRQ_SPORT3_RX_POS 12 +#define IRQ_SPORT3_TX_POS 16 +#define IRQ_EPPI1_POS 20 +#define IRQ_EPPI2_POS 24 +#define IRQ_SPI1_POS 28 + +/* IAR5 BIT FIELDS */ +#define IRQ_SPI2_POS 0 +#define IRQ_UART1_RX_POS 4 +#define IRQ_UART1_TX_POS 8 +#define IRQ_ATAPI_RX_POS 12 +#define IRQ_ATAPI_TX_POS 16 +#define IRQ_TWI0_POS 20 +#define IRQ_TWI1_POS 24 +#define IRQ_CAN0_RX_POS 28 + +/* IAR6 BIT FIELDS */ +#define IRQ_CAN0_TX_POS 0 +#define IRQ_MDMAS2_POS 4 +#define IRQ_MDMAS3_POS 8 +#define IRQ_MXVR_ERR_POS 12 +#define IRQ_MXVR_MSG_POS 16 +#define IRQ_MXVR_PKT_POS 20 +#define IRQ_EPPI1_ERR_POS 24 +#define IRQ_EPPI2_ERR_POS 28 + +/* IAR7 BIT FIELDS */ +#define IRQ_UART3_ERR_POS 0 +#define IRQ_HOST_ERR_POS 4 +#define IRQ_PIXC_ERR_POS 12 +#define IRQ_NFC_ERR_POS 16 +#define IRQ_ATAPI_ERR_POS 20 +#define IRQ_CAN1_ERR_POS 24 +#define IRQ_HS_DMA_ERR_POS 28 + +/* IAR8 BIT FIELDS */ +#define IRQ_PIXC_IN0_POS 0 +#define IRQ_PIXC_IN1_POS 4 +#define IRQ_PIXC_OUT_POS 8 +#define IRQ_SDH_POS 12 +#define IRQ_CNT_POS 16 +#define IRQ_KEY_POS 20 +#define IRQ_CAN1_RX_POS 24 +#define IRQ_CAN1_TX_POS 28 + +/* IAR9 BIT FIELDS */ +#define IRQ_SDH_MASK0_POS 0 +#define IRQ_SDH_MASK1_POS 4 +#define IRQ_USB_INT0_POS 12 +#define IRQ_USB_INT1_POS 16 +#define IRQ_USB_INT2_POS 20 +#define IRQ_USB_DMA_POS 24 +#define IRQ_OTPSEC_POS 28 + +/* IAR10 BIT FIELDS */ +#define IRQ_TIMER0_POS 24 +#define IRQ_TIMER1_POS 28 + +/* IAR11 BIT FIELDS */ +#define IRQ_TIMER2_POS 0 +#define IRQ_TIMER3_POS 4 +#define IRQ_TIMER4_POS 8 +#define IRQ_TIMER5_POS 12 +#define IRQ_TIMER6_POS 16 +#define IRQ_TIMER7_POS 20 +#define IRQ_PINT2_POS 24 +#define IRQ_PINT3_POS 28 + +#endif /* _BF548_IRQ_H_ */ diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h new file mode 100644 index 000000000000..0cb279e973d7 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/mem_init.h @@ -0,0 +1,189 @@ +/* + * File: include/asm-blackfin/mach-bf548/mem_init.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * Copyright 2004-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#if (CONFIG_MEM_MT46V32M16) + +#if defined CONFIG_CLKIN_HALF +#define CLKIN_HALF 1 +#else +#define CLKIN_HALF 0 +#endif + +#if defined CONFIG_PLL_BYPASS +#define PLL_BYPASS 1 +#else +#define PLL_BYPASS 0 +#endif + +/***************************************Currently Not Being Used *********************************/ +#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 +#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 +#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ)) +#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 +#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 + +#if (flash_EBIU_AMBCTL_TT > 3) +#define flash_EBIU_AMBCTL0_TT B0TT_4 +#endif +#if (flash_EBIU_AMBCTL_TT == 3) +#define flash_EBIU_AMBCTL0_TT B0TT_3 +#endif +#if (flash_EBIU_AMBCTL_TT == 2) +#define flash_EBIU_AMBCTL0_TT B0TT_2 +#endif +#if (flash_EBIU_AMBCTL_TT < 2) +#define flash_EBIU_AMBCTL0_TT B0TT_1 +#endif + +#if (flash_EBIU_AMBCTL_ST > 3) +#define flash_EBIU_AMBCTL0_ST B0ST_4 +#endif +#if (flash_EBIU_AMBCTL_ST == 3) +#define flash_EBIU_AMBCTL0_ST B0ST_3 +#endif +#if (flash_EBIU_AMBCTL_ST == 2) +#define flash_EBIU_AMBCTL0_ST B0ST_2 +#endif +#if (flash_EBIU_AMBCTL_ST < 2) +#define flash_EBIU_AMBCTL0_ST B0ST_1 +#endif + +#if (flash_EBIU_AMBCTL_HT > 2) +#define flash_EBIU_AMBCTL0_HT B0HT_3 +#endif +#if (flash_EBIU_AMBCTL_HT == 2) +#define flash_EBIU_AMBCTL0_HT B0HT_2 +#endif +#if (flash_EBIU_AMBCTL_HT == 1) +#define flash_EBIU_AMBCTL0_HT B0HT_1 +#endif +#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0) +#define flash_EBIU_AMBCTL0_HT B0HT_0 +#endif +#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0) +#define flash_EBIU_AMBCTL0_HT B0HT_1 +#endif + +#if (flash_EBIU_AMBCTL_WAT > 14) +#define flash_EBIU_AMBCTL0_WAT B0WAT_15 +#endif +#if (flash_EBIU_AMBCTL_WAT == 14) +#define flash_EBIU_AMBCTL0_WAT B0WAT_14 +#endif +#if (flash_EBIU_AMBCTL_WAT == 13) +#define flash_EBIU_AMBCTL0_WAT B0WAT_13 +#endif +#if (flash_EBIU_AMBCTL_WAT == 12) +#define flash_EBIU_AMBCTL0_WAT B0WAT_12 +#endif +#if (flash_EBIU_AMBCTL_WAT == 11) +#define flash_EBIU_AMBCTL0_WAT B0WAT_11 +#endif +#if (flash_EBIU_AMBCTL_WAT == 10) +#define flash_EBIU_AMBCTL0_WAT B0WAT_10 +#endif +#if (flash_EBIU_AMBCTL_WAT == 9) +#define flash_EBIU_AMBCTL0_WAT B0WAT_9 +#endif +#if (flash_EBIU_AMBCTL_WAT == 8) +#define flash_EBIU_AMBCTL0_WAT B0WAT_8 +#endif +#if (flash_EBIU_AMBCTL_WAT == 7) +#define flash_EBIU_AMBCTL0_WAT B0WAT_7 +#endif +#if (flash_EBIU_AMBCTL_WAT == 6) +#define flash_EBIU_AMBCTL0_WAT B0WAT_6 +#endif +#if (flash_EBIU_AMBCTL_WAT == 5) +#define flash_EBIU_AMBCTL0_WAT B0WAT_5 +#endif +#if (flash_EBIU_AMBCTL_WAT == 4) +#define flash_EBIU_AMBCTL0_WAT B0WAT_4 +#endif +#if (flash_EBIU_AMBCTL_WAT == 3) +#define flash_EBIU_AMBCTL0_WAT B0WAT_3 +#endif +#if (flash_EBIU_AMBCTL_WAT == 2) +#define flash_EBIU_AMBCTL0_WAT B0WAT_2 +#endif +#if (flash_EBIU_AMBCTL_WAT == 1) +#define flash_EBIU_AMBCTL0_WAT B0WAT_1 +#endif + +#if (flash_EBIU_AMBCTL_RAT > 14) +#define flash_EBIU_AMBCTL0_RAT B0RAT_15 +#endif +#if (flash_EBIU_AMBCTL_RAT == 14) +#define flash_EBIU_AMBCTL0_RAT B0RAT_14 +#endif +#if (flash_EBIU_AMBCTL_RAT == 13) +#define flash_EBIU_AMBCTL0_RAT B0RAT_13 +#endif +#if (flash_EBIU_AMBCTL_RAT == 12) +#define flash_EBIU_AMBCTL0_RAT B0RAT_12 +#endif +#if (flash_EBIU_AMBCTL_RAT == 11) +#define flash_EBIU_AMBCTL0_RAT B0RAT_11 +#endif +#if (flash_EBIU_AMBCTL_RAT == 10) +#define flash_EBIU_AMBCTL0_RAT B0RAT_10 +#endif +#if (flash_EBIU_AMBCTL_RAT == 9) +#define flash_EBIU_AMBCTL0_RAT B0RAT_9 +#endif +#if (flash_EBIU_AMBCTL_RAT == 8) +#define flash_EBIU_AMBCTL0_RAT B0RAT_8 +#endif +#if (flash_EBIU_AMBCTL_RAT == 7) +#define flash_EBIU_AMBCTL0_RAT B0RAT_7 +#endif +#if (flash_EBIU_AMBCTL_RAT == 6) +#define flash_EBIU_AMBCTL0_RAT B0RAT_6 +#endif +#if (flash_EBIU_AMBCTL_RAT == 5) +#define flash_EBIU_AMBCTL0_RAT B0RAT_5 +#endif +#if (flash_EBIU_AMBCTL_RAT == 4) +#define flash_EBIU_AMBCTL0_RAT B0RAT_4 +#endif +#if (flash_EBIU_AMBCTL_RAT == 3) +#define flash_EBIU_AMBCTL0_RAT B0RAT_3 +#endif +#if (flash_EBIU_AMBCTL_RAT == 2) +#define flash_EBIU_AMBCTL0_RAT B0RAT_2 +#endif +#if (flash_EBIU_AMBCTL_RAT == 1) +#define flash_EBIU_AMBCTL0_RAT B0RAT_1 +#endif + +#define flash_EBIU_AMBCTL0 \ + (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \ + flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN) diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h new file mode 100644 index 000000000000..72d80e8a6e81 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/mem_map.h @@ -0,0 +1,97 @@ +/* + * file: include/asm-blackfin/mach-bf548/mem_map.h + * based on: + * author: + * + * created: + * description: + * Memory MAP Common header file for blackfin BF537/6/4 of processors. + * rev: + * + * modified: + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + +#ifndef _MEM_MAP_548_H_ +#define _MEM_MAP_548_H_ + +#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ +#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ + +/* Async Memory Banks */ +#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ +#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */ +#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */ +#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */ +#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */ +#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */ +#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ +#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */ + +/* Boot ROM Memory */ + +#define BOOT_ROM_START 0xEF000000 + +/* Level 1 Memory */ + +/* Memory Map for ADSP-BF548 processors */ +#ifdef CONFIG_BLKFIN_ICACHE +#define BLKFIN_ICACHESIZE (16*1024) +#else +#define BLKFIN_ICACHESIZE (0*1024) +#endif + +#define L1_CODE_START 0xFFA00000 +#define L1_DATA_A_START 0xFF800000 +#define L1_DATA_B_START 0xFF900000 + +#define L1_CODE_LENGTH 0xC000 + +#ifdef CONFIG_BLKFIN_DCACHE + +#ifdef CONFIG_BLKFIN_DCACHE_BANKA +#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) +#define L1_DATA_A_LENGTH (0x8000 - 0x4000) +#define L1_DATA_B_LENGTH 0x8000 +#define BLKFIN_DCACHESIZE (16*1024) +#define BLKFIN_DSUPBANKS 1 +#else +#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) +#define L1_DATA_A_LENGTH (0x8000 - 0x4000) +#define L1_DATA_B_LENGTH (0x8000 - 0x4000) +#define BLKFIN_DCACHESIZE (32*1024) +#define BLKFIN_DSUPBANKS 2 +#endif + +#else +#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) +#define L1_DATA_A_LENGTH 0x8000 +#define L1_DATA_B_LENGTH 0x8000 +#define BLKFIN_DCACHESIZE (0*1024) +#define BLKFIN_DSUPBANKS 0 +#endif /*CONFIG_BLKFIN_DCACHE*/ + +/* Scratch Pad Memory */ + +#if defined(CONFIG_BF54x) +#define L1_SCRATCH_START 0xFFB00000 +#define L1_SCRATCH_LENGTH 0x1000 +#endif + +#endif/* _MEM_MAP_548_H_ */ diff --git a/include/asm-blackfin/mach-bf548/portmux.h b/include/asm-blackfin/mach-bf548/portmux.h new file mode 100644 index 000000000000..b382deb501a7 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/portmux.h @@ -0,0 +1,270 @@ +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0)) +#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0)) +#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0)) +#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0)) +#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0)) +#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0)) +#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0)) +#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0)) +#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0)) +#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0)) +#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0)) +#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0)) +#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0)) +#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0)) +#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0)) +#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0)) +#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1)) +#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1)) +#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1)) +#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1)) + +#define P_TWI1_SCL (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0)) +#define P_TWI1_SDA (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0)) +#define P_UART3_RTS (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0)) +#define P_UART3_CTS (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0)) +#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0)) +#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0)) +#define P_UART3_TX (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0)) +#define P_UART3_RX (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0)) +#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0)) +#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0)) +#define P_SPI2_SSEL2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0)) +#define P_SPI2_SSEL3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0)) +#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0)) +#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0)) +#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0)) +#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1)) +#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1)) +#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1)) +#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1)) + +#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0)) +#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0)) +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0)) +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0)) +#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0)) +#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0)) +#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0)) +#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0)) +#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0)) +#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0)) +#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0)) +#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0)) +#define P_SD_CLK (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0)) +#define P_SD_CMD (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0)) +#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1)) +#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1)) + +#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0)) +#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0)) +#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0)) +#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0)) +#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0)) +#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0)) +#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0)) +#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0)) +#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0)) +#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0)) +#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0)) +#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0)) +#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0)) +#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0)) +#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0)) +#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0)) + +#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1)) +#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1)) +#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1)) +#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1)) +#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1)) +#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1)) +#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1)) +#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1)) +#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1)) +#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1)) +#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1)) +#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1)) +#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1)) +#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1)) +#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1)) +#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1)) +#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2)) +#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2)) +#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2)) +#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2)) +#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2)) +#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2)) +#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2)) +#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2)) +#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2)) +#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2)) +#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2)) +#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2)) +#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2)) +#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2)) +#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2)) +#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2)) +#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3)) +#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3)) +#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3)) +#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3)) +#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3)) +#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3)) +#define P_KEY_ROW0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3)) +#define P_KEY_ROW1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3)) +#define P_KEY_ROW2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3)) +#define P_KEY_ROW3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3)) +#define P_KEY_COL0 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3)) +#define P_KEY_COL1 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3)) +#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3)) +#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3)) + +#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0)) +#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0)) +#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0)) +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0)) +#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0)) +#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0)) +#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0)) +#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0)) +#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0)) +#define P_TWI0_SCL (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0)) +#define P_TWI0_SDA (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0)) +#define P_KEY_COL7 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1)) +#define P_KEY_ROW6 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1)) +#define P_KEY_COL6 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1)) +#define P_KEY_ROW5 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1)) +#define P_KEY_COL5 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1)) +#define P_KEY_ROW4 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1)) +#define P_KEY_COL4 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1)) +#define P_KEY_ROW7 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1)) + +#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) +#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) +#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) +#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0)) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) +#define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) +#define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) +#define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) +#define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) +#define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) +#define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) +#define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) +#define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) +#define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) +#define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) +#define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1)) +#define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1)) +#define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1)) +#define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1)) +#define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) +#define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) + +#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) +#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) +#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0)) +#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0)) +#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0)) +#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) +#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) +#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) +#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) +#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) +#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) +#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) +#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) +#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) +#define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) +#define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) +#define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1)) +#define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1)) +#define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1)) +#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1)) +#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1)) +#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1)) +#define P_MTXONB (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) +#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2)) +#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2)) +#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2)) +#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3)) + +#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0)) +#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0)) +#define P_ATAPI_RESET (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0)) +#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0)) +#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0)) +#define P_MTX (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0)) +#define P_MRX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0)) +#define P_MRXONB (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0)) +#define P_A4 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0)) +#define P_A5 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0)) +#define P_A6 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0)) +#define P_A7 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0)) +#define P_A8 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0)) +#define P_A9 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0)) +#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1)) +#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1)) +#define P_TMR8 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1)) +#define P_TMR9 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1)) +#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1)) +#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1)) +#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1)) +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2)) +#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2)) +#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2)) + +#define P_A10 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0)) +#define P_A11 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0)) +#define P_A12 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0)) +#define P_A13 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0)) +#define P_A14 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0)) +#define P_A15 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0)) +#define P_A16 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0)) +#define P_A17 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0)) +#define P_A18 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0)) +#define P_A19 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0)) +#define P_A20 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0)) +#define P_A21 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0)) +#define P_A22 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0)) +#define P_A23 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0)) +#define P_A24 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0)) +#define P_A25 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0)) +#define P_NOR_CLK (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1)) + +#define P_AMC_ARDY_NOR_WAIT (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0)) +#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0)) +#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0)) +#define P_ATAPI_DIOR (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0)) +#define P_ATAPI_DIOW (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0)) +#define P_ATAPI_CS0 (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0)) +#define P_ATAPI_CS1 (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0)) +#define P_ATAPI_DMACK (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0)) +#define P_ATAPI_DMARQ (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0)) +#define P_ATAPI_INTRQ (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0)) +#define P_ATAPI_IORDY (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0)) +#define P_AMC_BR (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0)) +#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0)) +#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0)) + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h index b14f872e5703..1a8ec9e46922 100644 --- a/include/asm-blackfin/mach-bf561/cdefBF561.h +++ b/include/asm-blackfin/mach-bf561/cdefBF561.h @@ -57,12 +57,14 @@ /* Writing to VR_CTL initiates a PLL relock sequence. */ static __inline__ void bfin_write_VR_CTL(unsigned int val) { - unsigned long flags, iwr; + unsigned long flags, iwr0, iwr1; /* Enable the PLL Wakeup bit in SIC IWR */ - iwr = bfin_read32(SICA_IWR0); + iwr0 = bfin_read32(SICA_IWR0); + iwr1 = bfin_read32(SICA_IWR1); /* Only allow PPL Wakeup) */ bfin_write32(SICA_IWR0, IWR_ENABLE(0)); + bfin_write32(SICA_IWR1, 0); bfin_write16(VR_CTL, val); __builtin_bfin_ssync(); @@ -70,7 +72,8 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) local_irq_save(flags); asm("IDLE;"); local_irq_restore(flags); - bfin_write32(SICA_IWR0, iwr); + bfin_write32(SICA_IWR0, iwr0); + bfin_write32(SICA_IWR1, iwr1); } #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) diff --git a/include/asm-blackfin/mach-bf561/dma.h b/include/asm-blackfin/mach-bf561/dma.h index 21d982003e75..766334b7d8ab 100644 --- a/include/asm-blackfin/mach-bf561/dma.h +++ b/include/asm-blackfin/mach-bf561/dma.h @@ -32,4 +32,7 @@ #define CH_IMEM_STREAM1_SRC 34 #define CH_IMEM_STREAM1_DEST 35 +extern int channel2irq(unsigned int channel); +extern struct dma_register *base_addr[]; + #endif diff --git a/include/asm-blackfin/mach-bf561/portmux.h b/include/asm-blackfin/mach-bf561/portmux.h new file mode 100644 index 000000000000..10d11d5ffe23 --- /dev/null +++ b/include/asm-blackfin/mach-bf561/portmux.h @@ -0,0 +1,87 @@ +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define P_PPI0_CLK (P_DONTCARE) +#define P_PPI0_FS1 (P_DONTCARE) +#define P_PPI0_FS2 (P_DONTCARE) +#define P_PPI0_FS3 (P_DONTCARE) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40)) +#define P_PPI0_D0 (P_DONTCARE) +#define P_PPI0_D1 (P_DONTCARE) +#define P_PPI0_D2 (P_DONTCARE) +#define P_PPI0_D3 (P_DONTCARE) +#define P_PPI0_D4 (P_DONTCARE) +#define P_PPI0_D5 (P_DONTCARE) +#define P_PPI0_D6 (P_DONTCARE) +#define P_PPI0_D7 (P_DONTCARE) +#define P_PPI1_CLK (P_DONTCARE) +#define P_PPI1_FS1 (P_DONTCARE) +#define P_PPI1_FS2 (P_DONTCARE) +#define P_PPI1_FS3 (P_DONTCARE) +#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39)) +#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38)) +#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37)) +#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36)) +#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35)) +#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34)) +#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33)) +#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32)) +#define P_PPI1_D0 (P_DONTCARE) +#define P_PPI1_D1 (P_DONTCARE) +#define P_PPI1_D2 (P_DONTCARE) +#define P_PPI1_D3 (P_DONTCARE) +#define P_PPI1_D4 (P_DONTCARE) +#define P_PPI1_D5 (P_DONTCARE) +#define P_PPI1_D6 (P_DONTCARE) +#define P_PPI1_D7 (P_DONTCARE) +#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31)) +#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30)) +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29)) +#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27)) +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26)) +#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25)) +#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24)) +#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23)) +#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22)) +#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21)) +#define P_SPORT1_DRPRI (P_DONTCARE) +#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20)) +#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19)) +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18)) +#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17)) +#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16)) +#define P_SPORT0_DRPRI (P_DONTCARE) +#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15)) +#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) +#define P_TMR11 (P_DONTCARE) +#define P_TMR10 (P_DONTCARE) +#define P_TMR9 (P_DONTCARE) +#define P_TMR8 (P_DONTCARE) +#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2)) +#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1)) +#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0)) +#define P_SPI0_MOSI (P_DONTCARE) +#define P_SPI0_MIS0 (P_DONTCARE) +#define P_SPI0_SCK (P_DONTCARE) + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h index 58f878947cbc..94ed381e5606 100644 --- a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h +++ b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h @@ -40,16 +40,7 @@ #define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val) #define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) #ifdef ANOMALY_05000125 -static __inline__ void bfin_write_DMEM_CONTROL(unsigned int val) -{ - unsigned long flags, iwr; - - local_irq_save(flags); - __asm__(".align 8\n"); - bfin_write32(IMEM_CONTROL, val); - __builtin_bfin_ssync(); - local_irq_restore(flags); -} +extern void bfin_write_DMEM_CONTROL(unsigned int val); #else #define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val) #endif @@ -139,17 +130,7 @@ static __inline__ void bfin_write_DMEM_CONTROL(unsigned int val) */ #define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) #ifdef ANOMALY_05000125 -static __inline__ void bfin_write_IMEM_CONTROL(unsigned int val) -{ - unsigned long flags, iwr; - - local_irq_save(flags); - __asm__(".align 8\n"); - bfin_write32(IMEM_CONTROL, val); - __builtin_bfin_ssync(); - local_irq_restore(flags); - -} +extern void bfin_write_IMEM_CONTROL(unsigned int val); #else #define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val) #endif diff --git a/include/asm-blackfin/mman.h b/include/asm-blackfin/mman.h index 4d504f908c0c..b58f5ad3f024 100644 --- a/include/asm-blackfin/mman.h +++ b/include/asm-blackfin/mman.h @@ -22,8 +22,6 @@ #define MAP_NORESERVE 0x4000 /* don't check for reservations */ #define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ #define MAP_NONBLOCK 0x10000 /* do not block on IO */ -#define MAP_UNINITIALIZE 0x4000000 /* For anonymous mmap, memory could - be uninitialized. */ #define MS_ASYNC 1 /* sync memory asynchronously */ #define MS_INVALIDATE 2 /* invalidate the caches */ diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h index ffad947f1b2a..8bc86717021c 100644 --- a/include/asm-blackfin/page.h +++ b/include/asm-blackfin/page.h @@ -4,7 +4,11 @@ /* PAGE_SHIFT determines the page size */ #define PAGE_SHIFT 12 +#ifdef __ASSEMBLY__ +#define PAGE_SIZE (1 << PAGE_SHIFT) +#else #define PAGE_SIZE (1UL << PAGE_SHIFT) +#endif #define PAGE_MASK (~(PAGE_SIZE-1)) #ifdef __KERNEL__ diff --git a/include/asm-blackfin/portmux.h b/include/asm-blackfin/portmux.h new file mode 100644 index 000000000000..9d3681e42111 --- /dev/null +++ b/include/asm-blackfin/portmux.h @@ -0,0 +1,1133 @@ +/* + * Common header file for blackfin family of processors. + * + */ + +#ifndef _PORTMUX_H_ +#define _PORTMUX_H_ + +#define P_IDENT(x) ((x) & 0x1FF) +#define P_FUNCT(x) (((x) & 0x3) << 9) +#define P_FUNCT2MUX(x) (((x) >> 9) & 0x3) +#define P_DEFINED 0x8000 +#define P_UNDEF 0x4000 +#define P_MAYSHARE 0x2000 +#define P_DONTCARE 0x1000 + +#include <asm/gpio.h> +#include <asm/mach/portmux.h> + +#ifndef P_SPORT2_TFS +#define P_SPORT2_TFS P_UNDEF +#endif + +#ifndef P_SPORT2_DTSEC +#define P_SPORT2_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT2_DTPRI +#define P_SPORT2_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT2_TSCLK +#define P_SPORT2_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT2_RFS +#define P_SPORT2_RFS P_UNDEF +#endif + +#ifndef P_SPORT2_DRSEC +#define P_SPORT2_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT2_DRPRI +#define P_SPORT2_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT2_RSCLK +#define P_SPORT2_RSCLK P_UNDEF +#endif + +#ifndef P_SPORT3_TFS +#define P_SPORT3_TFS P_UNDEF +#endif + +#ifndef P_SPORT3_DTSEC +#define P_SPORT3_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT3_DTPRI +#define P_SPORT3_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT3_TSCLK +#define P_SPORT3_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT3_RFS +#define P_SPORT3_RFS P_UNDEF +#endif + +#ifndef P_SPORT3_DRSEC +#define P_SPORT3_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT3_DRPRI +#define P_SPORT3_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT3_RSCLK +#define P_SPORT3_RSCLK P_UNDEF +#endif + +#ifndef P_TMR4 +#define P_TMR4 P_UNDEF +#endif + +#ifndef P_TMR5 +#define P_TMR5 P_UNDEF +#endif + +#ifndef P_TMR6 +#define P_TMR6 P_UNDEF +#endif + +#ifndef P_TMR7 +#define P_TMR7 P_UNDEF +#endif + +#ifndef P_TWI1_SCL +#define P_TWI1_SCL P_UNDEF +#endif + +#ifndef P_TWI1_SDA +#define P_TWI1_SDA P_UNDEF +#endif + +#ifndef P_UART3_RTS +#define P_UART3_RTS P_UNDEF +#endif + +#ifndef P_UART3_CTS +#define P_UART3_CTS P_UNDEF +#endif + +#ifndef P_UART2_TX +#define P_UART2_TX P_UNDEF +#endif + +#ifndef P_UART2_RX +#define P_UART2_RX P_UNDEF +#endif + +#ifndef P_UART3_TX +#define P_UART3_TX P_UNDEF +#endif + +#ifndef P_UART3_RX +#define P_UART3_RX P_UNDEF +#endif + +#ifndef P_SPI2_SS +#define P_SPI2_SS P_UNDEF +#endif + +#ifndef P_SPI2_SSEL1 +#define P_SPI2_SSEL1 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL2 +#define P_SPI2_SSEL2 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL3 +#define P_SPI2_SSEL3 P_UNDEF +#endif + +#ifndef P_SPI2_SCK +#define P_SPI2_SCK P_UNDEF +#endif + +#ifndef P_SPI2_MOSI +#define P_SPI2_MOSI P_UNDEF +#endif + +#ifndef P_SPI2_MISO +#define P_SPI2_MISO P_UNDEF +#endif + +#ifndef P_TMR0 +#define P_TMR0 P_UNDEF +#endif + +#ifndef P_TMR1 +#define P_TMR1 P_UNDEF +#endif + +#ifndef P_TMR2 +#define P_TMR2 P_UNDEF +#endif + +#ifndef P_TMR3 +#define P_TMR3 P_UNDEF +#endif + +#ifndef P_SPORT0_TFS +#define P_SPORT0_TFS P_UNDEF +#endif + +#ifndef P_SPORT0_DTSEC +#define P_SPORT0_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT0_DTPRI +#define P_SPORT0_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT0_TSCLK +#define P_SPORT0_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT0_RFS +#define P_SPORT0_RFS P_UNDEF +#endif + +#ifndef P_SPORT0_DRSEC +#define P_SPORT0_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT0_DRPRI +#define P_SPORT0_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT0_RSCLK +#define P_SPORT0_RSCLK P_UNDEF +#endif + +#ifndef P_SD_D0 +#define P_SD_D0 P_UNDEF +#endif + +#ifndef P_SD_D1 +#define P_SD_D1 P_UNDEF +#endif + +#ifndef P_SD_D2 +#define P_SD_D2 P_UNDEF +#endif + +#ifndef P_SD_D3 +#define P_SD_D3 P_UNDEF +#endif + +#ifndef P_SD_CLK +#define P_SD_CLK P_UNDEF +#endif + +#ifndef P_SD_CMD +#define P_SD_CMD P_UNDEF +#endif + +#ifndef P_MMCLK +#define P_MMCLK P_UNDEF +#endif + +#ifndef P_MBCLK +#define P_MBCLK P_UNDEF +#endif + +#ifndef P_PPI1_D0 +#define P_PPI1_D0 P_UNDEF +#endif + +#ifndef P_PPI1_D1 +#define P_PPI1_D1 P_UNDEF +#endif + +#ifndef P_PPI1_D2 +#define P_PPI1_D2 P_UNDEF +#endif + +#ifndef P_PPI1_D3 +#define P_PPI1_D3 P_UNDEF +#endif + +#ifndef P_PPI1_D4 +#define P_PPI1_D4 P_UNDEF +#endif + +#ifndef P_PPI1_D5 +#define P_PPI1_D5 P_UNDEF +#endif + +#ifndef P_PPI1_D6 +#define P_PPI1_D6 P_UNDEF +#endif + +#ifndef P_PPI1_D7 +#define P_PPI1_D7 P_UNDEF +#endif + +#ifndef P_PPI1_D8 +#define P_PPI1_D8 P_UNDEF +#endif + +#ifndef P_PPI1_D9 +#define P_PPI1_D9 P_UNDEF +#endif + +#ifndef P_PPI1_D10 +#define P_PPI1_D10 P_UNDEF +#endif + +#ifndef P_PPI1_D11 +#define P_PPI1_D11 P_UNDEF +#endif + +#ifndef P_PPI1_D12 +#define P_PPI1_D12 P_UNDEF +#endif + +#ifndef P_PPI1_D13 +#define P_PPI1_D13 P_UNDEF +#endif + +#ifndef P_PPI1_D14 +#define P_PPI1_D14 P_UNDEF +#endif + +#ifndef P_PPI1_D15 +#define P_PPI1_D15 P_UNDEF +#endif + +#ifndef P_HOST_D8 +#define P_HOST_D8 P_UNDEF +#endif + +#ifndef P_HOST_D9 +#define P_HOST_D9 P_UNDEF +#endif + +#ifndef P_HOST_D10 +#define P_HOST_D10 P_UNDEF +#endif + +#ifndef P_HOST_D11 +#define P_HOST_D11 P_UNDEF +#endif + +#ifndef P_HOST_D12 +#define P_HOST_D12 P_UNDEF +#endif + +#ifndef P_HOST_D13 +#define P_HOST_D13 P_UNDEF +#endif + +#ifndef P_HOST_D14 +#define P_HOST_D14 P_UNDEF +#endif + +#ifndef P_HOST_D15 +#define P_HOST_D15 P_UNDEF +#endif + +#ifndef P_HOST_D0 +#define P_HOST_D0 P_UNDEF +#endif + +#ifndef P_HOST_D1 +#define P_HOST_D1 P_UNDEF +#endif + +#ifndef P_HOST_D2 +#define P_HOST_D2 P_UNDEF +#endif + +#ifndef P_HOST_D3 +#define P_HOST_D3 P_UNDEF +#endif + +#ifndef P_HOST_D4 +#define P_HOST_D4 P_UNDEF +#endif + +#ifndef P_HOST_D5 +#define P_HOST_D5 P_UNDEF +#endif + +#ifndef P_HOST_D6 +#define P_HOST_D6 P_UNDEF +#endif + +#ifndef P_HOST_D7 +#define P_HOST_D7 P_UNDEF +#endif + +#ifndef P_SPORT1_TFS +#define P_SPORT1_TFS P_UNDEF +#endif + +#ifndef P_SPORT1_DTSEC +#define P_SPORT1_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT1_DTPRI +#define P_SPORT1_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT1_TSCLK +#define P_SPORT1_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT1_RFS +#define P_SPORT1_RFS P_UNDEF +#endif + +#ifndef P_SPORT1_DRSEC +#define P_SPORT1_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT1_DRPRI +#define P_SPORT1_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT1_RSCLK +#define P_SPORT1_RSCLK P_UNDEF +#endif + +#ifndef P_PPI2_D0 +#define P_PPI2_D0 P_UNDEF +#endif + +#ifndef P_PPI2_D1 +#define P_PPI2_D1 P_UNDEF +#endif + +#ifndef P_PPI2_D2 +#define P_PPI2_D2 P_UNDEF +#endif + +#ifndef P_PPI2_D3 +#define P_PPI2_D3 P_UNDEF +#endif + +#ifndef P_PPI2_D4 +#define P_PPI2_D4 P_UNDEF +#endif + +#ifndef P_PPI2_D5 +#define P_PPI2_D5 P_UNDEF +#endif + +#ifndef P_PPI2_D6 +#define P_PPI2_D6 P_UNDEF +#endif + +#ifndef P_PPI2_D7 +#define P_PPI2_D7 P_UNDEF +#endif + +#ifndef P_PPI0_D18 +#define P_PPI0_D18 P_UNDEF +#endif + +#ifndef P_PPI0_D19 +#define P_PPI0_D19 P_UNDEF +#endif + +#ifndef P_PPI0_D20 +#define P_PPI0_D20 P_UNDEF +#endif + +#ifndef P_PPI0_D21 +#define P_PPI0_D21 P_UNDEF +#endif + +#ifndef P_PPI0_D22 +#define P_PPI0_D22 P_UNDEF +#endif + +#ifndef P_PPI0_D23 +#define P_PPI0_D23 P_UNDEF +#endif + +#ifndef P_KEY_ROW0 +#define P_KEY_ROW0 P_UNDEF +#endif + +#ifndef P_KEY_ROW1 +#define P_KEY_ROW1 P_UNDEF +#endif + +#ifndef P_KEY_ROW2 +#define P_KEY_ROW2 P_UNDEF +#endif + +#ifndef P_KEY_ROW3 +#define P_KEY_ROW3 P_UNDEF +#endif + +#ifndef P_KEY_COL0 +#define P_KEY_COL0 P_UNDEF +#endif + +#ifndef P_KEY_COL1 +#define P_KEY_COL1 P_UNDEF +#endif + +#ifndef P_KEY_COL2 +#define P_KEY_COL2 P_UNDEF +#endif + +#ifndef P_KEY_COL3 +#define P_KEY_COL3 P_UNDEF +#endif + +#ifndef P_SPI0_SCK +#define P_SPI0_SCK P_UNDEF +#endif + +#ifndef P_SPI0_MISO +#define P_SPI0_MISO P_UNDEF +#endif + +#ifndef P_SPI0_MOSI +#define P_SPI0_MOSI P_UNDEF +#endif + +#ifndef P_SPI0_SS +#define P_SPI0_SS P_UNDEF +#endif + +#ifndef P_SPI0_SSEL1 +#define P_SPI0_SSEL1 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL2 +#define P_SPI0_SSEL2 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL3 +#define P_SPI0_SSEL3 P_UNDEF +#endif + +#ifndef P_UART0_TX +#define P_UART0_TX P_UNDEF +#endif + +#ifndef P_UART0_RX +#define P_UART0_RX P_UNDEF +#endif + +#ifndef P_UART1_RTS +#define P_UART1_RTS P_UNDEF +#endif + +#ifndef P_UART1_CTS +#define P_UART1_CTS P_UNDEF +#endif + +#ifndef P_PPI1_CLK +#define P_PPI1_CLK P_UNDEF +#endif + +#ifndef P_PPI1_FS1 +#define P_PPI1_FS1 P_UNDEF +#endif + +#ifndef P_PPI1_FS2 +#define P_PPI1_FS2 P_UNDEF +#endif + +#ifndef P_TWI0_SCL +#define P_TWI0_SCL P_UNDEF +#endif + +#ifndef P_TWI0_SDA +#define P_TWI0_SDA P_UNDEF +#endif + +#ifndef P_KEY_COL7 +#define P_KEY_COL7 P_UNDEF +#endif + +#ifndef P_KEY_ROW6 +#define P_KEY_ROW6 P_UNDEF +#endif + +#ifndef P_KEY_COL6 +#define P_KEY_COL6 P_UNDEF +#endif + +#ifndef P_KEY_ROW5 +#define P_KEY_ROW5 P_UNDEF +#endif + +#ifndef P_KEY_COL5 +#define P_KEY_COL5 P_UNDEF +#endif + +#ifndef P_KEY_ROW4 +#define P_KEY_ROW4 P_UNDEF +#endif + +#ifndef P_KEY_COL4 +#define P_KEY_COL4 P_UNDEF +#endif + +#ifndef P_KEY_ROW7 +#define P_KEY_ROW7 P_UNDEF +#endif + +#ifndef P_PPI0_D0 +#define P_PPI0_D0 P_UNDEF +#endif + +#ifndef P_PPI0_D1 +#define P_PPI0_D1 P_UNDEF +#endif + +#ifndef P_PPI0_D2 +#define P_PPI0_D2 P_UNDEF +#endif + +#ifndef P_PPI0_D3 +#define P_PPI0_D3 P_UNDEF +#endif + +#ifndef P_PPI0_D4 +#define P_PPI0_D4 P_UNDEF +#endif + +#ifndef P_PPI0_D5 +#define P_PPI0_D5 P_UNDEF +#endif + +#ifndef P_PPI0_D6 +#define P_PPI0_D6 P_UNDEF +#endif + +#ifndef P_PPI0_D7 +#define P_PPI0_D7 P_UNDEF +#endif + +#ifndef P_PPI0_D8 +#define P_PPI0_D8 P_UNDEF +#endif + +#ifndef P_PPI0_D9 +#define P_PPI0_D9 P_UNDEF +#endif + +#ifndef P_PPI0_D10 +#define P_PPI0_D10 P_UNDEF +#endif + +#ifndef P_PPI0_D11 +#define P_PPI0_D11 P_UNDEF +#endif + +#ifndef P_PPI0_D12 +#define P_PPI0_D12 P_UNDEF +#endif + +#ifndef P_PPI0_D13 +#define P_PPI0_D13 P_UNDEF +#endif + +#ifndef P_PPI0_D14 +#define P_PPI0_D14 P_UNDEF +#endif + +#ifndef P_PPI0_D15 +#define P_PPI0_D15 P_UNDEF +#endif + +#ifndef P_ATAPI_D0A +#define P_ATAPI_D0A P_UNDEF +#endif + +#ifndef P_ATAPI_D1A +#define P_ATAPI_D1A P_UNDEF +#endif + +#ifndef P_ATAPI_D2A +#define P_ATAPI_D2A P_UNDEF +#endif + +#ifndef P_ATAPI_D3A +#define P_ATAPI_D3A P_UNDEF +#endif + +#ifndef P_ATAPI_D4A +#define P_ATAPI_D4A P_UNDEF +#endif + +#ifndef P_ATAPI_D5A +#define P_ATAPI_D5A P_UNDEF +#endif + +#ifndef P_ATAPI_D6A +#define P_ATAPI_D6A P_UNDEF +#endif + +#ifndef P_ATAPI_D7A +#define P_ATAPI_D7A P_UNDEF +#endif + +#ifndef P_ATAPI_D8A +#define P_ATAPI_D8A P_UNDEF +#endif + +#ifndef P_ATAPI_D9A +#define P_ATAPI_D9A P_UNDEF +#endif + +#ifndef P_ATAPI_D10A +#define P_ATAPI_D10A P_UNDEF +#endif + +#ifndef P_ATAPI_D11A +#define P_ATAPI_D11A P_UNDEF +#endif + +#ifndef P_ATAPI_D12A +#define P_ATAPI_D12A P_UNDEF +#endif + +#ifndef P_ATAPI_D13A +#define P_ATAPI_D13A P_UNDEF +#endif + +#ifndef P_ATAPI_D14A +#define P_ATAPI_D14A P_UNDEF +#endif + +#ifndef P_ATAPI_D15A +#define P_ATAPI_D15A P_UNDEF +#endif + +#ifndef P_PPI0_CLK +#define P_PPI0_CLK P_UNDEF +#endif + +#ifndef P_PPI0_FS1 +#define P_PPI0_FS1 P_UNDEF +#endif + +#ifndef P_PPI0_FS2 +#define P_PPI0_FS2 P_UNDEF +#endif + +#ifndef P_PPI0_D16 +#define P_PPI0_D16 P_UNDEF +#endif + +#ifndef P_PPI0_D17 +#define P_PPI0_D17 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL1 +#define P_SPI1_SSEL1 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL2 +#define P_SPI1_SSEL2 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL3 +#define P_SPI1_SSEL3 P_UNDEF +#endif + +#ifndef P_SPI1_SCK +#define P_SPI1_SCK P_UNDEF +#endif + +#ifndef P_SPI1_MISO +#define P_SPI1_MISO P_UNDEF +#endif + +#ifndef P_SPI1_MOSI +#define P_SPI1_MOSI P_UNDEF +#endif + +#ifndef P_SPI1_SS +#define P_SPI1_SS P_UNDEF +#endif + +#ifndef P_CAN0_TX +#define P_CAN0_TX P_UNDEF +#endif + +#ifndef P_CAN0_RX +#define P_CAN0_RX P_UNDEF +#endif + +#ifndef P_CAN1_TX +#define P_CAN1_TX P_UNDEF +#endif + +#ifndef P_CAN1_RX +#define P_CAN1_RX P_UNDEF +#endif + +#ifndef P_ATAPI_A0A +#define P_ATAPI_A0A P_UNDEF +#endif + +#ifndef P_ATAPI_A1A +#define P_ATAPI_A1A P_UNDEF +#endif + +#ifndef P_ATAPI_A2A +#define P_ATAPI_A2A P_UNDEF +#endif + +#ifndef P_HOST_CE +#define P_HOST_CE P_UNDEF +#endif + +#ifndef P_HOST_RD +#define P_HOST_RD P_UNDEF +#endif + +#ifndef P_HOST_WR +#define P_HOST_WR P_UNDEF +#endif + +#ifndef P_MTXONB +#define P_MTXONB P_UNDEF +#endif + +#ifndef P_PPI2_FS2 +#define P_PPI2_FS2 P_UNDEF +#endif + +#ifndef P_PPI2_FS1 +#define P_PPI2_FS1 P_UNDEF +#endif + +#ifndef P_PPI2_CLK +#define P_PPI2_CLK P_UNDEF +#endif + +#ifndef P_CNT_CZM +#define P_CNT_CZM P_UNDEF +#endif + +#ifndef P_UART1_TX +#define P_UART1_TX P_UNDEF +#endif + +#ifndef P_UART1_RX +#define P_UART1_RX P_UNDEF +#endif + +#ifndef P_ATAPI_RESET +#define P_ATAPI_RESET P_UNDEF +#endif + +#ifndef P_HOST_ADDR +#define P_HOST_ADDR P_UNDEF +#endif + +#ifndef P_HOST_ACK +#define P_HOST_ACK P_UNDEF +#endif + +#ifndef P_MTX +#define P_MTX P_UNDEF +#endif + +#ifndef P_MRX +#define P_MRX P_UNDEF +#endif + +#ifndef P_MRXONB +#define P_MRXONB P_UNDEF +#endif + +#ifndef P_A4 +#define P_A4 P_UNDEF +#endif + +#ifndef P_A5 +#define P_A5 P_UNDEF +#endif + +#ifndef P_A6 +#define P_A6 P_UNDEF +#endif + +#ifndef P_A7 +#define P_A7 P_UNDEF +#endif + +#ifndef P_A8 +#define P_A8 P_UNDEF +#endif + +#ifndef P_A9 +#define P_A9 P_UNDEF +#endif + +#ifndef P_PPI1_FS3 +#define P_PPI1_FS3 P_UNDEF +#endif + +#ifndef P_PPI2_FS3 +#define P_PPI2_FS3 P_UNDEF +#endif + +#ifndef P_TMR8 +#define P_TMR8 P_UNDEF +#endif + +#ifndef P_TMR9 +#define P_TMR9 P_UNDEF +#endif + +#ifndef P_TMR10 +#define P_TMR10 P_UNDEF +#endif +#ifndef P_TMR11 +#define P_TMR11 P_UNDEF +#endif + +#ifndef P_DMAR0 +#define P_DMAR0 P_UNDEF +#endif + +#ifndef P_DMAR1 +#define P_DMAR1 P_UNDEF +#endif + +#ifndef P_PPI0_FS3 +#define P_PPI0_FS3 P_UNDEF +#endif + +#ifndef P_CNT_CDG +#define P_CNT_CDG P_UNDEF +#endif + +#ifndef P_CNT_CUD +#define P_CNT_CUD P_UNDEF +#endif + +#ifndef P_A10 +#define P_A10 P_UNDEF +#endif + +#ifndef P_A11 +#define P_A11 P_UNDEF +#endif + +#ifndef P_A12 +#define P_A12 P_UNDEF +#endif + +#ifndef P_A13 +#define P_A13 P_UNDEF +#endif + +#ifndef P_A14 +#define P_A14 P_UNDEF +#endif + +#ifndef P_A15 +#define P_A15 P_UNDEF +#endif + +#ifndef P_A16 +#define P_A16 P_UNDEF +#endif + +#ifndef P_A17 +#define P_A17 P_UNDEF +#endif + +#ifndef P_A18 +#define P_A18 P_UNDEF +#endif + +#ifndef P_A19 +#define P_A19 P_UNDEF +#endif + +#ifndef P_A20 +#define P_A20 P_UNDEF +#endif + +#ifndef P_A21 +#define P_A21 P_UNDEF +#endif + +#ifndef P_A22 +#define P_A22 P_UNDEF +#endif + +#ifndef P_A23 +#define P_A23 P_UNDEF +#endif + +#ifndef P_A24 +#define P_A24 P_UNDEF +#endif + +#ifndef P_A25 +#define P_A25 P_UNDEF +#endif + +#ifndef P_NOR_CLK +#define P_NOR_CLK P_UNDEF +#endif + +#ifndef P_TMRCLK +#define P_TMRCLK P_UNDEF +#endif + +#ifndef P_AMC_ARDY_NOR_WAIT +#define P_AMC_ARDY_NOR_WAIT P_UNDEF +#endif + +#ifndef P_NAND_CE +#define P_NAND_CE P_UNDEF +#endif + +#ifndef P_NAND_RB +#define P_NAND_RB P_UNDEF +#endif + +#ifndef P_ATAPI_DIOR +#define P_ATAPI_DIOR P_UNDEF +#endif + +#ifndef P_ATAPI_DIOW +#define P_ATAPI_DIOW P_UNDEF +#endif + +#ifndef P_ATAPI_CS0 +#define P_ATAPI_CS0 P_UNDEF +#endif + +#ifndef P_ATAPI_CS1 +#define P_ATAPI_CS1 P_UNDEF +#endif + +#ifndef P_ATAPI_DMACK +#define P_ATAPI_DMACK P_UNDEF +#endif + +#ifndef P_ATAPI_DMARQ +#define P_ATAPI_DMARQ P_UNDEF +#endif + +#ifndef P_ATAPI_INTRQ +#define P_ATAPI_INTRQ P_UNDEF +#endif + +#ifndef P_ATAPI_IORDY +#define P_ATAPI_IORDY P_UNDEF +#endif + +#ifndef P_AMC_BR +#define P_AMC_BR P_UNDEF +#endif + +#ifndef P_AMC_BG +#define P_AMC_BG P_UNDEF +#endif + +#ifndef P_AMC_BGH +#define P_AMC_BGH P_UNDEF +#endif + +/* EMAC */ + +#ifndef P_MII0_ETxD0 +#define P_MII0_ETxD0 P_UNDEF +#endif + +#ifndef P_MII0_ETxD1 +#define P_MII0_ETxD1 P_UNDEF +#endif + +#ifndef P_MII0_ETxD2 +#define P_MII0_ETxD2 P_UNDEF +#endif + +#ifndef P_MII0_ETxD3 +#define P_MII0_ETxD3 P_UNDEF +#endif + +#ifndef P_MII0_ETxEN +#define P_MII0_ETxEN P_UNDEF +#endif + +#ifndef P_MII0_TxCLK +#define P_MII0_TxCLK P_UNDEF +#endif + +#ifndef P_MII0_PHYINT +#define P_MII0_PHYINT P_UNDEF +#endif + +#ifndef P_MII0_COL +#define P_MII0_COL P_UNDEF +#endif + +#ifndef P_MII0_ERxD0 +#define P_MII0_ERxD0 P_UNDEF +#endif + +#ifndef P_MII0_ERxD1 +#define P_MII0_ERxD1 P_UNDEF +#endif + +#ifndef P_MII0_ERxD2 +#define P_MII0_ERxD2 P_UNDEF +#endif + +#ifndef P_MII0_ERxD3 +#define P_MII0_ERxD3 P_UNDEF +#endif + +#ifndef P_MII0_ERxDV +#define P_MII0_ERxDV P_UNDEF +#endif + +#ifndef P_MII0_ERxCLK +#define P_MII0_ERxCLK P_UNDEF +#endif + +#ifndef P_MII0_ERxER +#define P_MII0_ERxER P_UNDEF +#endif + +#ifndef P_MII0_CRS +#define P_MII0_CRS P_UNDEF +#endif + +#ifndef P_RMII0_REF_CLK +#define P_RMII0_REF_CLK P_UNDEF +#endif + +#ifndef P_RMII0_MDINT +#define P_RMII0_MDINT P_UNDEF +#endif + +#ifndef P_RMII0_CRS_DV +#define P_RMII0_CRS_DV P_UNDEF +#endif + +#ifndef P_MDC +#define P_MDC P_UNDEF +#endif + +#ifndef P_MDIO +#define P_MDIO P_UNDEF +#endif + +#endif /* _PORTMUX_H_ */ diff --git a/include/asm-blackfin/termbits.h b/include/asm-blackfin/termbits.h index 2fd9dabdba77..4eac38de8ce1 100644 --- a/include/asm-blackfin/termbits.h +++ b/include/asm-blackfin/termbits.h @@ -17,6 +17,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-blackfin/trace.h b/include/asm-blackfin/trace.h new file mode 100644 index 000000000000..9c2474c9a589 --- /dev/null +++ b/include/asm-blackfin/trace.h @@ -0,0 +1,52 @@ +/* + * Common header file for blackfin family of processors. + * + */ + +#ifndef _BLACKFIN_TRACE_ +#define _BLACKFIN_TRACE_ + +#ifndef __ASSEMBLY__ +/* Trace Macros for C files */ + +#define trace_buffer_save(x) \ + do { \ + (x) = bfin_read_TBUFCTL(); \ + bfin_write_TBUFCTL((x) & ~TBUFEN); \ + } while (0) + +#define trace_buffer_restore(x) \ + do { \ + bfin_write_TBUFCTL((x)); \ + } while (0) + +#else +/* Trace Macros for Assembly files */ + +#define TRACE_BUFFER_START(preg, dreg) trace_buffer_start(preg, dreg) +#define TRACE_BUFFER_STOP(preg, dreg) trace_buffer_stop(preg, dreg) + +#define trace_buffer_stop(preg, dreg) \ + preg.L = LO(TBUFCTL); \ + preg.H = HI(TBUFCTL); \ + dreg = 0x1; \ + [preg] = dreg; + +#define trace_buffer_start(preg, dreg) \ + preg.L = LO(TBUFCTL); \ + preg.H = HI(TBUFCTL); \ + dreg = 0x13; \ + [preg] = dreg; + +#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE +# define DEBUG_START_HWTRACE(preg, dreg) trace_buffer_start(preg, dreg) +# define DEBUG_STOP_HWTRACE(preg, dreg) trace_buffer_stop(preg, dreg) + +#else +# define DEBUG_START_HWTRACE(preg, dreg) +# define DEBUG_STOP_HWTRACE(preg, dreg) +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* _BLACKFIN_TRACE_ */ diff --git a/include/asm-cris/ioctls.h b/include/asm-cris/ioctls.h index 97787c3c575f..4f4e52531fa0 100644 --- a/include/asm-cris/ioctls.h +++ b/include/asm-cris/ioctls.h @@ -48,6 +48,10 @@ #define TIOCSBRK 0x5427 /* BSD compatibility */ #define TIOCCBRK 0x5428 /* BSD compatibility */ #define TIOCGSID 0x5429 /* Return the session ID of FD */ +#define TCGETS2 _IOR('T',0x2A, struct termios2) +#define TCSETS2 _IOW('T',0x2B, struct termios2) +#define TCSETSW2 _IOW('T',0x2C, struct termios2) +#define TCSETSF2 _IOW('T',0x2D, struct termios2) #define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ diff --git a/include/asm-cris/pci.h b/include/asm-cris/pci.h index b2ac8a331da1..730ce40fdd0f 100644 --- a/include/asm-cris/pci.h +++ b/include/asm-cris/pci.h @@ -52,47 +52,11 @@ struct pci_dev; #define pci_unmap_len(PTR, LEN_NAME) (0) #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) -/* This is always fine. */ -#define pci_dac_dma_supported(pci_dev, mask) (1) - -static inline dma64_addr_t -pci_dac_page_to_dma(struct pci_dev *pdev, struct page *page, unsigned long offset, int direction) -{ - return ((dma64_addr_t) page_to_phys(page) + - (dma64_addr_t) offset); -} - -static inline struct page * -pci_dac_dma_to_page(struct pci_dev *pdev, dma64_addr_t dma_addr) -{ - return pfn_to_page(dma_addr >> PAGE_SHIFT); -} - -static inline unsigned long -pci_dac_dma_to_offset(struct pci_dev *pdev, dma64_addr_t dma_addr) -{ - return (dma_addr & ~PAGE_MASK); -} - -static inline void -pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) -{ -} - -static inline void -pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) -{ -} - #define HAVE_PCI_MMAP extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine); -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #endif /* __KERNEL__ */ /* implement the pci_ DMA API in terms of the generic device dma_ one */ diff --git a/include/asm-cris/pgtable.h b/include/asm-cris/pgtable.h index c94a7107019c..417f71116215 100644 --- a/include/asm-cris/pgtable.h +++ b/include/asm-cris/pgtable.h @@ -111,9 +111,7 @@ extern unsigned long empty_zero_page; * Undefined behaviour if not.. */ -static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; } static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } -static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_READ; } static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; } static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } @@ -124,18 +122,6 @@ static inline pte_t pte_wrprotect(pte_t pte) return pte; } -static inline pte_t pte_rdprotect(pte_t pte) -{ - pte_val(pte) &= ~(_PAGE_READ | _PAGE_SILENT_READ); - return pte; -} - -static inline pte_t pte_exprotect(pte_t pte) -{ - pte_val(pte) &= ~(_PAGE_READ | _PAGE_SILENT_READ); - return pte; -} - static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE); @@ -156,22 +142,6 @@ static inline pte_t pte_mkwrite(pte_t pte) return pte; } -static inline pte_t pte_mkread(pte_t pte) -{ - pte_val(pte) |= _PAGE_READ; - if (pte_val(pte) & _PAGE_ACCESSED) - pte_val(pte) |= _PAGE_SILENT_READ; - return pte; -} - -static inline pte_t pte_mkexec(pte_t pte) -{ - pte_val(pte) |= _PAGE_READ; - if (pte_val(pte) & _PAGE_ACCESSED) - pte_val(pte) |= _PAGE_SILENT_READ; - return pte; -} - static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_MODIFIED; diff --git a/include/asm-cris/termbits.h b/include/asm-cris/termbits.h index 8d8cec225fe1..71c1b36269b8 100644 --- a/include/asm-cris/termbits.h +++ b/include/asm-cris/termbits.h @@ -19,6 +19,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ @@ -155,6 +166,7 @@ struct ktermios { #define HUPCL 0002000 #define CLOCAL 0004000 #define CBAUDEX 0010000 +#define BOTHER 0010000 #define B57600 0010001 #define B115200 0010002 #define B230400 0010003 diff --git a/include/asm-cris/termios.h b/include/asm-cris/termios.h index c9dbd4d43368..b0124e6c2e41 100644 --- a/include/asm-cris/termios.h +++ b/include/asm-cris/termios.h @@ -81,8 +81,10 @@ struct termio { copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ }) -#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) -#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) +#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) +#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) +#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) +#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) #endif /* __KERNEL__ */ diff --git a/include/asm-frv/pci.h b/include/asm-frv/pci.h index f35a4511e7b9..585d9b49949a 100644 --- a/include/asm-frv/pci.h +++ b/include/asm-frv/pci.h @@ -22,10 +22,6 @@ struct pci_dev; #define pcibios_assign_all_busses() 0 -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - extern void pcibios_set_master(struct pci_dev *dev); extern void pcibios_penalize_isa_irq(int irq); @@ -44,9 +40,6 @@ extern void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, extern void pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle); -/* This is always fine. */ -#define pci_dac_dma_supported(pci_dev, mask) (1) - /* Return the index of the PCI controller for device PDEV. */ #define pci_controller_num(PDEV) (0) diff --git a/include/asm-frv/pgtable.h b/include/asm-frv/pgtable.h index 114aefae2701..adde69985255 100644 --- a/include/asm-frv/pgtable.h +++ b/include/asm-frv/pgtable.h @@ -377,19 +377,13 @@ static inline pmd_t *pmd_offset(pud_t *dir, unsigned long address) * The following only work if pte_present() is true. * Undefined behaviour if not.. */ -static inline int pte_read(pte_t pte) { return !((pte).pte & _PAGE_SUPER); } -static inline int pte_exec(pte_t pte) { return !((pte).pte & _PAGE_SUPER); } static inline int pte_dirty(pte_t pte) { return (pte).pte & _PAGE_DIRTY; } static inline int pte_young(pte_t pte) { return (pte).pte & _PAGE_ACCESSED; } static inline int pte_write(pte_t pte) { return !((pte).pte & _PAGE_WP); } -static inline pte_t pte_rdprotect(pte_t pte) { (pte).pte |= _PAGE_SUPER; return pte; } -static inline pte_t pte_exprotect(pte_t pte) { (pte).pte |= _PAGE_SUPER; return pte; } static inline pte_t pte_mkclean(pte_t pte) { (pte).pte &= ~_PAGE_DIRTY; return pte; } static inline pte_t pte_mkold(pte_t pte) { (pte).pte &= ~_PAGE_ACCESSED; return pte; } static inline pte_t pte_wrprotect(pte_t pte) { (pte).pte |= _PAGE_WP; return pte; } -static inline pte_t pte_mkread(pte_t pte) { (pte).pte &= ~_PAGE_SUPER; return pte; } -static inline pte_t pte_mkexec(pte_t pte) { (pte).pte &= ~_PAGE_SUPER; return pte; } static inline pte_t pte_mkdirty(pte_t pte) { (pte).pte |= _PAGE_DIRTY; return pte; } static inline pte_t pte_mkyoung(pte_t pte) { (pte).pte |= _PAGE_ACCESSED; return pte; } static inline pte_t pte_mkwrite(pte_t pte) { (pte).pte &= ~_PAGE_WP; return pte; } diff --git a/include/asm-frv/termbits.h b/include/asm-frv/termbits.h index 2d6d389cff49..74851b424d4f 100644 --- a/include/asm-frv/termbits.h +++ b/include/asm-frv/termbits.h @@ -17,6 +17,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-frv/uaccess.h b/include/asm-frv/uaccess.h index 3d90e1018ee2..53650c958f41 100644 --- a/include/asm-frv/uaccess.h +++ b/include/asm-frv/uaccess.h @@ -277,6 +277,8 @@ extern long __memcpy_user(void *dst, const void *src, unsigned long count); #endif +#define __clear_user clear_user + static inline unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n) { diff --git a/include/asm-frv/unistd.h b/include/asm-frv/unistd.h index d0ea6789b31e..7306c71a8926 100644 --- a/include/asm-frv/unistd.h +++ b/include/asm-frv/unistd.h @@ -326,10 +326,14 @@ #define __NR_move_pages 317 #define __NR_getcpu 318 #define __NR_epoll_pwait 319 +#define __NR_utimensat 320 +#define __NR_signalfd 321 +#define __NR_timerfd 322 +#define __NR_eventfd 323 #ifdef __KERNEL__ -#define NR_syscalls 320 +#define NR_syscalls 324 #define __ARCH_WANT_IPC_PARSE_VERSION /* #define __ARCH_WANT_OLD_READDIR */ diff --git a/include/asm-generic/dma-mapping-broken.h b/include/asm-generic/dma-mapping-broken.h index 29413d3d4605..e2468f894d2a 100644 --- a/include/asm-generic/dma-mapping-broken.h +++ b/include/asm-generic/dma-mapping-broken.h @@ -1,24 +1,82 @@ #ifndef _ASM_GENERIC_DMA_MAPPING_H #define _ASM_GENERIC_DMA_MAPPING_H -/* This is used for archs that do not support DMA */ +/* define the dma api to allow compilation but not linking of + * dma dependent code. Code that depends on the dma-mapping + * API needs to set 'depends on HAS_DMA' in its Kconfig + */ -static inline void * +struct scatterlist; + +extern void * dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, - gfp_t flag) -{ - BUG(); - return NULL; -} + gfp_t flag); -static inline void +extern void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, - dma_addr_t dma_handle) -{ - BUG(); -} + dma_addr_t dma_handle); #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) +extern dma_addr_t +dma_map_single(struct device *dev, void *ptr, size_t size, + enum dma_data_direction direction); + +extern void +dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, + enum dma_data_direction direction); + +extern int +dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction direction); + +extern void +dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, + enum dma_data_direction direction); + +extern dma_addr_t +dma_map_page(struct device *dev, struct page *page, unsigned long offset, + size_t size, enum dma_data_direction direction); + +extern void +dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, + enum dma_data_direction direction); + +extern void +dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, + enum dma_data_direction direction); + +extern void +dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle, + unsigned long offset, size_t size, + enum dma_data_direction direction); + +extern void +dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, + enum dma_data_direction direction); + +#define dma_sync_single_for_device dma_sync_single_for_cpu +#define dma_sync_single_range_for_device dma_sync_single_range_for_cpu +#define dma_sync_sg_for_device dma_sync_sg_for_cpu + +extern int +dma_mapping_error(dma_addr_t dma_addr); + +extern int +dma_supported(struct device *dev, u64 mask); + +extern int +dma_set_mask(struct device *dev, u64 mask); + +extern int +dma_get_cache_alignment(void); + +extern int +dma_is_consistent(struct device *dev, dma_addr_t dma_handle); + +extern void +dma_cache_sync(struct device *dev, void *vaddr, size_t size, + enum dma_data_direction direction); + #endif /* _ASM_GENERIC_DMA_MAPPING_H */ diff --git a/include/asm-generic/fcntl.h b/include/asm-generic/fcntl.h index c154b9d6e7e5..b8477414c5c8 100644 --- a/include/asm-generic/fcntl.h +++ b/include/asm-generic/fcntl.h @@ -48,6 +48,9 @@ #ifndef O_NOATIME #define O_NOATIME 01000000 #endif +#ifndef O_CLOEXEC +#define O_CLOEXEC 02000000 /* set close_on_exec */ +#endif #ifndef O_NDELAY #define O_NDELAY O_NONBLOCK #endif diff --git a/include/asm-h8300/dma-mapping.h b/include/asm-h8300/dma-mapping.h deleted file mode 100644 index d00e40099165..000000000000 --- a/include/asm-h8300/dma-mapping.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/dma-mapping-broken.h> diff --git a/include/asm-h8300/ioctls.h b/include/asm-h8300/ioctls.h index ac20457e5978..98a53d067269 100644 --- a/include/asm-h8300/ioctls.h +++ b/include/asm-h8300/ioctls.h @@ -47,6 +47,10 @@ #define TIOCSBRK 0x5427 /* BSD compatibility */ #define TIOCCBRK 0x5428 /* BSD compatibility */ #define TIOCGSID 0x5429 /* Return the session ID of FD */ +#define TCGETS2 _IOR('T',0x2A, struct termios2) +#define TCSETS2 _IOW('T',0x2B, struct termios2) +#define TCSETSW2 _IOW('T',0x2C, struct termios2) +#define TCSETSF2 _IOW('T',0x2D, struct termios2) #define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ diff --git a/include/asm-h8300/pci.h b/include/asm-h8300/pci.h index 0c771b05fdd5..97389b35aa35 100644 --- a/include/asm-h8300/pci.h +++ b/include/asm-h8300/pci.h @@ -22,8 +22,4 @@ static inline void pcibios_penalize_isa_irq(int irq, int active) #define PCI_DMA_BUS_IS_PHYS (1) -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #endif /* _ASM_H8300_PCI_H */ diff --git a/include/asm-h8300/termbits.h b/include/asm-h8300/termbits.h index 6a1f4d3807b4..31eca81db3f7 100644 --- a/include/asm-h8300/termbits.h +++ b/include/asm-h8300/termbits.h @@ -17,6 +17,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ @@ -130,6 +141,7 @@ struct ktermios { #define HUPCL 0002000 #define CLOCAL 0004000 #define CBAUDEX 0010000 +#define BOTHER 0010000 #define B57600 0010001 #define B115200 0010002 #define B230400 0010003 @@ -145,10 +157,12 @@ struct ktermios { #define B3000000 0010015 #define B3500000 0010016 #define B4000000 0010017 -#define CIBAUD 002003600000 /* input baud rate (not used) */ +#define CIBAUD 002003600000 /* input baud rate */ #define CMSPAR 010000000000 /* mark or space (stick) parity */ #define CRTSCTS 020000000000 /* flow control */ +#define IBSHIFT 16 /* shift from CBAUD to CIBAUD */ + /* c_lflag bits */ #define ISIG 0000001 #define ICANON 0000002 diff --git a/include/asm-h8300/termios.h b/include/asm-h8300/termios.h index fb2925d08c49..70eea64b4213 100644 --- a/include/asm-h8300/termios.h +++ b/include/asm-h8300/termios.h @@ -82,8 +82,10 @@ struct termio { copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ }) -#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) -#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) +#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) +#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) +#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) +#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) #endif /* __KERNEL__ */ diff --git a/include/asm-h8300/thread_info.h b/include/asm-h8300/thread_info.h index 45f09dc9caff..aee4009a498e 100644 --- a/include/asm-h8300/thread_info.h +++ b/include/asm-h8300/thread_info.h @@ -92,6 +92,7 @@ static inline struct thread_info *current_thread_info(void) #define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling TIF_NEED_RESCHED */ #define TIF_MEMDIE 5 +#define TIF_RESTORE_SIGMASK 6 /* restore signal mask in do_signal() */ /* as above, but as bit values */ #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) @@ -99,6 +100,7 @@ static inline struct thread_info *current_thread_info(void) #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) +#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) #define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */ diff --git a/include/asm-i386/boot.h b/include/asm-i386/boot.h index bd024ab4fe53..ed8affbf96cb 100644 --- a/include/asm-i386/boot.h +++ b/include/asm-i386/boot.h @@ -1,5 +1,5 @@ -#ifndef _LINUX_BOOT_H -#define _LINUX_BOOT_H +#ifndef _ASM_BOOT_H +#define _ASM_BOOT_H /* Don't touch these, unless you really know what you're doing. */ #define DEF_INITSEG 0x9000 @@ -17,4 +17,4 @@ + (CONFIG_PHYSICAL_ALIGN - 1)) \ & ~(CONFIG_PHYSICAL_ALIGN - 1)) -#endif /* _LINUX_BOOT_H */ +#endif /* _ASM_BOOT_H */ diff --git a/include/asm-i386/bootparam.h b/include/asm-i386/bootparam.h new file mode 100644 index 000000000000..427d8652bfde --- /dev/null +++ b/include/asm-i386/bootparam.h @@ -0,0 +1,85 @@ +#ifndef _ASM_BOOTPARAM_H +#define _ASM_BOOTPARAM_H + +#include <linux/types.h> +#include <linux/screen_info.h> +#include <linux/apm_bios.h> +#include <asm/e820.h> +#include <linux/edd.h> +#include <video/edid.h> + +struct setup_header { + u8 setup_sects; + u16 root_flags; + u32 syssize; + u16 ram_size; + u16 vid_mode; + u16 root_dev; + u16 boot_flag; + u16 jump; + u32 header; + u16 version; + u32 realmode_swtch; + u16 start_sys; + u16 kernel_version; + u8 type_of_loader; + u8 loadflags; +#define LOADED_HIGH 0x01 +#define CAN_USE_HEAP 0x80 + u16 setup_move_size; + u32 code32_start; + u32 ramdisk_image; + u32 ramdisk_size; + u32 bootsect_kludge; + u16 heap_end_ptr; + u16 _pad1; + u32 cmd_line_ptr; + u32 initrd_addr_max; + u32 kernel_alignment; + u8 relocatable_kernel; +} __attribute__((packed)); + +struct sys_desc_table { + u16 length; + u8 table[14]; +}; + +struct efi_info { + u32 _pad1; + u32 efi_systab; + u32 efi_memdesc_size; + u32 efi_memdec_version; + u32 efi_memmap; + u32 fi_memmap_size; + u32 _pad2[2]; +}; + +/* The so-called "zeropage" */ +struct boot_params { + struct screen_info screen_info; /* 0x000 */ + struct apm_bios_info apm_bios_info; /* 0x040 */ + u8 _pad2[12]; /* 0x054 */ + u32 speedstep_info[4]; /* 0x060 */ + u8 _pad3[16]; /* 0x070 */ + u8 hd0_info[16]; /* obsolete! */ /* 0x080 */ + u8 hd1_info[16]; /* obsolete! */ /* 0x090 */ + struct sys_desc_table sys_desc_table; /* 0x0a0 */ + u8 _pad4[144]; /* 0x0b0 */ + struct edid_info edid_info; /* 0x140 */ + struct efi_info efi_info; /* 0x1c0 */ + u32 alt_mem_k; /* 0x1e0 */ + u32 scratch; /* Scratch field! */ /* 0x1e4 */ + u8 e820_entries; /* 0x1e8 */ + u8 eddbuf_entries; /* 0x1e9 */ + u8 edd_mbr_sig_buf_entries; /* 0x1ea */ + u8 _pad6[6]; /* 0x1eb */ + struct setup_header hdr; /* setup header */ /* 0x1f1 */ + u8 _pad7[0x290-0x1f1-sizeof(struct setup_header)]; + u32 edd_mbr_sig_buffer[EDD_MBR_SIG_MAX]; /* 0x290 */ + struct e820entry e820_map[E820MAX]; /* 0x2d0 */ + u8 _pad8[48]; /* 0xcd0 */ + struct edd_info eddbuf[EDDMAXNR]; /* 0xd00 */ + u8 _pad9[276]; /* 0xeec */ +} __attribute__((packed)); + +#endif /* _ASM_BOOTPARAM_H */ diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h index f514e906643a..c961c03cf1e2 100644 --- a/include/asm-i386/cpufeature.h +++ b/include/asm-i386/cpufeature.h @@ -12,7 +12,7 @@ #endif #include <asm/required-features.h> -#define NCAPINTS 7 /* N 32-bit words worth of info */ +#define NCAPINTS 8 /* N 32-bit words worth of info */ /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ #define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */ @@ -81,6 +81,7 @@ #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ #define X86_FEATURE_LAPIC_TIMER_BROKEN (3*32+ 14) /* lapic timer broken in C1 */ #define X86_FEATURE_SYNC_RDTSC (3*32+15) /* RDTSC synchronizes the CPU */ +#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ @@ -108,11 +109,24 @@ #define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ #define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ -#define cpu_has(c, bit) \ - ((__builtin_constant_p(bit) && (bit) < 32 && \ - (1UL << (bit)) & REQUIRED_MASK1) ? \ - 1 : \ - test_bit(bit, (c)->x86_capability)) +/* + * Auxiliary flags: Linux defined - For features scattered in various + * CPUID levels like 0x6, 0xA etc + */ +#define X86_FEATURE_IDA (7*32+ 0) /* Intel Dynamic Acceleration */ + +#define cpu_has(c, bit) \ + (__builtin_constant_p(bit) && \ + ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \ + (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \ + (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \ + (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \ + (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \ + (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \ + (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \ + (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ) \ + ? 1 : \ + test_bit(bit, (c)->x86_capability)) #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) diff --git a/include/asm-i386/e820.h b/include/asm-i386/e820.h index 096a2a8eb1da..c03290ccecb2 100644 --- a/include/asm-i386/e820.h +++ b/include/asm-i386/e820.h @@ -25,13 +25,15 @@ #ifndef __ASSEMBLY__ +struct e820entry { + u64 addr; /* start of memory segment */ + u64 size; /* size of memory segment */ + u32 type; /* type of memory segment */ +} __attribute__((packed)); + struct e820map { - int nr_map; - struct e820entry { - unsigned long long addr; /* start of memory segment */ - unsigned long long size; /* size of memory segment */ - unsigned long type; /* type of memory segment */ - } map[E820MAX]; + u32 nr_map; + struct e820entry map[E820MAX]; }; extern struct e820map e820; diff --git a/include/asm-i386/fixmap.h b/include/asm-i386/fixmap.h index 80ea052ee3a4..249e753ac805 100644 --- a/include/asm-i386/fixmap.h +++ b/include/asm-i386/fixmap.h @@ -54,6 +54,8 @@ extern unsigned long __FIXADDR_TOP; enum fixed_addresses { FIX_HOLE, FIX_VDSO, + FIX_DBGP_BASE, + FIX_EARLYCON_MEM_BASE, #ifdef CONFIG_X86_LOCAL_APIC FIX_APIC_BASE, /* local (CPU) APIC) -- required for SMP or not */ #endif diff --git a/include/asm-i386/ide.h b/include/asm-i386/ide.h index 0fc240c80f49..e7817a3d6578 100644 --- a/include/asm-i386/ide.h +++ b/include/asm-i386/ide.h @@ -40,14 +40,13 @@ static __inline__ int ide_default_irq(unsigned long base) static __inline__ unsigned long ide_default_io_base(int index) { - struct pci_dev *pdev; /* * If PCI is present then it is not safe to poke around * the other legacy IDE ports. Only 0x1f0 and 0x170 are * defined compatibility mode ports for PCI. A user can * override this using ide= but we must default safe. */ - if ((pdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, NULL)) == NULL) { + if (no_pci_devices()) { switch(index) { case 2: return 0x1e8; case 3: return 0x168; @@ -55,7 +54,6 @@ static __inline__ unsigned long ide_default_io_base(int index) case 5: return 0x160; } } - pci_dev_put(pdev); switch (index) { case 0: return 0x1f0; case 1: return 0x170; diff --git a/include/asm-i386/io.h b/include/asm-i386/io.h index e797586a5bfc..7b65b5b00034 100644 --- a/include/asm-i386/io.h +++ b/include/asm-i386/io.h @@ -129,6 +129,7 @@ extern void iounmap(volatile void __iomem *addr); */ extern void *bt_ioremap(unsigned long offset, unsigned long size); extern void bt_iounmap(void *addr, unsigned long size); +extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys); /* Use early IO mappings for DMI because it's initialized early */ #define dmi_ioremap bt_ioremap diff --git a/include/asm-i386/pci.h b/include/asm-i386/pci.h index 64b6d0baedbc..392d3fe5d45e 100644 --- a/include/asm-i386/pci.h +++ b/include/asm-i386/pci.h @@ -56,48 +56,11 @@ struct pci_dev; #define pci_unmap_len(PTR, LEN_NAME) (0) #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) -/* This is always fine. */ -#define pci_dac_dma_supported(pci_dev, mask) (1) - -static inline dma64_addr_t -pci_dac_page_to_dma(struct pci_dev *pdev, struct page *page, unsigned long offset, int direction) -{ - return ((dma64_addr_t) page_to_phys(page) + - (dma64_addr_t) offset); -} - -static inline struct page * -pci_dac_dma_to_page(struct pci_dev *pdev, dma64_addr_t dma_addr) -{ - return pfn_to_page(dma_addr >> PAGE_SHIFT); -} - -static inline unsigned long -pci_dac_dma_to_offset(struct pci_dev *pdev, dma64_addr_t dma_addr) -{ - return (dma_addr & ~PAGE_MASK); -} - -static inline void -pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) -{ -} - -static inline void -pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) -{ - flush_write_buffers(); -} - #define HAVE_PCI_MMAP extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine); -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #ifdef CONFIG_PCI static inline void pci_dma_burst_advice(struct pci_dev *pdev, enum pci_dma_burst_strategy *strat, diff --git a/include/asm-i386/pgtable-2level.h b/include/asm-i386/pgtable-2level.h index a50fd1773de8..84b03cf56a79 100644 --- a/include/asm-i386/pgtable-2level.h +++ b/include/asm-i386/pgtable-2level.h @@ -57,14 +57,6 @@ static inline pte_t native_ptep_get_and_clear(pte_t *xp) #define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) /* - * All present user pages are user-executable: - */ -static inline int pte_exec(pte_t pte) -{ - return pte_user(pte); -} - -/* * All present pages are kernel-executable: */ static inline int pte_exec_kernel(pte_t pte) diff --git a/include/asm-i386/pgtable-3level.h b/include/asm-i386/pgtable-3level.h index eb0f1d7e96a1..948a33414118 100644 --- a/include/asm-i386/pgtable-3level.h +++ b/include/asm-i386/pgtable-3level.h @@ -20,26 +20,11 @@ #define pud_present(pud) 1 /* - * Is the pte executable? - */ -static inline int pte_x(pte_t pte) -{ - return !(pte_val(pte) & _PAGE_NX); -} - -/* - * All present user-pages with !NX bit are user-executable: - */ -static inline int pte_exec(pte_t pte) -{ - return pte_user(pte) && pte_x(pte); -} -/* * All present pages with !NX bit are kernel-executable: */ static inline int pte_exec_kernel(pte_t pte) { - return pte_x(pte); + return !(pte_val(pte) & _PAGE_NX); } /* Rules for using set_pte: the pte being assigned *must* be diff --git a/include/asm-i386/pgtable.h b/include/asm-i386/pgtable.h index 628fa7747d0c..01734e05e63b 100644 --- a/include/asm-i386/pgtable.h +++ b/include/asm-i386/pgtable.h @@ -79,7 +79,7 @@ void paging_init(void); * area for the same reason. ;) */ #define VMALLOC_OFFSET (8*1024*1024) -#define VMALLOC_START (((unsigned long) high_memory + vmalloc_earlyreserve + \ +#define VMALLOC_START (((unsigned long) high_memory + \ 2*VMALLOC_OFFSET-1) & ~(VMALLOC_OFFSET-1)) #ifdef CONFIG_HIGHMEM # define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE) @@ -218,8 +218,6 @@ extern unsigned long pg0[]; * The following only work if pte_present() is true. * Undefined behaviour if not.. */ -static inline int pte_user(pte_t pte) { return (pte).pte_low & _PAGE_USER; } -static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_USER; } static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_DIRTY; } static inline int pte_young(pte_t pte) { return (pte).pte_low & _PAGE_ACCESSED; } static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_RW; } @@ -230,13 +228,9 @@ static inline int pte_huge(pte_t pte) { return (pte).pte_low & _PAGE_PSE; } */ static inline int pte_file(pte_t pte) { return (pte).pte_low & _PAGE_FILE; } -static inline pte_t pte_rdprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_USER; return pte; } -static inline pte_t pte_exprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_USER; return pte; } static inline pte_t pte_mkclean(pte_t pte) { (pte).pte_low &= ~_PAGE_DIRTY; return pte; } static inline pte_t pte_mkold(pte_t pte) { (pte).pte_low &= ~_PAGE_ACCESSED; return pte; } static inline pte_t pte_wrprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_RW; return pte; } -static inline pte_t pte_mkread(pte_t pte) { (pte).pte_low |= _PAGE_USER; return pte; } -static inline pte_t pte_mkexec(pte_t pte) { (pte).pte_low |= _PAGE_USER; return pte; } static inline pte_t pte_mkdirty(pte_t pte) { (pte).pte_low |= _PAGE_DIRTY; return pte; } static inline pte_t pte_mkyoung(pte_t pte) { (pte).pte_low |= _PAGE_ACCESSED; return pte; } static inline pte_t pte_mkwrite(pte_t pte) { (pte).pte_low |= _PAGE_RW; return pte; } diff --git a/include/asm-i386/processor.h b/include/asm-i386/processor.h index 338668bfb0a2..422cffef00c9 100644 --- a/include/asm-i386/processor.h +++ b/include/asm-i386/processor.h @@ -119,6 +119,7 @@ void __init cpu_detect(struct cpuinfo_x86 *c); extern void identify_boot_cpu(void); extern void identify_secondary_cpu(struct cpuinfo_x86 *); extern void print_cpu_info(struct cpuinfo_x86 *); +extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); extern unsigned short num_cache_leaves; @@ -227,6 +228,10 @@ extern int bootloader_type; #define HAVE_ARCH_PICK_MMAP_LAYOUT +extern void hard_disable_TSC(void); +extern void disable_TSC(void); +extern void hard_enable_TSC(void); + /* * Size of io_bitmap. */ diff --git a/include/asm-i386/required-features.h b/include/asm-i386/required-features.h index 9db866c1e64c..65848a007050 100644 --- a/include/asm-i386/required-features.h +++ b/include/asm-i386/required-features.h @@ -3,32 +3,53 @@ /* Define minimum CPUID feature set for kernel These bits are checked really early to actually display a visible error message before the - kernel dies. Only add word 0 bits here + kernel dies. Make sure to assign features to the proper mask! Some requirements that are not in CPUID yet are also in the - CONFIG_X86_MINIMUM_CPU mode which is checked too. + CONFIG_X86_MINIMUM_CPU_FAMILY which is checked too. The real information is in arch/i386/Kconfig.cpu, this just converts the CONFIGs into a bitmask */ +#ifndef CONFIG_MATH_EMULATION +# define NEED_FPU (1<<(X86_FEATURE_FPU & 31)) +#else +# define NEED_FPU 0 +#endif + #ifdef CONFIG_X86_PAE -#define NEED_PAE (1<<X86_FEATURE_PAE) +# define NEED_PAE (1<<(X86_FEATURE_PAE & 31)) #else -#define NEED_PAE 0 +# define NEED_PAE 0 #endif #ifdef CONFIG_X86_CMOV -#define NEED_CMOV (1<<X86_FEATURE_CMOV) +# define NEED_CMOV (1<<(X86_FEATURE_CMOV & 31)) #else -#define NEED_CMOV 0 +# define NEED_CMOV 0 #endif #ifdef CONFIG_X86_CMPXCHG64 -#define NEED_CMPXCHG64 (1<<X86_FEATURE_CX8) +# define NEED_CX8 (1<<(X86_FEATURE_CX8 & 31)) +#else +# define NEED_CX8 0 +#endif + +#define REQUIRED_MASK0 (NEED_FPU|NEED_PAE|NEED_CMOV|NEED_CX8) + +#ifdef CONFIG_X86_USE_3DNOW +# define NEED_3DNOW (1<<(X86_FEATURE_3DNOW & 31)) #else -#define NEED_CMPXCHG64 0 +# define NEED_3DNOW 0 #endif -#define REQUIRED_MASK1 (NEED_PAE|NEED_CMOV|NEED_CMPXCHG64) +#define REQUIRED_MASK1 (NEED_3DNOW) + +#define REQUIRED_MASK2 0 +#define REQUIRED_MASK3 0 +#define REQUIRED_MASK4 0 +#define REQUIRED_MASK5 0 +#define REQUIRED_MASK6 0 +#define REQUIRED_MASK7 0 #endif diff --git a/include/asm-i386/setup.h b/include/asm-i386/setup.h index 0e8077cbfdac..0d5bff9dc4a5 100644 --- a/include/asm-i386/setup.h +++ b/include/asm-i386/setup.h @@ -26,12 +26,15 @@ #define NEW_CL_POINTER 0x228 /* Relative to real mode data */ #ifndef __ASSEMBLY__ + +#include <asm/bootparam.h> + /* * This is set up by the setup-routine at boot-time */ -extern unsigned char boot_params[PARAM_SIZE]; +extern struct boot_params boot_params; -#define PARAM (boot_params) +#define PARAM ((char *)&boot_params) #define SCREEN_INFO (*(struct screen_info *) (PARAM+0)) #define EXT_MEM_K (*(unsigned short *) (PARAM+2)) #define ALT_MEM_K (*(unsigned long *) (PARAM+0x1e0)) @@ -39,8 +42,7 @@ extern unsigned char boot_params[PARAM_SIZE]; #define E820_MAP ((struct e820entry *) (PARAM+E820MAP)) #define APM_BIOS_INFO (*(struct apm_bios_info *) (PARAM+0x40)) #define IST_INFO (*(struct ist_info *) (PARAM+0x60)) -#define DRIVE_INFO (*(struct drive_info_struct *) (PARAM+0x80)) -#define SYS_DESC_TABLE (*(struct sys_desc_table_struct*)(PARAM+0xa0)) +#define SYS_DESC_TABLE (*(struct sys_desc_table *)(PARAM+0xa0)) #define EFI_SYSTAB ((efi_system_table_t *) *((unsigned long *)(PARAM+0x1c4))) #define EFI_MEMDESC_SIZE (*((unsigned long *) (PARAM+0x1c8))) #define EFI_MEMDESC_VERSION (*((unsigned long *) (PARAM+0x1cc))) diff --git a/include/asm-i386/thread_info.h b/include/asm-i386/thread_info.h index 4cb0f91ae64f..54424e045e01 100644 --- a/include/asm-i386/thread_info.h +++ b/include/asm-i386/thread_info.h @@ -137,6 +137,7 @@ static inline struct thread_info *current_thread_info(void) #define TIF_DEBUG 17 /* uses debug registers */ #define TIF_IO_BITMAP 18 /* uses I/O bitmap */ #define TIF_FREEZE 19 /* is freezing for suspend */ +#define TIF_NOTSC 20 /* TSC is not accessible in userland */ #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) #define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) @@ -151,6 +152,7 @@ static inline struct thread_info *current_thread_info(void) #define _TIF_DEBUG (1<<TIF_DEBUG) #define _TIF_IO_BITMAP (1<<TIF_IO_BITMAP) #define _TIF_FREEZE (1<<TIF_FREEZE) +#define _TIF_NOTSC (1<<TIF_NOTSC) /* work to do on interrupt/exception return */ #define _TIF_WORK_MASK \ @@ -160,7 +162,8 @@ static inline struct thread_info *current_thread_info(void) #define _TIF_ALLWORK_MASK (0x0000FFFF & ~_TIF_SECCOMP) /* flags to check in __switch_to() */ -#define _TIF_WORK_CTXSW (_TIF_DEBUG|_TIF_IO_BITMAP) +#define _TIF_WORK_CTXSW_NEXT (_TIF_IO_BITMAP | _TIF_NOTSC | _TIF_DEBUG) +#define _TIF_WORK_CTXSW_PREV (_TIF_IO_BITMAP | _TIF_NOTSC) /* * Thread-synchronous status. diff --git a/include/asm-ia64/compat.h b/include/asm-ia64/compat.h index 40d01d80610d..0f6e5264ab8f 100644 --- a/include/asm-ia64/compat.h +++ b/include/asm-ia64/compat.h @@ -31,8 +31,10 @@ typedef s32 compat_timer_t; typedef s32 compat_int_t; typedef s32 compat_long_t; +typedef s64 __attribute__((aligned(4))) compat_s64; typedef u32 compat_uint_t; typedef u32 compat_ulong_t; +typedef u64 __attribute__((aligned(4))) compat_u64; struct compat_timespec { compat_time_t tv_sec; diff --git a/include/asm-ia64/mca.h b/include/asm-ia64/mca.h index 41098f459684..edd5d01028df 100644 --- a/include/asm-ia64/mca.h +++ b/include/asm-ia64/mca.h @@ -48,6 +48,7 @@ enum { IA64_MCA_RENDEZ_CHECKIN_NOTDONE = 0x0, IA64_MCA_RENDEZ_CHECKIN_DONE = 0x1, IA64_MCA_RENDEZ_CHECKIN_INIT = 0x2, + IA64_MCA_RENDEZ_CHECKIN_CONCURRENT_MCA = 0x3, }; /* Information maintained by the MC infrastructure */ diff --git a/include/asm-ia64/pci.h b/include/asm-ia64/pci.h index 5a5d1c2ce39d..0149097b736d 100644 --- a/include/asm-ia64/pci.h +++ b/include/asm-ia64/pci.h @@ -71,14 +71,6 @@ pcibios_penalize_isa_irq (int irq, int active) #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ (((PTR)->LEN_NAME) = (VAL)) -/* The ia64 platform always supports 64-bit addressing. */ -#define pci_dac_dma_supported(pci_dev, mask) (1) -#define pci_dac_page_to_dma(dev,pg,off,dir) ((dma_addr_t) page_to_bus(pg) + (off)) -#define pci_dac_dma_to_page(dev,dma_addr) (virt_to_page(bus_to_virt(dma_addr))) -#define pci_dac_dma_to_offset(dev,dma_addr) offset_in_page(dma_addr) -#define pci_dac_dma_sync_single_for_cpu(dev,dma_addr,len,dir) do { } while (0) -#define pci_dac_dma_sync_single_for_device(dev,dma_addr,len,dir) do { mb(); } while (0) - #ifdef CONFIG_PCI static inline void pci_dma_burst_advice(struct pci_dev *pdev, enum pci_dma_burst_strategy *strat, @@ -104,10 +96,12 @@ extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma, #define HAVE_PCI_LEGACY extern int pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma); -extern ssize_t pci_read_legacy_io(struct kobject *kobj, char *buf, loff_t off, - size_t count); -extern ssize_t pci_write_legacy_io(struct kobject *kobj, char *buf, loff_t off, - size_t count); +extern ssize_t pci_read_legacy_io(struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count); +extern ssize_t pci_write_legacy_io(struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count); extern int pci_mmap_legacy_mem(struct kobject *kobj, struct bin_attribute *attr, struct vm_area_struct *vma); @@ -143,10 +137,6 @@ static inline int pci_proc_domain(struct pci_bus *bus) return (pci_domain_nr(bus) != 0); } -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - extern void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, struct resource *res); diff --git a/include/asm-ia64/pgtable.h b/include/asm-ia64/pgtable.h index 6580f31b3135..f923d811c421 100644 --- a/include/asm-ia64/pgtable.h +++ b/include/asm-ia64/pgtable.h @@ -297,8 +297,6 @@ ia64_phys_addr_valid (unsigned long addr) /* * The following have defined behavior only work if pte_present() is true. */ -#define pte_user(pte) ((pte_val(pte) & _PAGE_PL_MASK) == _PAGE_PL_3) -#define pte_read(pte) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) < 6) #define pte_write(pte) ((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) <= 4) #define pte_exec(pte) ((pte_val(pte) & _PAGE_AR_RX) != 0) #define pte_dirty(pte) ((pte_val(pte) & _PAGE_D) != 0) @@ -310,7 +308,6 @@ ia64_phys_addr_valid (unsigned long addr) */ #define pte_wrprotect(pte) (__pte(pte_val(pte) & ~_PAGE_AR_RW)) #define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_AR_RW)) -#define pte_mkexec(pte) (__pte(pte_val(pte) | _PAGE_AR_RX)) #define pte_mkold(pte) (__pte(pte_val(pte) & ~_PAGE_A)) #define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_A)) #define pte_mkclean(pte) (__pte(pte_val(pte) & ~_PAGE_D)) diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h index d3566a298fa4..676b31a08c61 100644 --- a/include/asm-ia64/sn/sn_sal.h +++ b/include/asm-ia64/sn/sn_sal.h @@ -32,6 +32,7 @@ #define SN_SAL_NO_FAULT_ZONE_VIRTUAL 0x02000010 #define SN_SAL_NO_FAULT_ZONE_PHYSICAL 0x02000011 #define SN_SAL_PRINT_ERROR 0x02000012 +#define SN_SAL_REGISTER_PMI_HANDLER 0x02000014 #define SN_SAL_SET_ERROR_HANDLING_FEATURES 0x0200001a // reentrant #define SN_SAL_GET_FIT_COMPT 0x0200001b // reentrant #define SN_SAL_GET_SAPIC_INFO 0x0200001d @@ -680,6 +681,25 @@ sn_register_nofault_code(u64 start_addr, u64 end_addr, u64 return_addr, } /* + * Register or unregister a function to handle a PMI received by a CPU. + * Before calling the registered handler, SAL sets r1 to the value that + * was passed in as the global_pointer. + * + * If the handler pointer is NULL, then the currently registered handler + * will be unregistered. + * + * Returns 0 on success, or a negative value if an error occurred. + */ +static inline int +sn_register_pmi_handler(u64 handler, u64 global_pointer) +{ + struct ia64_sal_retval ret_stuff; + ia64_sal_oemcall(&ret_stuff, SN_SAL_REGISTER_PMI_HANDLER, handler, + global_pointer, 0, 0, 0, 0, 0); + return ret_stuff.status; +} + +/* * Change or query the coherence domain for this partition. Each cpu-based * nasid is represented by a bit in an array of 64-bit words: * 0 = not in this partition's coherency domain diff --git a/include/asm-ia64/termbits.h b/include/asm-ia64/termbits.h index 4531a511bde5..7fae3109ef47 100644 --- a/include/asm-ia64/termbits.h +++ b/include/asm-ia64/termbits.h @@ -26,6 +26,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-m32r/dma-mapping.h b/include/asm-m32r/dma-mapping.h deleted file mode 100644 index f9b58ebba361..000000000000 --- a/include/asm-m32r/dma-mapping.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_M32R_DMA_MAPPING_H -#define _ASM_M32R_DMA_MAPPING_H - -#include <asm-generic/dma-mapping-broken.h> - -#endif /* _ASM_M32R_DMA_MAPPING_H */ diff --git a/include/asm-m32r/ioctls.h b/include/asm-m32r/ioctls.h index d23cfc45738a..b9f54bb5d7cf 100644 --- a/include/asm-m32r/ioctls.h +++ b/include/asm-m32r/ioctls.h @@ -47,6 +47,10 @@ #define TIOCSBRK 0x5427 /* BSD compatibility */ #define TIOCCBRK 0x5428 /* BSD compatibility */ #define TIOCGSID 0x5429 /* Return the session ID of FD */ +#define TCGETS2 _IOR('T',0x2A, struct termios2) +#define TCSETS2 _IOW('T',0x2B, struct termios2) +#define TCSETSW2 _IOW('T',0x2C, struct termios2) +#define TCSETSF2 _IOW('T',0x2D, struct termios2) #define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ diff --git a/include/asm-m32r/pgtable.h b/include/asm-m32r/pgtable.h index 6604303fc47c..35af58c6b812 100644 --- a/include/asm-m32r/pgtable.h +++ b/include/asm-m32r/pgtable.h @@ -191,16 +191,6 @@ extern unsigned long empty_zero_page[1024]; * The following only work if pte_present() is true. * Undefined behaviour if not.. */ -static inline int pte_read(pte_t pte) -{ - return pte_val(pte) & _PAGE_READ; -} - -static inline int pte_exec(pte_t pte) -{ - return pte_val(pte) & _PAGE_EXEC; -} - static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; @@ -224,18 +214,6 @@ static inline int pte_file(pte_t pte) return pte_val(pte) & _PAGE_FILE; } -static inline pte_t pte_rdprotect(pte_t pte) -{ - pte_val(pte) &= ~_PAGE_READ; - return pte; -} - -static inline pte_t pte_exprotect(pte_t pte) -{ - pte_val(pte) &= ~_PAGE_EXEC; - return pte; -} - static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; @@ -254,18 +232,6 @@ static inline pte_t pte_wrprotect(pte_t pte) return pte; } -static inline pte_t pte_mkread(pte_t pte) -{ - pte_val(pte) |= _PAGE_READ; - return pte; -} - -static inline pte_t pte_mkexec(pte_t pte) -{ - pte_val(pte) |= _PAGE_EXEC; - return pte; -} - static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; diff --git a/include/asm-m32r/termbits.h b/include/asm-m32r/termbits.h index e402641dfbad..bc104008b55b 100644 --- a/include/asm-m32r/termbits.h +++ b/include/asm-m32r/termbits.h @@ -17,6 +17,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ @@ -129,6 +140,7 @@ struct ktermios { #define HUPCL 0002000 #define CLOCAL 0004000 #define CBAUDEX 0010000 +#define BOTHER 0010000 #define B57600 0010001 #define B115200 0010002 #define B230400 0010003 @@ -144,11 +156,13 @@ struct ktermios { #define B3000000 0010015 #define B3500000 0010016 #define B4000000 0010017 -#define CIBAUD 002003600000 /* input baud rate (not used) */ +#define CIBAUD 002003600000 /** input baud rate */ #define CTVB 004000000000 /* VisioBraille Terminal flow control */ #define CMSPAR 010000000000 /* mark or space (stick) parity */ #define CRTSCTS 020000000000 /* flow control */ +#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ + /* c_lflag bits */ #define ISIG 0000001 #define ICANON 0000002 diff --git a/include/asm-m32r/termios.h b/include/asm-m32r/termios.h index 4943dd8db44d..93ce79fd342a 100644 --- a/include/asm-m32r/termios.h +++ b/include/asm-m32r/termios.h @@ -81,8 +81,10 @@ struct termio { copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ }) -#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) -#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) +#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) +#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) +#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) +#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) #endif /* __KERNEL__ */ diff --git a/include/asm-m68k/atari_SLM.h b/include/asm-m68k/atari_SLM.h deleted file mode 100644 index 42f4fcdd8bc7..000000000000 --- a/include/asm-m68k/atari_SLM.h +++ /dev/null @@ -1,28 +0,0 @@ - -#ifndef _ATARI_SLM_H -#define _ATARI_SLM_H - -/* Atari SLM laser printer specific ioctls */ - -#define SLMIOGSTAT 0xa100 -#define SLMIOGPSIZE 0xa101 -#define SLMIOGMFEED 0xa102 - -#define SLMIORESET 0xa140 - -#define SLMIOSPSIZE 0xa181 -#define SLMIOSMFEED 0xa182 - -/* Status returning structure (SLMIOGSTAT) */ -struct SLM_status { - int stat; /* numeric status code */ - char str[40]; /* status string */ -}; - -/* Paper size structure (SLMIO[GS]PSIZE) */ -struct SLM_paper_size { - int width; - int height; -}; - -#endif /* _ATARI_SLM_H */ diff --git a/include/asm-m68k/atari_acsi.h b/include/asm-m68k/atari_acsi.h deleted file mode 100644 index 10fea68f191a..000000000000 --- a/include/asm-m68k/atari_acsi.h +++ /dev/null @@ -1,37 +0,0 @@ -#ifndef _ASM_ATARI_ACSI_H -#define _ASM_ATARI_ACSI_H - -/* Functions exported by drivers/block/acsi.c */ - -void acsi_delay_start( void ); -void acsi_delay_end( long usec ); -int acsi_wait_for_IRQ( unsigned timeout ); -int acsi_wait_for_noIRQ( unsigned timeout ); -int acsicmd_nodma( const char *cmd, int enable); -int acsi_getstatus( void ); -int acsi_extstatus( char *buffer, int cnt ); -void acsi_end_extstatus( void ); -int acsi_extcmd( unsigned char *buffer, int cnt ); - -/* The ACSI buffer is guarantueed to reside in ST-RAM and may be used by other - * drivers that work on the ACSI bus, too. It's data are valid only as long as - * the ST-DMA is locked. */ -extern char *acsi_buffer; -extern unsigned long phys_acsi_buffer; - -/* Utility macros */ - -/* Send one data byte over the bus and set mode for next operation - * with one move.l -- Atari recommends this... - */ - -#define DMA_LONG_WRITE(data,mode) \ - do { \ - *((unsigned long *)&dma_wd.fdc_acces_seccount) = \ - ((data)<<16) | (mode); \ - } while(0) - -#define ENABLE_IRQ() atari_turnon_irq( IRQ_MFP_ACSI ) -#define DISABLE_IRQ() atari_turnoff_irq( IRQ_MFP_ACSI ) - -#endif /* _ASM_ATARI_ACSI_H */ diff --git a/include/asm-m68k/motorola_pgtable.h b/include/asm-m68k/motorola_pgtable.h index b5b78c01eb6c..d029b75bcf04 100644 --- a/include/asm-m68k/motorola_pgtable.h +++ b/include/asm-m68k/motorola_pgtable.h @@ -164,21 +164,15 @@ static inline void pgd_set(pgd_t *pgdp, pmd_t *pmdp) * The following only work if pte_present() is true. * Undefined behaviour if not.. */ -static inline int pte_read(pte_t pte) { return 1; } static inline int pte_write(pte_t pte) { return !(pte_val(pte) & _PAGE_RONLY); } -static inline int pte_exec(pte_t pte) { return 1; } static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) |= _PAGE_RONLY; return pte; } -static inline pte_t pte_rdprotect(pte_t pte) { return pte; } -static inline pte_t pte_exprotect(pte_t pte) { return pte; } static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; } static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) &= ~_PAGE_RONLY; return pte; } -static inline pte_t pte_mkread(pte_t pte) { return pte; } -static inline pte_t pte_mkexec(pte_t pte) { return pte; } static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; } static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; } static inline pte_t pte_mknocache(pte_t pte) diff --git a/include/asm-m68k/pci.h b/include/asm-m68k/pci.h index 9d2c07abe44f..678cb0b52314 100644 --- a/include/asm-m68k/pci.h +++ b/include/asm-m68k/pci.h @@ -54,8 +54,4 @@ static inline void pcibios_penalize_isa_irq(int irq, int active) */ #define PCI_DMA_BUS_IS_PHYS (1) -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #endif /* _ASM_M68K_PCI_H */ diff --git a/include/asm-m68k/sun3_pgtable.h b/include/asm-m68k/sun3_pgtable.h index b9e62c1e7ae3..b766fc261bde 100644 --- a/include/asm-m68k/sun3_pgtable.h +++ b/include/asm-m68k/sun3_pgtable.h @@ -165,21 +165,15 @@ static inline void pgd_clear (pgd_t *pgdp) {} * Undefined behaviour if not... * [we have the full set here even if they don't change from m68k] */ -static inline int pte_read(pte_t pte) { return 1; } static inline int pte_write(pte_t pte) { return pte_val(pte) & SUN3_PAGE_WRITEABLE; } -static inline int pte_exec(pte_t pte) { return 1; } static inline int pte_dirty(pte_t pte) { return pte_val(pte) & SUN3_PAGE_MODIFIED; } static inline int pte_young(pte_t pte) { return pte_val(pte) & SUN3_PAGE_ACCESSED; } static inline int pte_file(pte_t pte) { return pte_val(pte) & SUN3_PAGE_ACCESSED; } static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~SUN3_PAGE_WRITEABLE; return pte; } -static inline pte_t pte_rdprotect(pte_t pte) { return pte; } -static inline pte_t pte_exprotect(pte_t pte) { return pte; } static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~SUN3_PAGE_MODIFIED; return pte; } static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~SUN3_PAGE_ACCESSED; return pte; } static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= SUN3_PAGE_WRITEABLE; return pte; } -static inline pte_t pte_mkread(pte_t pte) { return pte; } -static inline pte_t pte_mkexec(pte_t pte) { return pte; } static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= SUN3_PAGE_MODIFIED; return pte; } static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= SUN3_PAGE_ACCESSED; return pte; } static inline pte_t pte_mknocache(pte_t pte) { pte_val(pte) |= SUN3_PAGE_NOCACHE; return pte; } diff --git a/include/asm-m68k/termbits.h b/include/asm-m68k/termbits.h index a194092240fb..0e520f328f53 100644 --- a/include/asm-m68k/termbits.h +++ b/include/asm-m68k/termbits.h @@ -17,6 +17,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-m68knommu/pci.h b/include/asm-m68knommu/pci.h index e04c77e1184d..a13f3cc87451 100644 --- a/include/asm-m68knommu/pci.h +++ b/include/asm-m68knommu/pci.h @@ -24,16 +24,6 @@ static inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask) return 1; } -/* - * Not supporting more than 32-bit PCI bus addresses now, but - * must satisfy references to this function. Change if needed. - */ -#define pci_dac_dma_supported(pci_dev, mask) (0) - -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #endif /* CONFIG_COMEMPCI */ #endif /* M68KNOMMU_PCI_H */ diff --git a/include/asm-mips/compat.h b/include/asm-mips/compat.h index 432653d7ae09..568c76cdd900 100644 --- a/include/asm-mips/compat.h +++ b/include/asm-mips/compat.h @@ -37,8 +37,10 @@ typedef s32 compat_key_t; typedef s32 compat_int_t; typedef s32 compat_long_t; +typedef s64 compat_s64; typedef u32 compat_uint_t; typedef u32 compat_ulong_t; +typedef u64 compat_u64; struct compat_timespec { compat_time_t tv_sec; @@ -132,7 +134,8 @@ typedef u32 compat_uptr_t; static inline void __user *compat_ptr(compat_uptr_t uptr) { - return (void __user *)(long)uptr; + /* cast to a __user pointer via "unsigned long" makes sparse happy */ + return (void __user *)(unsigned long)(long)uptr; } static inline compat_uptr_t ptr_to_compat(void __user *uptr) diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index 12bcc1f9fba9..7ba92890ea13 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -212,7 +212,8 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, */ if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) && flags == _CACHE_UNCACHED) - return (void __iomem *)CKSEG1ADDR(phys_addr); + return (void __iomem *) + (unsigned long)CKSEG1ADDR(phys_addr); } return __ioremap(offset, size, flags); diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h index 3ca6a076124d..97102ebc54b1 100644 --- a/include/asm-mips/irq.h +++ b/include/asm-mips/irq.h @@ -24,7 +24,7 @@ static inline int irq_canonicalize(int irq) #define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ #endif -#ifdef CONFIG_MIPS_MT_SMTC +#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP /* * Clear interrupt mask handling "backstop" if irq_hwmask * entry so indicates. This implies that the ack() or end() diff --git a/include/asm-mips/mach-tx49xx/ioremap.h b/include/asm-mips/mach-tx49xx/ioremap.h index 88cf546719b8..1e7beae72229 100644 --- a/include/asm-mips/mach-tx49xx/ioremap.h +++ b/include/asm-mips/mach-tx49xx/ioremap.h @@ -36,7 +36,8 @@ static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, static inline int plat_iounmap(const volatile void __iomem *addr) { - return (unsigned long)addr >= (unsigned long)(int)TXX9_DIRECTMAP_BASE; + return (unsigned long)addr >= + (unsigned long)(int)(TXX9_DIRECTMAP_BASE & 0xffffffff); } #endif /* __ASM_MACH_TX49XX_IOREMAP_H */ diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 706b3691f57e..18f47f1e8cd5 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -707,10 +707,10 @@ do { \ */ #define __read_64bit_c0_split(source, sel) \ ({ \ - unsigned long long val; \ - unsigned long flags; \ + unsigned long long __val; \ + unsigned long __flags; \ \ - local_irq_save(flags); \ + local_irq_save(__flags); \ if (sel == 0) \ __asm__ __volatile__( \ ".set\tmips64\n\t" \ @@ -719,7 +719,7 @@ do { \ "dsrl\t%M0, %M0, 32\n\t" \ "dsrl\t%L0, %L0, 32\n\t" \ ".set\tmips0" \ - : "=r" (val)); \ + : "=r" (__val)); \ else \ __asm__ __volatile__( \ ".set\tmips64\n\t" \ @@ -728,17 +728,17 @@ do { \ "dsrl\t%M0, %M0, 32\n\t" \ "dsrl\t%L0, %L0, 32\n\t" \ ".set\tmips0" \ - : "=r" (val)); \ - local_irq_restore(flags); \ + : "=r" (__val)); \ + local_irq_restore(__flags); \ \ - val; \ + __val; \ }) #define __write_64bit_c0_split(source, sel, val) \ do { \ - unsigned long flags; \ + unsigned long __flags; \ \ - local_irq_save(flags); \ + local_irq_save(__flags); \ if (sel == 0) \ __asm__ __volatile__( \ ".set\tmips64\n\t" \ @@ -759,7 +759,7 @@ do { \ "dmtc0\t%L0, " #source ", " #sel "\n\t" \ ".set\tmips0" \ : : "r" (val)); \ - local_irq_restore(flags); \ + local_irq_restore(__flags); \ } while (0) #define read_c0_index() __read_32bit_c0_register($0, 0) diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h index a59d54749eef..4fcc185cb2d1 100644 --- a/include/asm-mips/pci.h +++ b/include/asm-mips/pci.h @@ -121,20 +121,6 @@ extern unsigned int PCI_DMA_BUS_IS_PHYS; #endif /* CONFIG_DMA_NEED_PCI_MAP_STATE */ -/* This is always fine. */ -#define pci_dac_dma_supported(pci_dev, mask) (1) - -extern dma64_addr_t pci_dac_page_to_dma(struct pci_dev *pdev, - struct page *page, unsigned long offset, int direction); -extern struct page *pci_dac_dma_to_page(struct pci_dev *pdev, - dma64_addr_t dma_addr); -extern unsigned long pci_dac_dma_to_offset(struct pci_dev *pdev, - dma64_addr_t dma_addr); -extern void pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, - dma64_addr_t dma_addr, size_t len, int direction); -extern void pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, - dma64_addr_t dma_addr, size_t len, int direction); - #ifdef CONFIG_PCI static inline void pci_dma_burst_advice(struct pci_dev *pdev, enum pci_dma_burst_strategy *strat, @@ -181,10 +167,6 @@ static inline int pci_proc_domain(struct pci_bus *bus) /* implement the pci_ DMA API in terms of the generic device dma_ one */ #include <asm-generic/pci-dma-compat.h> -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - /* Do platform specific device initialization at pci_enable_device() time */ extern int pcibios_plat_dev_init(struct pci_dev *dev); diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h index 27d77d981937..2e2d70d13ff6 100644 --- a/include/asm-mips/pgtable.h +++ b/include/asm-mips/pgtable.h @@ -178,9 +178,7 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; * The following only work if pte_present() is true. * Undefined behaviour if not.. */ -static inline int pte_user(pte_t pte) { BUG(); return 0; } #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) -static inline int pte_read(pte_t pte) { return pte.pte_low & _PAGE_READ; } static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; } static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; } static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; } @@ -193,13 +191,6 @@ static inline pte_t pte_wrprotect(pte_t pte) return pte; } -static inline pte_t pte_rdprotect(pte_t pte) -{ - pte.pte_low &= ~(_PAGE_READ | _PAGE_SILENT_READ); - pte.pte_high &= ~_PAGE_SILENT_READ; - return pte; -} - static inline pte_t pte_mkclean(pte_t pte) { pte.pte_low &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE); @@ -224,16 +215,6 @@ static inline pte_t pte_mkwrite(pte_t pte) return pte; } -static inline pte_t pte_mkread(pte_t pte) -{ - pte.pte_low |= _PAGE_READ; - if (pte.pte_low & _PAGE_ACCESSED) { - pte.pte_low |= _PAGE_SILENT_READ; - pte.pte_high |= _PAGE_SILENT_READ; - } - return pte; -} - static inline pte_t pte_mkdirty(pte_t pte) { pte.pte_low |= _PAGE_MODIFIED; @@ -253,7 +234,6 @@ static inline pte_t pte_mkyoung(pte_t pte) return pte; } #else -static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; } static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; } static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } @@ -265,12 +245,6 @@ static inline pte_t pte_wrprotect(pte_t pte) return pte; } -static inline pte_t pte_rdprotect(pte_t pte) -{ - pte_val(pte) &= ~(_PAGE_READ | _PAGE_SILENT_READ); - return pte; -} - static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE); @@ -291,14 +265,6 @@ static inline pte_t pte_mkwrite(pte_t pte) return pte; } -static inline pte_t pte_mkread(pte_t pte) -{ - pte_val(pte) |= _PAGE_READ; - if (pte_val(pte) & _PAGE_ACCESSED) - pte_val(pte) |= _PAGE_SILENT_READ; - return pte; -} - static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_MODIFIED; diff --git a/include/asm-mips/rtc.h b/include/asm-mips/rtc.h deleted file mode 100644 index 82ad401c7dca..000000000000 --- a/include/asm-mips/rtc.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * include/asm-mips/rtc.h - * - * (Really an interface for drivers/char/genrtc.c) - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * Please read the COPYING file for all license details. - */ - -#ifndef _MIPS_RTC_H -#define _MIPS_RTC_H - -#ifdef __KERNEL__ - -#include <linux/rtc.h> -#include <asm/time.h> - -#define RTC_PIE 0x40 /* periodic interrupt enable */ -#define RTC_AIE 0x20 /* alarm interrupt enable */ -#define RTC_UIE 0x10 /* update-finished interrupt enable */ - -/* some dummy definitions */ -#define RTC_BATT_BAD 0x100 /* battery bad */ -#define RTC_SQWE 0x08 /* enable square-wave output */ -#define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ -#define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ -#define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ - -static inline unsigned int get_rtc_time(struct rtc_time *time) -{ - unsigned long nowtime; - - nowtime = rtc_mips_get_time(); - to_tm(nowtime, time); - time->tm_year -= 1900; - - return RTC_24H; -} - -static inline int set_rtc_time(struct rtc_time *time) -{ - unsigned long nowtime; - int ret; - - nowtime = mktime(time->tm_year+1900, time->tm_mon+1, - time->tm_mday, time->tm_hour, time->tm_min, - time->tm_sec); - ret = rtc_mips_set_time(nowtime); - - return ret; -} - -static inline unsigned int get_rtc_ss(void) -{ - struct rtc_time h; - - get_rtc_time(&h); - return h.tm_sec; -} - -static inline int get_rtc_pll(struct rtc_pll_info *pll) -{ - return -EINVAL; -} - -static inline int set_rtc_pll(struct rtc_pll_info *pll) -{ - return -EINVAL; -} -#endif -#endif diff --git a/include/asm-mips/termbits.h b/include/asm-mips/termbits.h index 0bbe07b42a07..5bfdc3b64510 100644 --- a/include/asm-mips/termbits.h +++ b/include/asm-mips/termbits.h @@ -30,6 +30,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-mips/tlbdebug.h b/include/asm-mips/tlbdebug.h index fff7a73e22d0..bb8f5c29c3d9 100644 --- a/include/asm-mips/tlbdebug.h +++ b/include/asm-mips/tlbdebug.h @@ -11,10 +11,6 @@ /* * TLB debugging functions: */ -extern void dump_tlb(int first, int last); extern void dump_tlb_all(void); -extern void dump_tlb_wired(void); -extern void dump_tlb_addr(unsigned long addr); -extern void dump_tlb_nonwired(void); #endif /* __ASM_TLBDEBUG_H */ diff --git a/include/asm-mips/vr41xx/giu.h b/include/asm-mips/vr41xx/giu.h index 8109cda557dc..0bcdd3a5c256 100644 --- a/include/asm-mips/vr41xx/giu.h +++ b/include/asm-mips/vr41xx/giu.h @@ -20,6 +20,15 @@ #ifndef __NEC_VR41XX_GIU_H #define __NEC_VR41XX_GIU_H +/* + * NEC VR4100 series GIU platform device IDs. + */ +enum { + GPIO_50PINS_PULLUPDOWN, + GPIO_36PINS, + GPIO_48PINS_EDGE_SELECT, +}; + typedef enum { IRQ_TRIGGER_LEVEL, IRQ_TRIGGER_EDGE, diff --git a/include/asm-mips/vr41xx/siu.h b/include/asm-mips/vr41xx/siu.h index 1fcf6e8082b4..98cdb4096485 100644 --- a/include/asm-mips/vr41xx/siu.h +++ b/include/asm-mips/vr41xx/siu.h @@ -20,6 +20,8 @@ #ifndef __NEC_VR41XX_SIU_H #define __NEC_VR41XX_SIU_H +#define SIU_PORTS_MAX 2 + typedef enum { SIU_INTERFACE_RS232C, SIU_INTERFACE_IRDA, diff --git a/include/asm-parisc/compat.h b/include/asm-parisc/compat.h index 11f4222597a0..5a85d1b025c8 100644 --- a/include/asm-parisc/compat.h +++ b/include/asm-parisc/compat.h @@ -31,8 +31,10 @@ typedef s32 compat_timer_t; typedef s32 compat_int_t; typedef s32 compat_long_t; +typedef s64 compat_s64; typedef u32 compat_uint_t; typedef u32 compat_ulong_t; +typedef u64 compat_u64; struct compat_timespec { compat_time_t tv_sec; diff --git a/include/asm-parisc/fcntl.h b/include/asm-parisc/fcntl.h index 317851fa78f3..1e1c824764ee 100644 --- a/include/asm-parisc/fcntl.h +++ b/include/asm-parisc/fcntl.h @@ -3,21 +3,22 @@ /* open/fcntl - O_SYNC is only implemented on blocks devices and on files located on an ext2 file system */ -#define O_APPEND 00000010 -#define O_BLKSEEK 00000100 /* HPUX only */ -#define O_CREAT 00000400 /* not fcntl */ -#define O_EXCL 00002000 /* not fcntl */ -#define O_LARGEFILE 00004000 -#define O_SYNC 00100000 -#define O_NONBLOCK 00200004 /* HPUX has separate NDELAY & NONBLOCK */ -#define O_NOCTTY 00400000 /* not fcntl */ -#define O_DSYNC 01000000 /* HPUX only */ -#define O_RSYNC 02000000 /* HPUX only */ -#define O_NOATIME 04000000 +#define O_APPEND 000000010 +#define O_BLKSEEK 000000100 /* HPUX only */ +#define O_CREAT 000000400 /* not fcntl */ +#define O_EXCL 000002000 /* not fcntl */ +#define O_LARGEFILE 000004000 +#define O_SYNC 000100000 +#define O_NONBLOCK 000200004 /* HPUX has separate NDELAY & NONBLOCK */ +#define O_NOCTTY 000400000 /* not fcntl */ +#define O_DSYNC 001000000 /* HPUX only */ +#define O_RSYNC 002000000 /* HPUX only */ +#define O_NOATIME 004000000 +#define O_CLOEXEC 010000000 /* set close_on_exec */ -#define O_DIRECTORY 00010000 /* must be a directory */ -#define O_NOFOLLOW 00000200 /* don't follow links */ -#define O_INVISIBLE 04000000 /* invisible I/O, for DMAPI/XDSM */ +#define O_DIRECTORY 000010000 /* must be a directory */ +#define O_NOFOLLOW 000000200 /* don't follow links */ +#define O_INVISIBLE 004000000 /* invisible I/O, for DMAPI/XDSM */ #define F_GETLK64 8 #define F_SETLK64 9 diff --git a/include/asm-parisc/pci.h b/include/asm-parisc/pci.h index 7b3be9ac0dda..61fbd57a8323 100644 --- a/include/asm-parisc/pci.h +++ b/include/asm-parisc/pci.h @@ -238,9 +238,6 @@ extern inline void pcibios_register_hba(struct pci_hba_data *x) #define PCIBIOS_MIN_IO 0x10 #define PCIBIOS_MIN_MEM 0x1000 /* NBPG - but pci/setup-res.c dies */ -/* Don't support DAC yet. */ -#define pci_dac_dma_supported(pci_dev, mask) (0) - /* export the pci_ DMA API in terms of the dma_ one */ #include <asm-generic/pci-dma-compat.h> @@ -284,10 +281,6 @@ pcibios_select_root(struct pci_dev *pdev, struct resource *res) return root; } -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - static inline void pcibios_penalize_isa_irq(int irq, int active) { /* We don't need to penalize isa irq's */ diff --git a/include/asm-parisc/pgtable.h b/include/asm-parisc/pgtable.h index beb2adb979d9..7e222c8ba739 100644 --- a/include/asm-parisc/pgtable.h +++ b/include/asm-parisc/pgtable.h @@ -335,18 +335,14 @@ extern inline void pgd_clear(pgd_t * pgdp) { } * The following only work if pte_present() is true. * Undefined behaviour if not.. */ -extern inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; } extern inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } extern inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } extern inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } extern inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } -extern inline int pte_user(pte_t pte) { return pte_val(pte) & _PAGE_USER; } -extern inline pte_t pte_rdprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_READ; return pte; } extern inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; } extern inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } extern inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_WRITE; return pte; } -extern inline pte_t pte_mkread(pte_t pte) { pte_val(pte) |= _PAGE_READ; return pte; } extern inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; } extern inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; } extern inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return pte; } diff --git a/include/asm-parisc/termbits.h b/include/asm-parisc/termbits.h index a46e299a9391..e847fe979684 100644 --- a/include/asm-parisc/termbits.h +++ b/include/asm-parisc/termbits.h @@ -17,6 +17,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-powerpc/compat.h b/include/asm-powerpc/compat.h index aacaabd28ac1..64ab1ddbdf85 100644 --- a/include/asm-powerpc/compat.h +++ b/include/asm-powerpc/compat.h @@ -33,8 +33,10 @@ typedef s32 compat_timer_t; typedef s32 compat_int_t; typedef s32 compat_long_t; +typedef s64 compat_s64; typedef u32 compat_uint_t; typedef u32 compat_ulong_t; +typedef u64 compat_u64; struct compat_timespec { compat_time_t tv_sec; diff --git a/include/asm-powerpc/dma-mapping.h b/include/asm-powerpc/dma-mapping.h index a19a6f1a1cf1..f6bd804d9090 100644 --- a/include/asm-powerpc/dma-mapping.h +++ b/include/asm-powerpc/dma-mapping.h @@ -61,7 +61,6 @@ struct dma_mapping_ops { void (*unmap_sg)(struct device *dev, struct scatterlist *sg, int nents, enum dma_data_direction direction); int (*dma_supported)(struct device *dev, u64 mask); - int (*dac_dma_supported)(struct device *dev, u64 mask); int (*set_dma_mask)(struct device *dev, u64 dma_mask); }; diff --git a/include/asm-powerpc/pci.h b/include/asm-powerpc/pci.h index ce0f13e8eb14..e16e7bc9ab5c 100644 --- a/include/asm-powerpc/pci.h +++ b/include/asm-powerpc/pci.h @@ -74,18 +74,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) extern void set_pci_dma_ops(struct dma_mapping_ops *dma_ops); extern struct dma_mapping_ops *get_pci_dma_ops(void); -/* For DAC DMA, we currently don't support it by default, but - * we let 64-bit platforms override this. - */ -static inline int pci_dac_dma_supported(struct pci_dev *hwdev,u64 mask) -{ - struct dma_mapping_ops *d = get_pci_dma_ops(); - - if (d && d->dac_dma_supported) - return d->dac_dma_supported(&hwdev->dev, mask); - return 0; -} - static inline void pci_dma_burst_advice(struct pci_dev *pdev, enum pci_dma_burst_strategy *strat, unsigned long *strategy_parameter) @@ -124,12 +112,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, } #endif -/* - * At present there are very few 32-bit PPC machines that can have - * memory above the 4GB point, and we don't support that. - */ -#define pci_dac_dma_supported(pci_dev, mask) (0) - /* Return the index of the PCI controller for device PDEV. */ #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index @@ -243,8 +225,6 @@ extern void of_scan_bus(struct device_node *node, struct pci_bus *bus); extern int pci_read_irq_line(struct pci_dev *dev); -extern void pcibios_add_platform_entries(struct pci_dev *dev); - struct file; extern pgprot_t pci_phys_mem_access_prot(struct file *file, unsigned long pfn, diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h index 7fb730c62f83..973c1c13bdc0 100644 --- a/include/asm-powerpc/pgtable-ppc32.h +++ b/include/asm-powerpc/pgtable-ppc32.h @@ -512,9 +512,7 @@ extern unsigned long empty_zero_page[1024]; * The following only work if pte_present() is true. * Undefined behaviour if not.. */ -static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; } static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; } -static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; } static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } @@ -522,21 +520,13 @@ static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; } static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; } -static inline pte_t pte_rdprotect(pte_t pte) { - pte_val(pte) &= ~_PAGE_USER; return pte; } static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; } -static inline pte_t pte_exprotect(pte_t pte) { - pte_val(pte) &= ~_PAGE_EXEC; return pte; } static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; } static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } -static inline pte_t pte_mkread(pte_t pte) { - pte_val(pte) |= _PAGE_USER; return pte; } -static inline pte_t pte_mkexec(pte_t pte) { - pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; } static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_RW; return pte; } static inline pte_t pte_mkdirty(pte_t pte) { diff --git a/include/asm-powerpc/pgtable-ppc64.h b/include/asm-powerpc/pgtable-ppc64.h index 3cfd98f44bfe..0c879121c8fc 100644 --- a/include/asm-powerpc/pgtable-ppc64.h +++ b/include/asm-powerpc/pgtable-ppc64.h @@ -232,9 +232,7 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) * The following only work if pte_present() is true. * Undefined behaviour if not.. */ -static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER;} static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW;} -static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC;} static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY;} static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED;} static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE;} @@ -242,20 +240,12 @@ static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE;} static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; } static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; } -static inline pte_t pte_rdprotect(pte_t pte) { - pte_val(pte) &= ~_PAGE_USER; return pte; } -static inline pte_t pte_exprotect(pte_t pte) { - pte_val(pte) &= ~_PAGE_EXEC; return pte; } static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~(_PAGE_RW); return pte; } static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~(_PAGE_DIRTY); return pte; } static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } -static inline pte_t pte_mkread(pte_t pte) { - pte_val(pte) |= _PAGE_USER; return pte; } -static inline pte_t pte_mkexec(pte_t pte) { - pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; } static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_RW; return pte; } static inline pte_t pte_mkdirty(pte_t pte) { diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h index 9d162028dab9..d2442cd72a59 100644 --- a/include/asm-ppc/pci.h +++ b/include/asm-ppc/pci.h @@ -102,12 +102,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, } #endif -/* - * At present there are very few 32-bit PPC machines that can have - * memory above the 4GB point, and we don't support that. - */ -#define pci_dac_dma_supported(pci_dev, mask) (0) - /* Return the index of the PCI controller for device PDEV. */ #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index @@ -145,8 +139,6 @@ pcibios_select_root(struct pci_dev *pdev, struct resource *res) return root; } -extern void pcibios_add_platform_entries(struct pci_dev *dev); - struct file; extern pgprot_t pci_phys_mem_access_prot(struct file *file, unsigned long pfn, diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h index 9d0ce9ff5840..18aa776313b9 100644 --- a/include/asm-ppc/pgtable.h +++ b/include/asm-ppc/pgtable.h @@ -533,9 +533,7 @@ static inline int pgd_present(pgd_t pgd) { return 1; } * The following only work if pte_present() is true. * Undefined behaviour if not.. */ -static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; } static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; } -static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; } static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } @@ -543,21 +541,13 @@ static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; } static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; } -static inline pte_t pte_rdprotect(pte_t pte) { - pte_val(pte) &= ~_PAGE_USER; return pte; } static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; } -static inline pte_t pte_exprotect(pte_t pte) { - pte_val(pte) &= ~_PAGE_EXEC; return pte; } static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; } static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } -static inline pte_t pte_mkread(pte_t pte) { - pte_val(pte) |= _PAGE_USER; return pte; } -static inline pte_t pte_mkexec(pte_t pte) { - pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; } static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_RW; return pte; } static inline pte_t pte_mkdirty(pte_t pte) { diff --git a/include/asm-s390/compat.h b/include/asm-s390/compat.h index 296f4f1a20e1..7f4ad623f7d5 100644 --- a/include/asm-s390/compat.h +++ b/include/asm-s390/compat.h @@ -60,8 +60,10 @@ typedef s32 compat_timer_t; typedef s32 compat_int_t; typedef s32 compat_long_t; +typedef s64 compat_s64; typedef u32 compat_uint_t; typedef u32 compat_ulong_t; +typedef u64 compat_u64; struct compat_timespec { compat_time_t tv_sec; diff --git a/include/asm-s390/dma-mapping.h b/include/asm-s390/dma-mapping.h deleted file mode 100644 index 3f8c12fde0f0..000000000000 --- a/include/asm-s390/dma-mapping.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * include/asm-s390/dma-mapping.h - * - * S390 version - * - * This file exists so that #include <dma-mapping.h> doesn't break anything. - */ - -#ifndef _ASM_DMA_MAPPING_H -#define _ASM_DMA_MAPPING_H - -#endif /* _ASM_DMA_MAPPING_H */ diff --git a/include/asm-s390/pgtable.h b/include/asm-s390/pgtable.h index 0a307bb2f353..26215a976127 100644 --- a/include/asm-s390/pgtable.h +++ b/include/asm-s390/pgtable.h @@ -530,14 +530,6 @@ static inline int pte_young(pte_t pte) return 0; } -static inline int pte_read(pte_t pte) -{ - /* All pages are readable since we don't use the fetch - * protection bit in the storage key. - */ - return 1; -} - /* * pgd/pmd/pte modification functions */ diff --git a/include/asm-s390/termbits.h b/include/asm-s390/termbits.h index 585c78a6e407..811b9a9cdc08 100644 --- a/include/asm-s390/termbits.h +++ b/include/asm-s390/termbits.h @@ -25,6 +25,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-sh/bugs.h b/include/asm-sh/bugs.h index 5a117ec43c77..aeee8da9c54f 100644 --- a/include/asm-sh/bugs.h +++ b/include/asm-sh/bugs.h @@ -22,7 +22,7 @@ static void __init check_bugs(void) current_cpu_data.loops_per_jiffy = loops_per_jiffy; switch (current_cpu_data.type) { - case CPU_SH7604 ... CPU_SH7619: + case CPU_SH7619: *p++ = '2'; break; case CPU_SH7206: @@ -35,7 +35,7 @@ static void __init check_bugs(void) case CPU_SH7750 ... CPU_SH4_501: *p++ = '4'; break; - case CPU_SH7770 ... CPU_SH7785: + case CPU_SH7770 ... CPU_SHX3: *p++ = '4'; *p++ = 'a'; break; diff --git a/include/asm-sh/cache.h b/include/asm-sh/cache.h index 9a3cb6ba9d15..7a18649d1ccb 100644 --- a/include/asm-sh/cache.h +++ b/include/asm-sh/cache.h @@ -9,6 +9,7 @@ #define __ASM_SH_CACHE_H #ifdef __KERNEL__ +#include <linux/init.h> #include <asm/cpu/cache.h> #define SH_CACHE_VALID 1 @@ -48,6 +49,9 @@ struct cache_info { unsigned long flags; }; + +int __init detect_cpu_and_cache_system(void); + #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ #endif /* __ASM_SH_CACHE_H */ diff --git a/include/asm-sh/cpu-sh2/cache.h b/include/asm-sh/cpu-sh2/cache.h index 20b9796842dc..f02ba7a672b2 100644 --- a/include/asm-sh/cpu-sh2/cache.h +++ b/include/asm-sh/cpu-sh2/cache.h @@ -12,23 +12,7 @@ #define L1_CACHE_SHIFT 4 -#if defined(CONFIG_CPU_SUBTYPE_SH7604) -#define CCR 0xfffffe92 /* Address of Cache Control Register */ - -#define CCR_CACHE_CE 0x01 /* Cache enable */ -#define CCR_CACHE_ID 0x02 /* Instruction Replacement disable */ -#define CCR_CACHE_OD 0x04 /* Data Replacement disable */ -#define CCR_CACHE_TW 0x08 /* Two-way mode */ -#define CCR_CACHE_CP 0x10 /* Cache purge */ - -#define CACHE_OC_ADDRESS_ARRAY 0x60000000 - -#define CCR_CACHE_ENABLE CCR_CACHE_CE -#define CCR_CACHE_INVALIDATE CCR_CACHE_CP -#define CCR_CACHE_ORA CCR_CACHE_TW -#define CCR_CACHE_WT 0x00 /* SH-2 is _always_ write-through */ - -#elif defined(CONFIG_CPU_SUBTYPE_SH7619) +#if defined(CONFIG_CPU_SUBTYPE_SH7619) #define CCR1 0xffffffec #define CCR CCR1 @@ -49,5 +33,5 @@ #define CCR_CACHE_ENABLE CCR_CACHE_CE #define CCR_CACHE_INVALIDATE CCR_CACHE_CF #endif -#endif /* __ASM_CPU_SH2_CACHE_H */ +#endif /* __ASM_CPU_SH2_CACHE_H */ diff --git a/include/asm-sh/cpu-sh3/timer.h b/include/asm-sh/cpu-sh3/timer.h index b2394cf76f49..4928b08f9d19 100644 --- a/include/asm-sh/cpu-sh3/timer.h +++ b/include/asm-sh/cpu-sh3/timer.h @@ -29,7 +29,7 @@ #endif #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710) -#define TMU_TSTR 0xa412fe92 /* Byte access */ +#define TMU_012_TSTR 0xa412fe92 /* Byte access */ #define TMU0_TCOR 0xa412fe94 /* Long access */ #define TMU0_TCNT 0xa412fe98 /* Long access */ @@ -44,7 +44,7 @@ #define TMU2_TCR 0xa412feb4 /* Word access */ #else -#define TMU_TSTR 0xfffffe92 /* Byte access */ +#define TMU_012_TSTR 0xfffffe92 /* Byte access */ #define TMU0_TCOR 0xfffffe94 /* Long access */ #define TMU0_TCNT 0xfffffe98 /* Long access */ diff --git a/include/asm-sh/cpu-sh4/freq.h b/include/asm-sh/cpu-sh4/freq.h index 39f41fcd509d..026025b51cea 100644 --- a/include/asm-sh/cpu-sh4/freq.h +++ b/include/asm-sh/cpu-sh4/freq.h @@ -22,6 +22,8 @@ #define FRQCR0 0xffc80000 #define FRQCR1 0xffc80004 #define FRQMR1 0xffc80014 +#elif defined(CONFIG_CPU_SUBTYPE_SHX3) +#define FRQCR 0xffc00014 #else #define FRQCR 0xffc00000 #define FRQCR_PSTBY 0x0200 diff --git a/include/asm-sh/cpu-sh4/timer.h b/include/asm-sh/cpu-sh4/timer.h index 8a4af126c890..d1e796b96888 100644 --- a/include/asm-sh/cpu-sh4/timer.h +++ b/include/asm-sh/cpu-sh4/timer.h @@ -1,7 +1,7 @@ /* * include/asm-sh/cpu-sh4/timer.h * - * Copyright (C) 2004 Lineo Solutions, Inc. + * Copyright (C) 2004 Lineo Solutions, Inc. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -16,36 +16,45 @@ * SH7750S/SH7750R * SH7751/SH7751R * SH7760 + * SH-X3 * --------------------------------------------------------------------------- */ - -#if !defined(CONFIG_CPU_SUBTYPE_SH7760) -#define TMU_TOCR 0xffd80000 /* Byte access */ +#ifdef CONFIG_CPU_SUBTYPE_SHX3 +#define TMU_012_BASE 0xffc10000 +#define TMU_345_BASE 0xffc20000 +#else +#define TMU_012_BASE 0xffd80000 +#define TMU_345_BASE 0xfe100000 #endif -#define TMU_TSTR 0xffd80004 /* Byte access */ -#define TMU0_TCOR 0xffd80008 /* Long access */ -#define TMU0_TCNT 0xffd8000c /* Long access */ -#define TMU0_TCR 0xffd80010 /* Word access */ +#define TMU_TOCR TMU_012_BASE /* Not supported on all CPUs */ -#define TMU1_TCOR 0xffd80014 /* Long access */ -#define TMU1_TCNT 0xffd80018 /* Long access */ -#define TMU1_TCR 0xffd8001c /* Word access */ +#define TMU_012_TSTR (TMU_012_BASE + 0x04) +#define TMU_345_TSTR (TMU_345_BASE + 0x04) -#define TMU2_TCOR 0xffd80020 /* Long access */ -#define TMU2_TCNT 0xffd80024 /* Long access */ -#define TMU2_TCR 0xffd80028 /* Word access */ -#define TMU2_TCPR 0xffd8002c /* Long access */ +#define TMU0_TCOR (TMU_012_BASE + 0x08) +#define TMU0_TCNT (TMU_012_BASE + 0x0c) +#define TMU0_TCR (TMU_012_BASE + 0x10) -#if !defined(CONFIG_CPU_SUBTYPE_SH7760) -#define TMU3_TCOR 0xfe100008 /* Long access */ -#define TMU3_TCNT 0xfe10000c /* Long access */ -#define TMU3_TCR 0xfe100010 /* Word access */ +#define TMU1_TCOR (TMU_012_BASE + 0x14) +#define TMU1_TCNT (TMU_012_BASE + 0x18) +#define TMU1_TCR (TMU_012_BASE + 0x1c) -#define TMU4_TCOR 0xfe100014 /* Long access */ -#define TMU4_TCNT 0xfe100018 /* Long access */ -#define TMU4_TCR 0xfe10001c /* Word access */ -#endif +#define TMU2_TCOR (TMU_012_BASE + 0x20) +#define TMU2_TCNT (TMU_012_BASE + 0x24) +#define TMU2_TCR (TMU_012_BASE + 0x28) +#define TMU2_TCPR (TMU_012_BASE + 0x2c) -#endif /* __ASM_CPU_SH4_TIMER_H */ +#define TMU3_TCOR (TMU_345_BASE + 0x08) +#define TMU3_TCNT (TMU_345_BASE + 0x0c) +#define TMU3_TCR (TMU_345_BASE + 0x10) +#define TMU4_TCOR (TMU_345_BASE + 0x14) +#define TMU4_TCNT (TMU_345_BASE + 0x18) +#define TMU4_TCR (TMU_345_BASE + 0x1c) + +#define TMU5_TCOR (TMU_345_BASE + 0x20) +#define TMU5_TCNT (TMU_345_BASE + 0x24) +#define TMU5_TCR (TMU_345_BASE + 0x28) + +#endif /* __ASM_CPU_SH4_TIMER_H */ diff --git a/include/asm-sh/futex-irq.h b/include/asm-sh/futex-irq.h new file mode 100644 index 000000000000..a9f16a7f9aea --- /dev/null +++ b/include/asm-sh/futex-irq.h @@ -0,0 +1,111 @@ +#ifndef __ASM_SH_FUTEX_IRQ_H +#define __ASM_SH_FUTEX_IRQ_H + +#include <asm/system.h> + +static inline int atomic_futex_op_xchg_set(int oparg, int __user *uaddr, + int *oldval) +{ + unsigned long flags; + int ret; + + local_irq_save(flags); + + ret = get_user(*oldval, uaddr); + if (!ret) + ret = put_user(oparg, uaddr); + + local_irq_restore(flags); + + return ret; +} + +static inline int atomic_futex_op_xchg_add(int oparg, int __user *uaddr, + int *oldval) +{ + unsigned long flags; + int ret; + + local_irq_save(flags); + + ret = get_user(*oldval, uaddr); + if (!ret) + ret = put_user(*oldval + oparg, uaddr); + + local_irq_restore(flags); + + return ret; +} + +static inline int atomic_futex_op_xchg_or(int oparg, int __user *uaddr, + int *oldval) +{ + unsigned long flags; + int ret; + + local_irq_save(flags); + + ret = get_user(*oldval, uaddr); + if (!ret) + ret = put_user(*oldval | oparg, uaddr); + + local_irq_restore(flags); + + return ret; +} + +static inline int atomic_futex_op_xchg_and(int oparg, int __user *uaddr, + int *oldval) +{ + unsigned long flags; + int ret; + + local_irq_save(flags); + + ret = get_user(*oldval, uaddr); + if (!ret) + ret = put_user(*oldval & oparg, uaddr); + + local_irq_restore(flags); + + return ret; +} + +static inline int atomic_futex_op_xchg_xor(int oparg, int __user *uaddr, + int *oldval) +{ + unsigned long flags; + int ret; + + local_irq_save(flags); + + ret = get_user(*oldval, uaddr); + if (!ret) + ret = put_user(*oldval ^ oparg, uaddr); + + local_irq_restore(flags); + + return ret; +} + +static inline int atomic_futex_op_cmpxchg_inatomic(int __user *uaddr, + int oldval, int newval) +{ + unsigned long flags; + int ret, prev = 0; + + local_irq_save(flags); + + ret = get_user(prev, uaddr); + if (!ret && oldval == prev) + ret = put_user(newval, uaddr); + + local_irq_restore(flags); + + if (ret) + return ret; + + return prev; +} + +#endif /* __ASM_SH_FUTEX_IRQ_H */ diff --git a/include/asm-sh/futex.h b/include/asm-sh/futex.h index 6a332a9f099c..74ed3681d33c 100644 --- a/include/asm-sh/futex.h +++ b/include/asm-sh/futex.h @@ -1,6 +1,77 @@ -#ifndef _ASM_FUTEX_H -#define _ASM_FUTEX_H +#ifndef __ASM_SH_FUTEX_H +#define __ASM_SH_FUTEX_H -#include <asm-generic/futex.h> +#ifdef __KERNEL__ -#endif +#include <linux/futex.h> +#include <asm/errno.h> +#include <asm/uaccess.h> + +/* XXX: UP variants, fix for SH-4A and SMP.. */ +#include <asm/futex-irq.h> + +static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr) +{ + int op = (encoded_op >> 28) & 7; + int cmp = (encoded_op >> 24) & 15; + int oparg = (encoded_op << 8) >> 20; + int cmparg = (encoded_op << 20) >> 20; + int oldval = 0, ret; + + if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) + oparg = 1 << oparg; + + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + return -EFAULT; + + pagefault_disable(); + + switch (op) { + case FUTEX_OP_SET: + ret = atomic_futex_op_xchg_set(oparg, uaddr, &oldval); + break; + case FUTEX_OP_ADD: + ret = atomic_futex_op_xchg_add(oparg, uaddr, &oldval); + break; + case FUTEX_OP_OR: + ret = atomic_futex_op_xchg_or(oparg, uaddr, &oldval); + break; + case FUTEX_OP_ANDN: + ret = atomic_futex_op_xchg_and(~oparg, uaddr, &oldval); + break; + case FUTEX_OP_XOR: + ret = atomic_futex_op_xchg_xor(oparg, uaddr, &oldval); + break; + default: + ret = -ENOSYS; + break; + } + + pagefault_enable(); + + if (!ret) { + switch (cmp) { + case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break; + case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break; + case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break; + case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break; + case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break; + case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break; + default: ret = -ENOSYS; + } + } + + return ret; +} + +static inline int +futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) +{ + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + return -EFAULT; + + return atomic_futex_op_cmpxchg_inatomic(uaddr, oldval, newval); +} + +#endif /* __KERNEL__ */ +#endif /* __ASM_SH_FUTEX_H */ diff --git a/include/asm-sh/hd64461.h b/include/asm-sh/hd64461.h index 27e5c34e2659..4dd8592ca014 100644 --- a/include/asm-sh/hd64461.h +++ b/include/asm-sh/hd64461.h @@ -1,200 +1,241 @@ #ifndef __ASM_SH_HD64461 #define __ASM_SH_HD64461 /* - * $Id: hd64461.h,v 1.5 2004/03/16 00:07:51 lethal Exp $ + * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com> + * Copyright (C) 2004 Paul Mundt * Copyright (C) 2000 YAEGASHI Takeshi - * Hitachi HD64461 companion chip support + * + * Hitachi HD64461 companion chip support + * (please note manual reference 0x10000000 = 0xb0000000) */ /* Constants for PCMCIA mappings */ -#define HD64461_PCC_WINDOW 0x01000000 - -#define HD64461_PCC0_BASE 0xb8000000 /* area 6 */ -#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) -#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) -#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) - -#define HD64461_PCC1_BASE 0xb4000000 /* area 5 */ -#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) -#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) - -#define HD64461_STBCR 0x10000 -#define HD64461_STBCR_CKIO_STBY 0x2000 -#define HD64461_STBCR_SAFECKE_IST 0x1000 -#define HD64461_STBCR_SLCKE_IST 0x0800 -#define HD64461_STBCR_SAFECKE_OST 0x0400 -#define HD64461_STBCR_SLCKE_OST 0x0200 -#define HD64461_STBCR_SMIAST 0x0100 -#define HD64461_STBCR_SLCDST 0x0080 -#define HD64461_STBCR_SPC0ST 0x0040 -#define HD64461_STBCR_SPC1ST 0x0020 -#define HD64461_STBCR_SAFEST 0x0010 -#define HD64461_STBCR_STM0ST 0x0008 -#define HD64461_STBCR_STM1ST 0x0004 -#define HD64461_STBCR_SIRST 0x0002 -#define HD64461_STBCR_SURTST 0x0001 - -#define HD64461_SYSCR 0x10002 -#define HD64461_SCPUCR 0x10004 - -#define HD64461_LCDCBAR 0x11000 -#define HD64461_LCDCLOR 0x11002 -#define HD64461_LCDCCR 0x11004 -#define HD64461_LCDCCR_STBACK 0x0400 -#define HD64461_LCDCCR_STREQ 0x0100 -#define HD64461_LCDCCR_MOFF 0x0080 -#define HD64461_LCDCCR_REFSEL 0x0040 -#define HD64461_LCDCCR_EPON 0x0020 -#define HD64461_LCDCCR_SPON 0x0010 - -#define HD64461_LDR1 0x11010 -#define HD64461_LDR1_DON 0x01 -#define HD64461_LDR1_DINV 0x80 - -#define HD64461_LDR2 0x11012 -#define HD64461_LDHNCR 0x11014 -#define HD64461_LDHNSR 0x11016 -#define HD64461_LDVNTR 0x11018 -#define HD64461_LDVNDR 0x1101a -#define HD64461_LDVSPR 0x1101c -#define HD64461_LDR3 0x1101e - -#define HD64461_CPTWAR 0x11030 -#define HD64461_CPTWDR 0x11032 -#define HD64461_CPTRAR 0x11034 -#define HD64461_CPTRDR 0x11036 - -#define HD64461_GRDOR 0x11040 -#define HD64461_GRSCR 0x11042 -#define HD64461_GRCFGR 0x11044 -#define HD64461_GRCFGR_ACCSTATUS 0x10 -#define HD64461_GRCFGR_ACCRESET 0x08 -#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 -#define HD64461_GRCFGR_ACCSTART_LINE 0x04 -#define HD64461_GRCFGR_COLORDEPTH16 0x01 - -#define HD64461_LNSARH 0x11046 -#define HD64461_LNSARL 0x11048 -#define HD64461_LNAXLR 0x1104a -#define HD64461_LNDGR 0x1104c -#define HD64461_LNAXR 0x1104e -#define HD64461_LNERTR 0x11050 -#define HD64461_LNMDR 0x11052 -#define HD64461_BBTSSARH 0x11054 -#define HD64461_BBTSSARL 0x11056 -#define HD64461_BBTDSARH 0x11058 -#define HD64461_BBTDSARL 0x1105a -#define HD64461_BBTDWR 0x1105c -#define HD64461_BBTDHR 0x1105e -#define HD64461_BBTPARH 0x11060 -#define HD64461_BBTPARL 0x11062 -#define HD64461_BBTMARH 0x11064 -#define HD64461_BBTMARL 0x11066 -#define HD64461_BBTROPR 0x11068 -#define HD64461_BBTMDR 0x1106a +#define HD64461_PCC_WINDOW 0x01000000 + +/* Area 6 - Slot 0 - memory and/or IO card */ +#define HD64461_PCC0_BASE (CONFIG_HD64461_IOBASE + 0x8000000) +#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */ +#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */ +#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */ + +/* Area 5 - Slot 1 - memory card only */ +#define HD64461_PCC1_BASE (CONFIG_HD64461_IOBASE + 0x4000000) +#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */ +#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */ + +/* Standby Control Register for HD64461 */ +#define HD64461_STBCR CONFIG_HD64461_IOBASE +#define HD64461_STBCR_CKIO_STBY 0x2000 +#define HD64461_STBCR_SAFECKE_IST 0x1000 +#define HD64461_STBCR_SLCKE_IST 0x0800 +#define HD64461_STBCR_SAFECKE_OST 0x0400 +#define HD64461_STBCR_SLCKE_OST 0x0200 +#define HD64461_STBCR_SMIAST 0x0100 +#define HD64461_STBCR_SLCDST 0x0080 +#define HD64461_STBCR_SPC0ST 0x0040 +#define HD64461_STBCR_SPC1ST 0x0020 +#define HD64461_STBCR_SAFEST 0x0010 +#define HD64461_STBCR_STM0ST 0x0008 +#define HD64461_STBCR_STM1ST 0x0004 +#define HD64461_STBCR_SIRST 0x0002 +#define HD64461_STBCR_SURTST 0x0001 + +/* System Configuration Register */ +#define HD64461_SYSCR (CONFIG_HD64461_IOBASE + 0x02) + +/* CPU Data Bus Control Register */ +#define HD64461_SCPUCR (CONFIG_HD64461_IOBASE + 0x04) + +/* Base Adress Register */ +#define HD64461_LCDCBAR (CONFIG_HD64461_IOBASE + 0x1000) + +/* Line increment adress */ +#define HD64461_LCDCLOR (CONFIG_HD64461_IOBASE + 0x1002) + +/* Controls LCD controller */ +#define HD64461_LCDCCR (CONFIG_HD64461_IOBASE + 0x1004) + +/* LCCDR control bits */ +#define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */ +#define HD64461_LCDCCR_STREQ 0x0100 /* Standby Request */ +#define HD64461_LCDCCR_MOFF 0x0080 /* Memory Off */ +#define HD64461_LCDCCR_REFSEL 0x0040 /* Refresh Select */ +#define HD64461_LCDCCR_EPON 0x0020 /* End Power On */ +#define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */ + +/* Controls LCD (1) */ +#define HD64461_LDR1 (CONFIG_HD64461_IOBASE + 0x1010) +#define HD64461_LDR1_DON 0x01 /* Display On */ +#define HD64461_LDR1_DINV 0x80 /* Display Invert */ + +/* Controls LCD (2) */ +#define HD64461_LDR2 (CONFIG_HD64461_IOBASE + 0x1012) +#define HD64461_LDHNCR (CONFIG_HD64461_IOBASE + 0x1014) /* Number of horizontal characters */ +#define HD64461_LDHNSR (CONFIG_HD64461_IOBASE + 0x1016) /* Specify output start position + width of CL1 */ +#define HD64461_LDVNTR (CONFIG_HD64461_IOBASE + 0x1018) /* Specify total vertical lines */ +#define HD64461_LDVNDR (CONFIG_HD64461_IOBASE + 0x101a) /* specify number of display vertical lines */ +#define HD64461_LDVSPR (CONFIG_HD64461_IOBASE + 0x101c) /* specify vertical synchronization pos and AC nr */ + +/* Controls LCD (3) */ +#define HD64461_LDR3 (CONFIG_HD64461_IOBASE + 0x101e) + +/* Palette Registers */ +#define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x1030) /* Color Palette Write Adress Register */ +#define HD64461_CPTWDR (CONFIG_HD64461_IOBASE + 0x1032) /* Color Palette Write Data Register */ +#define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x1034) /* Color Palette Read Adress Register */ +#define HD64461_CPTRDR (CONFIG_HD64461_IOBASE + 0x1036) /* Color Palette Read Data Register */ + +#define HD64461_GRDOR (CONFIG_HD64461_IOBASE + 0x1040) /* Display Resolution Offset Register */ +#define HD64461_GRSCR (CONFIG_HD64461_IOBASE + 0x1042) /* Solid Color Register */ +#define HD64461_GRCFGR (CONFIG_HD64461_IOBASE + 0x1044) /* Accelerator Configuration Register */ + +#define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */ +#define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */ +#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 /* Accelerator Start BITBLT */ +#define HD64461_GRCFGR_ACCSTART_LINE 0x04 /* Accelerator Start Line Drawing */ +#define HD64461_GRCFGR_COLORDEPTH16 0x01 /* Sets Colordepth 16 for Accelerator */ +#define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */ + +/* Line Drawing Registers */ +#define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x1046) /* Line Start Adress Register (H) */ +#define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x1048) /* Line Start Adress Register (L) */ +#define HD64461_LNAXLR (CONFIG_HD64461_IOBASE + 0x104a) /* Axis Pixel Length Register */ +#define HD64461_LNDGR (CONFIG_HD64461_IOBASE + 0x104c) /* Diagonal Register */ +#define HD64461_LNAXR (CONFIG_HD64461_IOBASE + 0x104e) /* Axial Register */ +#define HD64461_LNERTR (CONFIG_HD64461_IOBASE + 0x1050) /* Start Error Term Register */ +#define HD64461_LNMDR (CONFIG_HD64461_IOBASE + 0x1052) /* Line Mode Register */ + +/* BitBLT Registers */ +#define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x1054) /* Source Start Adress Register (H) */ +#define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x1056) /* Source Start Adress Register (L) */ +#define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x1058) /* Destination Start Adress Register (H) */ +#define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x105a) /* Destination Start Adress Register (L) */ +#define HD64461_BBTDWR (CONFIG_HD64461_IOBASE + 0x105c) /* Destination Block Width Register */ +#define HD64461_BBTDHR (CONFIG_HD64461_IOBASE + 0x105e) /* Destination Block Height Register */ +#define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x1060) /* Pattern Start Adress Register (H) */ +#define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x1062) /* Pattern Start Adress Register (L) */ +#define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x1064) /* Mask Start Adress Register (H) */ +#define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x1066) /* Mask Start Adress Register (L) */ +#define HD64461_BBTROPR (CONFIG_HD64461_IOBASE + 0x1068) /* ROP Register */ +#define HD64461_BBTMDR (CONFIG_HD64461_IOBASE + 0x106a) /* BitBLT Mode Register */ /* PC Card Controller Registers */ -#define HD64461_PCC0ISR 0x12000 /* socket 0 interface status */ -#define HD64461_PCC0GCR 0x12002 /* socket 0 general control */ -#define HD64461_PCC0CSCR 0x12004 /* socket 0 card status change */ -#define HD64461_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */ -#define HD64461_PCC0SCR 0x12008 /* socket 0 software control */ -#define HD64461_PCC1ISR 0x12010 /* socket 1 interface status */ -#define HD64461_PCC1GCR 0x12012 /* socket 1 general control */ -#define HD64461_PCC1CSCR 0x12014 /* socket 1 card status change */ -#define HD64461_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */ -#define HD64461_PCC1SCR 0x12018 /* socket 1 software control */ +/* Maps to Physical Area 6 */ +#define HD64461_PCC0ISR (CONFIG_HD64461_IOBASE + 0x2000) /* socket 0 interface status */ +#define HD64461_PCC0GCR (CONFIG_HD64461_IOBASE + 0x2002) /* socket 0 general control */ +#define HD64461_PCC0CSCR (CONFIG_HD64461_IOBASE + 0x2004) /* socket 0 card status change */ +#define HD64461_PCC0CSCIER (CONFIG_HD64461_IOBASE + 0x2006) /* socket 0 card status change interrupt enable */ +#define HD64461_PCC0SCR (CONFIG_HD64461_IOBASE + 0x2008) /* socket 0 software control */ +/* Maps to Physical Area 5 */ +#define HD64461_PCC1ISR (CONFIG_HD64461_IOBASE + 0x2010) /* socket 1 interface status */ +#define HD64461_PCC1GCR (CONFIG_HD64461_IOBASE + 0x2012) /* socket 1 general control */ +#define HD64461_PCC1CSCR (CONFIG_HD64461_IOBASE + 0x2014) /* socket 1 card status change */ +#define HD64461_PCC1CSCIER (CONFIG_HD64461_IOBASE + 0x2016) /* socket 1 card status change interrupt enable */ +#define HD64461_PCC1SCR (CONFIG_HD64461_IOBASE + 0x2018) /* socket 1 software control */ /* PCC Interface Status Register */ -#define HD64461_PCCISR_READY 0x80 /* card ready */ -#define HD64461_PCCISR_MWP 0x40 /* card write-protected */ -#define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */ -#define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */ -#define HD64461_PCCISR_CD2 0x08 /* card detect 2 */ -#define HD64461_PCCISR_CD1 0x04 /* card detect 1 */ -#define HD64461_PCCISR_BVD2 0x02 /* battery 1 */ -#define HD64461_PCCISR_BVD1 0x01 /* battery 1 */ - -#define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */ -#define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */ -#define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */ -#define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */ -#define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */ -#define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */ +#define HD64461_PCCISR_READY 0x80 /* card ready */ +#define HD64461_PCCISR_MWP 0x40 /* card write-protected */ +#define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */ +#define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */ +#define HD64461_PCCISR_CD2 0x08 /* card detect 2 */ +#define HD64461_PCCISR_CD1 0x04 /* card detect 1 */ +#define HD64461_PCCISR_BVD2 0x02 /* battery 1 */ +#define HD64461_PCCISR_BVD1 0x01 /* battery 1 */ + +#define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */ +#define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */ +#define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */ +#define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */ +#define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */ +#define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */ /* PCC General Control Register */ -#define HD64461_PCCGCR_DRVE 0x80 /* output drive */ -#define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */ -#define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ -#define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */ -#define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */ -#define HD64461_PCCGCR_PA25 0x04 /* pin A25 */ -#define HD64461_PCCGCR_PA24 0x02 /* pin A24 */ -#define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */ +#define HD64461_PCCGCR_DRVE 0x80 /* output drive */ +#define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */ +#define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ +#define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */ +#define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */ +#define HD64461_PCCGCR_PA25 0x04 /* pin A25 */ +#define HD64461_PCCGCR_PA24 0x02 /* pin A24 */ +#define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */ /* PCC Card Status Change Register */ -#define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */ -#define HD64461_PCCCSCR_SRV1 0x40 /* reserved */ -#define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */ -#define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */ -#define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */ -#define HD64461_PCCCSCR_RC 0x04 /* READY change */ -#define HD64461_PCCCSCR_BW 0x02 /* battery warning change */ -#define HD64461_PCCCSCR_BD 0x01 /* battery dead change */ +#define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */ +#define HD64461_PCCCSCR_SRV1 0x40 /* reserved */ +#define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */ +#define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */ +#define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */ +#define HD64461_PCCCSCR_RC 0x04 /* READY change */ +#define HD64461_PCCCSCR_BW 0x02 /* battery warning change */ +#define HD64461_PCCCSCR_BD 0x01 /* battery dead change */ /* PCC Card Status Change Interrupt Enable Register */ -#define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */ -#define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */ -#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */ -#define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */ -#define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */ -#define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */ - -#define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */ -#define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */ -#define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */ -#define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */ -#define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/ +#define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */ +#define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */ +#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */ +#define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */ +#define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */ +#define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */ + +#define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */ +#define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */ +#define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */ +#define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */ +#define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/ /* PCC Software Control Register */ -#define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */ -#define HD64461_PCCSCR_SWP 0x01 /* write protect */ - -#define HD64461_P0OCR 0x1202a -#define HD64461_P1OCR 0x1202c -#define HD64461_PGCR 0x1202e - -#define HD64461_GPACR 0x14000 -#define HD64461_GPBCR 0x14002 -#define HD64461_GPCCR 0x14004 -#define HD64461_GPDCR 0x14006 -#define HD64461_GPADR 0x14010 -#define HD64461_GPBDR 0x14012 -#define HD64461_GPCDR 0x14014 -#define HD64461_GPDDR 0x14016 -#define HD64461_GPAICR 0x14020 -#define HD64461_GPBICR 0x14022 -#define HD64461_GPCICR 0x14024 -#define HD64461_GPDICR 0x14026 -#define HD64461_GPAISR 0x14040 -#define HD64461_GPBISR 0x14042 -#define HD64461_GPCISR 0x14044 -#define HD64461_GPDISR 0x14046 - -#define HD64461_NIRR 0x15000 -#define HD64461_NIMR 0x15002 - -#define HD64461_IRQBASE OFFCHIP_IRQ_BASE -#define HD64461_IRQ_NUM 16 - -#define HD64461_IRQ_UART (HD64461_IRQBASE+5) -#define HD64461_IRQ_IRDA (HD64461_IRQBASE+6) -#define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9) -#define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10) -#define HD64461_IRQ_GPIO (HD64461_IRQBASE+11) -#define HD64461_IRQ_AFE (HD64461_IRQBASE+12) -#define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13) -#define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14) +#define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */ +#define HD64461_PCCSCR_SWP 0x01 /* write protect */ + +/* PCC0 Output Pins Control Register */ +#define HD64461_P0OCR (CONFIG_HD64461_IOBASE + 0x202a) + +/* PCC1 Output Pins Control Register */ +#define HD64461_P1OCR (CONFIG_HD64461_IOBASE + 0x202c) + +/* PC Card General Control Register */ +#define HD64461_PGCR (CONFIG_HD64461_IOBASE + 0x202e) + +/* Port Control Registers */ +#define HD64461_GPACR (CONFIG_HD64461_IOBASE + 0x4000) /* Port A - Handles IRDA/TIMER */ +#define HD64461_GPBCR (CONFIG_HD64461_IOBASE + 0x4002) /* Port B - Handles UART */ +#define HD64461_GPCCR (CONFIG_HD64461_IOBASE + 0x4004) /* Port C - Handles PCMCIA 1 */ +#define HD64461_GPDCR (CONFIG_HD64461_IOBASE + 0x4006) /* Port D - Handles PCMCIA 1 */ + +/* Port Control Data Registers */ +#define HD64461_GPADR (CONFIG_HD64461_IOBASE + 0x4010) /* A */ +#define HD64461_GPBDR (CONFIG_HD64461_IOBASE + 0x4012) /* B */ +#define HD64461_GPCDR (CONFIG_HD64461_IOBASE + 0x4014) /* C */ +#define HD64461_GPDDR (CONFIG_HD64461_IOBASE + 0x4016) /* D */ + +/* Interrupt Control Registers */ +#define HD64461_GPAICR (CONFIG_HD64461_IOBASE + 0x4020) /* A */ +#define HD64461_GPBICR (CONFIG_HD64461_IOBASE + 0x4022) /* B */ +#define HD64461_GPCICR (CONFIG_HD64461_IOBASE + 0x4024) /* C */ +#define HD64461_GPDICR (CONFIG_HD64461_IOBASE + 0x4026) /* D */ + +/* Interrupt Status Registers */ +#define HD64461_GPAISR (CONFIG_HD64461_IOBASE + 0x4040) /* A */ +#define HD64461_GPBISR (CONFIG_HD64461_IOBASE + 0x4042) /* B */ +#define HD64461_GPCISR (CONFIG_HD64461_IOBASE + 0x4044) /* C */ +#define HD64461_GPDISR (CONFIG_HD64461_IOBASE + 0x4046) /* D */ + +/* Interrupt Request Register & Interrupt Mask Register */ +#define HD64461_NIRR (CONFIG_HD64461_IOBASE + 0x5000) +#define HD64461_NIMR (CONFIG_HD64461_IOBASE + 0x5002) + +#define HD64461_IRQBASE OFFCHIP_IRQ_BASE +#define HD64461_IRQ_NUM 16 + +#define HD64461_IRQ_UART (HD64461_IRQBASE+5) +#define HD64461_IRQ_IRDA (HD64461_IRQBASE+6) +#define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9) +#define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10) +#define HD64461_IRQ_GPIO (HD64461_IRQBASE+11) +#define HD64461_IRQ_AFE (HD64461_IRQBASE+12) +#define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13) +#define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14) #define __IO_PREFIX hd64461 #include <asm/io_generic.h> diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h index 80ee1cda7498..4ca3f765bacc 100644 --- a/include/asm-sh/hw_irq.h +++ b/include/asm-sh/hw_irq.h @@ -5,4 +5,46 @@ extern atomic_t irq_err_count; +struct intc2_data { + unsigned short irq; + unsigned char ipr_offset, ipr_shift; + unsigned char msk_offset, msk_shift; + unsigned char priority; +}; + +struct intc2_desc { + unsigned long prio_base; + unsigned long msk_base; + unsigned long mskclr_base; + struct intc2_data *intc2_data; + unsigned int nr_irqs; + struct irq_chip chip; +}; + +void register_intc2_controller(struct intc2_desc *); +void init_IRQ_intc2(void); + +struct ipr_data { + unsigned char irq; + unsigned char ipr_idx; /* Index for the IPR registered */ + unsigned char shift; /* Number of bits to shift the data */ + unsigned char priority; /* The priority */ +}; + +struct ipr_desc { + unsigned long *ipr_offsets; + unsigned int nr_offsets; + struct ipr_data *ipr_data; + unsigned int nr_irqs; + struct irq_chip chip; +}; + +void register_ipr_controller(struct ipr_desc *); +void init_IRQ_ipr(void); + +/* + * Enable individual interrupt mode for external IPR IRQs. + */ +void ipr_irq_enable_irlm(void); + #endif /* __ASM_SH_HW_IRQ_H */ diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h index e81bf21c801e..c61d902b8bff 100644 --- a/include/asm-sh/irq.h +++ b/include/asm-sh/irq.h @@ -31,47 +31,7 @@ extern unsigned short *irq_mask_register; * PINT IRQs */ void init_IRQ_pint(void); - -/* - * The shift value is now the number of bits to shift, not the number of - * bits/4. This is to make it easier to read the value directly from the - * datasheets. The IPR address, addr, will be set from ipr_idx via the - * map_ipridx_to_addr function. - */ -struct ipr_data { - unsigned int irq; - int ipr_idx; /* Index for the IPR registered */ - int shift; /* Number of bits to shift the data */ - int priority; /* The priority */ - unsigned int addr; /* Address of Interrupt Priority Register */ -}; - -/* - * Given an IPR IDX, map the value to an IPR register address. - */ -unsigned int map_ipridx_to_addr(int idx); - -/* - * Enable individual interrupt mode for external IPR IRQs. - */ -void ipr_irq_enable_irlm(void); - -/* - * Function for "on chip support modules". - */ -void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs); void make_imask_irq(unsigned int irq); -void init_IRQ_ipr(void); - -struct intc2_data { - unsigned short irq; - unsigned char ipr_offset, ipr_shift; - unsigned char msk_offset, msk_shift; - unsigned char priority; -}; - -void make_intc2_irq(struct intc2_data *, unsigned int nr_irqs); -void init_IRQ_intc2(void); static inline int generic_irq_demux(int irq) { diff --git a/include/asm-sh/machvec.h b/include/asm-sh/machvec.h index 70389b72ffef..088698bacf2f 100644 --- a/include/asm-sh/machvec.h +++ b/include/asm-sh/machvec.h @@ -13,7 +13,6 @@ #include <linux/types.h> #include <linux/time.h> #include <asm/machtypes.h> -#include <asm/machvec_init.h> struct device; @@ -68,4 +67,7 @@ extern struct sh_machine_vector sh_mv; #define get_system_type() sh_mv.mv_name +#define __initmv \ + __attribute_used__ __attribute__((__section__ (".machvec.init"))) + #endif /* _ASM_SH_MACHVEC_H */ diff --git a/include/asm-sh/machvec_init.h b/include/asm-sh/machvec_init.h deleted file mode 100644 index e397798ebd94..000000000000 --- a/include/asm-sh/machvec_init.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * include/asm-sh/machvec_init.h - * - * Copyright 2000 Stuart Menefy (stuart.menefy@st.com) - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - * This file has goodies to help simplify instantiation of machine vectors. - */ - -#ifndef __SH_MACHVEC_INIT_H -#define __SH_MACHVEC_INIT_H - - -/* - * In a GENERIC kernel, we have lots of these vectors floating about, - * all but one of which we want to go away. In a non-GENERIC kernel, - * we want only one, ever. - * - * Accomplish this in the GENERIC kernel by puting all of the vectors - * in the .init.data section where they'll go away. We'll copy the - * one we want to the real alpha_mv vector in setup_arch. - * - * Accomplish this in a non-GENERIC kernel by ifdef'ing out all but - * one of the vectors, which will not reside in .init.data. We then - * alias this one vector to alpha_mv, so no copy is needed. - * - * Upshot: set __initdata to nothing for non-GENERIC kernels. - * - * Note we do the same thing for the UNKNOWN kernel, as we need to write - * to the machine vector while setting it up. - */ - -#if defined(CONFIG_SH_GENERIC) || defined(CONFIG_SH_UNKNOWN) -#define __initmv __attribute__((unused,__section__ (".machvec.init"))) -#define ALIAS_MV(x) -#else -#define __initmv - -/* GCC actually has a syntax for defining aliases, but is under some - delusion that you shouldn't be able to declare it extern somewhere - else beforehand. Fine. We'll do it ourselves. */ -#if 0 -#define ALIAS_MV(system) \ - struct sh_machine_vector sh_mv __attribute__((alias("mv_"#system))); -#else -#define ALIAS_MV(system) \ - asm(".global sh_mv\nsh_mv = mv_"#system ); -#endif -#endif /* GENERIC */ - -#endif /* __SH_MACHVEC_INIT_H */ diff --git a/include/asm-sh/mmzone.h b/include/asm-sh/mmzone.h new file mode 100644 index 000000000000..7969f381dff2 --- /dev/null +++ b/include/asm-sh/mmzone.h @@ -0,0 +1,46 @@ +#ifndef __ASM_SH_MMZONE_H +#define __ASM_SH_MMZONE_H + +#ifdef __KERNEL__ + +#ifdef CONFIG_NEED_MULTIPLE_NODES +extern struct pglist_data *node_data[]; +#define NODE_DATA(nid) (node_data[nid]) + +#define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn) +#define node_end_pfn(nid) (NODE_DATA(nid)->node_start_pfn + \ + NODE_DATA(nid)->node_spanned_pages) + +static inline int pfn_to_nid(unsigned long pfn) +{ + int nid; + + for (nid = 0; nid < MAX_NUMNODES; nid++) + if (pfn >= node_start_pfn(nid) && pfn <= node_end_pfn(nid)) + break; + + return nid; +} + +static inline struct pglist_data *pfn_to_pgdat(unsigned long pfn) +{ + return NODE_DATA(pfn_to_nid(pfn)); +} + +/* arch/sh/mm/numa.c */ +void __init setup_bootmem_node(int nid, unsigned long start, unsigned long end); +#else +static inline void +setup_bootmem_node(int nid, unsigned long start, unsigned long end) +{ +} +#endif /* CONFIG_NEED_MULTIPLE_NODES */ + +/* Platform specific mem init */ +void __init plat_mem_setup(void); + +/* arch/sh/kernel/setup.c */ +void __init setup_bootmem_allocator(unsigned long start_pfn); + +#endif /* __KERNEL__ */ +#endif /* __ASM_SH_MMZONE_H */ diff --git a/include/asm-sh/page.h b/include/asm-sh/page.h index 7464de4ba07d..6bc9bba10105 100644 --- a/include/asm-sh/page.h +++ b/include/asm-sh/page.h @@ -60,6 +60,7 @@ extern void (*copy_page)(void *to, void *from); extern unsigned long shm_align_mask; extern unsigned long max_low_pfn, min_low_pfn; +extern unsigned long memory_start, memory_end; #ifdef CONFIG_MMU extern void clear_page_slow(void *to); @@ -134,7 +135,9 @@ typedef struct { unsigned long pgd; } pgd_t; #define PFN_START (__MEMORY_START >> PAGE_SHIFT) #define ARCH_PFN_OFFSET (PFN_START) #define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) +#ifdef CONFIG_FLATMEM #define pfn_valid(pfn) ((pfn) >= min_low_pfn && (pfn) < max_low_pfn) +#endif #define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ @@ -148,5 +151,12 @@ typedef struct { unsigned long pgd; } pgd_t; #define __HAVE_ARCH_GATE_AREA #endif +/* + * Slub defaults to 8-byte alignment, we're only interested in 4. + * Slab defaults to BYTES_PER_WORD, which ends up being the same anyways. + */ +#define ARCH_KMALLOC_MINALIGN 4 +#define ARCH_SLAB_MINALIGN 4 + #endif /* __KERNEL__ */ #endif /* __ASM_SH_PAGE_H */ diff --git a/include/asm-sh/parport.h b/include/asm-sh/parport.h new file mode 100644 index 000000000000..f67ba60a2acd --- /dev/null +++ b/include/asm-sh/parport.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 1999, 2000 Tim Waugh <tim@cyberelk.demon.co.uk> + * + * This file should only be included by drivers/parport/parport_pc.c. + */ +#ifndef __ASM_SH_PARPORT_H +#define __ASM_SH_PARPORT_H + +static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma); + +static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma) +{ + return parport_pc_find_isa_ports(autoirq, autodma); +} + +#endif /* __ASM_SH_PARPORT_H */ diff --git a/include/asm-sh/pci.h b/include/asm-sh/pci.h index b1f9a9e0231e..2757ce096ff7 100644 --- a/include/asm-sh/pci.h +++ b/include/asm-sh/pci.h @@ -110,11 +110,6 @@ static inline void pcibios_penalize_isa_irq(int irq, int active) #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) #endif -/* Not supporting more than 32-bit PCI bus addresses now, but - * must satisfy references to this function. Change if needed. - */ -#define pci_dac_dma_supported(pci_dev, mask) (0) - #ifdef CONFIG_PCI static inline void pci_dma_burst_advice(struct pci_dev *pdev, enum pci_dma_burst_strategy *strat, @@ -134,10 +129,6 @@ int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin); int pciauto_assign_resources(int busno, struct pci_channel *hose); #endif -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #endif /* __KERNEL__ */ /* generic pci stuff */ diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h index 5b523c7e7d99..22efffe45019 100644 --- a/include/asm-sh/pgtable.h +++ b/include/asm-sh/pgtable.h @@ -402,12 +402,8 @@ static inline void set_pte(pte_t *ptep, pte_t pte) #define pte_file(pte) (pte_val(pte) & _PAGE_FILE) #ifdef CONFIG_X2TLB -#define pte_read(pte) ((pte).pte_high & _PAGE_EXT_USER_READ) -#define pte_exec(pte) ((pte).pte_high & _PAGE_EXT_USER_EXEC) #define pte_write(pte) ((pte).pte_high & _PAGE_EXT_USER_WRITE) #else -#define pte_read(pte) (pte_val(pte) & _PAGE_USER) -#define pte_exec(pte) (pte_val(pte) & _PAGE_USER) #define pte_write(pte) (pte_val(pte) & _PAGE_RW) #endif @@ -420,20 +416,12 @@ static inline pte_t pte_##fn(pte_t pte) { pte.pte_##h op; return pte; } * individually toggled (and user permissions are entirely decoupled from * kernel permissions), we attempt to couple them a bit more sanely here. */ -PTE_BIT_FUNC(high, rdprotect, &= ~_PAGE_EXT_USER_READ); -PTE_BIT_FUNC(high, mkread, |= _PAGE_EXT_USER_READ | _PAGE_EXT_KERN_READ); PTE_BIT_FUNC(high, wrprotect, &= ~_PAGE_EXT_USER_WRITE); PTE_BIT_FUNC(high, mkwrite, |= _PAGE_EXT_USER_WRITE | _PAGE_EXT_KERN_WRITE); -PTE_BIT_FUNC(high, exprotect, &= ~_PAGE_EXT_USER_EXEC); -PTE_BIT_FUNC(high, mkexec, |= _PAGE_EXT_USER_EXEC | _PAGE_EXT_KERN_EXEC); PTE_BIT_FUNC(high, mkhuge, |= _PAGE_SZHUGE); #else -PTE_BIT_FUNC(low, rdprotect, &= ~_PAGE_USER); -PTE_BIT_FUNC(low, mkread, |= _PAGE_USER); PTE_BIT_FUNC(low, wrprotect, &= ~_PAGE_RW); PTE_BIT_FUNC(low, mkwrite, |= _PAGE_RW); -PTE_BIT_FUNC(low, exprotect, &= ~_PAGE_USER); -PTE_BIT_FUNC(low, mkexec, |= _PAGE_USER); PTE_BIT_FUNC(low, mkhuge, |= _PAGE_SZHUGE); #endif diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h index d42f68e724fa..2252e75daa26 100644 --- a/include/asm-sh/processor.h +++ b/include/asm-sh/processor.h @@ -36,7 +36,7 @@ */ enum cpu_type { /* SH-2 types */ - CPU_SH7604, CPU_SH7619, + CPU_SH7619, /* SH-2A types */ CPU_SH7206, @@ -52,7 +52,7 @@ enum cpu_type { CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501, /* SH-4A types */ - CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, + CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3, /* SH4AL-DSP types */ CPU_SH73180, CPU_SH7343, CPU_SH7722, @@ -228,11 +228,7 @@ static __inline__ void grab_fpu(struct pt_regs *regs) regs->sr &= ~SR_FD; } -#ifdef CONFIG_CPU_SH4 extern void save_fpu(struct task_struct *__tsk, struct pt_regs *regs); -#else -#define save_fpu(tsk) do { } while (0) -#endif #define unlazy_fpu(tsk, regs) do { \ if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) { \ diff --git a/include/asm-sh/rwsem.h b/include/asm-sh/rwsem.h index 4931ba817d73..1987f3ea7f1b 100644 --- a/include/asm-sh/rwsem.h +++ b/include/asm-sh/rwsem.h @@ -1,11 +1,15 @@ /* - * include/asm-ppc/rwsem.h: R/W semaphores for SH using the stuff + * include/asm-sh/rwsem.h: R/W semaphores for SH using the stuff * in lib/rwsem.c. */ #ifndef _ASM_SH_RWSEM_H #define _ASM_SH_RWSEM_H +#ifndef _LINUX_RWSEM_H +#error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead" +#endif + #ifdef __KERNEL__ #include <linux/list.h> #include <linux/spinlock.h> diff --git a/include/asm-sh/saturn/io.h b/include/asm-sh/saturn/io.h deleted file mode 100644 index f1b9b5d633f4..000000000000 --- a/include/asm-sh/saturn/io.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * include/asm-sh/saturn/io.h - * - * I/O functions for use on the Sega Saturn. - * - * Copyright (C) 2002 Paul Mundt - * - * Released under the terms of the GNU GPL v2.0. - */ -#ifndef __ASM_SH_SATURN_IO_H -#define __ASM_SH_SATURN_IO_H - -/* arch/sh/boards/saturn/io.c */ -extern unsigned long saturn_isa_port2addr(unsigned long offset); -extern void *saturn_ioremap(unsigned long offset, unsigned long size); -extern void saturn_iounmap(void *addr); - -#endif /* __ASM_SH_SATURN_IO_H */ - diff --git a/include/asm-sh/saturn/smpc.h b/include/asm-sh/saturn/smpc.h deleted file mode 100644 index 5de5c12d6347..000000000000 --- a/include/asm-sh/saturn/smpc.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * include/asm-sh/saturn/smpc.h - * - * System Manager / Peripheral Control definitions. - * - * Copyright (C) 2002 Paul Mundt - * - * Released under the terms of the GNU GPL v2.0. - */ -#ifndef __ASM_SH_SATURN_SMPC_H -#define __ASM_SH_SATURN_SMPC_H - -#include <asm/io.h> - -#define SMPC_COMMAND 0x2010001f /* SMPC command register */ -#define SMPC_RESULT 0x2010005f /* SMPC result register */ -#define SMPC_STATUS 0x20100063 /* SMPC status register */ - -#define SMPC_CMD_MSHON 0x0001 /* Master SH On */ -#define SMPC_CMD_SSHON 0x0002 /* Slave SH On */ -#define SMPC_CMD_SSHOFF 0x0003 /* Slave SH Off */ -#define SMPC_CMD_SNDON 0x0004 /* Sound On */ -#define SMPC_CMD_SNDOFF 0x0005 /* Sound Off */ -#define SMPC_CMD_CDON 0x0006 /* CD On */ -#define SMPC_CMD_CDOFF 0x0007 /* CD Off */ - -static inline void smpc_barrier(void) -{ - while ((ctrl_inb(SMPC_STATUS) & 0x0001) == 0x0001) - ; -} - -#endif /* __ASM_SH_SATURN_SMPC_H */ - diff --git a/include/asm-sh/sections.h b/include/asm-sh/sections.h index 57abd708b236..2a696b8ee4f5 100644 --- a/include/asm-sh/sections.h +++ b/include/asm-sh/sections.h @@ -3,7 +3,7 @@ #include <asm-generic/sections.h> -extern char _end[]; +extern long __machvec_start, __machvec_end; #endif /* __ASM_SH_SECTIONS_H */ diff --git a/include/asm-sh/setup.h b/include/asm-sh/setup.h index 1583c6b7bdaa..586a9711a75d 100644 --- a/include/asm-sh/setup.h +++ b/include/asm-sh/setup.h @@ -6,6 +6,7 @@ #ifdef __KERNEL__ int setup_early_printk(char *); +void sh_mv_setup(void); #endif /* __KERNEL__ */ diff --git a/include/asm-sh/sh03/io.h b/include/asm-sh/sh03/io.h index df3b187ef883..4ff1eb900301 100644 --- a/include/asm-sh/sh03/io.h +++ b/include/asm-sh/sh03/io.h @@ -14,22 +14,18 @@ #define INTC_IPRD 0xffd00010UL #define IRL0_IRQ 2 -#define IRL0_IPR_ADDR INTC_IPRD #define IRL0_IPR_POS 3 #define IRL0_PRIORITY 13 #define IRL1_IRQ 5 -#define IRL1_IPR_ADDR INTC_IPRD #define IRL1_IPR_POS 2 #define IRL1_PRIORITY 10 #define IRL2_IRQ 8 -#define IRL2_IPR_ADDR INTC_IPRD #define IRL2_IPR_POS 1 #define IRL2_PRIORITY 7 #define IRL3_IRQ 11 -#define IRL3_IPR_ADDR INTC_IPRD #define IRL3_IPR_POS 0 #define IRL3_PRIORITY 4 diff --git a/include/asm-sh/smp.h b/include/asm-sh/smp.h index caa7b93f1bce..b99ca786c0c1 100644 --- a/include/asm-sh/smp.h +++ b/include/asm-sh/smp.h @@ -39,4 +39,6 @@ extern struct smp_fn_call_struct smp_fn_call; #endif /* CONFIG_SMP */ +#define hard_smp_processor_id() (0) + #endif /* __ASM_SH_SMP_H */ diff --git a/include/asm-sh/snapgear.h b/include/asm-sh/snapgear.h index 2d712e72c9e5..3554e3a74e99 100644 --- a/include/asm-sh/snapgear.h +++ b/include/asm-sh/snapgear.h @@ -20,22 +20,18 @@ */ #define IRL0_IRQ 2 -#define IRL0_IPR_ADDR INTC_IPRD #define IRL0_IPR_POS 3 #define IRL0_PRIORITY 13 #define IRL1_IRQ 5 -#define IRL1_IPR_ADDR INTC_IPRD #define IRL1_IPR_POS 2 #define IRL1_PRIORITY 10 #define IRL2_IRQ 8 -#define IRL2_IPR_ADDR INTC_IPRD #define IRL2_IPR_POS 1 #define IRL2_PRIORITY 7 #define IRL3_IRQ 11 -#define IRL3_IPR_ADDR INTC_IPRD #define IRL3_IPR_POS 0 #define IRL3_PRIORITY 4 #endif diff --git a/include/asm-sh/sparsemem.h b/include/asm-sh/sparsemem.h new file mode 100644 index 000000000000..547a540b6667 --- /dev/null +++ b/include/asm-sh/sparsemem.h @@ -0,0 +1,16 @@ +#ifndef __ASM_SH_SPARSEMEM_H +#define __ASM_SH_SPARSEMEM_H + +#ifdef __KERNEL__ +/* + * SECTION_SIZE_BITS 2^N: how big each section will be + * MAX_PHYSADDR_BITS 2^N: how much physical address space we have + * MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space + */ +#define SECTION_SIZE_BITS 26 +#define MAX_PHYSADDR_BITS 32 +#define MAX_PHYSMEM_BITS 32 + +#endif + +#endif /* __ASM_SH_SPARSEMEM_H */ diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h index 82f3e229e621..7c75045ae22b 100644 --- a/include/asm-sh/system.h +++ b/include/asm-sh/system.h @@ -8,9 +8,13 @@ #include <linux/irqflags.h> #include <linux/compiler.h> +#include <linux/linkage.h> #include <asm/types.h> #include <asm/ptrace.h> +struct task_struct *__switch_to(struct task_struct *prev, + struct task_struct *next); + /* * switch_to() should switch tasks to task nr n, first */ @@ -122,7 +126,7 @@ static inline void sched_cacheflush(void) #define smp_read_barrier_depends() do { } while(0) #endif -#define set_mb(var, value) do { xchg(&var, value); } while (0) +#define set_mb(var, value) do { (void)xchg(&var, value); } while (0) /* * Jump to P2 area. @@ -271,6 +275,16 @@ extern unsigned int instruction_size(unsigned int insn); void disable_hlt(void); void enable_hlt(void); +void default_idle(void); + +asmlinkage void break_point_trap(void); +asmlinkage void debug_trap_handler(unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7, + struct pt_regs __regs); +asmlinkage void bug_trap_handler(unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7, + struct pt_regs __regs); + #define arch_align_stack(x) (x) #endif diff --git a/include/asm-sh/termbits.h b/include/asm-sh/termbits.h index f1b7b46f4e9a..7ee1b42eeab0 100644 --- a/include/asm-sh/termbits.h +++ b/include/asm-sh/termbits.h @@ -17,6 +17,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-sh/topology.h b/include/asm-sh/topology.h index cff001c316fe..f402a3b1cfa4 100644 --- a/include/asm-sh/topology.h +++ b/include/asm-sh/topology.h @@ -1,6 +1,36 @@ #ifndef _ASM_SH_TOPOLOGY_H #define _ASM_SH_TOPOLOGY_H +#ifdef CONFIG_NUMA + +/* sched_domains SD_NODE_INIT for sh machines */ +#define SD_NODE_INIT (struct sched_domain) { \ + .span = CPU_MASK_NONE, \ + .parent = NULL, \ + .child = NULL, \ + .groups = NULL, \ + .min_interval = 8, \ + .max_interval = 32, \ + .busy_factor = 32, \ + .imbalance_pct = 125, \ + .cache_nice_tries = 2, \ + .busy_idx = 3, \ + .idle_idx = 2, \ + .newidle_idx = 0, \ + .wake_idx = 1, \ + .forkexec_idx = 1, \ + .flags = SD_LOAD_BALANCE \ + | SD_BALANCE_FORK \ + | SD_BALANCE_EXEC \ + | SD_SERIALIZE \ + | SD_WAKE_BALANCE, \ + .last_balance = jiffies, \ + .balance_interval = 1, \ + .nr_balance_failed = 0, \ +} + +#endif + #include <asm-generic/topology.h> #endif /* _ASM_SH_TOPOLOGY_H */ diff --git a/include/asm-sh/uaccess.h b/include/asm-sh/uaccess.h index 5c49ed6715f2..f18a1a5c95c0 100644 --- a/include/asm-sh/uaccess.h +++ b/include/asm-sh/uaccess.h @@ -61,8 +61,6 @@ static inline void set_fs(mm_segment_t s) */ static inline int __access_ok(unsigned long addr, unsigned long size) { - extern unsigned long memory_start, memory_end; - return ((addr >= memory_start) && ((addr + size) < memory_end)); } #else /* CONFIG_MMU */ @@ -76,7 +74,7 @@ static inline int __access_ok(unsigned long addr, unsigned long size) * __access_ok: Check if address with size is OK or not. * * We do three checks: - * (1) is it user space? + * (1) is it user space? * (2) addr + size --> carry? * (3) addr + size >= 0x80000000 (PAGE_OFFSET) * @@ -142,11 +140,12 @@ static inline int access_ok(int type, const void __user *p, unsigned long size) __get_user_nocheck((x),(ptr),sizeof(*(ptr))) struct __large_struct { unsigned long buf[100]; }; -#define __m(x) (*(struct __large_struct *)(x)) +#define __m(x) (*(struct __large_struct __user *)(x)) #define __get_user_size(x,ptr,size,retval) \ do { \ retval = 0; \ + __chk_user_ptr(ptr); \ switch (size) { \ case 1: \ __get_user_asm(x, ptr, retval, "b"); \ @@ -175,6 +174,7 @@ do { \ #define __get_user_check(x,ptr,size) \ ({ \ long __gu_err, __gu_val; \ + __chk_user_ptr(ptr); \ switch (size) { \ case 1: \ __get_user_1(__gu_val, (ptr), __gu_err); \ @@ -300,6 +300,7 @@ extern void __get_user_unknown(void); #define __put_user_size(x,ptr,size,retval) \ do { \ retval = 0; \ + __chk_user_ptr(ptr); \ switch (size) { \ case 1: \ __put_user_asm(x, ptr, retval, "b"); \ @@ -328,7 +329,7 @@ do { \ #define __put_user_check(x,ptr,size) \ ({ \ long __pu_err = -EFAULT; \ - __typeof__(*(ptr)) *__pu_addr = (ptr); \ + __typeof__(*(ptr)) __user *__pu_addr = (ptr); \ \ if (__access_ok((unsigned long)__pu_addr,size)) \ __put_user_size((x),__pu_addr,(size),__pu_err); \ @@ -406,10 +407,10 @@ __asm__ __volatile__( \ #endif extern void __put_user_unknown(void); - + /* Generic arbitrary sized copy. */ /* Return the number of bytes NOT copied */ -extern __kernel_size_t __copy_user(void *to, const void *from, __kernel_size_t n); +__kernel_size_t __copy_user(void *to, const void *from, __kernel_size_t n); #define copy_to_user(to,from,n) ({ \ void *__copy_to = (void *) (to); \ @@ -420,14 +421,6 @@ __copy_res = __copy_user(__copy_to, (void *) (from), __copy_size); \ } else __copy_res = __copy_size; \ __copy_res; }) -#define __copy_to_user(to,from,n) \ - __copy_user((void *)(to), \ - (void *)(from), n) - -#define __copy_to_user_inatomic __copy_to_user -#define __copy_from_user_inatomic __copy_from_user - - #define copy_from_user(to,from,n) ({ \ void *__copy_to = (void *) (to); \ void *__copy_from = (void *) (from); \ @@ -438,9 +431,20 @@ __copy_res = __copy_user(__copy_to, __copy_from, __copy_size); \ } else __copy_res = __copy_size; \ __copy_res; }) -#define __copy_from_user(to,from,n) \ - __copy_user((void *)(to), \ - (void *)(from), n) +static __always_inline unsigned long +__copy_from_user(void *to, const void __user *from, unsigned long n) +{ + return __copy_user(to, (__force void *)from, n); +} + +static __always_inline unsigned long __must_check +__copy_to_user(void __user *to, const void *from, unsigned long n) +{ + return __copy_user((__force void *)to, from, n); +} + +#define __copy_to_user_inatomic __copy_to_user +#define __copy_from_user_inatomic __copy_from_user /* * Clear the area and return remaining number of bytes diff --git a/include/asm-sh/ubc.h b/include/asm-sh/ubc.h index ae9bbdeefbe1..38d46e01b846 100644 --- a/include/asm-sh/ubc.h +++ b/include/asm-sh/ubc.h @@ -51,9 +51,14 @@ #define BRCR_UBDE (1 << 0) #ifndef __ASSEMBLY__ -/* arch/sh/kernel/ubc.S */ -extern void ubc_wakeup(void); +/* arch/sh/kernel/cpu/ubc.S */ extern void ubc_sleep(void); + +#ifdef CONFIG_UBC_WAKEUP +extern void ubc_wakeup(void); +#else +#define ubc_wakeup() do { } while (0) +#endif #endif #endif /* __KERNEL__ */ diff --git a/include/asm-sh64/pci.h b/include/asm-sh64/pci.h index aa8043089bb6..57a67cf7a5c4 100644 --- a/include/asm-sh64/pci.h +++ b/include/asm-sh64/pci.h @@ -72,11 +72,6 @@ static inline void pcibios_penalize_isa_irq(int irq, int active) #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) #endif -/* Not supporting more than 32-bit PCI bus addresses now, but - * must satisfy references to this function. Change if needed. - */ -#define pci_dac_dma_supported(pci_dev, mask) (0) - /* These macros should be used after a pci_map_sg call has been done * to get bus addresses of each of the SG entries and their lengths. * You should only work with the number of sg entries pci_map_sg @@ -104,10 +99,6 @@ extern void pcibios_fixup_irqs(void); extern int pciauto_assign_resources(int busno, struct pci_channel *hose); #endif -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #endif /* __KERNEL__ */ /* generic pci stuff */ diff --git a/include/asm-sh64/pgtable.h b/include/asm-sh64/pgtable.h index b875482eb592..3488fe32e436 100644 --- a/include/asm-sh64/pgtable.h +++ b/include/asm-sh64/pgtable.h @@ -415,22 +415,15 @@ extern void __handle_bad_pmd_kernel(pmd_t * pmd); /* * The following have defined behavior only work if pte_present() is true. */ -static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; } -static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXECUTE; } static inline int pte_dirty(pte_t pte){ return pte_val(pte) & _PAGE_DIRTY; } static inline int pte_young(pte_t pte){ return pte_val(pte) & _PAGE_ACCESSED; } static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } static inline int pte_write(pte_t pte){ return pte_val(pte) & _PAGE_WRITE; } -static inline pte_t pte_rdprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_READ)); return pte; } static inline pte_t pte_wrprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_WRITE)); return pte; } -static inline pte_t pte_exprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_EXECUTE)); return pte; } static inline pte_t pte_mkclean(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_DIRTY)); return pte; } static inline pte_t pte_mkold(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_ACCESSED)); return pte; } - -static inline pte_t pte_mkread(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_READ)); return pte; } static inline pte_t pte_mkwrite(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_WRITE)); return pte; } -static inline pte_t pte_mkexec(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_EXECUTE)); return pte; } static inline pte_t pte_mkdirty(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; } static inline pte_t pte_mkyoung(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; } static inline pte_t pte_mkhuge(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_SZHUGE)); return pte; } diff --git a/include/asm-sparc/pci.h b/include/asm-sparc/pci.h index a750c688408b..b93b6c79e08f 100644 --- a/include/asm-sparc/pci.h +++ b/include/asm-sparc/pci.h @@ -142,8 +142,6 @@ static inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask) return 1; } -#define pci_dac_dma_supported(dev, mask) (0) - #ifdef CONFIG_PCI static inline void pci_dma_burst_advice(struct pci_dev *pdev, enum pci_dma_burst_strategy *strat, @@ -154,10 +152,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, } #endif -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #define PCI_DMA_ERROR_CODE (~(dma_addr_t)0x0) static inline int pci_dma_mapping_error(dma_addr_t dma_addr) diff --git a/include/asm-sparc/pgtable.h b/include/asm-sparc/pgtable.h index 59229aeba27b..a55f4c3488b0 100644 --- a/include/asm-sparc/pgtable.h +++ b/include/asm-sparc/pgtable.h @@ -151,7 +151,6 @@ BTFIXUPDEF_CALL_CONST(unsigned long, pgd_page_vaddr, pgd_t) BTFIXUPDEF_SETHI(none_mask) BTFIXUPDEF_CALL_CONST(int, pte_present, pte_t) BTFIXUPDEF_CALL(void, pte_clear, pte_t *) -BTFIXUPDEF_CALL(int, pte_read, pte_t) static inline int pte_none(pte_t pte) { @@ -160,7 +159,6 @@ static inline int pte_none(pte_t pte) #define pte_present(pte) BTFIXUP_CALL(pte_present)(pte) #define pte_clear(mm,addr,pte) BTFIXUP_CALL(pte_clear)(pte) -#define pte_read(pte) BTFIXUP_CALL(pte_read)(pte) BTFIXUPDEF_CALL_CONST(int, pmd_bad, pmd_t) BTFIXUPDEF_CALL_CONST(int, pmd_present, pmd_t) diff --git a/include/asm-sparc64/bugs.h b/include/asm-sparc64/bugs.h index bf39d86c0c9e..11ade6841971 100644 --- a/include/asm-sparc64/bugs.h +++ b/include/asm-sparc64/bugs.h @@ -4,12 +4,7 @@ */ #include <asm/sstate.h> -extern unsigned long loops_per_jiffy; - static void __init check_bugs(void) { -#ifndef CONFIG_SMP - cpu_data(0).udelay_val = loops_per_jiffy; -#endif sstate_running(); } diff --git a/include/asm-sparc64/compat.h b/include/asm-sparc64/compat.h index 36511ca51416..01fe6682b405 100644 --- a/include/asm-sparc64/compat.h +++ b/include/asm-sparc64/compat.h @@ -31,8 +31,10 @@ typedef s32 compat_timer_t; typedef s32 compat_int_t; typedef s32 compat_long_t; +typedef s64 compat_s64; typedef u32 compat_uint_t; typedef u32 compat_ulong_t; +typedef u64 compat_u64; struct compat_timespec { compat_time_t tv_sec; diff --git a/include/asm-sparc64/cpudata.h b/include/asm-sparc64/cpudata.h index 445026fbec35..98a6e609163e 100644 --- a/include/asm-sparc64/cpudata.h +++ b/include/asm-sparc64/cpudata.h @@ -19,7 +19,7 @@ typedef struct { unsigned int __softirq_pending; /* must be 1st, see rtrap.S */ unsigned int __pad0; unsigned long clock_tick; /* %tick's per second */ - unsigned long udelay_val; + unsigned long __pad; unsigned int __pad1; unsigned int __pad2; @@ -80,7 +80,8 @@ struct trap_per_cpu { unsigned int dev_mondo_qmask; unsigned int resum_qmask; unsigned int nonresum_qmask; - unsigned int __pad2[3]; + unsigned int __pad2[1]; + void *hdesc; } __attribute__((aligned(64))); extern struct trap_per_cpu trap_block[NR_CPUS]; extern void init_cur_cpu_trap(struct thread_info *); diff --git a/include/asm-sparc64/delay.h b/include/asm-sparc64/delay.h index a4aae6f80627..a77aa622d762 100644 --- a/include/asm-sparc64/delay.h +++ b/include/asm-sparc64/delay.h @@ -1,37 +1,17 @@ /* delay.h: Linux delay routines on sparc64. * - * Copyright (C) 1996, 2004 David S. Miller (davem@davemloft.net). - * - * Based heavily upon x86 variant which is: - * Copyright (C) 1993 Linus Torvalds - * - * Delay routines calling functions in arch/sparc64/lib/delay.c + * Copyright (C) 1996, 2004, 2007 David S. Miller (davem@davemloft.net). */ -#ifndef __SPARC64_DELAY_H -#define __SPARC64_DELAY_H - -#include <linux/param.h> -#include <asm/cpudata.h> +#ifndef _SPARC64_DELAY_H +#define _SPARC64_DELAY_H #ifndef __ASSEMBLY__ -extern void __bad_udelay(void); -extern void __bad_ndelay(void); - -extern void __udelay(unsigned long usecs); -extern void __ndelay(unsigned long nsecs); -extern void __const_udelay(unsigned long usecs); extern void __delay(unsigned long loops); - -#define udelay(n) (__builtin_constant_p(n) ? \ - ((n) > 20000 ? __bad_udelay() : __const_udelay((n) * 0x10c7ul)) : \ - __udelay(n)) - -#define ndelay(n) (__builtin_constant_p(n) ? \ - ((n) > 20000 ? __bad_ndelay() : __const_udelay((n) * 5ul)) : \ - __ndelay(n)) +extern void udelay(unsigned long usecs); +#define mdelay(n) udelay((n) * 1000) #endif /* !__ASSEMBLY__ */ -#endif /* defined(__SPARC64_DELAY_H) */ +#endif /* _SPARC64_DELAY_H */ diff --git a/include/asm-sparc64/hvtramp.h b/include/asm-sparc64/hvtramp.h new file mode 100644 index 000000000000..c7dd6ad056df --- /dev/null +++ b/include/asm-sparc64/hvtramp.h @@ -0,0 +1,37 @@ +#ifndef _SPARC64_HVTRAP_H +#define _SPARC64_HVTRAP_H + +#ifndef __ASSEMBLY__ + +#include <linux/types.h> + +struct hvtramp_mapping { + __u64 vaddr; + __u64 tte; +}; + +struct hvtramp_descr { + __u32 cpu; + __u32 num_mappings; + __u64 fault_info_va; + __u64 fault_info_pa; + __u64 thread_reg; + struct hvtramp_mapping maps[2]; +}; + +extern void hv_cpu_startup(unsigned long hvdescr_pa); + +#endif + +#define HVTRAMP_DESCR_CPU 0x00 +#define HVTRAMP_DESCR_NUM_MAPPINGS 0x04 +#define HVTRAMP_DESCR_FAULT_INFO_VA 0x08 +#define HVTRAMP_DESCR_FAULT_INFO_PA 0x10 +#define HVTRAMP_DESCR_THREAD_REG 0x18 +#define HVTRAMP_DESCR_MAPS 0x20 + +#define HVTRAMP_MAPPING_VADDR 0x00 +#define HVTRAMP_MAPPING_TTE 0x08 +#define HVTRAMP_MAPPING_SIZE 0x10 + +#endif /* _SPARC64_HVTRAP_H */ diff --git a/include/asm-sparc64/hypervisor.h b/include/asm-sparc64/hypervisor.h index db2130a95d68..524d49835dfd 100644 --- a/include/asm-sparc64/hypervisor.h +++ b/include/asm-sparc64/hypervisor.h @@ -98,7 +98,7 @@ #define HV_FAST_MACH_EXIT 0x00 #ifndef __ASSEMBLY__ -extern void sun4v_mach_exit(unsigned long exit_core); +extern void sun4v_mach_exit(unsigned long exit_code); #endif /* Domain services. */ diff --git a/include/asm-sparc64/irq.h b/include/asm-sparc64/irq.h index 90781e34a95c..e6c436ef9356 100644 --- a/include/asm-sparc64/irq.h +++ b/include/asm-sparc64/irq.h @@ -53,6 +53,8 @@ extern unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p, extern void sun4v_destroy_msi(unsigned int virt_irq); extern unsigned int sbus_build_irq(void *sbus, unsigned int ino); +extern void fixup_irqs(void); + static __inline__ void set_softint(unsigned long bits) { __asm__ __volatile__("wr %0, 0x0, %%set_softint" diff --git a/include/asm-sparc64/ldc.h b/include/asm-sparc64/ldc.h new file mode 100644 index 000000000000..bdb524a7b814 --- /dev/null +++ b/include/asm-sparc64/ldc.h @@ -0,0 +1,138 @@ +#ifndef _SPARC64_LDC_H +#define _SPARC64_LDC_H + +#include <asm/hypervisor.h> + +extern int ldom_domaining_enabled; +extern void ldom_set_var(const char *var, const char *value); +extern void ldom_reboot(const char *boot_command); +extern void ldom_power_off(void); + +/* The event handler will be evoked when link state changes + * or data becomes available on the receive side. + * + * For non-RAW links, if the LDC_EVENT_RESET event arrives the + * driver should reset all of it's internal state and reinvoke + * ldc_connect() to try and bring the link up again. + * + * For RAW links, ldc_connect() is not used. Instead the driver + * just waits for the LDC_EVENT_UP event. + */ +struct ldc_channel_config { + void (*event)(void *arg, int event); + + u32 mtu; + unsigned int rx_irq; + unsigned int tx_irq; + u8 mode; +#define LDC_MODE_RAW 0x00 +#define LDC_MODE_UNRELIABLE 0x01 +#define LDC_MODE_RESERVED 0x02 +#define LDC_MODE_STREAM 0x03 + + u8 debug; +#define LDC_DEBUG_HS 0x01 +#define LDC_DEBUG_STATE 0x02 +#define LDC_DEBUG_RX 0x04 +#define LDC_DEBUG_TX 0x08 +#define LDC_DEBUG_DATA 0x10 +}; + +#define LDC_EVENT_RESET 0x01 +#define LDC_EVENT_UP 0x02 +#define LDC_EVENT_DATA_READY 0x04 + +#define LDC_STATE_INVALID 0x00 +#define LDC_STATE_INIT 0x01 +#define LDC_STATE_BOUND 0x02 +#define LDC_STATE_READY 0x03 +#define LDC_STATE_CONNECTED 0x04 + +struct ldc_channel; + +/* Allocate state for a channel. */ +extern struct ldc_channel *ldc_alloc(unsigned long id, + const struct ldc_channel_config *cfgp, + void *event_arg); + +/* Shut down and free state for a channel. */ +extern void ldc_free(struct ldc_channel *lp); + +/* Register TX and RX queues of the link with the hypervisor. */ +extern int ldc_bind(struct ldc_channel *lp, const char *name); + +/* For non-RAW protocols we need to complete a handshake before + * communication can proceed. ldc_connect() does that, if the + * handshake completes successfully, an LDC_EVENT_UP event will + * be sent up to the driver. + */ +extern int ldc_connect(struct ldc_channel *lp); +extern int ldc_disconnect(struct ldc_channel *lp); + +extern int ldc_state(struct ldc_channel *lp); + +/* Read and write operations. Only valid when the link is up. */ +extern int ldc_write(struct ldc_channel *lp, const void *buf, + unsigned int size); +extern int ldc_read(struct ldc_channel *lp, void *buf, unsigned int size); + +#define LDC_MAP_SHADOW 0x01 +#define LDC_MAP_DIRECT 0x02 +#define LDC_MAP_IO 0x04 +#define LDC_MAP_R 0x08 +#define LDC_MAP_W 0x10 +#define LDC_MAP_X 0x20 +#define LDC_MAP_RW (LDC_MAP_R | LDC_MAP_W) +#define LDC_MAP_RWX (LDC_MAP_R | LDC_MAP_W | LDC_MAP_X) +#define LDC_MAP_ALL 0x03f + +struct ldc_trans_cookie { + u64 cookie_addr; + u64 cookie_size; +}; + +struct scatterlist; +extern int ldc_map_sg(struct ldc_channel *lp, + struct scatterlist *sg, int num_sg, + struct ldc_trans_cookie *cookies, int ncookies, + unsigned int map_perm); + +extern int ldc_map_single(struct ldc_channel *lp, + void *buf, unsigned int len, + struct ldc_trans_cookie *cookies, int ncookies, + unsigned int map_perm); + +extern void ldc_unmap(struct ldc_channel *lp, struct ldc_trans_cookie *cookies, + int ncookies); + +extern int ldc_copy(struct ldc_channel *lp, int copy_dir, + void *buf, unsigned int len, unsigned long offset, + struct ldc_trans_cookie *cookies, int ncookies); + +static inline int ldc_get_dring_entry(struct ldc_channel *lp, + void *buf, unsigned int len, + unsigned long offset, + struct ldc_trans_cookie *cookies, + int ncookies) +{ + return ldc_copy(lp, LDC_COPY_IN, buf, len, offset, cookies, ncookies); +} + +static inline int ldc_put_dring_entry(struct ldc_channel *lp, + void *buf, unsigned int len, + unsigned long offset, + struct ldc_trans_cookie *cookies, + int ncookies) +{ + return ldc_copy(lp, LDC_COPY_OUT, buf, len, offset, cookies, ncookies); +} + +extern void *ldc_alloc_exp_dring(struct ldc_channel *lp, unsigned int len, + struct ldc_trans_cookie *cookies, + int *ncookies, unsigned int map_perm); + +extern void ldc_free_exp_dring(struct ldc_channel *lp, void *buf, + unsigned int len, + struct ldc_trans_cookie *cookies, int ncookies); + +#endif /* _SPARC64_LDC_H */ diff --git a/include/asm-sparc64/mdesc.h b/include/asm-sparc64/mdesc.h index c6383982b53d..e97c43133752 100644 --- a/include/asm-sparc64/mdesc.h +++ b/include/asm-sparc64/mdesc.h @@ -2,38 +2,66 @@ #define _SPARC64_MDESC_H #include <linux/types.h> +#include <linux/cpumask.h> #include <asm/prom.h> -struct mdesc_node; -struct mdesc_arc { - const char *name; - struct mdesc_node *arc; -}; - -struct mdesc_node { - const char *name; - u64 node; - unsigned int unique_id; - unsigned int num_arcs; - unsigned int irqs[2]; - struct property *properties; - struct mdesc_node *hash_next; - struct mdesc_node *allnodes_next; - struct mdesc_arc arcs[0]; -}; - -extern struct mdesc_node *md_find_node_by_name(struct mdesc_node *from, - const char *name); -#define md_for_each_node_by_name(__mn, __name) \ - for (__mn = md_find_node_by_name(NULL, __name); __mn; \ - __mn = md_find_node_by_name(__mn, __name)) - -extern struct property *md_find_property(const struct mdesc_node *mp, - const char *name, - int *lenp); -extern const void *md_get_property(const struct mdesc_node *mp, - const char *name, - int *lenp); +struct mdesc_handle; + +/* Machine description operations are to be surrounded by grab and + * release calls. The mdesc_handle returned from the grab is + * the first argument to all of the operational calls that work + * on mdescs. + */ +extern struct mdesc_handle *mdesc_grab(void); +extern void mdesc_release(struct mdesc_handle *); + +#define MDESC_NODE_NULL (~(u64)0) + +extern u64 mdesc_node_by_name(struct mdesc_handle *handle, + u64 from_node, const char *name); +#define mdesc_for_each_node_by_name(__hdl, __node, __name) \ + for (__node = mdesc_node_by_name(__hdl, MDESC_NODE_NULL, __name); \ + (__node) != MDESC_NODE_NULL; \ + __node = mdesc_node_by_name(__hdl, __node, __name)) + +/* Access to property values returned from mdesc_get_property() are + * only valid inside of a mdesc_grab()/mdesc_release() sequence. + * Once mdesc_release() is called, the memory backed up by these + * pointers may reference freed up memory. + * + * Therefore callers must make copies of any property values + * they need. + * + * These same rules apply to mdesc_node_name(). + */ +extern const void *mdesc_get_property(struct mdesc_handle *handle, + u64 node, const char *name, int *lenp); +extern const char *mdesc_node_name(struct mdesc_handle *hp, u64 node); + +/* MD arc iteration, the standard sequence is: + * + * unsigned long arc; + * mdesc_for_each_arc(arc, handle, node, MDESC_ARC_TYPE_{FWD,BACK}) { + * unsigned long target = mdesc_arc_target(handle, arc); + * ... + * } + */ + +#define MDESC_ARC_TYPE_FWD "fwd" +#define MDESC_ARC_TYPE_BACK "back" + +extern u64 mdesc_next_arc(struct mdesc_handle *handle, u64 from, + const char *arc_type); +#define mdesc_for_each_arc(__arc, __hdl, __node, __type) \ + for (__arc = mdesc_next_arc(__hdl, __node, __type); \ + (__arc) != MDESC_NODE_NULL; \ + __arc = mdesc_next_arc(__hdl, __arc, __type)) + +extern u64 mdesc_arc_target(struct mdesc_handle *hp, u64 arc); + +extern void mdesc_update(void); + +extern void mdesc_fill_in_cpu_data(cpumask_t mask); extern void sun4v_mdesc_init(void); diff --git a/include/asm-sparc64/mmu_context.h b/include/asm-sparc64/mmu_context.h index 8d129032013e..9fc225ed5500 100644 --- a/include/asm-sparc64/mmu_context.h +++ b/include/asm-sparc64/mmu_context.h @@ -76,6 +76,9 @@ static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, str unsigned long ctx_valid, flags; int cpu; + if (unlikely(mm == &init_mm)) + return; + spin_lock_irqsave(&mm->context.lock, flags); ctx_valid = CTX_VALID(mm->context); if (!ctx_valid) diff --git a/include/asm-sparc64/pci.h b/include/asm-sparc64/pci.h index 47cea16e1bad..e11ac100f043 100644 --- a/include/asm-sparc64/pci.h +++ b/include/asm-sparc64/pci.h @@ -206,49 +206,6 @@ extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask); #define PCI64_REQUIRED_MASK (~(dma64_addr_t)0) #define PCI64_ADDR_BASE 0xfffc000000000000UL -/* Usage of the pci_dac_foo interfaces is only valid if this - * test passes. - */ -#define pci_dac_dma_supported(pci_dev, mask) \ - ((((mask) & PCI64_REQUIRED_MASK) == PCI64_REQUIRED_MASK) ? 1 : 0) - -static inline dma64_addr_t -pci_dac_page_to_dma(struct pci_dev *pdev, struct page *page, unsigned long offset, int direction) -{ - return (PCI64_ADDR_BASE + - __pa(page_address(page)) + offset); -} - -static inline struct page * -pci_dac_dma_to_page(struct pci_dev *pdev, dma64_addr_t dma_addr) -{ - unsigned long paddr = (dma_addr & PAGE_MASK) - PCI64_ADDR_BASE; - - return virt_to_page(__va(paddr)); -} - -static inline unsigned long -pci_dac_dma_to_offset(struct pci_dev *pdev, dma64_addr_t dma_addr) -{ - return (dma_addr & ~PAGE_MASK); -} - -static inline void -pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) -{ - /* DAC cycle addressing does not make use of the - * PCI controller's streaming cache, so nothing to do. - */ -} - -static inline void -pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) -{ - /* DAC cycle addressing does not make use of the - * PCI controller's streaming cache, so nothing to do. - */ -} - #define PCI_DMA_ERROR_CODE (~(dma_addr_t)0x0) static inline int pci_dma_mapping_error(dma_addr_t dma_addr) @@ -303,10 +260,6 @@ pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, extern struct resource *pcibios_select_root(struct pci_dev *, struct resource *); -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) { return PCI_IRQ_NONE; diff --git a/include/asm-sparc64/pgtable.h b/include/asm-sparc64/pgtable.h index 9e80ad43b29c..0393380d754a 100644 --- a/include/asm-sparc64/pgtable.h +++ b/include/asm-sparc64/pgtable.h @@ -573,24 +573,6 @@ static inline unsigned long pte_exec(pte_t pte) return (pte_val(pte) & mask); } -static inline unsigned long pte_read(pte_t pte) -{ - unsigned long mask; - - __asm__ __volatile__( - "\n661: mov %1, %0\n" - " nop\n" - " .section .sun4v_2insn_patch, \"ax\"\n" - " .word 661b\n" - " sethi %%uhi(%2), %0\n" - " sllx %0, 32, %0\n" - " .previous\n" - : "=r" (mask) - : "i" (_PAGE_READ_4U), "i" (_PAGE_READ_4V)); - - return (pte_val(pte) & mask); -} - static inline unsigned long pte_file(pte_t pte) { unsigned long val = pte_val(pte); diff --git a/include/asm-sparc64/power.h b/include/asm-sparc64/power.h new file mode 100644 index 000000000000..94495c1ac4f6 --- /dev/null +++ b/include/asm-sparc64/power.h @@ -0,0 +1,7 @@ +#ifndef _SPARC64_POWER_H +#define _SPARC64_POWER_H + +extern void wake_up_powerd(void); +extern int start_powerd(void); + +#endif /* !(_SPARC64_POWER_H) */ diff --git a/include/asm-sparc64/smp.h b/include/asm-sparc64/smp.h index 4fb8c4bfb848..e8a96a31761b 100644 --- a/include/asm-sparc64/smp.h +++ b/include/asm-sparc64/smp.h @@ -29,9 +29,6 @@ #include <asm/bitops.h> #include <asm/atomic.h> -extern cpumask_t phys_cpu_present_map; -#define cpu_possible_map phys_cpu_present_map - extern cpumask_t cpu_sibling_map[NR_CPUS]; extern cpumask_t cpu_core_map[NR_CPUS]; extern int sparc64_multi_core; @@ -44,7 +41,12 @@ extern int hard_smp_processor_id(void); #define raw_smp_processor_id() (current_thread_info()->cpu) extern void smp_fill_in_sib_core_maps(void); -extern unsigned char boot_cpu_id; +extern void cpu_play_dead(void); + +#ifdef CONFIG_HOTPLUG_CPU +extern int __cpu_disable(void); +extern void __cpu_die(unsigned int cpu); +#endif #endif /* !(__ASSEMBLY__) */ @@ -52,7 +54,6 @@ extern unsigned char boot_cpu_id; #define hard_smp_processor_id() 0 #define smp_fill_in_sib_core_maps() do { } while (0) -#define boot_cpu_id (0) #endif /* !(CONFIG_SMP) */ diff --git a/include/asm-sparc64/vio.h b/include/asm-sparc64/vio.h new file mode 100644 index 000000000000..83c96422e9d6 --- /dev/null +++ b/include/asm-sparc64/vio.h @@ -0,0 +1,404 @@ +#ifndef _SPARC64_VIO_H +#define _SPARC64_VIO_H + +#include <linux/kernel.h> +#include <linux/device.h> +#include <linux/mod_devicetable.h> +#include <linux/timer.h> +#include <linux/spinlock.h> +#include <linux/completion.h> +#include <linux/list.h> + +#include <asm/ldc.h> +#include <asm/mdesc.h> + +struct vio_msg_tag { + u8 type; +#define VIO_TYPE_CTRL 0x01 +#define VIO_TYPE_DATA 0x02 +#define VIO_TYPE_ERR 0x04 + + u8 stype; +#define VIO_SUBTYPE_INFO 0x01 +#define VIO_SUBTYPE_ACK 0x02 +#define VIO_SUBTYPE_NACK 0x04 + + u16 stype_env; +#define VIO_VER_INFO 0x0001 +#define VIO_ATTR_INFO 0x0002 +#define VIO_DRING_REG 0x0003 +#define VIO_DRING_UNREG 0x0004 +#define VIO_RDX 0x0005 +#define VIO_PKT_DATA 0x0040 +#define VIO_DESC_DATA 0x0041 +#define VIO_DRING_DATA 0x0042 +#define VNET_MCAST_INFO 0x0101 + + u32 sid; +}; + +struct vio_rdx { + struct vio_msg_tag tag; + u64 resv[6]; +}; + +struct vio_ver_info { + struct vio_msg_tag tag; + u16 major; + u16 minor; + u8 dev_class; +#define VDEV_NETWORK 0x01 +#define VDEV_NETWORK_SWITCH 0x02 +#define VDEV_DISK 0x03 +#define VDEV_DISK_SERVER 0x04 + + u8 resv1[3]; + u64 resv2[5]; +}; + +struct vio_dring_register { + struct vio_msg_tag tag; + u64 dring_ident; + u32 num_descr; + u32 descr_size; + u16 options; +#define VIO_TX_DRING 0x0001 +#define VIO_RX_DRING 0x0002 + u16 resv; + u32 num_cookies; + struct ldc_trans_cookie cookies[0]; +}; + +struct vio_dring_unregister { + struct vio_msg_tag tag; + u64 dring_ident; + u64 resv[5]; +}; + +/* Data transfer modes */ +#define VIO_PKT_MODE 0x01 /* Packet based transfer */ +#define VIO_DESC_MODE 0x02 /* In-band descriptors */ +#define VIO_DRING_MODE 0x03 /* Descriptor rings */ + +struct vio_dring_data { + struct vio_msg_tag tag; + u64 seq; + u64 dring_ident; + u32 start_idx; + u32 end_idx; + u8 state; +#define VIO_DRING_ACTIVE 0x01 +#define VIO_DRING_STOPPED 0x02 + + u8 __pad1; + u16 __pad2; + u32 __pad3; + u64 __par4[2]; +}; + +struct vio_dring_hdr { + u8 state; +#define VIO_DESC_FREE 0x01 +#define VIO_DESC_READY 0x02 +#define VIO_DESC_ACCEPTED 0x03 +#define VIO_DESC_DONE 0x04 + u8 ack; +#define VIO_ACK_ENABLE 0x01 +#define VIO_ACK_DISABLE 0x00 + + u16 __pad1; + u32 __pad2; +}; + +/* VIO disk specific structures and defines */ +struct vio_disk_attr_info { + struct vio_msg_tag tag; + u8 xfer_mode; + u8 vdisk_type; +#define VD_DISK_TYPE_SLICE 0x01 /* Slice in block device */ +#define VD_DISK_TYPE_DISK 0x02 /* Entire block device */ + u16 resv1; + u32 vdisk_block_size; + u64 operations; + u64 vdisk_size; + u64 max_xfer_size; + u64 resv2[2]; +}; + +struct vio_disk_desc { + struct vio_dring_hdr hdr; + u64 req_id; + u8 operation; +#define VD_OP_BREAD 0x01 /* Block read */ +#define VD_OP_BWRITE 0x02 /* Block write */ +#define VD_OP_FLUSH 0x03 /* Flush disk contents */ +#define VD_OP_GET_WCE 0x04 /* Get write-cache status */ +#define VD_OP_SET_WCE 0x05 /* Enable/disable write-cache */ +#define VD_OP_GET_VTOC 0x06 /* Get VTOC */ +#define VD_OP_SET_VTOC 0x07 /* Set VTOC */ +#define VD_OP_GET_DISKGEOM 0x08 /* Get disk geometry */ +#define VD_OP_SET_DISKGEOM 0x09 /* Set disk geometry */ +#define VD_OP_SCSICMD 0x0a /* SCSI control command */ +#define VD_OP_GET_DEVID 0x0b /* Get device ID */ +#define VD_OP_GET_EFI 0x0c /* Get EFI */ +#define VD_OP_SET_EFI 0x0d /* Set EFI */ + u8 slice; + u16 resv1; + u32 status; + u64 offset; + u64 size; + u32 ncookies; + u32 resv2; + struct ldc_trans_cookie cookies[0]; +}; + +#define VIO_DISK_VNAME_LEN 8 +#define VIO_DISK_ALABEL_LEN 128 +#define VIO_DISK_NUM_PART 8 + +struct vio_disk_vtoc { + u8 volume_name[VIO_DISK_VNAME_LEN]; + u16 sector_size; + u16 num_partitions; + u8 ascii_label[VIO_DISK_ALABEL_LEN]; + struct { + u16 id; + u16 perm_flags; + u32 resv; + u64 start_block; + u64 num_blocks; + } partitions[VIO_DISK_NUM_PART]; +}; + +struct vio_disk_geom { + u16 num_cyl; /* Num data cylinders */ + u16 alt_cyl; /* Num alternate cylinders */ + u16 beg_cyl; /* Cyl off of fixed head area */ + u16 num_hd; /* Num heads */ + u16 num_sec; /* Num sectors */ + u16 ifact; /* Interleave factor */ + u16 apc; /* Alts per cylinder (SCSI) */ + u16 rpm; /* Revolutions per minute */ + u16 phy_cyl; /* Num physical cylinders */ + u16 wr_skip; /* Num sects to skip, writes */ + u16 rd_skip; /* Num sects to skip, writes */ +}; + +struct vio_disk_devid { + u16 resv; + u16 type; + u32 len; + char id[0]; +}; + +struct vio_disk_efi { + u64 lba; + u64 len; + char data[0]; +}; + +/* VIO net specific structures and defines */ +struct vio_net_attr_info { + struct vio_msg_tag tag; + u8 xfer_mode; + u8 addr_type; +#define VNET_ADDR_ETHERMAC 0x01 + u16 ack_freq; + u32 resv1; + u64 addr; + u64 mtu; + u64 resv2[3]; +}; + +#define VNET_NUM_MCAST 7 + +struct vio_net_mcast_info { + struct vio_msg_tag tag; + u8 set; + u8 count; + u8 mcast_addr[VNET_NUM_MCAST * 6]; + u32 resv; +}; + +struct vio_net_desc { + struct vio_dring_hdr hdr; + u32 size; + u32 ncookies; + struct ldc_trans_cookie cookies[0]; +}; + +#define VIO_MAX_RING_COOKIES 24 + +struct vio_dring_state { + u64 ident; + void *base; + u64 snd_nxt; + u64 rcv_nxt; + u32 entry_size; + u32 num_entries; + u32 prod; + u32 cons; + u32 pending; + int ncookies; + struct ldc_trans_cookie cookies[VIO_MAX_RING_COOKIES]; +}; + +static inline void *vio_dring_cur(struct vio_dring_state *dr) +{ + return dr->base + (dr->entry_size * dr->prod); +} + +static inline void *vio_dring_entry(struct vio_dring_state *dr, + unsigned int index) +{ + return dr->base + (dr->entry_size * index); +} + +static inline u32 vio_dring_avail(struct vio_dring_state *dr, + unsigned int ring_size) +{ + /* Ensure build-time power-of-2. */ + BUILD_BUG_ON(ring_size & (ring_size - 1)); + + return (dr->pending - + ((dr->prod - dr->cons) & (ring_size - 1))); +} + +#define VIO_MAX_TYPE_LEN 64 +#define VIO_MAX_COMPAT_LEN 64 + +struct vio_dev { + u64 mp; + struct device_node *dp; + + char type[VIO_MAX_TYPE_LEN]; + char compat[VIO_MAX_COMPAT_LEN]; + int compat_len; + + unsigned long channel_id; + + unsigned int tx_irq; + unsigned int rx_irq; + + struct device dev; +}; + +struct vio_driver { + struct list_head node; + const struct vio_device_id *id_table; + int (*probe)(struct vio_dev *dev, const struct vio_device_id *id); + int (*remove)(struct vio_dev *dev); + void (*shutdown)(struct vio_dev *dev); + unsigned long driver_data; + struct device_driver driver; +}; + +struct vio_version { + u16 major; + u16 minor; +}; + +struct vio_driver_state; +struct vio_driver_ops { + int (*send_attr)(struct vio_driver_state *vio); + int (*handle_attr)(struct vio_driver_state *vio, void *pkt); + void (*handshake_complete)(struct vio_driver_state *vio); +}; + +struct vio_completion { + struct completion com; + int err; + int waiting_for; +}; + +struct vio_driver_state { + /* Protects VIO handshake and, optionally, driver private state. */ + spinlock_t lock; + + struct ldc_channel *lp; + + u32 _peer_sid; + u32 _local_sid; + struct vio_dring_state drings[2]; +#define VIO_DRIVER_TX_RING 0 +#define VIO_DRIVER_RX_RING 1 + + u8 hs_state; +#define VIO_HS_INVALID 0x00 +#define VIO_HS_GOTVERS 0x01 +#define VIO_HS_GOT_ATTR 0x04 +#define VIO_HS_SENT_DREG 0x08 +#define VIO_HS_SENT_RDX 0x10 +#define VIO_HS_GOT_RDX_ACK 0x20 +#define VIO_HS_GOT_RDX 0x40 +#define VIO_HS_SENT_RDX_ACK 0x80 +#define VIO_HS_COMPLETE (VIO_HS_GOT_RDX_ACK | VIO_HS_SENT_RDX_ACK) + + u8 dev_class; + + u8 dr_state; +#define VIO_DR_STATE_TXREG 0x01 +#define VIO_DR_STATE_RXREG 0x02 +#define VIO_DR_STATE_TXREQ 0x10 +#define VIO_DR_STATE_RXREQ 0x20 + + u8 debug; +#define VIO_DEBUG_HS 0x01 +#define VIO_DEBUG_DATA 0x02 + + void *desc_buf; + unsigned int desc_buf_len; + + struct vio_completion *cmp; + + struct vio_dev *vdev; + + struct timer_list timer; + + struct vio_version ver; + + struct vio_version *ver_table; + int ver_table_entries; + + char *name; + + struct vio_driver_ops *ops; +}; + +#define viodbg(TYPE, f, a...) \ +do { if (vio->debug & VIO_DEBUG_##TYPE) \ + printk(KERN_INFO "vio: ID[%lu] " f, \ + vio->vdev->channel_id, ## a); \ +} while (0) + +extern int vio_register_driver(struct vio_driver *drv); +extern void vio_unregister_driver(struct vio_driver *drv); + +static inline struct vio_driver *to_vio_driver(struct device_driver *drv) +{ + return container_of(drv, struct vio_driver, driver); +} + +static inline struct vio_dev *to_vio_dev(struct device *dev) +{ + return container_of(dev, struct vio_dev, dev); +} + +extern int vio_ldc_send(struct vio_driver_state *vio, void *data, int len); +extern void vio_link_state_change(struct vio_driver_state *vio, int event); +extern void vio_conn_reset(struct vio_driver_state *vio); +extern int vio_control_pkt_engine(struct vio_driver_state *vio, void *pkt); +extern int vio_validate_sid(struct vio_driver_state *vio, + struct vio_msg_tag *tp); +extern u32 vio_send_sid(struct vio_driver_state *vio); +extern int vio_ldc_alloc(struct vio_driver_state *vio, + struct ldc_channel_config *base_cfg, void *event_arg); +extern void vio_ldc_free(struct vio_driver_state *vio); +extern int vio_driver_init(struct vio_driver_state *vio, struct vio_dev *vdev, + u8 dev_class, struct vio_version *ver_table, + int ver_table_size, struct vio_driver_ops *ops, + char *name); + +extern void vio_port_up(struct vio_driver_state *vio); + +#endif /* _SPARC64_VIO_H */ diff --git a/include/asm-um/pgtable.h b/include/asm-um/pgtable.h index 1b1090a91a58..830fc6e5d49d 100644 --- a/include/asm-um/pgtable.h +++ b/include/asm-um/pgtable.h @@ -175,12 +175,6 @@ static inline int pte_none(pte_t pte) * The following only work if pte_present() is true. * Undefined behaviour if not.. */ -static inline int pte_user(pte_t pte) -{ - return((pte_get_bits(pte, _PAGE_USER)) && - !(pte_get_bits(pte, _PAGE_PROTNONE))); -} - static inline int pte_read(pte_t pte) { return((pte_get_bits(pte, _PAGE_USER)) && @@ -238,18 +232,6 @@ static inline pte_t pte_mknewprot(pte_t pte) return(pte); } -static inline pte_t pte_rdprotect(pte_t pte) -{ - pte_clear_bits(pte, _PAGE_USER); - return(pte_mknewprot(pte)); -} - -static inline pte_t pte_exprotect(pte_t pte) -{ - pte_clear_bits(pte, _PAGE_USER); - return(pte_mknewprot(pte)); -} - static inline pte_t pte_mkclean(pte_t pte) { pte_clear_bits(pte, _PAGE_DIRTY); diff --git a/include/asm-um/thread_info.h b/include/asm-um/thread_info.h index 18a13ba74605..6e5fd5c892d0 100644 --- a/include/asm-um/thread_info.h +++ b/include/asm-um/thread_info.h @@ -52,10 +52,21 @@ static inline struct thread_info *current_thread_info(void) return ti; } +#ifdef CONFIG_DEBUG_STACK_USAGE + +#define alloc_thread_info(tsk) \ + ((struct thread_info *) __get_free_pages(GFP_KERNEL | __GFP_ZERO, \ + CONFIG_KERNEL_STACK_ORDER)) +#else + /* thread information allocation */ #define alloc_thread_info(tsk) \ - ((struct thread_info *) kmalloc(THREAD_SIZE, GFP_KERNEL)) -#define free_thread_info(ti) kfree(ti) + ((struct thread_info *) __get_free_pages(GFP_KERNEL, \ + CONFIG_KERNEL_STACK_ORDER)) +#endif + +#define free_thread_info(ti) \ + free_pages((unsigned long)(ti),CONFIG_KERNEL_STACK_ORDER) #endif diff --git a/include/asm-v850/ioctls.h b/include/asm-v850/ioctls.h index 05c0dc9ce1ea..5313abd5f388 100644 --- a/include/asm-v850/ioctls.h +++ b/include/asm-v850/ioctls.h @@ -46,6 +46,10 @@ #define TIOCSBRK 0x5427 /* BSD compatibility */ #define TIOCCBRK 0x5428 /* BSD compatibility */ #define TIOCGSID 0x5429 /* Return the session ID of FD */ +#define TCGETS2 _IOR('T',0x2A, struct termios2) +#define TCSETS2 _IOW('T',0x2B, struct termios2) +#define TCSETSW2 _IOW('T',0x2C, struct termios2) +#define TCSETSF2 _IOW('T',0x2D, struct termios2) #define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ diff --git a/include/asm-v850/pci.h b/include/asm-v850/pci.h index 4581826e1cac..de2a7d0a81cc 100644 --- a/include/asm-v850/pci.h +++ b/include/asm-v850/pci.h @@ -116,8 +116,4 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); extern void pci_iounmap (struct pci_dev *dev, void __iomem *addr); -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #endif /* __V850_PCI_H__ */ diff --git a/include/asm-v850/rte_cb.h b/include/asm-v850/rte_cb.h index 9f7f02cb0391..e85d261b79bf 100644 --- a/include/asm-v850/rte_cb.h +++ b/include/asm-v850/rte_cb.h @@ -64,7 +64,6 @@ /* As we don't really support PCI DMA to cpu memory, and use bounce-buffers instead, perversely enough, this becomes always true! */ # define pci_dma_supported(dev, mask) 1 -# define pci_dac_dma_supported(dev, mask) 0 # define pcibios_assign_all_busses() 1 #endif /* CONFIG_RTE_MB_A_PCI */ diff --git a/include/asm-v850/termbits.h b/include/asm-v850/termbits.h index f3b433032089..295d7bf69451 100644 --- a/include/asm-v850/termbits.h +++ b/include/asm-v850/termbits.h @@ -17,6 +17,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ @@ -130,6 +141,7 @@ struct ktermios { #define HUPCL 0002000 #define CLOCAL 0004000 #define CBAUDEX 0010000 +#define BOTHER 0010000 #define B57600 0010001 #define B115200 0010002 #define B230400 0010003 @@ -145,10 +157,12 @@ struct ktermios { #define B3000000 0010015 #define B3500000 0010016 #define B4000000 0010017 -#define CIBAUD 002003600000 /* input baud rate (not used) */ +#define CIBAUD 002003600000 /* input baud rate */ #define CMSPAR 010000000000 /* mark or space (stick) parity */ #define CRTSCTS 020000000000 /* flow control */ +#define IBSHIFT 16 /* Shifr from CBAUD to CIBAUD */ + /* c_lflag bits */ #define ISIG 0000001 #define ICANON 0000002 diff --git a/include/asm-v850/termios.h b/include/asm-v850/termios.h index c2c2b1d58776..fcd171838d9c 100644 --- a/include/asm-v850/termios.h +++ b/include/asm-v850/termios.h @@ -80,8 +80,10 @@ struct termio { copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ }) -#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) -#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) +#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) +#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) +#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) +#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) #endif /* __KERNEL__ */ diff --git a/include/asm-x86_64/alternative.h b/include/asm-x86_64/alternative.h index a09427640764..eea7aecfac78 100644 --- a/include/asm-x86_64/alternative.h +++ b/include/asm-x86_64/alternative.h @@ -5,6 +5,41 @@ #include <linux/types.h> #include <linux/stddef.h> + +/* + * Alternative inline assembly for SMP. + * + * The LOCK_PREFIX macro defined here replaces the LOCK and + * LOCK_PREFIX macros used everywhere in the source tree. + * + * SMP alternatives use the same data structures as the other + * alternatives and the X86_FEATURE_UP flag to indicate the case of a + * UP system running a SMP kernel. The existing apply_alternatives() + * works fine for patching a SMP kernel for UP. + * + * The SMP alternative tables can be kept after boot and contain both + * UP and SMP versions of the instructions to allow switching back to + * SMP at runtime, when hotplugging in a new CPU, which is especially + * useful in virtualized environments. + * + * The very common lock prefix is handled as special case in a + * separate table which is a pure address list without replacement ptr + * and size information. That keeps the table sizes small. + */ + +#ifdef CONFIG_SMP +#define LOCK_PREFIX \ + ".section .smp_locks,\"a\"\n" \ + " .align 8\n" \ + " .quad 661f\n" /* address */ \ + ".previous\n" \ + "661:\n\tlock; " + +#else /* ! CONFIG_SMP */ +#define LOCK_PREFIX "" +#endif + +/* This must be included *after* the definition of LOCK_PREFIX */ #include <asm/cpufeature.h> struct alt_instr { @@ -108,39 +143,6 @@ static inline void alternatives_smp_switch(int smp) {} */ #define ASM_OUTPUT2(a, b) a, b -/* - * Alternative inline assembly for SMP. - * - * The LOCK_PREFIX macro defined here replaces the LOCK and - * LOCK_PREFIX macros used everywhere in the source tree. - * - * SMP alternatives use the same data structures as the other - * alternatives and the X86_FEATURE_UP flag to indicate the case of a - * UP system running a SMP kernel. The existing apply_alternatives() - * works fine for patching a SMP kernel for UP. - * - * The SMP alternative tables can be kept after boot and contain both - * UP and SMP versions of the instructions to allow switching back to - * SMP at runtime, when hotplugging in a new CPU, which is especially - * useful in virtualized environments. - * - * The very common lock prefix is handled as special case in a - * separate table which is a pure address list without replacement ptr - * and size information. That keeps the table sizes small. - */ - -#ifdef CONFIG_SMP -#define LOCK_PREFIX \ - ".section .smp_locks,\"a\"\n" \ - " .align 8\n" \ - " .quad 661f\n" /* address */ \ - ".previous\n" \ - "661:\n\tlock; " - -#else /* ! CONFIG_SMP */ -#define LOCK_PREFIX "" -#endif - struct paravirt_patch; #ifdef CONFIG_PARAVIRT void apply_paravirt(struct paravirt_patch *start, struct paravirt_patch *end); diff --git a/include/asm-x86_64/boot.h b/include/asm-x86_64/boot.h index 96b228e6e79c..3c46cea8db7f 100644 --- a/include/asm-x86_64/boot.h +++ b/include/asm-x86_64/boot.h @@ -1,15 +1 @@ -#ifndef _LINUX_BOOT_H -#define _LINUX_BOOT_H - -/* Don't touch these, unless you really know what you're doing. */ -#define DEF_INITSEG 0x9000 -#define DEF_SYSSEG 0x1000 -#define DEF_SETUPSEG 0x9020 -#define DEF_SYSSIZE 0x7F00 - -/* Internal svga startup constants */ -#define NORMAL_VGA 0xffff /* 80x25 mode */ -#define EXTENDED_VGA 0xfffe /* 80x50 mode */ -#define ASK_VGA 0xfffd /* ask for it at bootup */ - -#endif +#include <asm-i386/boot.h> diff --git a/include/asm-x86_64/bootparam.h b/include/asm-x86_64/bootparam.h new file mode 100644 index 000000000000..aa82e5238d82 --- /dev/null +++ b/include/asm-x86_64/bootparam.h @@ -0,0 +1 @@ +#include <asm-i386/bootparam.h> diff --git a/include/asm-x86_64/compat.h b/include/asm-x86_64/compat.h index b37ab8218ef0..53cb96b68a62 100644 --- a/include/asm-x86_64/compat.h +++ b/include/asm-x86_64/compat.h @@ -33,8 +33,10 @@ typedef s32 compat_key_t; typedef s32 compat_int_t; typedef s32 compat_long_t; +typedef s64 __attribute__((aligned(4))) compat_s64; typedef u32 compat_uint_t; typedef u32 compat_ulong_t; +typedef u64 __attribute__((aligned(4))) compat_u64; struct compat_timespec { compat_time_t tv_sec; diff --git a/include/asm-x86_64/cpufeature.h b/include/asm-x86_64/cpufeature.h index 0b3c686139f1..8baefc3beb2e 100644 --- a/include/asm-x86_64/cpufeature.h +++ b/include/asm-x86_64/cpufeature.h @@ -7,115 +7,24 @@ #ifndef __ASM_X8664_CPUFEATURE_H #define __ASM_X8664_CPUFEATURE_H -#define NCAPINTS 7 /* N 32-bit words worth of info */ +#include <asm-i386/cpufeature.h> -/* Intel-defined CPU features, CPUID level 0x00000001, word 0 */ -#define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */ -#define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */ -#define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */ -#define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */ -#define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */ -#define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */ -#define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */ -#define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Architecture */ -#define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */ -#define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */ -#define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */ -#define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */ -#define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */ -#define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */ -#define X86_FEATURE_CMOV (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */ -#define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */ -#define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */ -#define X86_FEATURE_PN (0*32+18) /* Processor serial number */ -#define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */ -#define X86_FEATURE_DS (0*32+21) /* Debug Store */ -#define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */ -#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */ -#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */ - /* of FPU context), and CR4.OSFXSR available */ -#define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD Extensions */ -#define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */ -#define X86_FEATURE_SELFSNOOP (0*32+27) /* CPU self snoop */ -#define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */ -#define X86_FEATURE_ACC (0*32+29) /* Automatic clock control */ -#define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */ - -/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ -/* Don't duplicate feature flags which are redundant with Intel! */ -#define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */ -#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */ -#define X86_FEATURE_FXSR_OPT (1*32+25) /* FXSR optimizations */ -#define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */ -#define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */ -#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */ -#define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */ - -/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ -#define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */ -#define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */ -#define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */ - -/* Other features, Linux-defined mapping, word 3 */ -/* This range is used for feature bits which conflict or are synthesized */ -#define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */ -#define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */ -#define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */ -#define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */ -#define X86_FEATURE_REP_GOOD (3*32+ 4) /* rep microcode works well on this CPU */ -#define X86_FEATURE_CONSTANT_TSC (3*32+5) /* TSC runs at constant rate */ -#define X86_FEATURE_SYNC_RDTSC (3*32+6) /* RDTSC syncs CPU core */ -#define X86_FEATURE_FXSAVE_LEAK (3*32+7) /* FIP/FOP/FDP leaks through FXSAVE */ -#define X86_FEATURE_UP (3*32+8) /* SMP kernel running on UP */ -#define X86_FEATURE_ARCH_PERFMON (3*32+9) /* Intel Architectural PerfMon */ -#define X86_FEATURE_PEBS (3*32+10) /* Precise-Event Based Sampling */ -#define X86_FEATURE_BTS (3*32+11) /* Branch Trace Store */ - -/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ -#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ -#define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */ -#define X86_FEATURE_DSCPL (4*32+ 4) /* CPL Qualified Debug Store */ -#define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */ -#define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */ -#define X86_FEATURE_CID (4*32+10) /* Context ID */ -#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */ -#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ - -/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ -#define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */ -#define X86_FEATURE_XSTORE_EN (5*32+ 3) /* on-CPU RNG enabled */ -#define X86_FEATURE_XCRYPT (5*32+ 6) /* on-CPU crypto (xcrypt insn) */ -#define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* on-CPU crypto enabled */ - -/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ -#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ -#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ - -#define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) -#define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability) - -#define cpu_has_fpu 1 +#undef cpu_has_vme #define cpu_has_vme 0 -#define cpu_has_de 1 -#define cpu_has_pse 1 -#define cpu_has_tsc 1 + +#undef cpu_has_pae #define cpu_has_pae ___BUG___ -#define cpu_has_pge 1 -#define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC) -#define cpu_has_mtrr 1 -#define cpu_has_mmx 1 -#define cpu_has_fxsr 1 -#define cpu_has_xmm 1 -#define cpu_has_xmm2 1 -#define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3) -#define cpu_has_ht boot_cpu_has(X86_FEATURE_HT) + +#undef cpu_has_mp #define cpu_has_mp 1 /* XXX */ + +#undef cpu_has_k6_mtrr #define cpu_has_k6_mtrr 0 + +#undef cpu_has_cyrix_arr #define cpu_has_cyrix_arr 0 + +#undef cpu_has_centaur_mcr #define cpu_has_centaur_mcr 0 -#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH) -#define cpu_has_ds boot_cpu_has(X86_FEATURE_DS) -#define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS) -#define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS) #endif /* __ASM_X8664_CPUFEATURE_H */ diff --git a/include/asm-x86_64/e820.h b/include/asm-x86_64/e820.h index 6216fa3f2802..3486e701bd86 100644 --- a/include/asm-x86_64/e820.h +++ b/include/asm-x86_64/e820.h @@ -11,8 +11,6 @@ #ifndef __E820_HEADER #define __E820_HEADER -#include <linux/mmzone.h> - #define E820MAP 0x2d0 /* our map */ #define E820MAX 128 /* number of entries in E820MAP */ #define E820NR 0x1e8 /* # entries in E820MAP */ @@ -30,7 +28,7 @@ struct e820entry { } __attribute__((packed)); struct e820map { - int nr_map; + u32 nr_map; struct e820entry map[E820MAX]; }; diff --git a/include/asm-x86_64/fixmap.h b/include/asm-x86_64/fixmap.h index e90e1677531b..2acb9b7f6418 100644 --- a/include/asm-x86_64/fixmap.h +++ b/include/asm-x86_64/fixmap.h @@ -35,6 +35,8 @@ enum fixed_addresses { VSYSCALL_LAST_PAGE, VSYSCALL_FIRST_PAGE = VSYSCALL_LAST_PAGE + ((VSYSCALL_END-VSYSCALL_START) >> PAGE_SHIFT) - 1, VSYSCALL_HPET, + FIX_DBGP_BASE, + FIX_EARLYCON_MEM_BASE, FIX_HPET_BASE, FIX_APIC_BASE, /* local (CPU) APIC) -- required for SMP or not */ FIX_IO_APIC_BASE_0, @@ -84,7 +86,7 @@ static __always_inline unsigned long fix_to_virt(const unsigned int idx) if (idx >= __end_of_fixed_addresses) __this_fixmap_does_not_exist(); - return __fix_to_virt(idx); + return __fix_to_virt(idx); } #endif diff --git a/include/asm-x86_64/io.h b/include/asm-x86_64/io.h index de2cd9a2303a..7475095c5061 100644 --- a/include/asm-x86_64/io.h +++ b/include/asm-x86_64/io.h @@ -144,6 +144,7 @@ extern void early_iounmap(void *addr, unsigned long size); */ extern void __iomem * ioremap_nocache (unsigned long offset, unsigned long size); extern void iounmap(volatile void __iomem *addr); +extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys); /* * ISA I/O bus memory addresses are 1:1 with the physical address. diff --git a/include/asm-x86_64/pci.h b/include/asm-x86_64/pci.h index 49c5e9280598..bda94fd5176f 100644 --- a/include/asm-x86_64/pci.h +++ b/include/asm-x86_64/pci.h @@ -54,14 +54,6 @@ extern int iommu_setup(char *opt); #if defined(CONFIG_IOMMU) || defined(CONFIG_CALGARY_IOMMU) -/* - * x86-64 always supports DAC, but sometimes it is useful to force - * devices through the IOMMU to get automatic sg list merging. - * Optional right now. - */ -extern int iommu_sac_force; -#define pci_dac_dma_supported(pci_dev, mask) (!iommu_sac_force) - #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ dma_addr_t ADDR_NAME; #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ @@ -78,8 +70,6 @@ extern int iommu_sac_force; #else /* No IOMMU */ -#define pci_dac_dma_supported(pci_dev, mask) 1 - #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) #define pci_unmap_addr(PTR, ADDR_NAME) (0) @@ -91,36 +81,6 @@ extern int iommu_sac_force; #include <asm-generic/pci-dma-compat.h> -static inline dma64_addr_t -pci_dac_page_to_dma(struct pci_dev *pdev, struct page *page, unsigned long offset, int direction) -{ - return ((dma64_addr_t) page_to_phys(page) + - (dma64_addr_t) offset); -} - -static inline struct page * -pci_dac_dma_to_page(struct pci_dev *pdev, dma64_addr_t dma_addr) -{ - return virt_to_page(__va(dma_addr)); -} - -static inline unsigned long -pci_dac_dma_to_offset(struct pci_dev *pdev, dma64_addr_t dma_addr) -{ - return (dma_addr & ~PAGE_MASK); -} - -static inline void -pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) -{ -} - -static inline void -pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) -{ - flush_write_buffers(); -} - #ifdef CONFIG_PCI static inline void pci_dma_burst_advice(struct pci_dev *pdev, enum pci_dma_burst_strategy *strat, @@ -135,10 +95,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine); -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #endif /* __KERNEL__ */ /* generic pci stuff */ diff --git a/include/asm-x86_64/pgtable.h b/include/asm-x86_64/pgtable.h index 0a71e0b9a619..4f169ac6b10a 100644 --- a/include/asm-x86_64/pgtable.h +++ b/include/asm-x86_64/pgtable.h @@ -266,21 +266,15 @@ static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot) * Undefined behaviour if not.. */ #define __LARGE_PTE (_PAGE_PSE|_PAGE_PRESENT) -static inline int pte_user(pte_t pte) { return pte_val(pte) & _PAGE_USER; } -static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; } -static inline int pte_exec(pte_t pte) { return !(pte_val(pte) & _PAGE_NX); } static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; } static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } static inline int pte_huge(pte_t pte) { return pte_val(pte) & _PAGE_PSE; } -static inline pte_t pte_rdprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; } -static inline pte_t pte_exprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; } static inline pte_t pte_mkclean(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_DIRTY)); return pte; } static inline pte_t pte_mkold(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_ACCESSED)); return pte; } static inline pte_t pte_wrprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_RW)); return pte; } -static inline pte_t pte_mkread(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_USER)); return pte; } static inline pte_t pte_mkexec(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_NX)); return pte; } static inline pte_t pte_mkdirty(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; } static inline pte_t pte_mkyoung(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; } diff --git a/include/asm-x86_64/processor.h b/include/asm-x86_64/processor.h index 461ffe4c1fcc..efc87a5aff7f 100644 --- a/include/asm-x86_64/processor.h +++ b/include/asm-x86_64/processor.h @@ -100,6 +100,7 @@ extern char ignore_irq13; extern void identify_cpu(struct cpuinfo_x86 *); extern void print_cpu_info(struct cpuinfo_x86 *); +extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); extern unsigned short num_cache_leaves; @@ -368,8 +369,6 @@ static inline void sync_core(void) asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory"); } -#define cpu_has_fpu 1 - #define ARCH_HAS_PREFETCH static inline void prefetch(void *x) { diff --git a/include/asm-x86_64/required-features.h b/include/asm-x86_64/required-features.h new file mode 100644 index 000000000000..e80d5761b00a --- /dev/null +++ b/include/asm-x86_64/required-features.h @@ -0,0 +1,46 @@ +#ifndef _ASM_REQUIRED_FEATURES_H +#define _ASM_REQUIRED_FEATURES_H 1 + +/* Define minimum CPUID feature set for kernel These bits are checked + really early to actually display a visible error message before the + kernel dies. Make sure to assign features to the proper mask! + + The real information is in arch/x86_64/Kconfig.cpu, this just converts + the CONFIGs into a bitmask */ + +/* x86-64 baseline features */ +#define NEED_FPU (1<<(X86_FEATURE_FPU & 31)) +#define NEED_PSE (1<<(X86_FEATURE_PSE & 31)) +#define NEED_MSR (1<<(X86_FEATURE_MSR & 31)) +#define NEED_PAE (1<<(X86_FEATURE_PAE & 31)) +#define NEED_CX8 (1<<(X86_FEATURE_CX8 & 31)) +#define NEED_PGE (1<<(X86_FEATURE_PGE & 31)) +#define NEED_FXSR (1<<(X86_FEATURE_FXSR & 31)) +#define NEED_CMOV (1<<(X86_FEATURE_CMOV & 31)) +#define NEED_XMM (1<<(X86_FEATURE_XMM & 31)) +#define NEED_XMM2 (1<<(X86_FEATURE_XMM2 & 31)) + +#define REQUIRED_MASK0 (NEED_FPU|NEED_PSE|NEED_MSR|NEED_PAE|\ + NEED_CX8|NEED_PGE|NEED_FXSR|NEED_CMOV|\ + NEED_XMM|NEED_XMM2) +#define SSE_MASK (NEED_XMM|NEED_XMM2) + +/* x86-64 baseline features */ +#define NEED_LM (1<<(X86_FEATURE_LM & 31)) + +#ifdef CONFIG_X86_USE_3DNOW +# define NEED_3DNOW (1<<(X86_FEATURE_3DNOW & 31)) +#else +# define NEED_3DNOW 0 +#endif + +#define REQUIRED_MASK1 (NEED_LM|NEED_3DNOW) + +#define REQUIRED_MASK2 0 +#define REQUIRED_MASK3 0 +#define REQUIRED_MASK4 0 +#define REQUIRED_MASK5 0 +#define REQUIRED_MASK6 0 +#define REQUIRED_MASK7 0 + +#endif diff --git a/include/asm-x86_64/segment.h b/include/asm-x86_64/segment.h index adf2bf1e187c..04b8ab21328f 100644 --- a/include/asm-x86_64/segment.h +++ b/include/asm-x86_64/segment.h @@ -3,6 +3,14 @@ #include <asm/cache.h> +/* Simple and small GDT entries for booting only */ + +#define GDT_ENTRY_BOOT_CS 2 +#define __BOOT_CS (GDT_ENTRY_BOOT_CS * 8) + +#define GDT_ENTRY_BOOT_DS (GDT_ENTRY_BOOT_CS + 1) +#define __BOOT_DS (GDT_ENTRY_BOOT_DS * 8) + #define __KERNEL_CS 0x10 #define __KERNEL_DS 0x18 diff --git a/include/asm-xtensa/pci.h b/include/asm-xtensa/pci.h index 24eb7fc25da8..66410acf18b4 100644 --- a/include/asm-xtensa/pci.h +++ b/include/asm-xtensa/pci.h @@ -64,9 +64,6 @@ struct pci_dev; #define pci_ubnmap_len(PTR, LEN_NAME) (0) #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) -/* We cannot access memory above 4GB */ -#define pci_dac_dma_supported(pci_dev, mask) (0) - /* Map a range of PCI memory or I/O space for a device into user space */ int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine); @@ -74,10 +71,6 @@ int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, /* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */ #define HAVE_PCI_MMAP 1 -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #endif /* __KERNEL__ */ /* Implement the pci_ DMA API in terms of the generic device dma_ one */ diff --git a/include/asm-xtensa/pgtable.h b/include/asm-xtensa/pgtable.h index 2d4b5db6ea63..e9fc512cc247 100644 --- a/include/asm-xtensa/pgtable.h +++ b/include/asm-xtensa/pgtable.h @@ -197,16 +197,13 @@ extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)]; /* Note: We use the _PAGE_USER bit to indicate write-protect kernel memory */ -static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; } static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; } static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~(_PAGE_RW | _PAGE_WRENABLE); return pte; } -static inline pte_t pte_rdprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_USER; return pte; } static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; } static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } -static inline pte_t pte_mkread(pte_t pte) { pte_val(pte) |= _PAGE_USER; return pte; } static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; } static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; } static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_RW; return pte; } diff --git a/include/asm-xtensa/termbits.h b/include/asm-xtensa/termbits.h index 057b9a3d8f83..9972c25ec86f 100644 --- a/include/asm-xtensa/termbits.h +++ b/include/asm-xtensa/termbits.h @@ -30,6 +30,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/linux/Kbuild b/include/linux/Kbuild index afae306b177c..bcf875e844fe 100644 --- a/include/linux/Kbuild +++ b/include/linux/Kbuild @@ -91,7 +91,6 @@ header-y += in6.h header-y += in_route.h header-y += ioctl.h header-y += ipmi_msgdefs.h -header-y += ip_mp_alg.h header-y += ipsec.h header-y += ipx.h header-y += irda.h @@ -226,6 +225,7 @@ unifdef-y += if_fddi.h unifdef-y += if_frad.h unifdef-y += if_ltalk.h unifdef-y += if_link.h +unifdef-y += if_pppol2tp.h unifdef-y += if_pppox.h unifdef-y += if_shaper.h unifdef-y += if_tr.h @@ -247,7 +247,6 @@ unifdef-y += isdn.h unifdef-y += isdnif.h unifdef-y += isdn_divertif.h unifdef-y += isdn_ppp.h -unifdef-y += isicom.h unifdef-y += jbd.h unifdef-y += joystick.h unifdef-y += kdev_t.h diff --git a/include/linux/aer.h b/include/linux/aer.h index 402e178b38eb..509656286e53 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -13,11 +13,13 @@ extern int pci_enable_pcie_error_reporting(struct pci_dev *dev); extern int pci_find_aer_capability(struct pci_dev *dev); extern int pci_disable_pcie_error_reporting(struct pci_dev *dev); extern int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev); +extern int pci_cleanup_aer_correct_error_status(struct pci_dev *dev); #else -#define pci_enable_pcie_error_reporting(dev) do { } while (0) -#define pci_find_aer_capability(dev) do { } while (0) -#define pci_disable_pcie_error_reporting(dev) do { } while (0) -#define pci_cleanup_aer_uncorrect_error_status(dev) do { } while (0) +#define pci_enable_pcie_error_reporting(dev) (-EINVAL) +#define pci_find_aer_capability(dev) (0) +#define pci_disable_pcie_error_reporting(dev) (-EINVAL) +#define pci_cleanup_aer_uncorrect_error_status(dev) (-EINVAL) +#define pci_cleanup_aer_correct_error_status(dev) (-EINVAL) #endif #endif //_AER_H_ diff --git a/include/linux/async_tx.h b/include/linux/async_tx.h new file mode 100644 index 000000000000..ff1255079fa1 --- /dev/null +++ b/include/linux/async_tx.h @@ -0,0 +1,156 @@ +/* + * Copyright © 2006, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ +#ifndef _ASYNC_TX_H_ +#define _ASYNC_TX_H_ +#include <linux/dmaengine.h> +#include <linux/spinlock.h> +#include <linux/interrupt.h> + +/** + * dma_chan_ref - object used to manage dma channels received from the + * dmaengine core. + * @chan - the channel being tracked + * @node - node for the channel to be placed on async_tx_master_list + * @rcu - for list_del_rcu + * @count - number of times this channel is listed in the pool + * (for channels with multiple capabiities) + */ +struct dma_chan_ref { + struct dma_chan *chan; + struct list_head node; + struct rcu_head rcu; + atomic_t count; +}; + +/** + * async_tx_flags - modifiers for the async_* calls + * @ASYNC_TX_XOR_ZERO_DST: this flag must be used for xor operations where the + * the destination address is not a source. The asynchronous case handles this + * implicitly, the synchronous case needs to zero the destination block. + * @ASYNC_TX_XOR_DROP_DST: this flag must be used if the destination address is + * also one of the source addresses. In the synchronous case the destination + * address is an implied source, whereas the asynchronous case it must be listed + * as a source. The destination address must be the first address in the source + * array. + * @ASYNC_TX_ASSUME_COHERENT: skip cache maintenance operations + * @ASYNC_TX_ACK: immediately ack the descriptor, precludes setting up a + * dependency chain + * @ASYNC_TX_DEP_ACK: ack the dependency descriptor. Useful for chaining. + * @ASYNC_TX_KMAP_SRC: if the transaction is to be performed synchronously + * take an atomic mapping (KM_USER0) on the source page(s) + * @ASYNC_TX_KMAP_DST: if the transaction is to be performed synchronously + * take an atomic mapping (KM_USER0) on the dest page(s) + */ +enum async_tx_flags { + ASYNC_TX_XOR_ZERO_DST = (1 << 0), + ASYNC_TX_XOR_DROP_DST = (1 << 1), + ASYNC_TX_ASSUME_COHERENT = (1 << 2), + ASYNC_TX_ACK = (1 << 3), + ASYNC_TX_DEP_ACK = (1 << 4), + ASYNC_TX_KMAP_SRC = (1 << 5), + ASYNC_TX_KMAP_DST = (1 << 6), +}; + +#ifdef CONFIG_DMA_ENGINE +void async_tx_issue_pending_all(void); +enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); +void async_tx_run_dependencies(struct dma_async_tx_descriptor *tx); +struct dma_chan * +async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx, + enum dma_transaction_type tx_type); +#else +static inline void async_tx_issue_pending_all(void) +{ + do { } while (0); +} + +static inline enum dma_status +dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) +{ + return DMA_SUCCESS; +} + +static inline void +async_tx_run_dependencies(struct dma_async_tx_descriptor *tx, + struct dma_chan *host_chan) +{ + do { } while (0); +} + +static inline struct dma_chan * +async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx, + enum dma_transaction_type tx_type) +{ + return NULL; +} +#endif + +/** + * async_tx_sync_epilog - actions to take if an operation is run synchronously + * @flags: async_tx flags + * @depend_tx: transaction depends on depend_tx + * @cb_fn: function to call when the transaction completes + * @cb_fn_param: parameter to pass to the callback routine + */ +static inline void +async_tx_sync_epilog(unsigned long flags, + struct dma_async_tx_descriptor *depend_tx, + dma_async_tx_callback cb_fn, void *cb_fn_param) +{ + if (cb_fn) + cb_fn(cb_fn_param); + + if (depend_tx && (flags & ASYNC_TX_DEP_ACK)) + async_tx_ack(depend_tx); +} + +void +async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx, + enum async_tx_flags flags, struct dma_async_tx_descriptor *depend_tx, + dma_async_tx_callback cb_fn, void *cb_fn_param); + +struct dma_async_tx_descriptor * +async_xor(struct page *dest, struct page **src_list, unsigned int offset, + int src_cnt, size_t len, enum async_tx_flags flags, + struct dma_async_tx_descriptor *depend_tx, + dma_async_tx_callback cb_fn, void *cb_fn_param); + +struct dma_async_tx_descriptor * +async_xor_zero_sum(struct page *dest, struct page **src_list, + unsigned int offset, int src_cnt, size_t len, + u32 *result, enum async_tx_flags flags, + struct dma_async_tx_descriptor *depend_tx, + dma_async_tx_callback cb_fn, void *cb_fn_param); + +struct dma_async_tx_descriptor * +async_memcpy(struct page *dest, struct page *src, unsigned int dest_offset, + unsigned int src_offset, size_t len, enum async_tx_flags flags, + struct dma_async_tx_descriptor *depend_tx, + dma_async_tx_callback cb_fn, void *cb_fn_param); + +struct dma_async_tx_descriptor * +async_memset(struct page *dest, int val, unsigned int offset, + size_t len, enum async_tx_flags flags, + struct dma_async_tx_descriptor *depend_tx, + dma_async_tx_callback cb_fn, void *cb_fn_param); + +struct dma_async_tx_descriptor * +async_trigger_callback(enum async_tx_flags flags, + struct dma_async_tx_descriptor *depend_tx, + dma_async_tx_callback cb_fn, void *cb_fn_param); +#endif /* _ASYNC_TX_H_ */ diff --git a/include/linux/ata.h b/include/linux/ata.h index 407dc7e098bc..b5a20162af32 100644 --- a/include/linux/ata.h +++ b/include/linux/ata.h @@ -164,6 +164,8 @@ enum { ATA_CMD_SET_MAX = 0xF9, ATA_CMD_SET_MAX_EXT = 0x37, ATA_CMD_READ_LOG_EXT = 0x2f, + ATA_CMD_PMP_READ = 0xE4, + ATA_CMD_PMP_WRITE = 0xE8, /* READ_LOG_EXT pages */ ATA_LOG_SATA_NCQ = 0x10, @@ -212,6 +214,28 @@ enum { 0=to device, 1=to host */ ATAPI_CDB_LEN = 16, + /* PMP stuff */ + SATA_PMP_MAX_PORTS = 15, + SATA_PMP_CTRL_PORT = 15, + + SATA_PMP_GSCR_DWORDS = 128, + SATA_PMP_GSCR_PROD_ID = 0, + SATA_PMP_GSCR_REV = 1, + SATA_PMP_GSCR_PORT_INFO = 2, + SATA_PMP_GSCR_ERROR = 32, + SATA_PMP_GSCR_ERROR_EN = 33, + SATA_PMP_GSCR_FEAT = 64, + SATA_PMP_GSCR_FEAT_EN = 96, + + SATA_PMP_PSCR_STATUS = 0, + SATA_PMP_PSCR_ERROR = 1, + SATA_PMP_PSCR_CONTROL = 2, + + SATA_PMP_FEAT_BIST = (1 << 0), + SATA_PMP_FEAT_PMREQ = (1 << 1), + SATA_PMP_FEAT_DYNSSC = (1 << 2), + SATA_PMP_FEAT_NOTIFY = (1 << 3), + /* cable types */ ATA_CBL_NONE = 0, ATA_CBL_PATA40 = 1, @@ -418,4 +442,9 @@ static inline int lba_48_ok(u64 block, u32 n_block) return ((block + n_block - 1) < ((u64)1 << 48)) && (n_block <= 65536); } +#define sata_pmp_gscr_vendor(gscr) ((gscr)[SATA_PMP_GSCR_PROD_ID] & 0xffff) +#define sata_pmp_gscr_devid(gscr) ((gscr)[SATA_PMP_GSCR_PROD_ID] >> 16) +#define sata_pmp_gscr_rev(gscr) (((gscr)[SATA_PMP_GSCR_REV] >> 8) & 0xff) +#define sata_pmp_gscr_ports(gscr) ((gscr)[SATA_PMP_GSCR_PORT_INFO] & 0xf) + #endif /* __LINUX_ATA_H__ */ diff --git a/include/linux/attribute_container.h b/include/linux/attribute_container.h index 93bfb0beb62a..8ff274933948 100644 --- a/include/linux/attribute_container.h +++ b/include/linux/attribute_container.h @@ -12,7 +12,6 @@ #include <linux/device.h> #include <linux/list.h> #include <linux/klist.h> -#include <linux/spinlock.h> struct attribute_container { struct list_head node; diff --git a/include/linux/audit.h b/include/linux/audit.h index fccc6e50298a..8ca7ca0b47f0 100644 --- a/include/linux/audit.h +++ b/include/linux/audit.h @@ -63,9 +63,12 @@ #define AUDIT_ADD_RULE 1011 /* Add syscall filtering rule */ #define AUDIT_DEL_RULE 1012 /* Delete syscall filtering rule */ #define AUDIT_LIST_RULES 1013 /* List syscall filtering rules */ +#define AUDIT_TTY_GET 1014 /* Get TTY auditing status */ +#define AUDIT_TTY_SET 1015 /* Set TTY auditing status */ #define AUDIT_FIRST_USER_MSG 1100 /* Userspace messages mostly uninteresting to kernel */ #define AUDIT_USER_AVC 1107 /* We filter this differently */ +#define AUDIT_USER_TTY 1124 /* Non-ICANON TTY input meaning */ #define AUDIT_LAST_USER_MSG 1199 #define AUDIT_FIRST_USER_MSG2 2100 /* More user space messages */ #define AUDIT_LAST_USER_MSG2 2999 @@ -92,6 +95,7 @@ #define AUDIT_KERNEL_OTHER 1316 /* For use by 3rd party modules */ #define AUDIT_FD_PAIR 1317 /* audit record for pipe/socketpair */ #define AUDIT_OBJ_PID 1318 /* ptrace target */ +#define AUDIT_TTY 1319 /* Input on an administrative TTY */ #define AUDIT_AVC 1400 /* SE Linux avc denial or grant */ #define AUDIT_SELINUX_ERR 1401 /* Internal SE Linux Errors */ @@ -289,6 +293,10 @@ struct audit_status { __u32 backlog; /* messages waiting in queue */ }; +struct audit_tty_status { + __u32 enabled; /* 1 = enabled, 0 = disabled */ +}; + /* audit_rule_data supports filter rules with both integer and string * fields. It corresponds with AUDIT_ADD_RULE, AUDIT_DEL_RULE and * AUDIT_LIST_RULES requests. @@ -515,11 +523,13 @@ extern void audit_log_d_path(struct audit_buffer *ab, const char *prefix, struct dentry *dentry, struct vfsmount *vfsmnt); +extern void audit_log_lost(const char *message); /* Private API (for audit.c only) */ extern int audit_filter_user(struct netlink_skb_parms *cb, int type); extern int audit_filter_type(int type); extern int audit_receive_filter(int type, int pid, int uid, int seq, void *data, size_t datasz, uid_t loginuid, u32 sid); +extern int audit_enabled; #else #define audit_log(c,g,t,f,...) do { ; } while (0) #define audit_log_start(c,g,t) ({ NULL; }) @@ -530,6 +540,7 @@ extern int audit_receive_filter(int type, int pid, int uid, int seq, #define audit_log_untrustedstring(a,s) do { ; } while (0) #define audit_log_n_untrustedstring(a,n,s) do { ; } while (0) #define audit_log_d_path(b,p,d,v) do { ; } while (0) +#define audit_enabled 0 #endif #endif #endif diff --git a/include/linux/backing-dev.h b/include/linux/backing-dev.h index f2542c24b328..7011d6255593 100644 --- a/include/linux/backing-dev.h +++ b/include/linux/backing-dev.h @@ -93,7 +93,6 @@ static inline int bdi_rw_congested(struct backing_dev_info *bdi) void clear_bdi_congested(struct backing_dev_info *bdi, int rw); void set_bdi_congested(struct backing_dev_info *bdi, int rw); long congestion_wait(int rw, long timeout); -long congestion_wait_interruptible(int rw, long timeout); void congestion_end(int rw); #define bdi_cap_writeback_dirty(bdi) \ diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index fae138bd2207..b32564a1e105 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -14,6 +14,7 @@ #include <linux/bio.h> #include <linux/module.h> #include <linux/stringify.h> +#include <linux/bsg.h> #include <asm/scatterlist.h> @@ -41,6 +42,8 @@ struct elevator_queue; typedef struct elevator_queue elevator_t; struct request_pm_state; struct blk_trace; +struct request; +struct sg_io_hdr; #define BLKDEV_MIN_RQ 4 #define BLKDEV_MAX_RQ 128 /* Default maximum */ @@ -314,6 +317,9 @@ struct request { */ rq_end_io_fn *end_io; void *end_io_data; + + /* for bidi */ + struct request *next_rq; }; /* @@ -468,6 +474,10 @@ struct request_queue unsigned int bi_size; struct mutex sysfs_lock; + +#if defined(CONFIG_BLK_DEV_BSG) + struct bsg_class_device bsg_dev; +#endif }; #define QUEUE_FLAG_CLUSTER 0 /* cluster several segments into 1 */ @@ -479,6 +489,7 @@ struct request_queue #define QUEUE_FLAG_REENTER 6 /* Re-entrancy avoidance */ #define QUEUE_FLAG_PLUGGED 7 /* queue is plugged */ #define QUEUE_FLAG_ELVSWITCH 8 /* don't use elevator, just do FIFO */ +#define QUEUE_FLAG_BIDI 9 /* queue supports bidi requests */ enum { /* @@ -543,6 +554,7 @@ enum { #define blk_sorted_rq(rq) ((rq)->cmd_flags & REQ_SORTED) #define blk_barrier_rq(rq) ((rq)->cmd_flags & REQ_HARDBARRIER) #define blk_fua_rq(rq) ((rq)->cmd_flags & REQ_FUA) +#define blk_bidi_rq(rq) ((rq)->next_rq != NULL) #define list_entry_rq(ptr) list_entry((ptr), struct request, queuelist) @@ -607,6 +619,11 @@ extern unsigned long blk_max_low_pfn, blk_max_pfn; #define BLK_BOUNCE_ANY ((u64)blk_max_pfn << PAGE_SHIFT) #define BLK_BOUNCE_ISA (ISA_DMA_THRESHOLD) +/* + * default timeout for SG_IO if none specified + */ +#define BLK_DEFAULT_SG_TIMEOUT (60 * HZ) + #ifdef CONFIG_MMU extern int init_emergency_isa_pool(void); extern void blk_queue_bounce(request_queue_t *q, struct bio **bio); @@ -637,7 +654,8 @@ extern void blk_requeue_request(request_queue_t *, struct request *); extern void blk_plug_device(request_queue_t *); extern int blk_remove_plug(request_queue_t *); extern void blk_recount_segments(request_queue_t *, struct bio *); -extern int scsi_cmd_ioctl(struct file *, struct gendisk *, unsigned int, void __user *); +extern int scsi_cmd_ioctl(struct file *, struct request_queue *, + struct gendisk *, unsigned int, void __user *); extern int sg_scsi_ioctl(struct file *, struct request_queue *, struct gendisk *, struct scsi_ioctl_command __user *); @@ -680,6 +698,12 @@ extern int blk_execute_rq(request_queue_t *, struct gendisk *, struct request *, int); extern void blk_execute_rq_nowait(request_queue_t *, struct gendisk *, struct request *, int, rq_end_io_fn *); +extern int blk_fill_sghdr_rq(request_queue_t *, struct request *, + struct sg_io_hdr *, int); +extern int blk_unmap_sghdr_rq(struct request *, struct sg_io_hdr *); +extern int blk_complete_sghdr_rq(struct request *, struct sg_io_hdr *, + struct bio *); +extern int blk_verify_command(unsigned char *, int); static inline request_queue_t *bdev_get_queue(struct block_device *bdev) { diff --git a/include/linux/bsg.h b/include/linux/bsg.h new file mode 100644 index 000000000000..bd998ca6cb2e --- /dev/null +++ b/include/linux/bsg.h @@ -0,0 +1,70 @@ +#ifndef BSG_H +#define BSG_H + +#define BSG_PROTOCOL_SCSI 0 + +#define BSG_SUB_PROTOCOL_SCSI_CMD 0 +#define BSG_SUB_PROTOCOL_SCSI_TMF 1 +#define BSG_SUB_PROTOCOL_SCSI_TRANSPORT 2 + +struct sg_io_v4 { + __s32 guard; /* [i] 'Q' to differentiate from v3 */ + __u32 protocol; /* [i] 0 -> SCSI , .... */ + __u32 subprotocol; /* [i] 0 -> SCSI command, 1 -> SCSI task + management function, .... */ + + __u32 request_len; /* [i] in bytes */ + __u64 request; /* [i], [*i] {SCSI: cdb} */ + __u32 request_attr; /* [i] {SCSI: task attribute} */ + __u32 request_tag; /* [i] {SCSI: task tag (only if flagged)} */ + __u32 request_priority; /* [i] {SCSI: task priority} */ + __u32 max_response_len; /* [i] in bytes */ + __u64 response; /* [i], [*o] {SCSI: (auto)sense data} */ + + /* "din_" for data in (from device); "dout_" for data out (to device) */ + __u32 dout_xfer_len; /* [i] bytes to be transferred to device */ + __u32 din_xfer_len; /* [i] bytes to be transferred from device */ + __u64 dout_xferp; /* [i], [*i] */ + __u64 din_xferp; /* [i], [*o] */ + + __u32 timeout; /* [i] units: millisecond */ + __u32 flags; /* [i] bit mask */ + __u64 usr_ptr; /* [i->o] unused internally */ + __u32 spare_in; /* [i] */ + + __u32 driver_status; /* [o] 0 -> ok */ + __u32 transport_status; /* [o] 0 -> ok */ + __u32 device_status; /* [o] {SCSI: command completion status} */ + __u32 retry_delay; /* [o] {SCSI: status auxiliary information} */ + __u32 info; /* [o] additional information */ + __u32 duration; /* [o] time to complete, in milliseconds */ + __u32 response_len; /* [o] bytes of response actually written */ + __s32 din_resid; /* [o] actual_din_xfer_len - din_xfer_len */ + __u32 generated_tag; /* [o] {SCSI: task tag that transport chose} */ + __u32 spare_out; /* [o] */ + + __u32 padding; +}; + +#ifdef __KERNEL__ + +#if defined(CONFIG_BLK_DEV_BSG) +struct bsg_class_device { + struct class_device *class_dev; + struct device *dev; + int minor; + struct list_head list; + struct request_queue *queue; +}; + +extern int bsg_register_queue(struct request_queue *, const char *); +extern void bsg_unregister_queue(struct request_queue *); +#else +struct bsg_class_device { }; +#define bsg_register_queue(disk, name) (0) +#define bsg_unregister_queue(disk) do { } while (0) +#endif + +#endif /* __KERNEL__ */ + +#endif diff --git a/include/linux/bug.h b/include/linux/bug.h index 42aa0a54b6f4..54398d2c6d8d 100644 --- a/include/linux/bug.h +++ b/include/linux/bug.h @@ -10,6 +10,8 @@ enum bug_trap_type { BUG_TRAP_TYPE_BUG = 2, }; +struct pt_regs; + #ifdef CONFIG_GENERIC_BUG #include <asm-generic/bug.h> @@ -20,7 +22,7 @@ static inline int is_warning_bug(const struct bug_entry *bug) const struct bug_entry *find_bug(unsigned long bugaddr); -enum bug_trap_type report_bug(unsigned long bug_addr); +enum bug_trap_type report_bug(unsigned long bug_addr, struct pt_regs *regs); int module_bug_finalize(const Elf_Ehdr *, const Elf_Shdr *, struct module *); @@ -31,7 +33,8 @@ int is_valid_bugaddr(unsigned long addr); #else /* !CONFIG_GENERIC_BUG */ -static inline enum bug_trap_type report_bug(unsigned long bug_addr) +static inline enum bug_trap_type report_bug(unsigned long bug_addr, + struct pt_regs *regs) { return BUG_TRAP_TYPE_BUG; } diff --git a/include/linux/capability.h b/include/linux/capability.h index bbf8df7de28f..2dfa58555934 100644 --- a/include/linux/capability.h +++ b/include/linux/capability.h @@ -44,7 +44,6 @@ typedef struct __user_cap_data_struct { #ifdef __KERNEL__ -#include <linux/spinlock.h> #include <asm/current.h> /* #define STRICT_CAP_T_TYPECHECKS */ diff --git a/include/linux/cdrom.h b/include/linux/cdrom.h index f50f04bdbc16..2b641b176e7f 100644 --- a/include/linux/cdrom.h +++ b/include/linux/cdrom.h @@ -414,8 +414,8 @@ struct cdrom_generic_command #define CDO_CHECK_TYPE 0x10 /* check type on open for data */ /* Special codes used when specifying changer slots. */ -#define CDSL_NONE ((int) (~0U>>1)-1) -#define CDSL_CURRENT ((int) (~0U>>1)) +#define CDSL_NONE (INT_MAX-1) +#define CDSL_CURRENT INT_MAX /* For partition based multisession access. IDE can handle 64 partitions * per drive - SCSI CD-ROM's use minors to differentiate between the diff --git a/include/linux/cobalt-nvram.h b/include/linux/cobalt-nvram.h deleted file mode 100644 index ea429562ff36..000000000000 --- a/include/linux/cobalt-nvram.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * $Id: cobalt-nvram.h,v 1.20 2001/10/17 23:16:55 thockin Exp $ - * cobalt-nvram.h : defines for the various fields in the cobalt NVRAM - * - * Copyright 2001,2002 Sun Microsystems, Inc. - */ - -#ifndef COBALT_NVRAM_H -#define COBALT_NVRAM_H - -#include <linux/nvram.h> - -#define COBT_CMOS_INFO_MAX 0x7f /* top address allowed */ -#define COBT_CMOS_BIOS_DRIVE_INFO 0x12 /* drive info would go here */ - -#define COBT_CMOS_CKS_START NVRAM_OFFSET(0x0e) -#define COBT_CMOS_CKS_END NVRAM_OFFSET(0x7f) - -/* flag bytes - 16 flags for now, leave room for more */ -#define COBT_CMOS_FLAG_BYTE_0 NVRAM_OFFSET(0x10) -#define COBT_CMOS_FLAG_BYTE_1 NVRAM_OFFSET(0x11) - -/* flags in flag bytes - up to 16 */ -#define COBT_CMOS_FLAG_MIN 0x0001 -#define COBT_CMOS_CONSOLE_FLAG 0x0001 /* console on/off */ -#define COBT_CMOS_DEBUG_FLAG 0x0002 /* ROM debug messages */ -#define COBT_CMOS_AUTO_PROMPT_FLAG 0x0004 /* boot to ROM prompt? */ -#define COBT_CMOS_CLEAN_BOOT_FLAG 0x0008 /* set by a clean shutdown */ -#define COBT_CMOS_HW_NOPROBE_FLAG 0x0010 /* go easy on the probing */ -#define COBT_CMOS_SYSFAULT_FLAG 0x0020 /* system fault detected */ -#define COBT_CMOS_OOPSPANIC_FLAG 0x0040 /* panic on oops */ -#define COBT_CMOS_DELAY_CACHE_FLAG 0x0080 /* delay cache initialization */ -#define COBT_CMOS_NOLOGO_FLAG 0x0100 /* hide "C" logo @ boot */ -#define COBT_CMOS_VERSION_FLAG 0x0200 /* the version field is valid */ -#define COBT_CMOS_FLAG_MAX 0x0200 - -/* leave byte 0x12 blank - Linux looks for drive info here */ - -/* CMOS structure version, valid if COBT_CMOS_VERSION_FLAG is true */ -#define COBT_CMOS_VERSION NVRAM_OFFSET(0x13) -#define COBT_CMOS_VER_BTOCODE 1 /* min. version needed for btocode */ - -/* index of default boot method */ -#define COBT_CMOS_BOOT_METHOD NVRAM_OFFSET(0x20) -#define COBT_CMOS_BOOT_METHOD_DISK 0 -#define COBT_CMOS_BOOT_METHOD_ROM 1 -#define COBT_CMOS_BOOT_METHOD_NET 2 - -#define COBT_CMOS_BOOT_DEV_MIN NVRAM_OFFSET(0x21) -/* major #, minor # of first through fourth boot device */ -#define COBT_CMOS_BOOT_DEV0_MAJ NVRAM_OFFSET(0x21) -#define COBT_CMOS_BOOT_DEV0_MIN NVRAM_OFFSET(0x22) -#define COBT_CMOS_BOOT_DEV1_MAJ NVRAM_OFFSET(0x23) -#define COBT_CMOS_BOOT_DEV1_MIN NVRAM_OFFSET(0x24) -#define COBT_CMOS_BOOT_DEV2_MAJ NVRAM_OFFSET(0x25) -#define COBT_CMOS_BOOT_DEV2_MIN NVRAM_OFFSET(0x26) -#define COBT_CMOS_BOOT_DEV3_MAJ NVRAM_OFFSET(0x27) -#define COBT_CMOS_BOOT_DEV3_MIN NVRAM_OFFSET(0x28) -#define COBT_CMOS_BOOT_DEV_MAX NVRAM_OFFSET(0x28) - -/* checksum of bytes 0xe-0x7f */ -#define COBT_CMOS_CHECKSUM NVRAM_OFFSET(0x2e) - -/* running uptime counter, units of 5 minutes (32 bits =~ 41000 years) */ -#define COBT_CMOS_UPTIME_0 NVRAM_OFFSET(0x30) -#define COBT_CMOS_UPTIME_1 NVRAM_OFFSET(0x31) -#define COBT_CMOS_UPTIME_2 NVRAM_OFFSET(0x32) -#define COBT_CMOS_UPTIME_3 NVRAM_OFFSET(0x33) - -/* count of successful boots (32 bits) */ -#define COBT_CMOS_BOOTCOUNT_0 NVRAM_OFFSET(0x38) -#define COBT_CMOS_BOOTCOUNT_1 NVRAM_OFFSET(0x39) -#define COBT_CMOS_BOOTCOUNT_2 NVRAM_OFFSET(0x3a) -#define COBT_CMOS_BOOTCOUNT_3 NVRAM_OFFSET(0x3b) - -/* 13 bytes: system serial number, same as on the back of the system */ -#define COBT_CMOS_SYS_SERNUM_LEN 13 -#define COBT_CMOS_SYS_SERNUM_0 NVRAM_OFFSET(0x40) -#define COBT_CMOS_SYS_SERNUM_1 NVRAM_OFFSET(0x41) -#define COBT_CMOS_SYS_SERNUM_2 NVRAM_OFFSET(0x42) -#define COBT_CMOS_SYS_SERNUM_3 NVRAM_OFFSET(0x43) -#define COBT_CMOS_SYS_SERNUM_4 NVRAM_OFFSET(0x44) -#define COBT_CMOS_SYS_SERNUM_5 NVRAM_OFFSET(0x45) -#define COBT_CMOS_SYS_SERNUM_6 NVRAM_OFFSET(0x46) -#define COBT_CMOS_SYS_SERNUM_7 NVRAM_OFFSET(0x47) -#define COBT_CMOS_SYS_SERNUM_8 NVRAM_OFFSET(0x48) -#define COBT_CMOS_SYS_SERNUM_9 NVRAM_OFFSET(0x49) -#define COBT_CMOS_SYS_SERNUM_10 NVRAM_OFFSET(0x4a) -#define COBT_CMOS_SYS_SERNUM_11 NVRAM_OFFSET(0x4b) -#define COBT_CMOS_SYS_SERNUM_12 NVRAM_OFFSET(0x4c) -/* checksum for serial num - 1 byte */ -#define COBT_CMOS_SYS_SERNUM_CSUM NVRAM_OFFSET(0x4f) - -#define COBT_CMOS_ROM_REV_MAJ NVRAM_OFFSET(0x50) -#define COBT_CMOS_ROM_REV_MIN NVRAM_OFFSET(0x51) -#define COBT_CMOS_ROM_REV_REV NVRAM_OFFSET(0x52) - -#define COBT_CMOS_BTO_CODE_0 NVRAM_OFFSET(0x53) -#define COBT_CMOS_BTO_CODE_1 NVRAM_OFFSET(0x54) -#define COBT_CMOS_BTO_CODE_2 NVRAM_OFFSET(0x55) -#define COBT_CMOS_BTO_CODE_3 NVRAM_OFFSET(0x56) - -#define COBT_CMOS_BTO_IP_CSUM NVRAM_OFFSET(0x57) -#define COBT_CMOS_BTO_IP_0 NVRAM_OFFSET(0x58) -#define COBT_CMOS_BTO_IP_1 NVRAM_OFFSET(0x59) -#define COBT_CMOS_BTO_IP_2 NVRAM_OFFSET(0x5a) -#define COBT_CMOS_BTO_IP_3 NVRAM_OFFSET(0x5b) - -#endif /* COBALT_NVRAM_H */ diff --git a/include/linux/configfs.h b/include/linux/configfs.h index fef6f3d0a4a7..8c6967f3fb11 100644 --- a/include/linux/configfs.h +++ b/include/linux/configfs.h @@ -40,9 +40,9 @@ #include <linux/types.h> #include <linux/list.h> #include <linux/kref.h> +#include <linux/mutex.h> #include <asm/atomic.h> -#include <asm/semaphore.h> #define CONFIGFS_ITEM_NAME_LEN 20 @@ -75,7 +75,6 @@ extern void config_item_init(struct config_item *); extern void config_item_init_type_name(struct config_item *item, const char *name, struct config_item_type *type); -extern void config_item_cleanup(struct config_item *); extern struct config_item * config_item_get(struct config_item *); extern void config_item_put(struct config_item *); @@ -87,12 +86,10 @@ struct config_item_type { struct configfs_attribute **ct_attrs; }; - /** * group - a group of config_items of a specific type, belonging * to a specific subsystem. */ - struct config_group { struct config_item cg_item; struct list_head cg_children; @@ -100,13 +97,11 @@ struct config_group { struct config_group **default_groups; }; - extern void config_group_init(struct config_group *group); extern void config_group_init_type_name(struct config_group *group, const char *name, struct config_item_type *type); - static inline struct config_group *to_config_group(struct config_item *item) { return item ? container_of(item,struct config_group,cg_item) : NULL; @@ -122,7 +117,8 @@ static inline void config_group_put(struct config_group *group) config_item_put(&group->cg_item); } -extern struct config_item *config_group_find_obj(struct config_group *, const char *); +extern struct config_item *config_group_find_item(struct config_group *, + const char *); struct configfs_attribute { @@ -131,6 +127,22 @@ struct configfs_attribute { mode_t ca_mode; }; +/* + * Users often need to create attribute structures for their configurable + * attributes, containing a configfs_attribute member and function pointers + * for the show() and store() operations on that attribute. They can use + * this macro (similar to sysfs' __ATTR) to make defining attributes easier. + */ +#define __CONFIGFS_ATTR(_name, _mode, _show, _store) \ +{ \ + .attr = { \ + .ca_name = __stringify(_name), \ + .ca_mode = _mode, \ + .ca_owner = THIS_MODULE, \ + }, \ + .show = _show, \ + .store = _store, \ +} /* * If allow_link() exists, the item can symlink(2) out to other @@ -157,12 +169,13 @@ struct configfs_group_operations { struct config_item *(*make_item)(struct config_group *group, const char *name); struct config_group *(*make_group)(struct config_group *group, const char *name); int (*commit_item)(struct config_item *item); + void (*disconnect_notify)(struct config_group *group, struct config_item *item); void (*drop_item)(struct config_group *group, struct config_item *item); }; struct configfs_subsystem { struct config_group su_group; - struct semaphore su_sem; + struct mutex su_mutex; }; static inline struct configfs_subsystem *to_configfs_subsystem(struct config_group *group) @@ -175,6 +188,11 @@ static inline struct configfs_subsystem *to_configfs_subsystem(struct config_gro int configfs_register_subsystem(struct configfs_subsystem *subsys); void configfs_unregister_subsystem(struct configfs_subsystem *subsys); +/* These functions can sleep and can alloc with GFP_KERNEL */ +/* WARNING: These cannot be called underneath configfs callbacks!! */ +int configfs_depend_item(struct configfs_subsystem *subsys, struct config_item *target); +void configfs_undepend_item(struct configfs_subsystem *subsys, struct config_item *target); + #endif /* __KERNEL__ */ #endif /* _CONFIGFS_H_ */ diff --git a/include/linux/console.h b/include/linux/console.h index 62ef6e11d0d2..56a7bcda49cb 100644 --- a/include/linux/console.h +++ b/include/linux/console.h @@ -15,7 +15,6 @@ #define _LINUX_CONSOLE_H_ 1 #include <linux/types.h> -#include <linux/spinlock.h> struct vc_data; struct console_font_op; @@ -99,6 +98,7 @@ struct console { struct tty_driver *(*device)(struct console *, int *); void (*unblank)(void); int (*setup)(struct console *, char *); + int (*early_setup)(void); short flags; short index; int cflag; @@ -107,6 +107,7 @@ struct console { }; extern int add_preferred_console(char *name, int idx, char *options); +extern int update_console_cmdline(char *name, int idx, char *name_new, int idx_new, char *options); extern void register_console(struct console *); extern int unregister_console(struct console *); extern struct console *console_drivers; diff --git a/include/linux/consolemap.h b/include/linux/consolemap.h index 82c9a1f11020..06b2768c603f 100644 --- a/include/linux/consolemap.h +++ b/include/linux/consolemap.h @@ -8,9 +8,12 @@ #define IBMPC_MAP 2 #define USER_MAP 3 +#include <linux/types.h> + struct vc_data; -extern unsigned char inverse_translate(struct vc_data *conp, int glyph); +extern u16 inverse_translate(struct vc_data *conp, int glyph, int use_unicode); extern unsigned short *set_translate(int m, struct vc_data *vc); extern int conv_uni_to_pc(struct vc_data *conp, long ucs); +extern u32 conv_8bit_to_uni(unsigned char c); void console_map_init(void); diff --git a/include/linux/cpu.h b/include/linux/cpu.h index 3b2df2523f1d..c2236bbff412 100644 --- a/include/linux/cpu.h +++ b/include/linux/cpu.h @@ -120,7 +120,6 @@ static inline void cpuhotplug_mutex_unlock(struct mutex *cpu_hp_mutex) #define lock_cpu_hotplug() do { } while (0) #define unlock_cpu_hotplug() do { } while (0) -#define lock_cpu_hotplug_interruptible() 0 #define hotcpu_notifier(fn, pri) do { (void)(fn); } while (0) #define register_hotcpu_notifier(nb) do { (void)(nb); } while (0) #define unregister_hotcpu_notifier(nb) do { (void)(nb); } while (0) diff --git a/include/linux/crypto.h b/include/linux/crypto.h index 0de7e2ace822..357e8cfedc37 100644 --- a/include/linux/crypto.h +++ b/include/linux/crypto.h @@ -295,28 +295,8 @@ struct blkcipher_tfm { }; struct cipher_tfm { - void *cit_iv; - unsigned int cit_ivsize; - u32 cit_mode; int (*cit_setkey)(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen); - int (*cit_encrypt)(struct crypto_tfm *tfm, - struct scatterlist *dst, - struct scatterlist *src, - unsigned int nbytes); - int (*cit_encrypt_iv)(struct crypto_tfm *tfm, - struct scatterlist *dst, - struct scatterlist *src, - unsigned int nbytes, u8 *iv); - int (*cit_decrypt)(struct crypto_tfm *tfm, - struct scatterlist *dst, - struct scatterlist *src, - unsigned int nbytes); - int (*cit_decrypt_iv)(struct crypto_tfm *tfm, - struct scatterlist *dst, - struct scatterlist *src, - unsigned int nbytes, u8 *iv); - void (*cit_xor_block)(u8 *dst, const u8 *src); void (*cit_encrypt_one)(struct crypto_tfm *tfm, u8 *dst, const u8 *src); void (*cit_decrypt_one)(struct crypto_tfm *tfm, u8 *dst, const u8 *src); }; diff --git a/include/linux/debugfs.h b/include/linux/debugfs.h index 5a9c49534d08..104e51e20e14 100644 --- a/include/linux/debugfs.h +++ b/include/linux/debugfs.h @@ -38,6 +38,9 @@ struct dentry *debugfs_create_symlink(const char *name, struct dentry *parent, void debugfs_remove(struct dentry *dentry); +struct dentry *debugfs_rename(struct dentry *old_dir, struct dentry *old_dentry, + struct dentry *new_dir, const char *new_name); + struct dentry *debugfs_create_u8(const char *name, mode_t mode, struct dentry *parent, u8 *value); struct dentry *debugfs_create_u16(const char *name, mode_t mode, @@ -85,6 +88,12 @@ static inline struct dentry *debugfs_create_symlink(const char *name, static inline void debugfs_remove(struct dentry *dentry) { } +static inline struct dentry *debugfs_rename(struct dentry *old_dir, struct dentry *old_dentry, + struct dentry *new_dir, char *new_name) +{ + return ERR_PTR(-ENODEV); +} + static inline struct dentry *debugfs_create_u8(const char *name, mode_t mode, struct dentry *parent, u8 *value) diff --git a/include/linux/device.h b/include/linux/device.h index 2e1a2988b7e1..be2debed70d2 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -238,7 +238,6 @@ extern int __must_check class_device_create_file(struct class_device *, * @devt: for internal use by the driver core only. * @node: for internal use by the driver core only. * @kobj: for internal use by the driver core only. - * @devt_attr: for internal use by the driver core only. * @groups: optional additional groups to be created * @dev: if set, a symlink to the struct device is created in the sysfs * directory for this struct class device. @@ -263,8 +262,6 @@ struct class_device { struct kobject kobj; struct class * class; /* required */ dev_t devt; /* dev_t, creates the sysfs "dev" */ - struct class_device_attribute *devt_attr; - struct class_device_attribute uevent_attr; struct device * dev; /* not necessary, but nice to have */ void * class_data; /* class-specific data */ struct class_device *parent; /* parent of this child device, if there is one */ @@ -419,8 +416,6 @@ struct device { struct device_type *type; unsigned is_registered:1; unsigned uevent_suppress:1; - struct device_attribute uevent_attr; - struct device_attribute *devt_attr; struct semaphore sem; /* semaphore to synchronize calls to * its driver. diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h index 9a663c6db16a..2dc21cbeb304 100644 --- a/include/linux/dma-mapping.h +++ b/include/linux/dma-mapping.h @@ -31,7 +31,11 @@ static inline int valid_dma_direction(int dma_direction) (dma_direction == DMA_FROM_DEVICE)); } +#ifdef CONFIG_HAS_DMA #include <asm/dma-mapping.h> +#else +#include <asm-generic/dma-mapping-broken.h> +#endif /* Backwards compat, remove in 2.7.x */ #define dma_sync_single dma_sync_single_for_cpu diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index c94d8f1d62e5..a3b6035b6c86 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -21,29 +21,40 @@ #ifndef DMAENGINE_H #define DMAENGINE_H -#ifdef CONFIG_DMA_ENGINE - #include <linux/device.h> #include <linux/uio.h> #include <linux/kref.h> #include <linux/completion.h> #include <linux/rcupdate.h> +#include <linux/dma-mapping.h> /** - * enum dma_event - resource PNP/power managment events + * enum dma_state - resource PNP/power managment state * @DMA_RESOURCE_SUSPEND: DMA device going into low power state * @DMA_RESOURCE_RESUME: DMA device returning to full power - * @DMA_RESOURCE_ADDED: DMA device added to the system + * @DMA_RESOURCE_AVAILABLE: DMA device available to the system * @DMA_RESOURCE_REMOVED: DMA device removed from the system */ -enum dma_event { +enum dma_state { DMA_RESOURCE_SUSPEND, DMA_RESOURCE_RESUME, - DMA_RESOURCE_ADDED, + DMA_RESOURCE_AVAILABLE, DMA_RESOURCE_REMOVED, }; /** + * enum dma_state_client - state of the channel in the client + * @DMA_ACK: client would like to use, or was using this channel + * @DMA_DUP: client has already seen this channel, or is not using this channel + * @DMA_NAK: client does not want to see any more channels + */ +enum dma_state_client { + DMA_ACK, + DMA_DUP, + DMA_NAK, +}; + +/** * typedef dma_cookie_t - an opaque DMA cookie * * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code @@ -65,6 +76,31 @@ enum dma_status { }; /** + * enum dma_transaction_type - DMA transaction types/indexes + */ +enum dma_transaction_type { + DMA_MEMCPY, + DMA_XOR, + DMA_PQ_XOR, + DMA_DUAL_XOR, + DMA_PQ_UPDATE, + DMA_ZERO_SUM, + DMA_PQ_ZERO_SUM, + DMA_MEMSET, + DMA_MEMCPY_CRC32C, + DMA_INTERRUPT, +}; + +/* last transaction type for creation of the capabilities mask */ +#define DMA_TX_TYPE_END (DMA_INTERRUPT + 1) + +/** + * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. + * See linux/cpumask.h + */ +typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; + +/** * struct dma_chan_percpu - the per-CPU part of struct dma_chan * @refcount: local_t used for open-coded "bigref" counting * @memcpy_count: transaction counter @@ -80,7 +116,6 @@ struct dma_chan_percpu { /** * struct dma_chan - devices supply DMA channels, clients use them - * @client: ptr to the client user of this chan, will be %NULL when unused * @device: ptr to the dma device who supplies this channel, always !%NULL * @cookie: last cookie value returned to client * @chan_id: channel ID for sysfs @@ -88,12 +123,10 @@ struct dma_chan_percpu { * @refcount: kref, used in "bigref" slow-mode * @slow_ref: indicates that the DMA channel is free * @rcu: the DMA channel's RCU head - * @client_node: used to add this to the client chan list * @device_node: used to add this to the device chan list * @local: per-cpu pointer to a struct dma_chan_percpu */ struct dma_chan { - struct dma_client *client; struct dma_device *device; dma_cookie_t cookie; @@ -105,11 +138,11 @@ struct dma_chan { int slow_ref; struct rcu_head rcu; - struct list_head client_node; struct list_head device_node; struct dma_chan_percpu *local; }; + void dma_chan_cleanup(struct kref *kref); static inline void dma_chan_get(struct dma_chan *chan) @@ -134,169 +167,206 @@ static inline void dma_chan_put(struct dma_chan *chan) /* * typedef dma_event_callback - function pointer to a DMA event callback + * For each channel added to the system this routine is called for each client. + * If the client would like to use the channel it returns '1' to signal (ack) + * the dmaengine core to take out a reference on the channel and its + * corresponding device. A client must not 'ack' an available channel more + * than once. When a channel is removed all clients are notified. If a client + * is using the channel it must 'ack' the removal. A client must not 'ack' a + * removed channel more than once. + * @client - 'this' pointer for the client context + * @chan - channel to be acted upon + * @state - available or removed */ -typedef void (*dma_event_callback) (struct dma_client *client, - struct dma_chan *chan, enum dma_event event); +struct dma_client; +typedef enum dma_state_client (*dma_event_callback) (struct dma_client *client, + struct dma_chan *chan, enum dma_state state); /** * struct dma_client - info on the entity making use of DMA services * @event_callback: func ptr to call when something happens - * @chan_count: number of chans allocated - * @chans_desired: number of chans requested. Can be +/- chan_count - * @lock: protects access to the channels list - * @channels: the list of DMA channels allocated + * @cap_mask: only return channels that satisfy the requested capabilities + * a value of zero corresponds to any capability * @global_node: list_head for global dma_client_list */ struct dma_client { dma_event_callback event_callback; - unsigned int chan_count; - unsigned int chans_desired; - - spinlock_t lock; - struct list_head channels; + dma_cap_mask_t cap_mask; struct list_head global_node; }; +typedef void (*dma_async_tx_callback)(void *dma_async_param); +/** + * struct dma_async_tx_descriptor - async transaction descriptor + * ---dma generic offload fields--- + * @cookie: tracking cookie for this transaction, set to -EBUSY if + * this tx is sitting on a dependency list + * @ack: the descriptor can not be reused until the client acknowledges + * receipt, i.e. has has a chance to establish any dependency chains + * @phys: physical address of the descriptor + * @tx_list: driver common field for operations that require multiple + * descriptors + * @chan: target channel for this operation + * @tx_submit: set the prepared descriptor(s) to be executed by the engine + * @tx_set_dest: set a destination address in a hardware descriptor + * @tx_set_src: set a source address in a hardware descriptor + * @callback: routine to call after this operation is complete + * @callback_param: general parameter to pass to the callback routine + * ---async_tx api specific fields--- + * @depend_list: at completion this list of transactions are submitted + * @depend_node: allow this transaction to be executed after another + * transaction has completed, possibly on another channel + * @parent: pointer to the next level up in the dependency chain + * @lock: protect the dependency list + */ +struct dma_async_tx_descriptor { + dma_cookie_t cookie; + int ack; + dma_addr_t phys; + struct list_head tx_list; + struct dma_chan *chan; + dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); + void (*tx_set_dest)(dma_addr_t addr, + struct dma_async_tx_descriptor *tx, int index); + void (*tx_set_src)(dma_addr_t addr, + struct dma_async_tx_descriptor *tx, int index); + dma_async_tx_callback callback; + void *callback_param; + struct list_head depend_list; + struct list_head depend_node; + struct dma_async_tx_descriptor *parent; + spinlock_t lock; +}; + /** * struct dma_device - info on the entity supplying DMA services * @chancnt: how many DMA channels are supported * @channels: the list of struct dma_chan * @global_node: list_head for global dma_device_list + * @cap_mask: one or more dma_capability flags + * @max_xor: maximum number of xor sources, 0 if no capability * @refcount: reference count * @done: IO completion struct * @dev_id: unique device ID + * @dev: struct device reference for dma mapping api * @device_alloc_chan_resources: allocate resources and return the * number of allocated descriptors * @device_free_chan_resources: release DMA channel's resources - * @device_memcpy_buf_to_buf: memcpy buf pointer to buf pointer - * @device_memcpy_buf_to_pg: memcpy buf pointer to struct page - * @device_memcpy_pg_to_pg: memcpy struct page/offset to struct page/offset - * @device_memcpy_complete: poll the status of an IOAT DMA transaction - * @device_memcpy_issue_pending: push appended descriptors to hardware + * @device_prep_dma_memcpy: prepares a memcpy operation + * @device_prep_dma_xor: prepares a xor operation + * @device_prep_dma_zero_sum: prepares a zero_sum operation + * @device_prep_dma_memset: prepares a memset operation + * @device_prep_dma_interrupt: prepares an end of chain interrupt operation + * @device_dependency_added: async_tx notifies the channel about new deps + * @device_issue_pending: push pending transactions to hardware */ struct dma_device { unsigned int chancnt; struct list_head channels; struct list_head global_node; + dma_cap_mask_t cap_mask; + int max_xor; struct kref refcount; struct completion done; int dev_id; + struct device *dev; int (*device_alloc_chan_resources)(struct dma_chan *chan); void (*device_free_chan_resources)(struct dma_chan *chan); - dma_cookie_t (*device_memcpy_buf_to_buf)(struct dma_chan *chan, - void *dest, void *src, size_t len); - dma_cookie_t (*device_memcpy_buf_to_pg)(struct dma_chan *chan, - struct page *page, unsigned int offset, void *kdata, - size_t len); - dma_cookie_t (*device_memcpy_pg_to_pg)(struct dma_chan *chan, - struct page *dest_pg, unsigned int dest_off, - struct page *src_pg, unsigned int src_off, size_t len); - enum dma_status (*device_memcpy_complete)(struct dma_chan *chan, + + struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( + struct dma_chan *chan, size_t len, int int_en); + struct dma_async_tx_descriptor *(*device_prep_dma_xor)( + struct dma_chan *chan, unsigned int src_cnt, size_t len, + int int_en); + struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)( + struct dma_chan *chan, unsigned int src_cnt, size_t len, + u32 *result, int int_en); + struct dma_async_tx_descriptor *(*device_prep_dma_memset)( + struct dma_chan *chan, int value, size_t len, int int_en); + struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( + struct dma_chan *chan); + + void (*device_dependency_added)(struct dma_chan *chan); + enum dma_status (*device_is_tx_complete)(struct dma_chan *chan, dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used); - void (*device_memcpy_issue_pending)(struct dma_chan *chan); + void (*device_issue_pending)(struct dma_chan *chan); }; /* --- public DMA engine API --- */ -struct dma_client *dma_async_client_register(dma_event_callback event_callback); +void dma_async_client_register(struct dma_client *client); void dma_async_client_unregister(struct dma_client *client); -void dma_async_client_chan_request(struct dma_client *client, - unsigned int number); +void dma_async_client_chan_request(struct dma_client *client); +dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, + void *dest, void *src, size_t len); +dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, + struct page *page, unsigned int offset, void *kdata, size_t len); +dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan, + struct page *dest_pg, unsigned int dest_off, struct page *src_pg, + unsigned int src_off, size_t len); +void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, + struct dma_chan *chan); -/** - * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses - * @chan: DMA channel to offload copy to - * @dest: destination address (virtual) - * @src: source address (virtual) - * @len: length - * - * Both @dest and @src must be mappable to a bus address according to the - * DMA mapping API rules for streaming mappings. - * Both @dest and @src must stay memory resident (kernel memory or locked - * user space pages). - */ -static inline dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, - void *dest, void *src, size_t len) +static inline void +async_tx_ack(struct dma_async_tx_descriptor *tx) { - int cpu = get_cpu(); - per_cpu_ptr(chan->local, cpu)->bytes_transferred += len; - per_cpu_ptr(chan->local, cpu)->memcpy_count++; - put_cpu(); - - return chan->device->device_memcpy_buf_to_buf(chan, dest, src, len); + tx->ack = 1; } -/** - * dma_async_memcpy_buf_to_pg - offloaded copy from address to page - * @chan: DMA channel to offload copy to - * @page: destination page - * @offset: offset in page to copy to - * @kdata: source address (virtual) - * @len: length - * - * Both @page/@offset and @kdata must be mappable to a bus address according - * to the DMA mapping API rules for streaming mappings. - * Both @page/@offset and @kdata must stay memory resident (kernel memory or - * locked user space pages) - */ -static inline dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, - struct page *page, unsigned int offset, void *kdata, size_t len) +#define first_dma_cap(mask) __first_dma_cap(&(mask)) +static inline int __first_dma_cap(const dma_cap_mask_t *srcp) { - int cpu = get_cpu(); - per_cpu_ptr(chan->local, cpu)->bytes_transferred += len; - per_cpu_ptr(chan->local, cpu)->memcpy_count++; - put_cpu(); + return min_t(int, DMA_TX_TYPE_END, + find_first_bit(srcp->bits, DMA_TX_TYPE_END)); +} - return chan->device->device_memcpy_buf_to_pg(chan, page, offset, - kdata, len); +#define next_dma_cap(n, mask) __next_dma_cap((n), &(mask)) +static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp) +{ + return min_t(int, DMA_TX_TYPE_END, + find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1)); } -/** - * dma_async_memcpy_pg_to_pg - offloaded copy from page to page - * @chan: DMA channel to offload copy to - * @dest_pg: destination page - * @dest_off: offset in page to copy to - * @src_pg: source page - * @src_off: offset in page to copy from - * @len: length - * - * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus - * address according to the DMA mapping API rules for streaming mappings. - * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident - * (kernel memory or locked user space pages). - */ -static inline dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan, - struct page *dest_pg, unsigned int dest_off, struct page *src_pg, - unsigned int src_off, size_t len) +#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) +static inline void +__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) { - int cpu = get_cpu(); - per_cpu_ptr(chan->local, cpu)->bytes_transferred += len; - per_cpu_ptr(chan->local, cpu)->memcpy_count++; - put_cpu(); + set_bit(tx_type, dstp->bits); +} - return chan->device->device_memcpy_pg_to_pg(chan, dest_pg, dest_off, - src_pg, src_off, len); +#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) +static inline int +__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) +{ + return test_bit(tx_type, srcp->bits); } +#define for_each_dma_cap_mask(cap, mask) \ + for ((cap) = first_dma_cap(mask); \ + (cap) < DMA_TX_TYPE_END; \ + (cap) = next_dma_cap((cap), (mask))) + /** - * dma_async_memcpy_issue_pending - flush pending copies to HW + * dma_async_issue_pending - flush pending transactions to HW * @chan: target DMA channel * * This allows drivers to push copies to HW in batches, * reducing MMIO writes where possible. */ -static inline void dma_async_memcpy_issue_pending(struct dma_chan *chan) +static inline void dma_async_issue_pending(struct dma_chan *chan) { - return chan->device->device_memcpy_issue_pending(chan); + return chan->device->device_issue_pending(chan); } +#define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan) + /** - * dma_async_memcpy_complete - poll for transaction completion + * dma_async_is_tx_complete - poll for transaction completion * @chan: DMA channel * @cookie: transaction identifier to check status of * @last: returns last completed cookie, can be NULL @@ -306,12 +376,15 @@ static inline void dma_async_memcpy_issue_pending(struct dma_chan *chan) * internal state and can be used with dma_async_is_complete() to check * the status of multiple cookies without re-checking hardware state. */ -static inline enum dma_status dma_async_memcpy_complete(struct dma_chan *chan, +static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) { - return chan->device->device_memcpy_complete(chan, cookie, last, used); + return chan->device->device_is_tx_complete(chan, cookie, last, used); } +#define dma_async_memcpy_complete(chan, cookie, last, used)\ + dma_async_is_tx_complete(chan, cookie, last, used) + /** * dma_async_is_complete - test a cookie against chan state * @cookie: transaction identifier to test status of @@ -334,6 +407,7 @@ static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, return DMA_IN_PROGRESS; } +enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); /* --- DMA device --- */ @@ -362,5 +436,4 @@ dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov, struct dma_pinned_list *pinned_list, struct page *page, unsigned int offset, size_t len); -#endif /* CONFIG_DMA_ENGINE */ #endif /* DMAENGINE_H */ diff --git a/include/linux/dmi.h b/include/linux/dmi.h index 904bf3d2d90b..b8ac7b01c45e 100644 --- a/include/linux/dmi.h +++ b/include/linux/dmi.h @@ -12,9 +12,17 @@ enum dmi_field { DMI_PRODUCT_NAME, DMI_PRODUCT_VERSION, DMI_PRODUCT_SERIAL, + DMI_PRODUCT_UUID, DMI_BOARD_VENDOR, DMI_BOARD_NAME, DMI_BOARD_VERSION, + DMI_BOARD_SERIAL, + DMI_BOARD_ASSET_TAG, + DMI_CHASSIS_VENDOR, + DMI_CHASSIS_TYPE, + DMI_CHASSIS_VERSION, + DMI_CHASSIS_SERIAL, + DMI_CHASSIS_ASSET_TAG, DMI_STRING_MAX, }; diff --git a/include/linux/ds17287rtc.h b/include/linux/ds17287rtc.h index c281ba42e28f..d85d3f497b96 100644 --- a/include/linux/ds17287rtc.h +++ b/include/linux/ds17287rtc.h @@ -11,7 +11,6 @@ #define __LINUX_DS17287RTC_H #include <linux/rtc.h> /* get the user-level API */ -#include <linux/spinlock.h> /* spinlock_t */ #include <linux/mc146818rtc.h> /* Register A */ diff --git a/include/linux/edd.h b/include/linux/edd.h index b2b3e68aa512..7b647822d6dc 100644 --- a/include/linux/edd.h +++ b/include/linux/edd.h @@ -49,10 +49,6 @@ #define EDD_MBR_SIG_MAX 16 /* max number of signatures to store */ #define EDD_MBR_SIG_NR_BUF 0x1ea /* addr of number of MBR signtaures at EDD_MBR_SIG_BUF in boot_params - treat this as 1 byte */ -#define EDD_CL_EQUALS 0x3d646465 /* "edd=" */ -#define EDD_CL_OFF 0x666f /* "of" for off */ -#define EDD_CL_SKIP 0x6b73 /* "sk" for skipmbr */ -#define EDD_CL_ON 0x6e6f /* "on" for on */ #ifndef __ASSEMBLY__ diff --git a/include/linux/etherdevice.h b/include/linux/etherdevice.h index 071c67abed86..6cdb97365e47 100644 --- a/include/linux/etherdevice.h +++ b/include/linux/etherdevice.h @@ -39,13 +39,8 @@ extern void eth_header_cache_update(struct hh_cache *hh, struct net_device *dev extern int eth_header_cache(struct neighbour *neigh, struct hh_cache *hh); -extern struct net_device *alloc_etherdev(int sizeof_priv); -static inline void eth_copy_and_sum (struct sk_buff *dest, - const unsigned char *src, - int len, int base) -{ - memcpy (dest->data, src, len); -} +extern struct net_device *alloc_etherdev_mq(int sizeof_priv, unsigned int queue_count); +#define alloc_etherdev(sizeof_priv) alloc_etherdev_mq(sizeof_priv, 1) /** * is_zero_ether_addr - Determine if give Ethernet address is all zeros. diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h index f2d248f8cc92..3a632244f31b 100644 --- a/include/linux/ethtool.h +++ b/include/linux/ethtool.h @@ -265,6 +265,7 @@ u32 ethtool_op_get_link(struct net_device *dev); u32 ethtool_op_get_tx_csum(struct net_device *dev); int ethtool_op_set_tx_csum(struct net_device *dev, u32 data); int ethtool_op_set_tx_hw_csum(struct net_device *dev, u32 data); +int ethtool_op_set_tx_ipv6_csum(struct net_device *dev, u32 data); u32 ethtool_op_get_sg(struct net_device *dev); int ethtool_op_set_sg(struct net_device *dev, u32 data); u32 ethtool_op_get_tso(struct net_device *dev); diff --git a/include/linux/ext2_fs_sb.h b/include/linux/ext2_fs_sb.h index 4eda0ed76a48..d149f2959e67 100644 --- a/include/linux/ext2_fs_sb.h +++ b/include/linux/ext2_fs_sb.h @@ -33,6 +33,8 @@ struct ext2_sb_info { unsigned long s_gdb_count; /* Number of group descriptor blocks */ unsigned long s_desc_per_block; /* Number of group descriptors per block */ unsigned long s_groups_count; /* Number of groups in the fs */ + unsigned long s_overhead_last; /* Last calculated overhead */ + unsigned long s_blocks_last; /* Last seen block count */ struct buffer_head * s_sbh; /* Buffer containing the super block */ struct ext2_super_block * s_es; /* Pointer to the super block in the buffer */ struct buffer_head ** s_group_desc; diff --git a/include/linux/ext3_fs_sb.h b/include/linux/ext3_fs_sb.h index f61309c81cc4..d3c08353edf6 100644 --- a/include/linux/ext3_fs_sb.h +++ b/include/linux/ext3_fs_sb.h @@ -38,6 +38,8 @@ struct ext3_sb_info { unsigned long s_gdb_count; /* Number of group descriptor blocks */ unsigned long s_desc_per_block; /* Number of group descriptors per block */ unsigned long s_groups_count; /* Number of groups in the fs */ + unsigned long s_overhead_last; /* Last calculated overhead */ + unsigned long s_blocks_last; /* Last seen block count */ struct buffer_head * s_sbh; /* Buffer containing the super block */ struct ext3_super_block * s_es; /* Pointer to the super block in the buffer */ struct buffer_head ** s_group_desc; diff --git a/include/linux/ext4_fs_sb.h b/include/linux/ext4_fs_sb.h index 691a713139ce..2347557a327a 100644 --- a/include/linux/ext4_fs_sb.h +++ b/include/linux/ext4_fs_sb.h @@ -39,6 +39,8 @@ struct ext4_sb_info { unsigned long s_gdb_count; /* Number of group descriptor blocks */ unsigned long s_desc_per_block; /* Number of group descriptors per block */ unsigned long s_groups_count; /* Number of groups in the fs */ + unsigned long s_overhead_last; /* Last calculated overhead */ + unsigned long s_blocks_last; /* Last seen block count */ struct buffer_head * s_sbh; /* Buffer containing the super block */ struct ext4_super_block * s_es; /* Pointer to the super block in the buffer */ struct buffer_head ** s_group_desc; diff --git a/include/linux/file.h b/include/linux/file.h index a59001e9ea58..0114fbc78061 100644 --- a/include/linux/file.h +++ b/include/linux/file.h @@ -73,6 +73,7 @@ extern struct file * FASTCALL(fget_light(unsigned int fd, int *fput_needed)); extern void FASTCALL(set_close_on_exec(unsigned int fd, int flag)); extern void put_filp(struct file *); extern int get_unused_fd(void); +extern int get_unused_fd_flags(int flags); extern void FASTCALL(put_unused_fd(unsigned int fd)); struct kmem_cache; diff --git a/include/linux/fs.h b/include/linux/fs.h index 4f0b3bf5983c..e68780810279 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -44,7 +44,7 @@ extern int get_max_files(void); struct inodes_stat_t { int nr_inodes; int nr_unused; - int dummy[5]; + int dummy[5]; /* padding for sysctl ABI compatibility */ }; extern struct inodes_stat_t inodes_stat; @@ -820,6 +820,10 @@ struct file_lock { union { struct nfs_lock_info nfs_fl; struct nfs4_lock_info nfs4_fl; + struct { + struct list_head link; /* link in AFS vnode's pending_locks list */ + int state; /* state of grant or error if -ve */ + } afs; } fl_u; }; @@ -1610,6 +1614,9 @@ extern int __invalidate_device(struct block_device *); extern int invalidate_partition(struct gendisk *, int); #endif extern int invalidate_inodes(struct super_block *); +unsigned long __invalidate_mapping_pages(struct address_space *mapping, + pgoff_t start, pgoff_t end, + bool be_atomic); unsigned long invalidate_mapping_pages(struct address_space *mapping, pgoff_t start, pgoff_t end); diff --git a/include/linux/fuse.h b/include/linux/fuse.h index 534744efe30d..9fbe9d258e22 100644 --- a/include/linux/fuse.h +++ b/include/linux/fuse.h @@ -339,7 +339,7 @@ struct fuse_dirent { char name[0]; }; -#define FUSE_NAME_OFFSET ((unsigned) ((struct fuse_dirent *) 0)->name) +#define FUSE_NAME_OFFSET offsetof(struct fuse_dirent, name) #define FUSE_DIRENT_ALIGN(x) (((x) + sizeof(__u64) - 1) & ~(sizeof(__u64) - 1)) #define FUSE_DIRENT_SIZE(d) \ FUSE_DIRENT_ALIGN(FUSE_NAME_OFFSET + (d)->namelen) diff --git a/include/linux/hrtimer.h b/include/linux/hrtimer.h index 17c29dca8354..540799bc85f8 100644 --- a/include/linux/hrtimer.h +++ b/include/linux/hrtimer.h @@ -329,12 +329,13 @@ extern void sysrq_timer_list_show(void); #ifdef CONFIG_TIMER_STATS extern void timer_stats_update_stats(void *timer, pid_t pid, void *startf, - void *timerf, char * comm); + void *timerf, char *comm, + unsigned int timer_flag); static inline void timer_stats_account_hrtimer(struct hrtimer *timer) { timer_stats_update_stats(timer, timer->start_pid, timer->start_site, - timer->function, timer->start_comm); + timer->function, timer->start_comm, 0); } extern void __timer_stats_hrtimer_set_start_info(struct hrtimer *timer, diff --git a/include/linux/i2c.h b/include/linux/i2c.h index cae7d618030c..2eaba21b9b1a 100644 --- a/include/linux/i2c.h +++ b/include/linux/i2c.h @@ -90,7 +90,7 @@ extern s32 i2c_smbus_write_block_data(struct i2c_client * client, const u8 *values); /* Returns the number of read bytes */ extern s32 i2c_smbus_read_i2c_block_data(struct i2c_client * client, - u8 command, u8 *values); + u8 command, u8 length, u8 *values); extern s32 i2c_smbus_write_i2c_block_data(struct i2c_client * client, u8 command, u8 length, const u8 *values); @@ -150,15 +150,20 @@ struct i2c_driver { /** * struct i2c_client - represent an I2C slave device + * @flags: I2C_CLIENT_TEN indicates the device uses a ten bit chip address; + * I2C_CLIENT_PEC indicates it uses SMBus Packet Error Checking * @addr: Address used on the I2C bus connected to the parent adapter. * @name: Indicates the type of the device, usually a chip name that's * generic enough to hide second-sourcing and compatible revisions. + * @adapter: manages the bus segment hosting this I2C device * @dev: Driver model device node for the slave. + * @irq: indicates the IRQ generated by this device (if any) * @driver_name: Identifies new-style driver used with this device; also * used as the module name for hotplug/coldplug modprobe support. * * An i2c_client identifies a single device (i.e. chip) connected to an - * i2c bus. The behaviour is defined by the routines of the driver. + * i2c bus. The behaviour exposed to Linux is defined by the driver + * managing the device. */ struct i2c_client { unsigned short flags; /* div., see below */ @@ -180,7 +185,8 @@ struct i2c_client { static inline struct i2c_client *kobj_to_i2c_client(struct kobject *kobj) { - return to_i2c_client(container_of(kobj, struct device, kobj)); + struct device * const dev = container_of(kobj, struct device, kobj); + return to_i2c_client(dev); } static inline void *i2c_get_clientdata (struct i2c_client *dev) @@ -201,7 +207,7 @@ static inline void i2c_set_clientdata (struct i2c_client *dev, void *data) * @addr: stored in i2c_client.addr * @platform_data: stored in i2c_client.dev.platform_data * @irq: stored in i2c_client.irq - + * * I2C doesn't actually support hardware probing, although controllers and * devices may be able to use I2C_SMBUS_QUICK to tell whether or not there's * a device at a given address. Drivers commonly need more information than @@ -210,7 +216,7 @@ static inline void i2c_set_clientdata (struct i2c_client *dev, void *data) * i2c_board_info is used to build tables of information listing I2C devices * that are present. This information is used to grow the driver model tree * for "new style" I2C drivers. For mainboards this is done statically using - * i2c_register_board_info(), where @bus_num represents an adapter that isn't + * i2c_register_board_info(); bus numbers identify adapters that aren't * yet available. For add-on boards, i2c_new_device() does this dynamically * with the adapter already known. */ @@ -518,8 +524,9 @@ union i2c_smbus_data { #define I2C_SMBUS_WORD_DATA 3 #define I2C_SMBUS_PROC_CALL 4 #define I2C_SMBUS_BLOCK_DATA 5 -#define I2C_SMBUS_I2C_BLOCK_DATA 6 +#define I2C_SMBUS_I2C_BLOCK_BROKEN 6 #define I2C_SMBUS_BLOCK_PROC_CALL 7 /* SMBus 2.0 */ +#define I2C_SMBUS_I2C_BLOCK_DATA 8 /* ----- commands for the ioctl like i2c_command call: diff --git a/include/linux/i2o.h b/include/linux/i2o.h index 52f53e2e70c3..333a370a3bdc 100644 --- a/include/linux/i2o.h +++ b/include/linux/i2o.h @@ -31,6 +31,7 @@ #include <linux/slab.h> #include <linux/workqueue.h> /* work_struct */ #include <linux/mempool.h> +#include <linux/mutex.h> #include <asm/io.h> #include <asm/semaphore.h> /* Needed for MUTEX init macros */ @@ -425,7 +426,7 @@ struct i2o_device { struct device device; - struct semaphore lock; /* device lock */ + struct mutex lock; /* device lock */ }; /* @@ -544,7 +545,7 @@ struct i2o_controller { struct i2o_dma hrt; /* HW Resource Table */ i2o_lct *lct; /* Logical Config Table */ struct i2o_dma dlct; /* Temp LCT */ - struct semaphore lct_lock; /* Lock for LCT updates */ + struct mutex lct_lock; /* Lock for LCT updates */ struct i2o_dma status_block; /* IOP status block */ struct i2o_io base; /* controller messaging unit */ diff --git a/include/linux/idr.h b/include/linux/idr.h index 826803449db7..0edda411959c 100644 --- a/include/linux/idr.h +++ b/include/linux/idr.h @@ -78,9 +78,41 @@ void *idr_find(struct idr *idp, int id); int idr_pre_get(struct idr *idp, gfp_t gfp_mask); int idr_get_new(struct idr *idp, void *ptr, int *id); int idr_get_new_above(struct idr *idp, void *ptr, int starting_id, int *id); +int idr_for_each(struct idr *idp, + int (*fn)(int id, void *p, void *data), void *data); void *idr_replace(struct idr *idp, void *ptr, int id); void idr_remove(struct idr *idp, int id); +void idr_remove_all(struct idr *idp); void idr_destroy(struct idr *idp); void idr_init(struct idr *idp); + +/* + * IDA - IDR based id allocator, use when translation from id to + * pointer isn't necessary. + */ +#define IDA_CHUNK_SIZE 128 /* 128 bytes per chunk */ +#define IDA_BITMAP_LONGS (128 / sizeof(long) - 1) +#define IDA_BITMAP_BITS (IDA_BITMAP_LONGS * sizeof(long) * 8) + +struct ida_bitmap { + long nr_busy; + unsigned long bitmap[IDA_BITMAP_LONGS]; +}; + +struct ida { + struct idr idr; + struct ida_bitmap *free_bitmap; +}; + +#define IDA_INIT(name) { .idr = IDR_INIT(name), .free_bitmap = NULL, } +#define DEFINE_IDA(name) struct ida name = IDA_INIT(name) + +int ida_pre_get(struct ida *ida, gfp_t gfp_mask); +int ida_get_new_above(struct ida *ida, int starting_id, int *p_id); +int ida_get_new(struct ida *ida, int *p_id); +void ida_remove(struct ida *ida, int id); +void ida_destroy(struct ida *ida); +void ida_init(struct ida *ida); + #endif /* __IDR_H__ */ diff --git a/include/linux/ieee80211.h b/include/linux/ieee80211.h index ecd61e8438a5..272f8c8c90da 100644 --- a/include/linux/ieee80211.h +++ b/include/linux/ieee80211.h @@ -227,6 +227,17 @@ struct ieee80211_cts { #define WLAN_CAPABILITY_SHORT_SLOT_TIME (1<<10) #define WLAN_CAPABILITY_DSSS_OFDM (1<<13) +/* 802.11g ERP information element */ +#define WLAN_ERP_NON_ERP_PRESENT (1<<0) +#define WLAN_ERP_USE_PROTECTION (1<<1) +#define WLAN_ERP_BARKER_PREAMBLE (1<<2) + +/* WLAN_ERP_BARKER_PREAMBLE values */ +enum { + WLAN_ERP_PREAMBLE_SHORT = 0, + WLAN_ERP_PREAMBLE_LONG = 1, +}; + /* Status codes */ enum ieee80211_statuscode { WLAN_STATUS_SUCCESS = 0, diff --git a/include/linux/if_link.h b/include/linux/if_link.h index 604c2434f71c..422084d18ce1 100644 --- a/include/linux/if_link.h +++ b/include/linux/if_link.h @@ -76,6 +76,8 @@ enum #define IFLA_WEIGHT IFLA_WEIGHT IFLA_OPERSTATE, IFLA_LINKMODE, + IFLA_LINKINFO, +#define IFLA_LINKINFO IFLA_LINKINFO __IFLA_MAX }; @@ -140,4 +142,49 @@ struct ifla_cacheinfo __u32 retrans_time; }; +enum +{ + IFLA_INFO_UNSPEC, + IFLA_INFO_KIND, + IFLA_INFO_DATA, + IFLA_INFO_XSTATS, + __IFLA_INFO_MAX, +}; + +#define IFLA_INFO_MAX (__IFLA_INFO_MAX - 1) + +/* VLAN section */ + +enum +{ + IFLA_VLAN_UNSPEC, + IFLA_VLAN_ID, + IFLA_VLAN_FLAGS, + IFLA_VLAN_EGRESS_QOS, + IFLA_VLAN_INGRESS_QOS, + __IFLA_VLAN_MAX, +}; + +#define IFLA_VLAN_MAX (__IFLA_VLAN_MAX - 1) + +struct ifla_vlan_flags { + __u32 flags; + __u32 mask; +}; + +enum +{ + IFLA_VLAN_QOS_UNSPEC, + IFLA_VLAN_QOS_MAPPING, + __IFLA_VLAN_QOS_MAX +}; + +#define IFLA_VLAN_QOS_MAX (__IFLA_VLAN_QOS_MAX - 1) + +struct ifla_vlan_qos_mapping +{ + __u32 from; + __u32 to; +}; + #endif /* _LINUX_IF_LINK_H */ diff --git a/include/linux/if_macvlan.h b/include/linux/if_macvlan.h new file mode 100644 index 000000000000..0d9d7ea2c1cc --- /dev/null +++ b/include/linux/if_macvlan.h @@ -0,0 +1,9 @@ +#ifndef _LINUX_IF_MACVLAN_H +#define _LINUX_IF_MACVLAN_H + +#ifdef __KERNEL__ + +extern struct sk_buff *(*macvlan_handle_frame_hook)(struct sk_buff *); + +#endif /* __KERNEL__ */ +#endif /* _LINUX_IF_MACVLAN_H */ diff --git a/include/linux/if_ppp.h b/include/linux/if_ppp.h index 768372f07caa..0f2f70d4e48c 100644 --- a/include/linux/if_ppp.h +++ b/include/linux/if_ppp.h @@ -110,6 +110,21 @@ struct ifpppcstatsreq { struct ppp_comp_stats stats; }; +/* For PPPIOCGL2TPSTATS */ +struct pppol2tp_ioc_stats { + __u16 tunnel_id; /* redundant */ + __u16 session_id; /* if zero, get tunnel stats */ + __u32 using_ipsec:1; /* valid only for session_id == 0 */ + aligned_u64 tx_packets; + aligned_u64 tx_bytes; + aligned_u64 tx_errors; + aligned_u64 rx_packets; + aligned_u64 rx_bytes; + aligned_u64 rx_seq_discards; + aligned_u64 rx_oos_packets; + aligned_u64 rx_errors; +}; + #define ifr__name b.ifr_ifrn.ifrn_name #define stats_ptr b.ifr_ifru.ifru_data @@ -146,6 +161,7 @@ struct ifpppcstatsreq { #define PPPIOCDISCONN _IO('t', 57) /* disconnect channel */ #define PPPIOCATTCHAN _IOW('t', 56, int) /* attach to ppp channel */ #define PPPIOCGCHAN _IOR('t', 55, int) /* get ppp channel number */ +#define PPPIOCGL2TPSTATS _IOR('t', 54, struct pppol2tp_ioc_stats) #define SIOCGPPPSTATS (SIOCDEVPRIVATE + 0) #define SIOCGPPPVER (SIOCDEVPRIVATE + 1) /* NEVER change this!! */ diff --git a/include/linux/if_pppol2tp.h b/include/linux/if_pppol2tp.h new file mode 100644 index 000000000000..516203b6fdeb --- /dev/null +++ b/include/linux/if_pppol2tp.h @@ -0,0 +1,69 @@ +/*************************************************************************** + * Linux PPP over L2TP (PPPoL2TP) Socket Implementation (RFC 2661) + * + * This file supplies definitions required by the PPP over L2TP driver + * (pppol2tp.c). All version information wrt this file is located in pppol2tp.c + * + * License: + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#ifndef __LINUX_IF_PPPOL2TP_H +#define __LINUX_IF_PPPOL2TP_H + +#include <asm/types.h> + +#ifdef __KERNEL__ +#include <linux/in.h> +#endif + +/* Structure used to connect() the socket to a particular tunnel UDP + * socket. + */ +struct pppol2tp_addr +{ + pid_t pid; /* pid that owns the fd. + * 0 => current */ + int fd; /* FD of UDP socket to use */ + + struct sockaddr_in addr; /* IP address and port to send to */ + + __be16 s_tunnel, s_session; /* For matching incoming packets */ + __be16 d_tunnel, d_session; /* For sending outgoing packets */ +}; + +/* Socket options: + * DEBUG - bitmask of debug message categories + * SENDSEQ - 0 => don't send packets with sequence numbers + * 1 => send packets with sequence numbers + * RECVSEQ - 0 => receive packet sequence numbers are optional + * 1 => drop receive packets without sequence numbers + * LNSMODE - 0 => act as LAC. + * 1 => act as LNS. + * REORDERTO - reorder timeout (in millisecs). If 0, don't try to reorder. + */ +enum { + PPPOL2TP_SO_DEBUG = 1, + PPPOL2TP_SO_RECVSEQ = 2, + PPPOL2TP_SO_SENDSEQ = 3, + PPPOL2TP_SO_LNSMODE = 4, + PPPOL2TP_SO_REORDERTO = 5, +}; + +/* Debug message categories for the DEBUG socket option */ +enum { + PPPOL2TP_MSG_DEBUG = (1 << 0), /* verbose debug (if + * compiled in) */ + PPPOL2TP_MSG_CONTROL = (1 << 1), /* userspace - kernel + * interface */ + PPPOL2TP_MSG_SEQ = (1 << 2), /* sequence numbers */ + PPPOL2TP_MSG_DATA = (1 << 3), /* data packets */ +}; + + + +#endif diff --git a/include/linux/if_pppox.h b/include/linux/if_pppox.h index 6f987be60fe2..25652545ba6e 100644 --- a/include/linux/if_pppox.h +++ b/include/linux/if_pppox.h @@ -27,6 +27,7 @@ #include <asm/semaphore.h> #include <linux/ppp_channel.h> #endif /* __KERNEL__ */ +#include <linux/if_pppol2tp.h> /* For user-space programs to pick up these definitions * which they wouldn't get otherwise without defining __KERNEL__ @@ -50,8 +51,9 @@ struct pppoe_addr{ * Protocols supported by AF_PPPOX */ #define PX_PROTO_OE 0 /* Currently just PPPoE */ -#define PX_MAX_PROTO 1 - +#define PX_PROTO_OL2TP 1 /* Now L2TP also */ +#define PX_MAX_PROTO 2 + struct sockaddr_pppox { sa_family_t sa_family; /* address family, AF_PPPOX */ unsigned int sa_protocol; /* protocol identifier */ @@ -60,6 +62,16 @@ struct sockaddr_pppox { }sa_addr; }__attribute__ ((packed)); +/* The use of the above union isn't viable because the size of this + * struct must stay fixed over time -- applications use sizeof(struct + * sockaddr_pppox) to fill it. We use a protocol specific sockaddr + * type instead. + */ +struct sockaddr_pppol2tp { + sa_family_t sa_family; /* address family, AF_PPPOX */ + unsigned int sa_protocol; /* protocol identifier */ + struct pppol2tp_addr pppol2tp; +}__attribute__ ((packed)); /********************************************************************* * diff --git a/include/linux/if_tun.h b/include/linux/if_tun.h index 88aef7b86ef4..42eb6945b93e 100644 --- a/include/linux/if_tun.h +++ b/include/linux/if_tun.h @@ -36,6 +36,7 @@ struct tun_struct { unsigned long flags; int attached; uid_t owner; + gid_t group; wait_queue_head_t read_wait; struct sk_buff_head readq; @@ -78,6 +79,7 @@ struct tun_struct { #define TUNSETPERSIST _IOW('T', 203, int) #define TUNSETOWNER _IOW('T', 204, int) #define TUNSETLINK _IOW('T', 205, int) +#define TUNSETGROUP _IOW('T', 206, int) /* TUNSETIFF ifr flags */ #define IFF_TUN 0x0001 diff --git a/include/linux/if_vlan.h b/include/linux/if_vlan.h index 81e9bc93569b..f8443fdb124a 100644 --- a/include/linux/if_vlan.h +++ b/include/linux/if_vlan.h @@ -99,7 +99,7 @@ static inline void vlan_group_set_device(struct vlan_group *vg, int vlan_id, } struct vlan_priority_tci_mapping { - unsigned long priority; + u32 priority; unsigned short vlan_qos; /* This should be shifted when first set, so we only do it * at provisioning time. * ((skb->priority << 13) & 0xE000) @@ -112,7 +112,10 @@ struct vlan_dev_info { /** This will be the mapping that correlates skb->priority to * 3 bits of VLAN QOS tags... */ - unsigned long ingress_priority_map[8]; + unsigned int nr_ingress_mappings; + u32 ingress_priority_map[8]; + + unsigned int nr_egress_mappings; struct vlan_priority_tci_mapping *egress_priority_map[16]; /* hash table */ unsigned short vlan_id; /* The VLAN Identifier for this interface. */ @@ -124,14 +127,8 @@ struct vlan_dev_info { * like DHCP that use packet-filtering and don't understand * 802.1Q */ - struct dev_mc_list *old_mc_list; /* old multi-cast list for the VLAN interface.. - * we save this so we can tell what changes were - * made, in order to feed the right changes down - * to the real hardware... - */ - int old_allmulti; /* similar to above. */ - int old_promiscuity; /* similar to above. */ struct net_device *real_dev; /* the underlying device/interface */ + unsigned char real_dev_addr[ETH_ALEN]; struct proc_dir_entry *dent; /* Holds the proc data */ unsigned long cnt_inc_headroom_on_tx; /* How many times did we have to grow the skb on TX. */ unsigned long cnt_encap_on_xmit; /* How many times did we have to encapsulate the skb on TX. */ @@ -395,6 +392,10 @@ enum vlan_ioctl_cmds { GET_VLAN_VID_CMD /* Get the VID of this VLAN (specified by name) */ }; +enum vlan_flags { + VLAN_FLAG_REORDER_HDR = 0x1, +}; + enum vlan_name_types { VLAN_NAME_TYPE_PLUS_VID, /* Name will look like: vlan0005 */ VLAN_NAME_TYPE_RAW_PLUS_VID, /* name will look like: eth1.0005 */ diff --git a/include/linux/init.h b/include/linux/init.h index 56ec4c62eee0..5b5285316339 100644 --- a/include/linux/init.h +++ b/include/linux/init.h @@ -171,9 +171,6 @@ struct obs_kernel_param { #define __setup(str, fn) \ __setup_param(str, fn, fn, 0) -#define __obsolete_setup(str) \ - __setup_null_param(str, __LINE__) - /* NOTE: fn is as per module_param, not __setup! Emits warning if fn * returns non-zero. */ #define early_param(str, fn) \ @@ -239,7 +236,6 @@ void __init parse_early_param(void); #define __setup_param(str, unique_id, fn) /* nothing */ #define __setup_null_param(str, unique_id) /* nothing */ #define __setup(str, func) /* nothing */ -#define __obsolete_setup(str) /* nothing */ #endif /* Data marked not to be saved by software suspend */ diff --git a/include/linux/init_task.h b/include/linux/init_task.h index 276ccaa2670c..cab741c2d603 100644 --- a/include/linux/init_task.h +++ b/include/linux/init_task.h @@ -8,6 +8,7 @@ #include <linux/lockdep.h> #include <linux/ipc.h> #include <linux/pid_namespace.h> +#include <linux/user_namespace.h> #define INIT_FDTABLE \ { \ @@ -78,6 +79,7 @@ extern struct nsproxy init_nsproxy; .uts_ns = &init_uts_ns, \ .mnt_ns = NULL, \ INIT_IPC_NS(ipc_ns) \ + .user_ns = &init_user_ns, \ } #define INIT_SIGHAND(sighand) { \ diff --git a/include/linux/io.h b/include/linux/io.h index 8423dd376514..e3b2dda6c8eb 100644 --- a/include/linux/io.h +++ b/include/linux/io.h @@ -63,32 +63,7 @@ void __iomem * devm_ioremap(struct device *dev, unsigned long offset, void __iomem * devm_ioremap_nocache(struct device *dev, unsigned long offset, unsigned long size); void devm_iounmap(struct device *dev, void __iomem *addr); - -/** - * check_signature - find BIOS signatures - * @io_addr: mmio address to check - * @signature: signature block - * @length: length of signature - * - * Perform a signature comparison with the mmio address io_addr. This - * address should have been obtained by ioremap. - * Returns 1 on a match. - */ - -static inline int check_signature(const volatile void __iomem *io_addr, - const unsigned char *signature, int length) -{ - int retval = 0; - do { - if (readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} +int check_signature(const volatile void __iomem *io_addr, + const unsigned char *signature, int length); #endif /* _LINUX_IO_H */ diff --git a/include/linux/ip_mp_alg.h b/include/linux/ip_mp_alg.h deleted file mode 100644 index e234e2008f5d..000000000000 --- a/include/linux/ip_mp_alg.h +++ /dev/null @@ -1,22 +0,0 @@ -/* ip_mp_alg.h: IPV4 multipath algorithm support, user-visible values. - * - * Copyright (C) 2004, 2005 Einar Lueck <elueck@de.ibm.com> - * Copyright (C) 2005 David S. Miller <davem@davemloft.net> - */ - -#ifndef _LINUX_IP_MP_ALG_H -#define _LINUX_IP_MP_ALG_H - -enum ip_mp_alg { - IP_MP_ALG_NONE, - IP_MP_ALG_RR, - IP_MP_ALG_DRR, - IP_MP_ALG_RANDOM, - IP_MP_ALG_WRANDOM, - __IP_MP_ALG_MAX -}; - -#define IP_MP_ALG_MAX (__IP_MP_ALG_MAX - 1) - -#endif /* _LINUX_IP_MP_ALG_H */ - diff --git a/include/linux/ipc.h b/include/linux/ipc.h index 1980867a64a4..3fd3ddd5f0d9 100644 --- a/include/linux/ipc.h +++ b/include/linux/ipc.h @@ -52,6 +52,7 @@ struct ipc_perm #ifdef __KERNEL__ #include <linux/kref.h> +#include <linux/spinlock.h> #define IPCMNI 32768 /* <= MAX_INT limit for ipc arrays (including sysctl changes) */ @@ -92,6 +93,7 @@ extern struct ipc_namespace init_ipc_ns; #ifdef CONFIG_SYSVIPC #define INIT_IPC_NS(ns) .ns = &init_ipc_ns, +extern void free_ipc_ns(struct kref *kref); extern struct ipc_namespace *copy_ipcs(unsigned long flags, struct ipc_namespace *ns); #else @@ -103,13 +105,9 @@ static inline struct ipc_namespace *copy_ipcs(unsigned long flags, } #endif -#ifdef CONFIG_IPC_NS -extern void free_ipc_ns(struct kref *kref); -#endif - static inline struct ipc_namespace *get_ipc_ns(struct ipc_namespace *ns) { -#ifdef CONFIG_IPC_NS +#ifdef CONFIG_SYSVIPC if (ns) kref_get(&ns->kref); #endif @@ -118,7 +116,7 @@ static inline struct ipc_namespace *get_ipc_ns(struct ipc_namespace *ns) static inline void put_ipc_ns(struct ipc_namespace *ns) { -#ifdef CONFIG_IPC_NS +#ifdef CONFIG_SYSVIPC kref_put(&ns->kref, free_ipc_ns); #endif } @@ -126,5 +124,3 @@ static inline void put_ipc_ns(struct ipc_namespace *ns) #endif /* __KERNEL__ */ #endif /* _LINUX_IPC_H */ - - diff --git a/include/linux/ipv6.h b/include/linux/ipv6.h index 648bd1f0912d..97983dc9df13 100644 --- a/include/linux/ipv6.h +++ b/include/linux/ipv6.h @@ -27,8 +27,8 @@ struct in6_ifreq { int ifr6_ifindex; }; -#define IPV6_SRCRT_STRICT 0x01 /* this hop must be a neighbor */ -#define IPV6_SRCRT_TYPE_0 0 /* IPv6 type 0 Routing Header */ +#define IPV6_SRCRT_STRICT 0x01 /* Deprecated; will be removed */ +#define IPV6_SRCRT_TYPE_0 0 /* Deprecated; will be removed */ #define IPV6_SRCRT_TYPE_2 2 /* IPv6 type 2 Routing Header */ /* @@ -247,7 +247,7 @@ struct inet6_skb_parm { __u16 lastopt; __u32 nhoff; __u16 flags; -#ifdef CONFIG_IPV6_MIP6 +#if defined(CONFIG_IPV6_MIP6) || defined(CONFIG_IPV6_MIP6_MODULE) __u16 dsthao; #endif @@ -299,8 +299,8 @@ struct ipv6_pinfo { /* pktoption flags */ union { struct { - __u16 srcrt:2, - osrcrt:2, + __u16 srcrt:1, + osrcrt:1, rxinfo:1, rxoinfo:1, rxhlim:1, diff --git a/include/linux/irda.h b/include/linux/irda.h index 945ba3110874..8e3735714c1c 100644 --- a/include/linux/irda.h +++ b/include/linux/irda.h @@ -216,6 +216,34 @@ struct if_irda_req { #define ifr_dtr ifr_ifru.ifru_line.dtr #define ifr_rts ifr_ifru.ifru_line.rts + +/* IrDA netlink definitions */ +#define IRDA_NL_NAME "irda" +#define IRDA_NL_VERSION 1 + +enum irda_nl_commands { + IRDA_NL_CMD_UNSPEC, + IRDA_NL_CMD_SET_MODE, + IRDA_NL_CMD_GET_MODE, + + __IRDA_NL_CMD_AFTER_LAST +}; +#define IRDA_NL_CMD_MAX (__IRDA_NL_CMD_AFTER_LAST - 1) + +enum nl80211_attrs { + IRDA_NL_ATTR_UNSPEC, + IRDA_NL_ATTR_IFNAME, + IRDA_NL_ATTR_MODE, + + __IRDA_NL_ATTR_AFTER_LAST +}; +#define IRDA_NL_ATTR_MAX (__IRDA_NL_ATTR_AFTER_LAST - 1) + +/* IrDA modes */ +#define IRDA_MODE_PRIMARY 0x1 +#define IRDA_MODE_SECONDARY 0x2 +#define IRDA_MODE_MONITOR 0x4 + #endif /* KERNEL_IRDA_H */ diff --git a/include/linux/irq.h b/include/linux/irq.h index 1695054e8c63..44657197fcb0 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -161,6 +161,7 @@ struct irq_desc { unsigned int wake_depth; /* nested wake enables */ unsigned int irq_count; /* For detecting broken IRQs */ unsigned int irqs_unhandled; + unsigned long last_unhandled; /* Aging timer for unhandled count */ spinlock_t lock; #ifdef CONFIG_SMP cpumask_t affinity; diff --git a/include/linux/kobject.h b/include/linux/kobject.h index c288e41ba331..06cbf41d32d2 100644 --- a/include/linux/kobject.h +++ b/include/linux/kobject.h @@ -55,7 +55,7 @@ struct kobject { struct kobject * parent; struct kset * kset; struct kobj_type * ktype; - struct dentry * dentry; + struct sysfs_dirent * sd; wait_queue_head_t poll; }; @@ -71,13 +71,14 @@ extern void kobject_init(struct kobject *); extern void kobject_cleanup(struct kobject *); extern int __must_check kobject_add(struct kobject *); -extern int __must_check kobject_shadow_add(struct kobject *, struct dentry *); +extern int __must_check kobject_shadow_add(struct kobject *kobj, + struct sysfs_dirent *shadow_parent); extern void kobject_del(struct kobject *); extern int __must_check kobject_rename(struct kobject *, const char *new_name); extern int __must_check kobject_shadow_rename(struct kobject *kobj, - struct dentry *new_parent, - const char *new_name); + struct sysfs_dirent *new_parent, + const char *new_name); extern int __must_check kobject_move(struct kobject *, struct kobject *); extern int __must_check kobject_register(struct kobject *); diff --git a/include/linux/ktime.h b/include/linux/ktime.h index 2b139f66027f..dae7143644fe 100644 --- a/include/linux/ktime.h +++ b/include/linux/ktime.h @@ -279,6 +279,16 @@ static inline s64 ktime_to_us(const ktime_t kt) return (s64) tv.tv_sec * USEC_PER_SEC + tv.tv_usec; } +static inline s64 ktime_us_delta(const ktime_t later, const ktime_t earlier) +{ + return ktime_to_us(ktime_sub(later, earlier)); +} + +static inline ktime_t ktime_add_us(const ktime_t kt, const u64 usec) +{ + return ktime_add_ns(kt, usec * 1000); +} + /* * The resolution of the clocks. The resolution value is returned in * the clock_getres() system call to give application programmers an diff --git a/include/linux/leds.h b/include/linux/leds.h index 88afceffb7cb..494bed7c2fc1 100644 --- a/include/linux/leds.h +++ b/include/linux/leds.h @@ -13,7 +13,6 @@ #define __LINUX_LEDS_H_INCLUDED #include <linux/list.h> -#include <linux/spinlock.h> struct device; struct class_device; diff --git a/include/linux/libata.h b/include/linux/libata.h index a3df64677ac3..47cd2a1c5544 100644 --- a/include/linux/libata.h +++ b/include/linux/libata.h @@ -196,7 +196,6 @@ enum { ATA_PFLAG_SCSI_HOTPLUG = (1 << 6), /* SCSI hotplug scheduled */ ATA_PFLAG_INITIALIZING = (1 << 7), /* being initialized, don't touch */ - ATA_PFLAG_FLUSH_PORT_TASK = (1 << 16), /* flush port task */ ATA_PFLAG_SUSPENDED = (1 << 17), /* port is suspended (power) */ ATA_PFLAG_PM_PENDING = (1 << 18), /* PM operation pending */ ATA_PFLAG_GTM_VALID = (1 << 19), /* acpi_gtm data valid */ @@ -435,6 +434,7 @@ struct ata_device { struct ata_port *ap; unsigned int devno; /* 0 or 1 */ unsigned long flags; /* ATA_DFLAG_xxx */ + unsigned int horkage; /* List of broken features */ struct scsi_device *sdev; /* attached SCSI device */ #ifdef CONFIG_ATA_ACPI acpi_handle acpi_handle; @@ -466,7 +466,6 @@ struct ata_device { /* error history */ struct ata_ering ering; int spdn_cnt; - unsigned int horkage; /* List of broken features */ }; /* Offset into struct ata_device. Fields above it are maintained @@ -794,7 +793,6 @@ extern void ata_id_string(const u16 *id, unsigned char *s, extern void ata_id_c_string(const u16 *id, unsigned char *s, unsigned int ofs, unsigned int len); extern void ata_id_to_dma_mode(struct ata_device *dev, u8 unknown); -extern unsigned long ata_device_blacklisted(const struct ata_device *dev); extern void ata_bmdma_setup (struct ata_queued_cmd *qc); extern void ata_bmdma_start (struct ata_queued_cmd *qc); extern void ata_bmdma_stop(struct ata_queued_cmd *qc); @@ -871,11 +869,11 @@ struct pci_bits { unsigned long val; }; -extern int ata_pci_init_native_host(struct ata_host *host); +extern int ata_pci_init_sff_host(struct ata_host *host); extern int ata_pci_init_bmdma(struct ata_host *host); -extern int ata_pci_prepare_native_host(struct pci_dev *pdev, - const struct ata_port_info * const * ppi, - struct ata_host **r_host); +extern int ata_pci_prepare_sff_host(struct pci_dev *pdev, + const struct ata_port_info * const * ppi, + struct ata_host **r_host); extern int pci_test_config_bits(struct pci_dev *pdev, const struct pci_bits *bits); extern unsigned long ata_pci_default_filter(struct ata_device *, unsigned long); #endif /* CONFIG_PCI */ diff --git a/include/linux/lockd/lockd.h b/include/linux/lockd/lockd.h index 05707e2fccae..e2d1ce36b367 100644 --- a/include/linux/lockd/lockd.h +++ b/include/linux/lockd/lockd.h @@ -39,6 +39,7 @@ struct nlm_host { struct hlist_node h_hash; /* doubly linked list */ struct sockaddr_in h_addr; /* peer address */ + struct sockaddr_in h_saddr; /* our address (optional) */ struct rpc_clnt * h_rpcclnt; /* RPC client to talk to peer */ char * h_name; /* remote hostname */ u32 h_version; /* interface version */ diff --git a/include/linux/lzo.h b/include/linux/lzo.h new file mode 100644 index 000000000000..d793497ec1ca --- /dev/null +++ b/include/linux/lzo.h @@ -0,0 +1,44 @@ +#ifndef __LZO_H__ +#define __LZO_H__ +/* + * LZO Public Kernel Interface + * A mini subset of the LZO real-time data compression library + * + * Copyright (C) 1996-2005 Markus F.X.J. Oberhumer <markus@oberhumer.com> + * + * The full LZO package can be found at: + * http://www.oberhumer.com/opensource/lzo/ + * + * Changed for kernel use by: + * Nitin Gupta <nitingupta910@gmail.com> + * Richard Purdie <rpurdie@openedhand.com> + */ + +#define LZO1X_MEM_COMPRESS (16384 * sizeof(unsigned char *)) +#define LZO1X_1_MEM_COMPRESS LZO1X_MEM_COMPRESS + +#define lzo1x_worst_compress(x) ((x) + ((x) / 16) + 64 + 3) + +/* This requires 'workmem' of size LZO1X_1_MEM_COMPRESS */ +int lzo1x_1_compress(const unsigned char *src, size_t src_len, + unsigned char *dst, size_t *dst_len, void *wrkmem); + +/* safe decompression with overrun testing */ +int lzo1x_decompress_safe(const unsigned char *src, size_t src_len, + unsigned char *dst, size_t *dst_len); + +/* + * Return values (< 0 = Error) + */ +#define LZO_E_OK 0 +#define LZO_E_ERROR (-1) +#define LZO_E_OUT_OF_MEMORY (-2) +#define LZO_E_NOT_COMPRESSIBLE (-3) +#define LZO_E_INPUT_OVERRUN (-4) +#define LZO_E_OUTPUT_OVERRUN (-5) +#define LZO_E_LOOKBEHIND_OVERRUN (-6) +#define LZO_E_EOF_NOT_FOUND (-7) +#define LZO_E_INPUT_NOT_CONSUMED (-8) +#define LZO_E_NOT_YET_IMPLEMENTED (-9) + +#endif diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h index b372f5910fc1..cfb78fb2c046 100644 --- a/include/linux/mlx4/device.h +++ b/include/linux/mlx4/device.h @@ -172,6 +172,7 @@ struct mlx4_caps { int num_pds; int reserved_pds; int mtt_entry_sz; + u32 max_msg_sz; u32 page_size_cap; u32 flags; u16 stat_rate_support; @@ -322,6 +323,7 @@ int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); +int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); diff --git a/include/linux/mlx4/qp.h b/include/linux/mlx4/qp.h index 10c57d279144..3968b943259a 100644 --- a/include/linux/mlx4/qp.h +++ b/include/linux/mlx4/qp.h @@ -282,6 +282,9 @@ int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt, struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar, int sqd_event, struct mlx4_qp *qp); +int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp, + struct mlx4_qp_context *context); + static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn) { return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1)); diff --git a/include/linux/mm.h b/include/linux/mm.h index 1c1207472bb4..97d0cddfd223 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -2,7 +2,6 @@ #define _LINUX_MM_H #include <linux/errno.h> -#include <linux/capability.h> #ifdef __KERNEL__ @@ -27,7 +26,6 @@ extern unsigned long max_mapnr; extern unsigned long num_physpages; extern void * high_memory; -extern unsigned long vmalloc_earlyreserve; extern int page_cluster; #ifdef CONFIG_SYSCTL @@ -1072,6 +1070,10 @@ extern unsigned long get_unmapped_area(struct file *, unsigned long, unsigned lo extern unsigned long do_mmap_pgoff(struct file *file, unsigned long addr, unsigned long len, unsigned long prot, unsigned long flag, unsigned long pgoff); +extern unsigned long mmap_region(struct file *file, unsigned long addr, + unsigned long len, unsigned long flags, + unsigned int vm_flags, unsigned long pgoff, + int accountable); static inline unsigned long do_mmap(struct file *file, unsigned long addr, unsigned long len, unsigned long prot, diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h index d09b1345a3a1..04b1636a970b 100644 --- a/include/linux/mmzone.h +++ b/include/linux/mmzone.h @@ -566,6 +566,11 @@ int sysctl_min_unmapped_ratio_sysctl_handler(struct ctl_table *, int, int sysctl_min_slab_ratio_sysctl_handler(struct ctl_table *, int, struct file *, void __user *, size_t *, loff_t *); +extern int numa_zonelist_order_handler(struct ctl_table *, int, + struct file *, void __user *, size_t *, loff_t *); +extern char numa_zonelist_order[]; +#define NUMA_ZONELIST_ORDER_LEN 16 /* string buffer size */ + #include <linux/topology.h> /* Returns the number of the current Node. */ #ifndef numa_node_id diff --git a/include/linux/mnt_namespace.h b/include/linux/mnt_namespace.h index 1fa4d9813b31..8eed44f8ca73 100644 --- a/include/linux/mnt_namespace.h +++ b/include/linux/mnt_namespace.h @@ -14,7 +14,7 @@ struct mnt_namespace { int event; }; -extern struct mnt_namespace *copy_mnt_ns(int, struct mnt_namespace *, +extern struct mnt_namespace *copy_mnt_ns(unsigned long, struct mnt_namespace *, struct fs_struct *); extern void __put_mnt_ns(struct mnt_namespace *ns); diff --git a/include/linux/module.h b/include/linux/module.h index e6e0f86ef5fc..b6a646cea1cb 100644 --- a/include/linux/module.h +++ b/include/linux/module.h @@ -6,7 +6,6 @@ * Rewritten by Richard Henderson <rth@tamu.edu> Dec 1996 * Rewritten again by Rusty Russell, 2002 */ -#include <linux/spinlock.h> #include <linux/list.h> #include <linux/stat.h> #include <linux/compiler.h> diff --git a/include/linux/msdos_fs.h b/include/linux/msdos_fs.h index 0e09c005dda8..f950921523f5 100644 --- a/include/linux/msdos_fs.h +++ b/include/linux/msdos_fs.h @@ -146,7 +146,7 @@ struct fat_boot_fsinfo { }; struct msdos_dir_entry { - __u8 name[8],ext[3]; /* name and extension */ + __u8 name[MSDOS_NAME];/* name and extension */ __u8 attr; /* attribute bits */ __u8 lcase; /* Case for base and extension */ __u8 ctime_cs; /* Creation time, centiseconds (0-199) */ diff --git a/include/linux/ncp_fs.h b/include/linux/ncp_fs.h index 83e39eb054d3..88766e43e121 100644 --- a/include/linux/ncp_fs.h +++ b/include/linux/ncp_fs.h @@ -148,8 +148,6 @@ struct ncp_nls_ioctl #include <linux/ncp_fs_i.h> #include <linux/ncp_fs_sb.h> -/* undef because public define in umsdos_fs.h (ncp_fs.h isn't public) */ -#undef PRINTK /* define because it is easy to change PRINTK to {*}PRINTK */ #define PRINTK(format, args...) printk(KERN_DEBUG format , ## args) diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 3a70f553b28f..da7a13c97eb8 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -108,6 +108,14 @@ struct wireless_dev; #define MAX_HEADER (LL_MAX_HEADER + 48) #endif +struct net_device_subqueue +{ + /* Give a control state for each queue. This struct may contain + * per-queue locks in the future. + */ + unsigned long state; +}; + /* * Network device statistics. Akin to the 2.0 ether stats but * with byte counters. @@ -177,19 +185,25 @@ struct netif_rx_stats DECLARE_PER_CPU(struct netif_rx_stats, netdev_rx_stat); +struct dev_addr_list +{ + struct dev_addr_list *next; + u8 da_addr[MAX_ADDR_LEN]; + u8 da_addrlen; + u8 da_synced; + int da_users; + int da_gusers; +}; /* * We tag multicasts with these structures. */ - -struct dev_mc_list -{ - struct dev_mc_list *next; - __u8 dmi_addr[MAX_ADDR_LEN]; - unsigned char dmi_addrlen; - int dmi_users; - int dmi_gusers; -}; + +#define dev_mc_list dev_addr_list +#define dmi_addr da_addr +#define dmi_addrlen da_addrlen +#define dmi_users da_users +#define dmi_gusers da_gusers struct hh_cache { @@ -314,9 +328,10 @@ struct net_device /* Net device features */ unsigned long features; #define NETIF_F_SG 1 /* Scatter/gather IO. */ -#define NETIF_F_IP_CSUM 2 /* Can checksum only TCP/UDP over IPv4. */ +#define NETIF_F_IP_CSUM 2 /* Can checksum TCP/UDP over IPv4. */ #define NETIF_F_NO_CSUM 4 /* Does not require checksum. F.e. loopack. */ #define NETIF_F_HW_CSUM 8 /* Can checksum all the packets. */ +#define NETIF_F_IPV6_CSUM 16 /* Can checksum TCP/UDP over IPV6 */ #define NETIF_F_HIGHDMA 32 /* Can DMA to high memory. */ #define NETIF_F_FRAGLIST 64 /* Scatter/gather IO. */ #define NETIF_F_HW_VLAN_TX 128 /* Transmit VLAN hw acceleration */ @@ -325,6 +340,7 @@ struct net_device #define NETIF_F_VLAN_CHALLENGED 1024 /* Device cannot handle VLAN packets */ #define NETIF_F_GSO 2048 /* Enable software GSO. */ #define NETIF_F_LLTX 4096 /* LockLess TX */ +#define NETIF_F_MULTI_QUEUE 16384 /* Has multiple TX/RX queues */ /* Segmentation offload features */ #define NETIF_F_GSO_SHIFT 16 @@ -338,8 +354,11 @@ struct net_device /* List of features with software fallbacks. */ #define NETIF_F_GSO_SOFTWARE (NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6) + #define NETIF_F_GEN_CSUM (NETIF_F_NO_CSUM | NETIF_F_HW_CSUM) -#define NETIF_F_ALL_CSUM (NETIF_F_IP_CSUM | NETIF_F_GEN_CSUM) +#define NETIF_F_V4_CSUM (NETIF_F_GEN_CSUM | NETIF_F_IP_CSUM) +#define NETIF_F_V6_CSUM (NETIF_F_GEN_CSUM | NETIF_F_IPV6_CSUM) +#define NETIF_F_ALL_CSUM (NETIF_F_V4_CSUM | NETIF_F_V6_CSUM) struct net_device *next_sched; @@ -388,7 +407,10 @@ struct net_device unsigned char addr_len; /* hardware address length */ unsigned short dev_id; /* for shared network cards */ - struct dev_mc_list *mc_list; /* Multicast mac addresses */ + struct dev_addr_list *uc_list; /* Secondary unicast mac addresses */ + int uc_count; /* Number of installed ucasts */ + int uc_promisc; + struct dev_addr_list *mc_list; /* Multicast mac addresses */ int mc_count; /* Number of installed mcasts */ int promiscuity; int allmulti; @@ -493,6 +515,11 @@ struct net_device void *saddr, unsigned len); int (*rebuild_header)(struct sk_buff *skb); +#define HAVE_CHANGE_RX_FLAGS + void (*change_rx_flags)(struct net_device *dev, + int flags); +#define HAVE_SET_RX_MODE + void (*set_rx_mode)(struct net_device *dev); #define HAVE_MULTICAST void (*set_multicast_list)(struct net_device *dev); #define HAVE_SET_MAC_ADDR @@ -535,22 +562,29 @@ struct net_device /* bridge stuff */ struct net_bridge_port *br_port; + /* macvlan */ + struct macvlan_port *macvlan_port; /* class/net/name entry */ struct device dev; /* space for optional statistics and wireless sysfs groups */ struct attribute_group *sysfs_groups[3]; + + /* rtnetlink link ops */ + const struct rtnl_link_ops *rtnl_link_ops; + + /* The TX queue control structures */ + unsigned int egress_subqueue_count; + struct net_device_subqueue egress_subqueue[0]; }; #define to_net_dev(d) container_of(d, struct net_device, dev) #define NETDEV_ALIGN 32 #define NETDEV_ALIGN_CONST (NETDEV_ALIGN - 1) -static inline void *netdev_priv(struct net_device *dev) +static inline void *netdev_priv(const struct net_device *dev) { - return (char *)dev + ((sizeof(struct net_device) - + NETDEV_ALIGN_CONST) - & ~NETDEV_ALIGN_CONST); + return dev->priv; } #define SET_MODULE_OWNER(dev) do { } while (0) @@ -702,6 +736,62 @@ static inline int netif_running(const struct net_device *dev) return test_bit(__LINK_STATE_START, &dev->state); } +/* + * Routines to manage the subqueues on a device. We only need start + * stop, and a check if it's stopped. All other device management is + * done at the overall netdevice level. + * Also test the device if we're multiqueue. + */ +static inline void netif_start_subqueue(struct net_device *dev, u16 queue_index) +{ +#ifdef CONFIG_NETDEVICES_MULTIQUEUE + clear_bit(__LINK_STATE_XOFF, &dev->egress_subqueue[queue_index].state); +#endif +} + +static inline void netif_stop_subqueue(struct net_device *dev, u16 queue_index) +{ +#ifdef CONFIG_NETDEVICES_MULTIQUEUE +#ifdef CONFIG_NETPOLL_TRAP + if (netpoll_trap()) + return; +#endif + set_bit(__LINK_STATE_XOFF, &dev->egress_subqueue[queue_index].state); +#endif +} + +static inline int netif_subqueue_stopped(const struct net_device *dev, + u16 queue_index) +{ +#ifdef CONFIG_NETDEVICES_MULTIQUEUE + return test_bit(__LINK_STATE_XOFF, + &dev->egress_subqueue[queue_index].state); +#else + return 0; +#endif +} + +static inline void netif_wake_subqueue(struct net_device *dev, u16 queue_index) +{ +#ifdef CONFIG_NETDEVICES_MULTIQUEUE +#ifdef CONFIG_NETPOLL_TRAP + if (netpoll_trap()) + return; +#endif + if (test_and_clear_bit(__LINK_STATE_XOFF, + &dev->egress_subqueue[queue_index].state)) + __netif_schedule(dev); +#endif +} + +static inline int netif_is_multiqueue(const struct net_device *dev) +{ +#ifdef CONFIG_NETDEVICES_MULTIQUEUE + return (!!(NETIF_F_MULTI_QUEUE & dev->features)); +#else + return 0; +#endif +} /* Use this variant when it is known for sure that it * is executing from interrupt context. @@ -992,15 +1082,26 @@ static inline void netif_tx_disable(struct net_device *dev) extern void ether_setup(struct net_device *dev); /* Support for loadable net-drivers */ -extern struct net_device *alloc_netdev(int sizeof_priv, const char *name, - void (*setup)(struct net_device *)); +extern struct net_device *alloc_netdev_mq(int sizeof_priv, const char *name, + void (*setup)(struct net_device *), + unsigned int queue_count); +#define alloc_netdev(sizeof_priv, name, setup) \ + alloc_netdev_mq(sizeof_priv, name, setup, 1) extern int register_netdev(struct net_device *dev); extern void unregister_netdev(struct net_device *dev); -/* Functions used for multicast support */ -extern void dev_mc_upload(struct net_device *dev); +/* Functions used for secondary unicast and multicast support */ +extern void dev_set_rx_mode(struct net_device *dev); +extern void __dev_set_rx_mode(struct net_device *dev); +extern int dev_unicast_delete(struct net_device *dev, void *addr, int alen); +extern int dev_unicast_add(struct net_device *dev, void *addr, int alen); extern int dev_mc_delete(struct net_device *dev, void *addr, int alen, int all); extern int dev_mc_add(struct net_device *dev, void *addr, int alen, int newonly); +extern int dev_mc_sync(struct net_device *to, struct net_device *from); +extern void dev_mc_unsync(struct net_device *to, struct net_device *from); extern void dev_mc_discard(struct net_device *dev); +extern int __dev_addr_delete(struct dev_addr_list **list, int *count, void *addr, int alen, int all); +extern int __dev_addr_add(struct dev_addr_list **list, int *count, void *addr, int alen, int newonly); +extern void __dev_addr_discard(struct dev_addr_list **list); extern void dev_set_promiscuity(struct net_device *dev, int inc); extern void dev_set_allmulti(struct net_device *dev, int inc); extern void netdev_state_change(struct net_device *dev); diff --git a/include/linux/netfilter.h b/include/linux/netfilter.h index 10b5c6275706..0eed0b7ab2df 100644 --- a/include/linux/netfilter.h +++ b/include/linux/netfilter.h @@ -275,7 +275,8 @@ struct nf_queue_handler { }; extern int nf_register_queue_handler(int pf, struct nf_queue_handler *qh); -extern int nf_unregister_queue_handler(int pf); +extern int nf_unregister_queue_handler(int pf, + struct nf_queue_handler *qh); extern void nf_unregister_queue_handlers(struct nf_queue_handler *qh); extern void nf_reinject(struct sk_buff *skb, struct nf_info *info, diff --git a/include/linux/netfilter/nf_conntrack_pptp.h b/include/linux/netfilter/nf_conntrack_pptp.h index 9d8144a488cd..c93061f33144 100644 --- a/include/linux/netfilter/nf_conntrack_pptp.h +++ b/include/linux/netfilter/nf_conntrack_pptp.h @@ -4,6 +4,8 @@ #include <linux/netfilter/nf_conntrack_common.h> +extern const char *pptp_msg_name[]; + /* state of the control session */ enum pptp_ctrlsess_state { PPTP_SESSION_NONE, /* no session present */ diff --git a/include/linux/netfilter/x_tables.h b/include/linux/netfilter/x_tables.h index 7e733a6ba4f6..64f425a855bb 100644 --- a/include/linux/netfilter/x_tables.h +++ b/include/linux/netfilter/x_tables.h @@ -141,22 +141,22 @@ struct xt_match /* Arguments changed since 2.6.9, as this must now handle non-linear skb, using skb_header_pointer and skb_ip_make_writable. */ - int (*match)(const struct sk_buff *skb, - const struct net_device *in, - const struct net_device *out, - const struct xt_match *match, - const void *matchinfo, - int offset, - unsigned int protoff, - int *hotdrop); + bool (*match)(const struct sk_buff *skb, + const struct net_device *in, + const struct net_device *out, + const struct xt_match *match, + const void *matchinfo, + int offset, + unsigned int protoff, + bool *hotdrop); /* Called when user tries to insert an entry of this type. */ /* Should return true or false. */ - int (*checkentry)(const char *tablename, - const void *ip, - const struct xt_match *match, - void *matchinfo, - unsigned int hook_mask); + bool (*checkentry)(const char *tablename, + const void *ip, + const struct xt_match *match, + void *matchinfo, + unsigned int hook_mask); /* Called when entry of this type deleted. */ void (*destroy)(const struct xt_match *match, void *matchinfo); @@ -202,11 +202,11 @@ struct xt_target hook_mask is a bitmask of hooks from which it can be called. */ /* Should return true or false. */ - int (*checkentry)(const char *tablename, - const void *entry, - const struct xt_target *target, - void *targinfo, - unsigned int hook_mask); + bool (*checkentry)(const char *tablename, + const void *entry, + const struct xt_target *target, + void *targinfo, + unsigned int hook_mask); /* Called when entry of this type deleted. */ void (*destroy)(const struct xt_target *target, void *targinfo); diff --git a/include/linux/netfilter/xt_connlimit.h b/include/linux/netfilter/xt_connlimit.h new file mode 100644 index 000000000000..90ae8b474cb8 --- /dev/null +++ b/include/linux/netfilter/xt_connlimit.h @@ -0,0 +1,17 @@ +#ifndef _XT_CONNLIMIT_H +#define _XT_CONNLIMIT_H + +struct xt_connlimit_data; + +struct xt_connlimit_info { + union { + u_int32_t v4_mask; + u_int32_t v6_mask[4]; + }; + unsigned int limit, inverse; + + /* this needs to be at the end */ + struct xt_connlimit_data *data __attribute__((aligned(8))); +}; + +#endif /* _XT_CONNLIMIT_H */ diff --git a/include/linux/netfilter/xt_u32.h b/include/linux/netfilter/xt_u32.h new file mode 100644 index 000000000000..9947f56cdbdd --- /dev/null +++ b/include/linux/netfilter/xt_u32.h @@ -0,0 +1,40 @@ +#ifndef _XT_U32_H +#define _XT_U32_H 1 + +enum xt_u32_ops { + XT_U32_AND, + XT_U32_LEFTSH, + XT_U32_RIGHTSH, + XT_U32_AT, +}; + +struct xt_u32_location_element { + u_int32_t number; + u_int8_t nextop; +}; + +struct xt_u32_value_element { + u_int32_t min; + u_int32_t max; +}; + +/* + * Any way to allow for an arbitrary number of elements? + * For now, I settle with a limit of 10 each. + */ +#define XT_U32_MAXSIZE 10 + +struct xt_u32_test { + struct xt_u32_location_element location[XT_U32_MAXSIZE+1]; + struct xt_u32_value_element value[XT_U32_MAXSIZE+1]; + u_int8_t nnums; + u_int8_t nvalues; +}; + +struct xt_u32 { + struct xt_u32_test tests[XT_U32_MAXSIZE+1]; + u_int8_t ntests; + u_int8_t invert; +}; + +#endif /* _XT_U32_H */ diff --git a/include/linux/netfilter_ipv4/ipt_CLUSTERIP.h b/include/linux/netfilter_ipv4/ipt_CLUSTERIP.h index d9bceedfb3dc..daf50be22c9d 100644 --- a/include/linux/netfilter_ipv4/ipt_CLUSTERIP.h +++ b/include/linux/netfilter_ipv4/ipt_CLUSTERIP.h @@ -18,13 +18,13 @@ struct clusterip_config; struct ipt_clusterip_tgt_info { u_int32_t flags; - + /* only relevant for new ones */ u_int8_t clustermac[6]; u_int16_t num_total_nodes; u_int16_t num_local_nodes; u_int16_t local_nodes[CLUSTERIP_MAX_NODES]; - enum clusterip_hashmode hash_mode; + u_int32_t hash_mode; u_int32_t hash_initval; struct clusterip_config *config; diff --git a/include/linux/netfilter_ipv6/ip6_tables.h b/include/linux/netfilter_ipv6/ip6_tables.h index 4686f8342cbd..9a720f05888f 100644 --- a/include/linux/netfilter_ipv6/ip6_tables.h +++ b/include/linux/netfilter_ipv6/ip6_tables.h @@ -44,8 +44,14 @@ struct ip6t_ip6 { char iniface[IFNAMSIZ], outiface[IFNAMSIZ]; unsigned char iniface_mask[IFNAMSIZ], outiface_mask[IFNAMSIZ]; - /* ARGH, HopByHop uses 0, so can't do 0 = ANY, - instead IP6T_F_NOPROTO must be set */ + /* Upper protocol number + * - The allowed value is 0 (any) or protocol number of last parsable + * header, which is 50 (ESP), 59 (No Next Header), 135 (MH), or + * the non IPv6 extension headers. + * - The protocol numbers of IPv6 extension headers except of ESP and + * MH do not match any packets. + * - You also need to set IP6T_FLAGS_PROTO to "flags" to check protocol. + */ u_int16_t proto; /* TOS to match iff flags & IP6T_F_TOS */ u_int8_t tos; diff --git a/include/linux/nfs4.h b/include/linux/nfs4.h index 7e7f33a38fc0..8726491de154 100644 --- a/include/linux/nfs4.h +++ b/include/linux/nfs4.h @@ -15,6 +15,7 @@ #include <linux/types.h> +#define NFS4_BITMAP_SIZE 2 #define NFS4_VERIFIER_SIZE 8 #define NFS4_STATEID_SIZE 16 #define NFS4_FHSIZE 128 diff --git a/include/linux/nfs4_mount.h b/include/linux/nfs4_mount.h index 26b4c83f831d..a0dcf6655657 100644 --- a/include/linux/nfs4_mount.h +++ b/include/linux/nfs4_mount.h @@ -65,6 +65,7 @@ struct nfs4_mount_data { #define NFS4_MOUNT_NOCTO 0x0010 /* 1 */ #define NFS4_MOUNT_NOAC 0x0020 /* 1 */ #define NFS4_MOUNT_STRICTLOCK 0x1000 /* 1 */ -#define NFS4_MOUNT_FLAGMASK 0xFFFF +#define NFS4_MOUNT_UNSHARED 0x8000 /* 1 */ +#define NFS4_MOUNT_FLAGMASK 0x9033 #endif diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h index 0543439a97af..c098ae194f79 100644 --- a/include/linux/nfs_fs.h +++ b/include/linux/nfs_fs.h @@ -30,7 +30,9 @@ #ifdef __KERNEL__ #include <linux/in.h> +#include <linux/kref.h> #include <linux/mm.h> +#include <linux/namei.h> #include <linux/pagemap.h> #include <linux/rbtree.h> #include <linux/rwsem.h> @@ -69,9 +71,8 @@ struct nfs_access_entry { struct nfs4_state; struct nfs_open_context { - atomic_t count; - struct vfsmount *vfsmnt; - struct dentry *dentry; + struct kref kref; + struct path path; struct rpc_cred *cred; struct nfs4_state *state; fl_owner_t lockowner; @@ -155,13 +156,9 @@ struct nfs_inode { /* * This is the list of dirty unwritten pages. */ - spinlock_t req_lock; - struct list_head dirty; - struct list_head commit; struct radix_tree_root nfs_page_tree; - unsigned int ndirty, - ncommit, + unsigned long ncommit, npages; /* Open contexts for shared mmap writes */ @@ -187,6 +184,7 @@ struct nfs_inode { #define NFS_INO_INVALID_ACCESS 0x0008 /* cached access cred invalid */ #define NFS_INO_INVALID_ACL 0x0010 /* cached acls are invalid */ #define NFS_INO_REVAL_PAGECACHE 0x0020 /* must revalidate pagecache */ +#define NFS_INO_REVAL_FORCED 0x0040 /* force revalidation ignoring a delegation */ /* * Bit offsets in flags field @@ -496,21 +494,18 @@ static inline void nfs3_forget_cached_acls(struct inode *inode) /* * linux/fs/mount_clnt.c - * (Used only by nfsroot module) */ -extern int nfsroot_mount(struct sockaddr_in *, char *, struct nfs_fh *, - int, int); +extern int nfs_mount(struct sockaddr *, size_t, char *, char *, + int, int, struct nfs_fh *); /* * inline functions */ -static inline loff_t -nfs_size_to_loff_t(__u64 size) +static inline loff_t nfs_size_to_loff_t(__u64 size) { - loff_t maxsz = (((loff_t) ULONG_MAX) << PAGE_CACHE_SHIFT) + PAGE_CACHE_SIZE - 1; - if (size > maxsz) - return maxsz; + if (size > (__u64) OFFSET_MAX - 1) + return OFFSET_MAX - 1; return (loff_t) size; } @@ -557,6 +552,7 @@ extern void * nfs_root_data(void); #define NFSDBG_ROOT 0x0080 #define NFSDBG_CALLBACK 0x0100 #define NFSDBG_CLIENT 0x0200 +#define NFSDBG_MOUNT 0x0400 #define NFSDBG_ALL 0xFFFF #ifdef __KERNEL__ diff --git a/include/linux/nfs_fs_sb.h b/include/linux/nfs_fs_sb.h index 52b4378311c8..0cac49bc0955 100644 --- a/include/linux/nfs_fs_sb.h +++ b/include/linux/nfs_fs_sb.h @@ -16,7 +16,6 @@ struct nfs_client { #define NFS_CS_INITING 1 /* busy initialising */ int cl_nfsversion; /* NFS protocol version */ unsigned long cl_res_state; /* NFS resources state */ -#define NFS_CS_RPCIOD 0 /* - rpciod started */ #define NFS_CS_CALLBACK 1 /* - callback started */ #define NFS_CS_IDMAP 2 /* - idmap started */ #define NFS_CS_RENEWD 3 /* - renewd started */ @@ -35,7 +34,8 @@ struct nfs_client { nfs4_verifier cl_confirm; unsigned long cl_state; - u32 cl_lockowner_id; + struct rb_root cl_openowner_id; + struct rb_root cl_lockowner_id; /* * The following rwsem ensures exclusive access to the server @@ -44,9 +44,7 @@ struct nfs_client { struct rw_semaphore cl_sem; struct list_head cl_delegations; - struct list_head cl_state_owners; - struct list_head cl_unused; - int cl_nunused; + struct rb_root cl_state_owners; spinlock_t cl_lock; unsigned long cl_lease_time; diff --git a/include/linux/nfs_mount.h b/include/linux/nfs_mount.h index cc8b9c59acb8..a3ade89a64d2 100644 --- a/include/linux/nfs_mount.h +++ b/include/linux/nfs_mount.h @@ -37,7 +37,7 @@ struct nfs_mount_data { int acdirmin; /* 1 */ int acdirmax; /* 1 */ struct sockaddr_in addr; /* 1 */ - char hostname[256]; /* 1 */ + char hostname[NFS_MAXNAMLEN + 1]; /* 1 */ int namlen; /* 2 */ unsigned int bsize; /* 3 */ struct nfs3_fh root; /* 4 */ @@ -62,6 +62,7 @@ struct nfs_mount_data { #define NFS_MOUNT_STRICTLOCK 0x1000 /* reserved for NFSv4 */ #define NFS_MOUNT_SECFLAVOUR 0x2000 /* 5 */ #define NFS_MOUNT_NORDIRPLUS 0x4000 /* 5 */ +#define NFS_MOUNT_UNSHARED 0x8000 /* 5 */ #define NFS_MOUNT_FLAGMASK 0xFFFF #endif diff --git a/include/linux/nfs_page.h b/include/linux/nfs_page.h index bd193af80162..78e60798d10e 100644 --- a/include/linux/nfs_page.h +++ b/include/linux/nfs_page.h @@ -16,12 +16,13 @@ #include <linux/sunrpc/auth.h> #include <linux/nfs_xdr.h> -#include <asm/atomic.h> +#include <linux/kref.h> /* * Valid flags for the radix tree */ -#define NFS_PAGE_TAG_WRITEBACK 0 +#define NFS_PAGE_TAG_LOCKED 0 +#define NFS_PAGE_TAG_COMMIT 1 /* * Valid flags for a dirty buffer @@ -33,8 +34,7 @@ struct nfs_inode; struct nfs_page { - struct list_head wb_list, /* Defines state of page: */ - *wb_list_head; /* read/write/commit */ + struct list_head wb_list; /* Defines state of page: */ struct page *wb_page; /* page to read in/write out */ struct nfs_open_context *wb_context; /* File state context info */ atomic_t wb_complete; /* i/os we're waiting for */ @@ -42,7 +42,7 @@ struct nfs_page { unsigned int wb_offset, /* Offset & ~PAGE_CACHE_MASK */ wb_pgbase, /* Start of page data */ wb_bytes; /* Length of request */ - atomic_t wb_count; /* reference count */ + struct kref wb_kref; /* reference count */ unsigned long wb_flags; struct nfs_writeverf wb_verf; /* Commit cookie */ }; @@ -71,8 +71,8 @@ extern void nfs_clear_request(struct nfs_page *req); extern void nfs_release_request(struct nfs_page *req); -extern int nfs_scan_list(struct nfs_inode *nfsi, struct list_head *head, struct list_head *dst, - pgoff_t idx_start, unsigned int npages); +extern int nfs_scan_list(struct nfs_inode *nfsi, struct list_head *dst, + pgoff_t idx_start, unsigned int npages, int tag); extern void nfs_pageio_init(struct nfs_pageio_descriptor *desc, struct inode *inode, int (*doio)(struct inode *, struct list_head *, unsigned int, size_t, int), @@ -84,12 +84,11 @@ extern void nfs_pageio_complete(struct nfs_pageio_descriptor *desc); extern void nfs_pageio_cond_complete(struct nfs_pageio_descriptor *, pgoff_t); extern int nfs_wait_on_request(struct nfs_page *); extern void nfs_unlock_request(struct nfs_page *req); -extern int nfs_set_page_writeback_locked(struct nfs_page *req); -extern void nfs_clear_page_writeback(struct nfs_page *req); +extern void nfs_clear_page_tag_locked(struct nfs_page *req); /* - * Lock the page of an asynchronous request without incrementing the wb_count + * Lock the page of an asynchronous request without getting a new reference */ static inline int nfs_lock_request_dontget(struct nfs_page *req) @@ -98,14 +97,14 @@ nfs_lock_request_dontget(struct nfs_page *req) } /* - * Lock the page of an asynchronous request + * Lock the page of an asynchronous request and take a reference */ static inline int nfs_lock_request(struct nfs_page *req) { if (test_and_set_bit(PG_BUSY, &req->wb_flags)) return 0; - atomic_inc(&req->wb_count); + kref_get(&req->wb_kref); return 1; } @@ -118,7 +117,6 @@ static inline void nfs_list_add_request(struct nfs_page *req, struct list_head *head) { list_add_tail(&req->wb_list, head); - req->wb_list_head = head; } @@ -132,7 +130,6 @@ nfs_list_remove_request(struct nfs_page *req) if (list_empty(&req->wb_list)) return; list_del_init(&req->wb_list); - req->wb_list_head = NULL; } static inline struct nfs_page * diff --git a/include/linux/nfs_xdr.h b/include/linux/nfs_xdr.h index 10c26ed0db71..38d77681cf27 100644 --- a/include/linux/nfs_xdr.h +++ b/include/linux/nfs_xdr.h @@ -119,7 +119,7 @@ struct nfs_openargs { struct nfs_seqid * seqid; int open_flags; __u64 clientid; - __u32 id; + __u64 id; union { struct iattr * attrs; /* UNCHECKED, GUARDED */ nfs4_verifier verifier; /* EXCLUSIVE */ @@ -144,6 +144,7 @@ struct nfs_openres { nfs4_stateid delegation; __u32 do_recall; __u64 maxsize; + __u32 attrset[NFS4_BITMAP_SIZE]; }; /* @@ -180,7 +181,7 @@ struct nfs_closeres { * */ struct nfs_lowner { __u64 clientid; - u32 id; + __u64 id; }; struct nfs_lock_args { diff --git a/include/linux/nsproxy.h b/include/linux/nsproxy.h index 189e0dc993ab..ce06188b7a56 100644 --- a/include/linux/nsproxy.h +++ b/include/linux/nsproxy.h @@ -28,10 +28,11 @@ struct nsproxy { struct ipc_namespace *ipc_ns; struct mnt_namespace *mnt_ns; struct pid_namespace *pid_ns; + struct user_namespace *user_ns; }; extern struct nsproxy init_nsproxy; -int copy_namespaces(int flags, struct task_struct *tsk); +int copy_namespaces(unsigned long flags, struct task_struct *tsk); void get_task_namespaces(struct task_struct *tsk); void free_nsproxy(struct nsproxy *ns); int unshare_nsproxy_namespaces(unsigned long, struct nsproxy **, diff --git a/include/linux/pci.h b/include/linux/pci.h index 086a0e5a6318..5e84f2e8d54c 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -111,7 +111,8 @@ enum pcie_reset_state { typedef unsigned short __bitwise pci_bus_flags_t; enum pci_bus_flags { - PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, + PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, + PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, }; struct pci_cap_saved_state { @@ -138,6 +139,7 @@ struct pci_dev { unsigned short subsystem_vendor; unsigned short subsystem_device; unsigned int class; /* 3 bytes: (base,sub,prog-if) */ + u8 revision; /* PCI revision, low byte of class word */ u8 hdr_type; /* PCI header type (`multi' flag masked out) */ u8 rom_base_reg; /* which config register controls the ROM */ u8 pin; /* which interrupt pin this device uses */ @@ -313,7 +315,7 @@ struct pci_dynids { /* ---------------------------------------------------------------- */ /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides - * a set fof callbacks in struct pci_error_handlers, then that device driver + * a set of callbacks in struct pci_error_handlers, then that device driver * will be notified of PCI bus errors, and will be driven to recovery * when an error occurs. */ @@ -370,7 +372,6 @@ struct pci_driver { int (*suspend_late) (struct pci_dev *dev, pm_message_t state); int (*resume_early) (struct pci_dev *dev); int (*resume) (struct pci_dev *dev); /* Device woken up */ - int (*enable_wake) (struct pci_dev *dev, pci_power_t state, int enable); /* Enable wake event */ void (*shutdown) (struct pci_dev *dev); struct pci_error_handlers *err_handler; @@ -431,6 +432,8 @@ extern struct bus_type pci_bus_type; * code, or pci core code. */ extern struct list_head pci_root_buses; /* list of all known PCI buses */ extern struct list_head pci_devices; /* list of all devices */ +/* Some device drivers need know if pci is initiated */ +extern int no_pci_devices(void); void pcibios_fixup_bus(struct pci_bus *); int __must_check pcibios_enable_device(struct pci_dev *, int mask); @@ -475,7 +478,7 @@ extern void pci_sort_breadthfirst(void); /* Generic PCI functions exported to card drivers */ struct pci_dev __deprecated *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from); -struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn); +struct pci_dev __deprecated *pci_find_slot (unsigned int bus, unsigned int devfn); int pci_find_capability (struct pci_dev *dev, int cap); int pci_find_next_capability (struct pci_dev *dev, u8 pos, int cap); int pci_find_ext_capability (struct pci_dev *dev, int cap); @@ -544,11 +547,16 @@ void pci_set_master(struct pci_dev *dev); int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); #define HAVE_PCI_SET_MWI int __must_check pci_set_mwi(struct pci_dev *dev); +int pci_try_set_mwi(struct pci_dev *dev); void pci_clear_mwi(struct pci_dev *dev); void pci_intx(struct pci_dev *dev, int enable); void pci_msi_off(struct pci_dev *dev); int pci_set_dma_mask(struct pci_dev *dev, u64 mask); int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask); +int pcix_get_max_mmrbc(struct pci_dev *dev); +int pcix_get_mmrbc(struct pci_dev *dev); +int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); +int pcie_set_readrq(struct pci_dev *dev, int rq); void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno); int __must_check pci_assign_resource(struct pci_dev *dev, int i); int __must_check pci_assign_resource_fixed(struct pci_dev *dev, int i); @@ -560,6 +568,7 @@ void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); void __iomem __must_check *pci_map_rom_copy(struct pci_dev *pdev, size_t *size); void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); void pci_remove_rom(struct pci_dev *pdev); +size_t pci_get_rom_size(void __iomem *rom, size_t size); /* Power management related routines */ int pci_save_state(struct pci_dev *dev); @@ -717,6 +726,7 @@ static inline struct pci_dev *pci_get_class(unsigned int class, struct pci_dev * { return NULL; } #define pci_dev_present(ids) (0) +#define no_pci_devices() (1) #define pci_find_present(ids) (NULL) #define pci_dev_put(dev) do { } while (0) @@ -876,5 +886,7 @@ extern int pci_pci_problems; extern unsigned long pci_cardbus_io_size; extern unsigned long pci_cardbus_mem_size; +extern int pcibios_add_platform_entries(struct pci_dev *dev); + #endif /* __KERNEL__ */ #endif /* LINUX_PCI_H */ diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 75c4d4d06892..2c7add169539 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -133,6 +133,9 @@ /* Vendors and devices. Sort key: vendor first, device next. */ +#define PCI_VENDOR_ID_TTTECH 0x0357 +#define PCI_DEVICE_ID_TTTECH_MC322 0x000a + #define PCI_VENDOR_ID_DYNALINK 0x0675 #define PCI_DEVICE_ID_DYNALINK_IS64PH 0x1702 @@ -371,6 +374,7 @@ #define PCI_DEVICE_ID_ATI_IXP600_SMBUS 0x4385 #define PCI_DEVICE_ID_ATI_IXP600_IDE 0x438c #define PCI_DEVICE_ID_ATI_IXP700_SATA 0x4390 +#define PCI_DEVICE_ID_ATI_IXP700_SMBUS 0x4395 #define PCI_DEVICE_ID_ATI_IXP700_IDE 0x439c #define PCI_VENDOR_ID_VLSI 0x1004 @@ -475,6 +479,9 @@ #define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM_PCIE 0x0361 #define PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL 0x252 +#define PCI_VENDOR_ID_UNISYS 0x1018 +#define PCI_DEVICE_ID_UNISYS_DMA_DIRECTOR 0x001C + #define PCI_VENDOR_ID_COMPEX2 0x101a /* pci.ids says "AT&T GIS (NCR)" */ #define PCI_DEVICE_ID_COMPEX2_100VG 0x0005 @@ -732,7 +739,6 @@ #define PCI_DEVICE_ID_ELSA_MICROLINK 0x1000 #define PCI_DEVICE_ID_ELSA_QS3000 0x3000 - #define PCI_VENDOR_ID_BUSLOGIC 0x104B #define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140 #define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER 0x1040 @@ -778,7 +784,6 @@ #define PCI_VENDOR_ID_SONY 0x104d - /* Winbond have two vendor IDs! See 0x10ad as well */ #define PCI_VENDOR_ID_WINBOND2 0x1050 #define PCI_DEVICE_ID_WINBOND2_89C940F 0x5a5a @@ -816,7 +821,6 @@ #define PCI_DEVICE_ID_PROMISE_20276 0x5275 #define PCI_DEVICE_ID_PROMISE_20277 0x7275 - #define PCI_VENDOR_ID_UMC 0x1060 #define PCI_DEVICE_ID_UMC_UM8673F 0x0101 #define PCI_DEVICE_ID_UMC_UM8886BF 0x673a @@ -832,7 +836,6 @@ #define PCI_DEVICE_ID_MYLEX_DAC960_BA 0xBA56 #define PCI_DEVICE_ID_MYLEX_DAC960_GEM 0xB166 - #define PCI_VENDOR_ID_APPLE 0x106b #define PCI_DEVICE_ID_APPLE_BANDIT 0x0001 #define PCI_DEVICE_ID_APPLE_HYDRA 0x000e @@ -868,7 +871,6 @@ #define PCI_DEVICE_ID_YAMAHA_744 0x0010 #define PCI_DEVICE_ID_YAMAHA_754 0x0012 - #define PCI_VENDOR_ID_QLOGIC 0x1077 #define PCI_DEVICE_ID_QLOGIC_ISP10160 0x1016 #define PCI_DEVICE_ID_QLOGIC_ISP1020 0x1020 @@ -899,12 +901,9 @@ #define PCI_DEVICE_ID_CYRIX_5530_AUDIO 0x0103 #define PCI_DEVICE_ID_CYRIX_5530_VIDEO 0x0104 - - #define PCI_VENDOR_ID_CONTAQ 0x1080 #define PCI_DEVICE_ID_CONTAQ_82C693 0xc693 - #define PCI_VENDOR_ID_OLICOM 0x108d #define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 #define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 @@ -936,23 +935,19 @@ #define PCI_DEVICE_ID_SII_3112 0x3112 #define PCI_DEVICE_ID_SII_1210SA 0x0240 - #define PCI_VENDOR_ID_BROOKTREE 0x109e #define PCI_DEVICE_ID_BROOKTREE_878 0x0878 #define PCI_DEVICE_ID_BROOKTREE_879 0x0879 - #define PCI_VENDOR_ID_SGI 0x10a9 #define PCI_DEVICE_ID_SGI_IOC3 0x0003 +#define PCI_DEVICE_ID_SGI_LITHIUM 0x1002 #define PCI_DEVICE_ID_SGI_IOC4 0x100a -#define PCI_VENDOR_ID_SGI_LITHIUM 0x1002 - #define PCI_VENDOR_ID_WINBOND 0x10ad #define PCI_DEVICE_ID_WINBOND_82C105 0x0105 #define PCI_DEVICE_ID_WINBOND_83C553 0x0565 - #define PCI_VENDOR_ID_PLX 0x10b5 #define PCI_DEVICE_ID_PLX_R685 0x1030 #define PCI_DEVICE_ID_PLX_ROMULUS 0x106a @@ -986,7 +981,6 @@ #define PCI_DEVICE_ID_3COM_3CR990SVR97 0x9909 #define PCI_DEVICE_ID_3COM_3CR990SVR 0x990a - #define PCI_VENDOR_ID_AL 0x10b9 #define PCI_DEVICE_ID_AL_M1533 0x1533 #define PCI_DEVICE_ID_AL_M1535 0x1535 @@ -1009,18 +1003,14 @@ #define PCI_DEVICE_ID_AL_M5451 0x5451 #define PCI_DEVICE_ID_AL_M7101 0x7101 - - #define PCI_VENDOR_ID_NEOMAGIC 0x10c8 #define PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO 0x8005 #define PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO 0x8006 #define PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO 0x8016 - #define PCI_VENDOR_ID_TCONRAD 0x10da #define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508 - #define PCI_VENDOR_ID_NVIDIA 0x10de #define PCI_DEVICE_ID_NVIDIA_TNT 0x0020 #define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028 @@ -1241,9 +1231,6 @@ #define PCI_DEVICE_ID_IMS_TT128 0x9128 #define PCI_DEVICE_ID_IMS_TT3D 0x9135 - - - #define PCI_VENDOR_ID_INTERG 0x10ea #define PCI_DEVICE_ID_INTERG_1682 0x1682 #define PCI_DEVICE_ID_INTERG_2000 0x2000 @@ -1262,7 +1249,6 @@ #define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5 #define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI 0x3fc6 - #define PCI_VENDOR_ID_INIT 0x1101 #define PCI_VENDOR_ID_CREATIVE 0x1102 /* duplicate: ECTIVA */ @@ -1357,7 +1343,6 @@ #define PCI_VENDOR_ID_SIEMENS 0x110A #define PCI_DEVICE_ID_SIEMENS_DSCC4 0x2102 - #define PCI_VENDOR_ID_VORTEX 0x1119 #define PCI_DEVICE_ID_VORTEX_GDT60x0 0x0000 #define PCI_DEVICE_ID_VORTEX_GDT6000B 0x0001 @@ -1383,8 +1368,8 @@ #define PCI_VENDOR_ID_EF 0x111a #define PCI_DEVICE_ID_EF_ATM_FPGA 0x0000 #define PCI_DEVICE_ID_EF_ATM_ASIC 0x0002 -#define PCI_VENDOR_ID_EF_ATM_LANAI2 0x0003 -#define PCI_VENDOR_ID_EF_ATM_LANAIHB 0x0005 +#define PCI_DEVICE_ID_EF_ATM_LANAI2 0x0003 +#define PCI_DEVICE_ID_EF_ATM_LANAIHB 0x0005 #define PCI_VENDOR_ID_IDT 0x111d #define PCI_DEVICE_ID_IDT_IDT77201 0x0001 @@ -1392,7 +1377,6 @@ #define PCI_VENDOR_ID_FORE 0x1127 #define PCI_DEVICE_ID_FORE_PCA200E 0x0300 - #define PCI_VENDOR_ID_PHILIPS 0x1131 #define PCI_DEVICE_ID_PHILIPS_SAA7146 0x7146 #define PCI_DEVICE_ID_PHILIPS_SAA9730 0x9730 @@ -1411,7 +1395,6 @@ #define PCI_DEVICE_ID_ZIATECH_5550_HC 0x5550 - #define PCI_VENDOR_ID_SYSKONNECT 0x1148 #define PCI_DEVICE_ID_SYSKONNECT_TR 0x4200 #define PCI_DEVICE_ID_SYSKONNECT_GE 0x4300 @@ -1419,7 +1402,6 @@ #define PCI_DEVICE_ID_SYSKONNECT_9DXX 0x4400 #define PCI_DEVICE_ID_SYSKONNECT_9MXX 0x4500 - #define PCI_VENDOR_ID_DIGI 0x114f #define PCI_DEVICE_ID_DIGI_DF_M_IOM2_E 0x0070 #define PCI_DEVICE_ID_DIGI_DF_M_E 0x0071 @@ -1430,12 +1412,10 @@ #define PCI_DEVICE_ID_NEO_2RJ45 0x00CA #define PCI_DEVICE_ID_NEO_2RJ45PRI 0x00CB - #define PCI_VENDOR_ID_XIRCOM 0x115d #define PCI_DEVICE_ID_XIRCOM_RBM56G 0x0101 #define PCI_DEVICE_ID_XIRCOM_X3201_MDM 0x0103 - #define PCI_VENDOR_ID_SERVERWORKS 0x1166 #define PCI_DEVICE_ID_SERVERWORKS_HE 0x0008 #define PCI_DEVICE_ID_SERVERWORKS_LE 0x0009 @@ -1504,7 +1484,6 @@ #define PCI_DEVICE_ID_ZEITNET_1221 0x0001 #define PCI_DEVICE_ID_ZEITNET_1225 0x0002 - #define PCI_VENDOR_ID_FUJITSU_ME 0x119e #define PCI_DEVICE_ID_FUJITSU_FS155 0x0001 #define PCI_DEVICE_ID_FUJITSU_FS50 0x0003 @@ -1522,28 +1501,23 @@ #define PCI_DEVICE_ID_V3_V960 0x0001 #define PCI_DEVICE_ID_V3_V351 0x0002 - #define PCI_VENDOR_ID_ATT 0x11c1 #define PCI_DEVICE_ID_ATT_VENUS_MODEM 0x480 - #define PCI_VENDOR_ID_SPECIALIX 0x11cb #define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000 #define PCI_DEVICE_ID_SPECIALIX_RIO 0x8000 #define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004 - #define PCI_VENDOR_ID_ANALOG_DEVICES 0x11d4 #define PCI_DEVICE_ID_AD1889JS 0x1889 - #define PCI_DEVICE_ID_SEGA_BBA 0x1234 #define PCI_VENDOR_ID_ZORAN 0x11de #define PCI_DEVICE_ID_ZORAN_36057 0x6057 #define PCI_DEVICE_ID_ZORAN_36120 0x6120 - #define PCI_VENDOR_ID_COMPEX 0x11f6 #define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112 @@ -1602,8 +1576,6 @@ #define PCI_DEVICE_ID_3DFX_VOODOO3 0x0005 #define PCI_DEVICE_ID_3DFX_VOODOO5 0x0009 - - #define PCI_VENDOR_ID_AVM 0x1244 #define PCI_DEVICE_ID_AVM_B1 0x0700 #define PCI_DEVICE_ID_AVM_C4 0x0800 @@ -1612,7 +1584,6 @@ #define PCI_DEVICE_ID_AVM_C2 0x1100 #define PCI_DEVICE_ID_AVM_T1 0x1200 - #define PCI_VENDOR_ID_STALLION 0x124d /* Allied Telesyn */ @@ -1635,7 +1606,6 @@ #define PCI_VENDOR_ID_SATSAGEM 0x1267 #define PCI_DEVICE_ID_SATSAGEM_NICCY 0x1016 - #define PCI_VENDOR_ID_ENSONIQ 0x1274 #define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880 #define PCI_DEVICE_ID_ENSONIQ_ES1370 0x5000 @@ -1658,7 +1628,6 @@ #define PCI_VENDOR_ID_ALTEON 0x12ae - #define PCI_SUBVENDOR_ID_CONNECT_TECH 0x12c4 #define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232 0x0001 #define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232 0x0002 @@ -1689,7 +1658,6 @@ #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485 0x0331 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485 0x0332 - #define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2 #define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018 @@ -1799,7 +1767,6 @@ #define PCI_DEVICE_ID_LMC_SSI 0x0005 #define PCI_DEVICE_ID_LMC_T1 0x0006 - #define PCI_VENDOR_ID_NETGEAR 0x1385 #define PCI_DEVICE_ID_NETGEAR_GA620 0x620a @@ -1902,6 +1869,8 @@ #define PCI_DEVICE_ID_OXSEMI_16PCI952 0x9521 #define PCI_DEVICE_ID_OXSEMI_16PCI952PP 0x9523 +#define PCI_VENDOR_ID_CHELSIO 0x1425 + #define PCI_VENDOR_ID_SAMSUNG 0x144d #define PCI_VENDOR_ID_MYRICOM 0x14c1 @@ -2010,13 +1979,10 @@ #define PCI_DEVICE_ID_ENE_720 0x1421 #define PCI_DEVICE_ID_ENE_722 0x1422 -#define PCI_VENDOR_ID_CHELSIO 0x1425 - #define PCI_SUBVENDOR_ID_PERLE 0x155f #define PCI_SUBDEVICE_ID_PCI_RAS4 0xf001 #define PCI_SUBDEVICE_ID_PCI_RAS8 0xf010 - #define PCI_VENDOR_ID_SYBA 0x1592 #define PCI_DEVICE_ID_SYBA_2P_EPP 0x0782 #define PCI_DEVICE_ID_SYBA_1P_ECP 0x0783 @@ -2035,8 +2001,10 @@ #define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c #define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 -#define PCI_VENDOR_ID_PDC 0x15e9 +#define PCI_VENDOR_ID_QUICKNET 0x15e2 +#define PCI_DEVICE_ID_QUICKNET_XJ 0x0500 +#define PCI_VENDOR_ID_PDC 0x15e9 #define PCI_VENDOR_ID_FARSITE 0x1619 #define PCI_DEVICE_ID_FARSITE_T2P 0x0400 @@ -2053,6 +2021,8 @@ #define PCI_DEVICE_ID_BCM1250_PCI 0x0001 #define PCI_DEVICE_ID_BCM1250_HT 0x0002 +#define PCI_VENDOR_ID_ATHEROS 0x168c + #define PCI_VENDOR_ID_NETCELL 0x169c #define PCI_DEVICE_ID_REVOLUTION 0x0044 @@ -2091,7 +2061,6 @@ #define PCI_DEVICE_ID_HERC_WIN 0x5732 #define PCI_DEVICE_ID_HERC_UNI 0x5832 - #define PCI_VENDOR_ID_SITECOM 0x182d #define PCI_DEVICE_ID_SITECOM_DC105V2 0x3069 @@ -2127,12 +2096,9 @@ #define PCI_DEVICE_ID_3DLABS_PERMEDIA2 0x0007 #define PCI_DEVICE_ID_3DLABS_PERMEDIA2V 0x0009 - #define PCI_VENDOR_ID_AKS 0x416c #define PCI_DEVICE_ID_AKS_ALADDINCARD 0x0100 - - #define PCI_VENDOR_ID_S3 0x5333 #define PCI_DEVICE_ID_S3_TRIO 0x8811 #define PCI_DEVICE_ID_S3_868 0x8880 @@ -2144,7 +2110,6 @@ #define PCI_VENDOR_ID_DUNORD 0x5544 #define PCI_DEVICE_ID_DUNORD_I3000 0x0001 - #define PCI_VENDOR_ID_DCI 0x6666 #define PCI_DEVICE_ID_DCI_PCCOM4 0x0001 #define PCI_DEVICE_ID_DCI_PCCOM8 0x0002 @@ -2388,7 +2353,6 @@ #define PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN 0x0500 #define PCI_DEVICE_ID_ADAPTEC2_SCAMP 0x0503 - #define PCI_VENDOR_ID_HOLTEK 0x9412 #define PCI_DEVICE_ID_HOLTEK_6565 0x6565 @@ -2404,6 +2368,8 @@ #define PCI_DEVICE_ID_NETMOS_9845 0x9845 #define PCI_DEVICE_ID_NETMOS_9855 0x9855 +#define PCI_VENDOR_ID_3COM_2 0xa727 + #define PCI_SUBVENDOR_ID_EXSYS 0xd84d #define PCI_SUBDEVICE_ID_EXSYS_4014 0x4014 #define PCI_SUBDEVICE_ID_EXSYS_4055 0x4055 @@ -2412,13 +2378,7 @@ #define PCI_DEVICE_ID_TIGERJET_300 0x0001 #define PCI_DEVICE_ID_TIGERJET_100 0x0002 -#define PCI_VENDOR_ID_TTTECH 0x0357 -#define PCI_DEVICE_ID_TTTECH_MC322 0x000A - #define PCI_VENDOR_ID_XILINX_RME 0xea60 #define PCI_DEVICE_ID_RME_DIGI32 0x9896 #define PCI_DEVICE_ID_RME_DIGI32_PRO 0x9897 #define PCI_DEVICE_ID_RME_DIGI32_8 0x9898 - -#define PCI_VENDOR_ID_QUICKNET 0x15E2 -#define PCI_DEVICE_ID_QUICKNET_XJ 0x0500 diff --git a/include/linux/percpu.h b/include/linux/percpu.h index b72be2f79e6a..926adaae0f96 100644 --- a/include/linux/percpu.h +++ b/include/linux/percpu.h @@ -1,7 +1,7 @@ #ifndef __LINUX_PERCPU_H #define __LINUX_PERCPU_H -#include <linux/spinlock.h> /* For preempt_disable() */ +#include <linux/preempt.h> #include <linux/slab.h> /* For kmalloc() */ #include <linux/smp.h> #include <linux/string.h> /* For memset() */ diff --git a/include/linux/percpu_counter.h b/include/linux/percpu_counter.h index f5aa593ccf32..3d9f70972cdf 100644 --- a/include/linux/percpu_counter.h +++ b/include/linux/percpu_counter.h @@ -8,6 +8,7 @@ #include <linux/spinlock.h> #include <linux/smp.h> +#include <linux/list.h> #include <linux/threads.h> #include <linux/percpu.h> #include <linux/types.h> @@ -17,6 +18,9 @@ struct percpu_counter { spinlock_t lock; s64 count; +#ifdef CONFIG_HOTPLUG_CPU + struct list_head list; /* All percpu_counters are on a list */ +#endif s32 *counters; }; @@ -26,18 +30,8 @@ struct percpu_counter { #define FBC_BATCH (NR_CPUS*4) #endif -static inline void percpu_counter_init(struct percpu_counter *fbc, s64 amount) -{ - spin_lock_init(&fbc->lock); - fbc->count = amount; - fbc->counters = alloc_percpu(s32); -} - -static inline void percpu_counter_destroy(struct percpu_counter *fbc) -{ - free_percpu(fbc->counters); -} - +void percpu_counter_init(struct percpu_counter *fbc, s64 amount); +void percpu_counter_destroy(struct percpu_counter *fbc); void percpu_counter_mod(struct percpu_counter *fbc, s32 amount); s64 percpu_counter_sum(struct percpu_counter *fbc); diff --git a/include/linux/pid_namespace.h b/include/linux/pid_namespace.h index 169c6c24209b..b9a17e08ff0f 100644 --- a/include/linux/pid_namespace.h +++ b/include/linux/pid_namespace.h @@ -29,7 +29,7 @@ static inline void get_pid_ns(struct pid_namespace *ns) kref_get(&ns->kref); } -extern struct pid_namespace *copy_pid_ns(int flags, struct pid_namespace *ns); +extern struct pid_namespace *copy_pid_ns(unsigned long flags, struct pid_namespace *ns); extern void free_pid_ns(struct kref *kref); static inline void put_pid_ns(struct pid_namespace *ns) diff --git a/include/linux/pkt_cls.h b/include/linux/pkt_cls.h index c3f01b3085a4..30b8571e6b34 100644 --- a/include/linux/pkt_cls.h +++ b/include/linux/pkt_cls.h @@ -403,16 +403,13 @@ enum * 1..32767 Reserved for ematches inside kernel tree * 32768..65535 Free to use, not reliable */ -enum -{ - TCF_EM_CONTAINER, - TCF_EM_CMP, - TCF_EM_NBYTE, - TCF_EM_U32, - TCF_EM_META, - TCF_EM_TEXT, - __TCF_EM_MAX -}; +#define TCF_EM_CONTAINER 0 +#define TCF_EM_CMP 1 +#define TCF_EM_NBYTE 2 +#define TCF_EM_U32 3 +#define TCF_EM_META 4 +#define TCF_EM_TEXT 5 +#define TCF_EM_MAX 5 enum { diff --git a/include/linux/pkt_sched.h b/include/linux/pkt_sched.h index d10f35338507..268c51599eb8 100644 --- a/include/linux/pkt_sched.h +++ b/include/linux/pkt_sched.h @@ -101,6 +101,15 @@ struct tc_prio_qopt __u8 priomap[TC_PRIO_MAX+1]; /* Map: logical priority -> PRIO band */ }; +enum +{ + TCA_PRIO_UNSPEC, + TCA_PRIO_MQ, + __TCA_PRIO_MAX +}; + +#define TCA_PRIO_MAX (__TCA_PRIO_MAX - 1) + /* TBF section */ struct tc_tbf_qopt diff --git a/include/linux/pm.h b/include/linux/pm.h index b2c4fde4e994..273781c82e4d 100644 --- a/include/linux/pm.h +++ b/include/linux/pm.h @@ -267,15 +267,10 @@ struct dev_pm_info { unsigned can_wakeup:1; #ifdef CONFIG_PM unsigned should_wakeup:1; - pm_message_t prev_state; - void * saved_state; - struct device * pm_parent; struct list_head entry; #endif }; -extern void device_pm_set_parent(struct device * dev, struct device * parent); - extern int device_power_down(pm_message_t state); extern void device_power_up(void); extern void device_resume(void); diff --git a/include/linux/prctl.h b/include/linux/prctl.h index 52a9be41250d..e2eff9079fe9 100644 --- a/include/linux/prctl.h +++ b/include/linux/prctl.h @@ -59,4 +59,8 @@ # define PR_ENDIAN_LITTLE 1 /* True little endian mode */ # define PR_ENDIAN_PPC_LITTLE 2 /* "PowerPC" pseudo little endian */ +/* Get/set process seccomp mode */ +#define PR_GET_SECCOMP 21 +#define PR_SET_SECCOMP 22 + #endif /* _LINUX_PRCTL_H */ diff --git a/include/linux/prefetch.h b/include/linux/prefetch.h index fc86f274147f..1adfe668d031 100644 --- a/include/linux/prefetch.h +++ b/include/linux/prefetch.h @@ -27,7 +27,7 @@ prefetch(x) - prefetches the cacheline at "x" for read prefetchw(x) - prefetches the cacheline at "x" for write - spin_lock_prefetch(x) - prefectches the spinlock *x for taking + spin_lock_prefetch(x) - prefetches the spinlock *x for taking there is also PREFETCH_STRIDE which is the architecure-prefered "lookahead" size for prefetching streamed operations. diff --git a/include/linux/proc_fs.h b/include/linux/proc_fs.h index 3469f96bc8b2..28e3664fdf1b 100644 --- a/include/linux/proc_fs.h +++ b/include/linux/proc_fs.h @@ -7,6 +7,8 @@ #include <linux/magic.h> #include <asm/atomic.h> +struct completion; + /* * The proc filesystem constants/structures */ @@ -56,6 +58,14 @@ struct proc_dir_entry { gid_t gid; loff_t size; const struct inode_operations *proc_iops; + /* + * NULL ->proc_fops means "PDE is going away RSN" or + * "PDE is just created". In either case, e.g. ->read_proc won't be + * called because it's too late or too early, respectively. + * + * If you're allocating ->proc_fops dynamically, save a pointer + * somewhere. + */ const struct file_operations *proc_fops; get_info_t *get_info; struct module *owner; @@ -66,6 +76,9 @@ struct proc_dir_entry { atomic_t count; /* use count */ int deleted; /* delete flag */ void *set; + int pde_users; /* number of callers into module in progress */ + spinlock_t pde_unload_lock; /* proc_fops checks and pde_users bumps */ + struct completion *pde_unload_completion; }; struct kcore_list { diff --git a/include/linux/raid/raid5.h b/include/linux/raid/raid5.h index d8286db60b96..93678f57ccbe 100644 --- a/include/linux/raid/raid5.h +++ b/include/linux/raid/raid5.h @@ -116,13 +116,46 @@ * attach a request to an active stripe (add_stripe_bh()) * lockdev attach-buffer unlockdev * handle a stripe (handle_stripe()) - * lockstripe clrSTRIPE_HANDLE ... (lockdev check-buffers unlockdev) .. change-state .. record io needed unlockstripe schedule io + * lockstripe clrSTRIPE_HANDLE ... + * (lockdev check-buffers unlockdev) .. + * change-state .. + * record io/ops needed unlockstripe schedule io/ops * release an active stripe (release_stripe()) * lockdev if (!--cnt) { if STRIPE_HANDLE, add to handle_list else add to inactive-list } unlockdev * * The refcount counts each thread that have activated the stripe, * plus raid5d if it is handling it, plus one for each active request - * on a cached buffer. + * on a cached buffer, and plus one if the stripe is undergoing stripe + * operations. + * + * Stripe operations are performed outside the stripe lock, + * the stripe operations are: + * -copying data between the stripe cache and user application buffers + * -computing blocks to save a disk access, or to recover a missing block + * -updating the parity on a write operation (reconstruct write and + * read-modify-write) + * -checking parity correctness + * -running i/o to disk + * These operations are carried out by raid5_run_ops which uses the async_tx + * api to (optionally) offload operations to dedicated hardware engines. + * When requesting an operation handle_stripe sets the pending bit for the + * operation and increments the count. raid5_run_ops is then run whenever + * the count is non-zero. + * There are some critical dependencies between the operations that prevent some + * from being requested while another is in flight. + * 1/ Parity check operations destroy the in cache version of the parity block, + * so we prevent parity dependent operations like writes and compute_blocks + * from starting while a check is in progress. Some dma engines can perform + * the check without damaging the parity block, in these cases the parity + * block is re-marked up to date (assuming the check was successful) and is + * not re-read from disk. + * 2/ When a write operation is requested we immediately lock the affected + * blocks, and mark them as not up to date. This causes new read requests + * to be held off, as well as parity checks and compute block operations. + * 3/ Once a compute block operation has been requested handle_stripe treats + * that block as if it is up to date. raid5_run_ops guaruntees that any + * operation that is dependent on the compute block result is initiated after + * the compute block completes. */ struct stripe_head { @@ -136,15 +169,46 @@ struct stripe_head { spinlock_t lock; int bm_seq; /* sequence number for bitmap flushes */ int disks; /* disks in stripe */ + /* stripe_operations + * @pending - pending ops flags (set for request->issue->complete) + * @ack - submitted ops flags (set for issue->complete) + * @complete - completed ops flags (set for complete) + * @target - STRIPE_OP_COMPUTE_BLK target + * @count - raid5_runs_ops is set to run when this is non-zero + */ + struct stripe_operations { + unsigned long pending; + unsigned long ack; + unsigned long complete; + int target; + int count; + u32 zero_sum_result; + } ops; struct r5dev { struct bio req; struct bio_vec vec; struct page *page; - struct bio *toread, *towrite, *written; + struct bio *toread, *read, *towrite, *written; sector_t sector; /* sector of this page */ unsigned long flags; } dev[1]; /* allocated with extra space depending of RAID geometry */ }; + +/* stripe_head_state - collects and tracks the dynamic state of a stripe_head + * for handle_stripe. It is only valid under spin_lock(sh->lock); + */ +struct stripe_head_state { + int syncing, expanding, expanded; + int locked, uptodate, to_read, to_write, failed, written; + int to_fill, compute, req_compute, non_overwrite; + int failed_num; +}; + +/* r6_state - extra state data only relevant to r6 */ +struct r6_state { + int p_failed, q_failed, qd_idx, failed_num[2]; +}; + /* Flags */ #define R5_UPTODATE 0 /* page contains current data */ #define R5_LOCKED 1 /* IO has been submitted on "req" */ @@ -158,6 +222,15 @@ struct stripe_head { #define R5_ReWrite 9 /* have tried to over-write the readerror */ #define R5_Expanded 10 /* This block now has post-expand data */ +#define R5_Wantcompute 11 /* compute_block in progress treat as + * uptodate + */ +#define R5_Wantfill 12 /* dev->toread contains a bio that needs + * filling + */ +#define R5_Wantprexor 13 /* distinguish blocks ready for rmw from + * other "towrites" + */ /* * Write method */ @@ -180,6 +253,24 @@ struct stripe_head { #define STRIPE_EXPAND_SOURCE 10 #define STRIPE_EXPAND_READY 11 /* + * Operations flags (in issue order) + */ +#define STRIPE_OP_BIOFILL 0 +#define STRIPE_OP_COMPUTE_BLK 1 +#define STRIPE_OP_PREXOR 2 +#define STRIPE_OP_BIODRAIN 3 +#define STRIPE_OP_POSTXOR 4 +#define STRIPE_OP_CHECK 5 +#define STRIPE_OP_IO 6 + +/* modifiers to the base operations + * STRIPE_OP_MOD_REPAIR_PD - compute the parity block and write it back + * STRIPE_OP_MOD_DMA_CHECK - parity is not corrupted by the check + */ +#define STRIPE_OP_MOD_REPAIR_PD 7 +#define STRIPE_OP_MOD_DMA_CHECK 8 + +/* * Plugging: * * To improve write throughput, we need to delay the handling of some diff --git a/include/linux/raid/xor.h b/include/linux/raid/xor.h index f0d67cbdea40..3e120587eada 100644 --- a/include/linux/raid/xor.h +++ b/include/linux/raid/xor.h @@ -3,9 +3,10 @@ #include <linux/raid/md.h> -#define MAX_XOR_BLOCKS 5 +#define MAX_XOR_BLOCKS 4 -extern void xor_block(unsigned int count, unsigned int bytes, void **ptr); +extern void xor_blocks(unsigned int count, unsigned int bytes, + void *dest, void **srcs); struct xor_block_template { struct xor_block_template *next; diff --git a/include/linux/rtnetlink.h b/include/linux/rtnetlink.h index 1fae30af91f3..c91476ce314a 100644 --- a/include/linux/rtnetlink.h +++ b/include/linux/rtnetlink.h @@ -261,7 +261,7 @@ enum rtattr_type_t RTA_FLOW, RTA_CACHEINFO, RTA_SESSION, - RTA_MP_ALGO, + RTA_MP_ALGO, /* no longer used */ RTA_TABLE, __RTA_MAX }; @@ -570,10 +570,16 @@ static __inline__ int rtattr_strcmp(const struct rtattr *rta, const char *str) } extern int rtattr_parse(struct rtattr *tb[], int maxattr, struct rtattr *rta, int len); +extern int __rtattr_parse_nested_compat(struct rtattr *tb[], int maxattr, + struct rtattr *rta, int len); #define rtattr_parse_nested(tb, max, rta) \ rtattr_parse((tb), (max), RTA_DATA((rta)), RTA_PAYLOAD((rta))) +#define rtattr_parse_nested_compat(tb, max, rta, data, len) \ +({ data = RTA_PAYLOAD(rta) >= len ? RTA_DATA(rta) : NULL; \ + __rtattr_parse_nested_compat(tb, max, rta, len); }) + extern int rtnetlink_send(struct sk_buff *skb, u32 pid, u32 group, int echo); extern int rtnl_unicast(struct sk_buff *skb, u32 pid); extern int rtnl_notify(struct sk_buff *skb, u32 pid, u32 group, @@ -638,6 +644,18 @@ extern void __rta_fill(struct sk_buff *skb, int attrtype, int attrlen, const voi ({ (start)->rta_len = skb_tail_pointer(skb) - (unsigned char *)(start); \ (skb)->len; }) +#define RTA_NEST_COMPAT(skb, type, attrlen, data) \ +({ struct rtattr *__start = (struct rtattr *)skb_tail_pointer(skb); \ + RTA_PUT(skb, type, attrlen, data); \ + RTA_NEST(skb, type); \ + __start; }) + +#define RTA_NEST_COMPAT_END(skb, start) \ +({ struct rtattr *__nest = (void *)(start) + NLMSG_ALIGN((start)->rta_len); \ + (start)->rta_len = skb_tail_pointer(skb) - (unsigned char *)(start); \ + RTA_NEST_END(skb, __nest); \ + (skb)->len; }) + #define RTA_NEST_CANCEL(skb, start) \ ({ if (start) \ skb_trim(skb, (unsigned char *) (start) - (skb)->data); \ diff --git a/include/linux/sched.h b/include/linux/sched.h index cfb680585ab8..731edaca8ffd 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -26,6 +26,7 @@ #define CLONE_STOPPED 0x02000000 /* Start in stopped state */ #define CLONE_NEWUTS 0x04000000 /* New utsname group? */ #define CLONE_NEWIPC 0x08000000 /* New ipcs */ +#define CLONE_NEWUSER 0x10000000 /* New user namespace */ /* * Scheduling policies @@ -287,6 +288,7 @@ extern signed long schedule_timeout_uninterruptible(signed long timeout); asmlinkage void schedule(void); struct nsproxy; +struct user_namespace; /* Maximum number of active map areas.. This is a random (large) number */ #define DEFAULT_MAX_MAP_COUNT 65536 @@ -529,6 +531,10 @@ struct signal_struct { #ifdef CONFIG_TASKSTATS struct taskstats *stats; #endif +#ifdef CONFIG_AUDIT + unsigned audit_tty; + struct tty_audit_buf *tty_audit_buf; +#endif }; /* Context switch must be unlocked if interrupts are to be enabled */ @@ -972,7 +978,8 @@ struct task_struct { unsigned int rt_priority; cputime_t utime, stime; unsigned long nvcsw, nivcsw; /* context switch counts */ - struct timespec start_time; + struct timespec start_time; /* monotonic time */ + struct timespec real_start_time; /* boot based time */ /* mm fault and swap info: this can arguably be seen as either mm-specific or thread-specific */ unsigned long min_flt, maj_flt; @@ -1403,7 +1410,7 @@ extern struct task_struct *find_task_by_pid_type(int type, int pid); extern void __set_special_pids(pid_t session, pid_t pgrp); /* per-UID process charging. */ -extern struct user_struct * alloc_uid(uid_t); +extern struct user_struct * alloc_uid(struct user_namespace *, uid_t); static inline struct user_struct *get_uid(struct user_struct *u) { atomic_inc(&u->__count); diff --git a/include/linux/screen_info.h b/include/linux/screen_info.h index b02308ee7667..3ee412bc00ec 100644 --- a/include/linux/screen_info.h +++ b/include/linux/screen_info.h @@ -10,7 +10,7 @@ struct screen_info { u8 orig_x; /* 0x00 */ u8 orig_y; /* 0x01 */ - u16 dontuse1; /* 0x02 -- EXT_MEM_K sits here */ + u16 ext_mem_k; /* 0x02 */ u16 orig_video_page; /* 0x04 */ u8 orig_video_mode; /* 0x06 */ u8 orig_video_cols; /* 0x07 */ @@ -27,7 +27,7 @@ struct screen_info { u16 lfb_depth; /* 0x16 */ u32 lfb_base; /* 0x18 */ u32 lfb_size; /* 0x1c */ - u16 dontuse2, dontuse3; /* 0x20 -- CL_MAGIC and CL_OFFSET here */ + u16 cl_magic, cl_offset; /* 0x20 */ u16 lfb_linelength; /* 0x24 */ u8 red_size; /* 0x26 */ u8 red_pos; /* 0x27 */ @@ -42,9 +42,8 @@ struct screen_info { u16 pages; /* 0x32 */ u16 vesa_attributes; /* 0x34 */ u32 capabilities; /* 0x36 */ - /* 0x3a -- 0x3b reserved for future expansion */ - /* 0x3c -- 0x3f micro stack for relocatable kernels */ -}; + u8 _reserved[6]; /* 0x3a */ +} __attribute__((packed)); extern struct screen_info screen_info; diff --git a/include/linux/scx200_gpio.h b/include/linux/scx200_gpio.h index 1a82d30c4b17..d2b058130eb1 100644 --- a/include/linux/scx200_gpio.h +++ b/include/linux/scx200_gpio.h @@ -1,5 +1,3 @@ -#include <linux/spinlock.h> - u32 scx200_gpio_configure(unsigned index, u32 set, u32 clear); extern unsigned scx200_gpio_base; diff --git a/include/linux/seccomp.h b/include/linux/seccomp.h index 3e8b1cf54303..262a8dccfa81 100644 --- a/include/linux/seccomp.h +++ b/include/linux/seccomp.h @@ -4,8 +4,6 @@ #ifdef CONFIG_SECCOMP -#define NR_SECCOMP_MODES 1 - #include <linux/thread_info.h> #include <asm/seccomp.h> @@ -18,20 +16,23 @@ static inline void secure_computing(int this_syscall) __secure_computing(this_syscall); } -static inline int has_secure_computing(struct thread_info *ti) -{ - return unlikely(test_ti_thread_flag(ti, TIF_SECCOMP)); -} +extern long prctl_get_seccomp(void); +extern long prctl_set_seccomp(unsigned long); #else /* CONFIG_SECCOMP */ typedef struct { } seccomp_t; #define secure_computing(x) do { } while (0) -/* static inline to preserve typechecking */ -static inline int has_secure_computing(struct thread_info *ti) + +static inline long prctl_get_seccomp(void) +{ + return -EINVAL; +} + +static inline long prctl_set_seccomp(unsigned long arg2) { - return 0; + return -EINVAL; } #endif /* CONFIG_SECCOMP */ diff --git a/include/linux/security.h b/include/linux/security.h index 9eb9e0fe0331..c11dc8aa0351 100644 --- a/include/linux/security.h +++ b/include/linux/security.h @@ -71,6 +71,7 @@ struct xfrm_user_sec_ctx; extern int cap_netlink_send(struct sock *sk, struct sk_buff *skb); extern int cap_netlink_recv(struct sk_buff *skb, int cap); +extern unsigned long mmap_min_addr; /* * Values used in the task_security_ops calls */ @@ -1241,8 +1242,9 @@ struct security_operations { int (*file_ioctl) (struct file * file, unsigned int cmd, unsigned long arg); int (*file_mmap) (struct file * file, - unsigned long reqprot, - unsigned long prot, unsigned long flags); + unsigned long reqprot, unsigned long prot, + unsigned long flags, unsigned long addr, + unsigned long addr_only); int (*file_mprotect) (struct vm_area_struct * vma, unsigned long reqprot, unsigned long prot); @@ -1814,9 +1816,12 @@ static inline int security_file_ioctl (struct file *file, unsigned int cmd, static inline int security_file_mmap (struct file *file, unsigned long reqprot, unsigned long prot, - unsigned long flags) + unsigned long flags, + unsigned long addr, + unsigned long addr_only) { - return security_ops->file_mmap (file, reqprot, prot, flags); + return security_ops->file_mmap (file, reqprot, prot, flags, addr, + addr_only); } static inline int security_file_mprotect (struct vm_area_struct *vma, @@ -2489,7 +2494,9 @@ static inline int security_file_ioctl (struct file *file, unsigned int cmd, static inline int security_file_mmap (struct file *file, unsigned long reqprot, unsigned long prot, - unsigned long flags) + unsigned long flags, + unsigned long addr, + unsigned long addr_only) { return 0; } diff --git a/include/linux/seq_file.h b/include/linux/seq_file.h index 3e3cccbb1cac..83783ab0f552 100644 --- a/include/linux/seq_file.h +++ b/include/linux/seq_file.h @@ -50,5 +50,16 @@ int seq_release_private(struct inode *, struct file *); #define SEQ_START_TOKEN ((void *)1) +/* + * Helpers for iteration over list_head-s in seq_files + */ + +extern struct list_head *seq_list_start(struct list_head *head, + loff_t pos); +extern struct list_head *seq_list_start_head(struct list_head *head, + loff_t pos); +extern struct list_head *seq_list_next(void *v, struct list_head *head, + loff_t *ppos); + #endif #endif diff --git a/include/linux/serial.h b/include/linux/serial.h index 33fc8cb8ddfb..deb714314fb1 100644 --- a/include/linux/serial.h +++ b/include/linux/serial.h @@ -177,11 +177,5 @@ struct serial_icounter_struct { #ifdef __KERNEL__ #include <linux/compiler.h> -/* Allow architectures to override entries in serial8250_ports[] at run time: */ -struct uart_port; /* forward declaration */ -extern int early_serial_setup(struct uart_port *port); -extern int early_serial_console_init(char *options); -extern int serial8250_start_console(struct uart_port *port, char *options); - #endif /* __KERNEL__ */ #endif /* _LINUX_SERIAL_H */ diff --git a/include/linux/serial_8250.h b/include/linux/serial_8250.h index 71310d80c09a..706ee9a4c80c 100644 --- a/include/linux/serial_8250.h +++ b/include/linux/serial_8250.h @@ -60,4 +60,8 @@ void serial8250_unregister_port(int line); void serial8250_suspend_port(int line); void serial8250_resume_port(int line); +extern int serial8250_find_port(struct uart_port *p); +extern int serial8250_find_port_for_earlycon(void); +extern int setup_early_serial8250_console(char *cmdline); + #endif diff --git a/include/linux/serio.h b/include/linux/serio.h index 1ebf0455e224..d9377ce9ffd1 100644 --- a/include/linux/serio.h +++ b/include/linux/serio.h @@ -209,5 +209,6 @@ static inline void serio_unpin_driver(struct serio *serio) #define SERIO_PENMOUNT 0x31 #define SERIO_TOUCHRIGHT 0x32 #define SERIO_TOUCHWIN 0x33 +#define SERIO_TAOSEVM 0x34 #endif diff --git a/include/linux/signal.h b/include/linux/signal.h index 9a5eac508e5e..ea91abe740da 100644 --- a/include/linux/signal.h +++ b/include/linux/signal.h @@ -6,7 +6,6 @@ #ifdef __KERNEL__ #include <linux/list.h> -#include <linux/spinlock.h> /* * Real Time signals may be queued. diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h index 6f0b2f7d0010..ce256438e619 100644 --- a/include/linux/skbuff.h +++ b/include/linux/skbuff.h @@ -65,13 +65,20 @@ * is able to produce some skb->csum, it MUST use COMPLETE, * not UNNECESSARY. * + * PARTIAL: identical to the case for output below. This may occur + * on a packet received directly from another Linux OS, e.g., + * a virtualised Linux kernel on the same host. The packet can + * be treated in the same way as UNNECESSARY except that on + * output (i.e., forwarding) the checksum must be filled in + * by the OS or the hardware. + * * B. Checksumming on output. * * NONE: skb is checksummed by protocol or csum is not required. * * PARTIAL: device is required to csum packet as seen by hard_start_xmit - * from skb->transport_header to the end and to record the checksum - * at skb->transport_header + skb->csum. + * from skb->csum_start to the end and to record the checksum + * at skb->csum_start + skb->csum_offset. * * Device must show its capabilities in dev->features, set * at device setup time. @@ -82,6 +89,7 @@ * TCP/UDP over IPv4. Sigh. Vendors like this * way by an unknown reason. Though, see comment above * about CHECKSUM_UNNECESSARY. 8) + * NETIF_F_IPV6_CSUM about as dumb as the last one but does IPv6 instead. * * Any questions? No questions, good. --ANK */ @@ -147,8 +155,8 @@ struct skb_shared_info { /* We divide dataref into two halves. The higher 16 bits hold references * to the payload part of skb->data. The lower 16 bits hold references to - * the entire skb->data. It is up to the users of the skb to agree on - * where the payload starts. + * the entire skb->data. A clone of a headerless skb holds the length of + * the header in skb->hdr_len. * * All users must obey the rule that the skb->data reference count must be * greater than or equal to the payload reference count. @@ -196,7 +204,6 @@ typedef unsigned char *sk_buff_data_t; * @sk: Socket we are owned by * @tstamp: Time we arrived * @dev: Device we arrived on/are leaving by - * @iif: ifindex of device we arrived on * @transport_header: Transport layer header * @network_header: Network layer header * @mac_header: Link layer header @@ -206,6 +213,7 @@ typedef unsigned char *sk_buff_data_t; * @len: Length of actual data * @data_len: Data length * @mac_len: Length of link layer header + * @hdr_len: writable header length of cloned skb * @csum: Checksum (must include start/offset pair) * @csum_start: Offset from skb->head where checksumming should start * @csum_offset: Offset from csum_start where checksum should be stored @@ -227,9 +235,12 @@ typedef unsigned char *sk_buff_data_t; * @mark: Generic packet mark * @nfct: Associated connection, if any * @ipvs_property: skbuff is owned by ipvs + * @nf_trace: netfilter packet trace flag * @nfctinfo: Relationship of this skb to the connection * @nfct_reasm: netfilter conntrack re-assembly pointer * @nf_bridge: Saved data about a bridged frame - see br_netfilter.c + * @iif: ifindex of device we arrived on + * @queue_mapping: Queue mapping for multiqueue devices * @tc_index: Traffic control index * @tc_verd: traffic control verdict * @dma_cookie: a cookie to one of several possible DMA operations @@ -245,8 +256,6 @@ struct sk_buff { struct sock *sk; ktime_t tstamp; struct net_device *dev; - int iif; - /* 4 byte hole on 64 bit*/ struct dst_entry *dst; struct sec_path *sp; @@ -260,8 +269,9 @@ struct sk_buff { char cb[48]; unsigned int len, - data_len, - mac_len; + data_len; + __u16 mac_len, + hdr_len; union { __wsum csum; struct { @@ -277,7 +287,8 @@ struct sk_buff { nfctinfo:3; __u8 pkt_type:3, fclone:2, - ipvs_property:1; + ipvs_property:1, + nf_trace:1; __be16 protocol; void (*destructor)(struct sk_buff *skb); @@ -288,12 +299,18 @@ struct sk_buff { #ifdef CONFIG_BRIDGE_NETFILTER struct nf_bridge_info *nf_bridge; #endif + + int iif; + __u16 queue_mapping; + #ifdef CONFIG_NET_SCHED __u16 tc_index; /* traffic control index */ #ifdef CONFIG_NET_CLS_ACT __u16 tc_verd; /* traffic control verdict */ #endif #endif + /* 2 byte hole */ + #ifdef CONFIG_NET_DMA dma_cookie_t dma_cookie; #endif @@ -1322,6 +1339,20 @@ static inline struct sk_buff *netdev_alloc_skb(struct net_device *dev, } /** + * skb_clone_writable - is the header of a clone writable + * @skb: buffer to check + * @len: length up to which to write + * + * Returns true if modifying the header part of the cloned buffer + * does not requires the data to be copied. + */ +static inline int skb_clone_writable(struct sk_buff *skb, int len) +{ + return !skb_header_cloned(skb) && + skb_headroom(skb) + len <= skb->hdr_len; +} + +/** * skb_cow - copy header of skb when it is required * @skb: buffer to cow * @headroom: needed headroom @@ -1608,7 +1639,7 @@ static inline int skb_csum_unnecessary(const struct sk_buff *skb) * if skb->ip_summed is CHECKSUM_UNNECESSARY which indicates that the * hardware has already verified the correctness of the checksum. */ -static inline unsigned int skb_checksum_complete(struct sk_buff *skb) +static inline __sum16 skb_checksum_complete(struct sk_buff *skb) { return skb_csum_unnecessary(skb) ? 0 : __skb_checksum_complete(skb); @@ -1709,6 +1740,20 @@ static inline void skb_init_secmark(struct sk_buff *skb) { } #endif +static inline void skb_set_queue_mapping(struct sk_buff *skb, u16 queue_mapping) +{ +#ifdef CONFIG_NETDEVICES_MULTIQUEUE + skb->queue_mapping = queue_mapping; +#endif +} + +static inline void skb_copy_queue_mapping(struct sk_buff *to, const struct sk_buff *from) +{ +#ifdef CONFIG_NETDEVICES_MULTIQUEUE + to->queue_mapping = from->queue_mapping; +#endif +} + static inline int skb_is_gso(const struct sk_buff *skb) { return skb_shinfo(skb)->gso_size; diff --git a/include/linux/slab.h b/include/linux/slab.h index cebcd3833c76..27402fea9b79 100644 --- a/include/linux/slab.h +++ b/include/linux/slab.h @@ -14,8 +14,6 @@ #include <linux/gfp.h> #include <linux/types.h> -typedef struct kmem_cache kmem_cache_t __deprecated; - /* * Flags to pass to kmem_cache_create(). * The ones marked DEBUG are only valid if CONFIG_SLAB_DEBUG is set. @@ -44,7 +42,6 @@ struct kmem_cache *kmem_cache_create(const char *, size_t, size_t, void (*)(void *, struct kmem_cache *, unsigned long)); void kmem_cache_destroy(struct kmem_cache *); int kmem_cache_shrink(struct kmem_cache *); -void *kmem_cache_alloc(struct kmem_cache *, gfp_t); void *kmem_cache_zalloc(struct kmem_cache *, gfp_t); void kmem_cache_free(struct kmem_cache *, void *); unsigned int kmem_cache_size(struct kmem_cache *); @@ -63,16 +60,6 @@ int kmem_ptr_validate(struct kmem_cache *cachep, const void *ptr); sizeof(struct __struct), __alignof__(struct __struct),\ (__flags), NULL, NULL) -#ifdef CONFIG_NUMA -extern void *kmem_cache_alloc_node(struct kmem_cache *, gfp_t flags, int node); -#else -static inline void *kmem_cache_alloc_node(struct kmem_cache *cachep, - gfp_t flags, int node) -{ - return kmem_cache_alloc(cachep, flags); -} -#endif - /* * The largest kmalloc size supported by the slab allocators is * 32 megabyte (2^25) or the maximum allocatable page order if that is @@ -91,7 +78,6 @@ static inline void *kmem_cache_alloc_node(struct kmem_cache *cachep, /* * Common kmalloc functions provided by all allocators */ -void *__kmalloc(size_t, gfp_t); void *__kzalloc(size_t, gfp_t); void * __must_check krealloc(const void *, size_t, gfp_t); void kfree(const void *); @@ -102,40 +88,6 @@ size_t ksize(const void *); * @n: number of elements. * @size: element size. * @flags: the type of memory to allocate. - */ -static inline void *kcalloc(size_t n, size_t size, gfp_t flags) -{ - if (n != 0 && size > ULONG_MAX / n) - return NULL; - return __kzalloc(n * size, flags); -} - -/* - * Allocator specific definitions. These are mainly used to establish optimized - * ways to convert kmalloc() calls to kmem_cache_alloc() invocations by selecting - * the appropriate general cache at compile time. - */ - -#if defined(CONFIG_SLAB) || defined(CONFIG_SLUB) -#ifdef CONFIG_SLUB -#include <linux/slub_def.h> -#else -#include <linux/slab_def.h> -#endif /* !CONFIG_SLUB */ -#else - -/* - * Fallback definitions for an allocator not wanting to provide - * its own optimized kmalloc definitions (like SLOB). - */ - -/** - * kmalloc - allocate memory - * @size: how many bytes of memory are required. - * @flags: the type of memory to allocate. - * - * kmalloc is the normal method of allocating memory - * in the kernel. * * The @flags argument may be one of: * @@ -143,7 +95,7 @@ static inline void *kcalloc(size_t n, size_t size, gfp_t flags) * * %GFP_KERNEL - Allocate normal kernel ram. May sleep. * - * %GFP_ATOMIC - Allocation will not sleep. + * %GFP_ATOMIC - Allocation will not sleep. May use emergency pools. * For example, use this inside interrupt handlers. * * %GFP_HIGHUSER - Allocate pages from high memory. @@ -152,18 +104,22 @@ static inline void *kcalloc(size_t n, size_t size, gfp_t flags) * * %GFP_NOFS - Do not make any fs calls while trying to get memory. * + * %GFP_NOWAIT - Allocation will not sleep. + * + * %GFP_THISNODE - Allocate node-local memory only. + * + * %GFP_DMA - Allocation suitable for DMA. + * Should only be used for kmalloc() caches. Otherwise, use a + * slab created with SLAB_DMA. + * * Also it is possible to set different flags by OR'ing * in one or more of the following additional @flags: * * %__GFP_COLD - Request cache-cold pages instead of * trying to return cache-warm pages. * - * %__GFP_DMA - Request memory from the DMA-capable zone. - * * %__GFP_HIGH - This allocation has high priority and may use emergency pools. * - * %__GFP_HIGHMEM - Allocated memory may be from highmem. - * * %__GFP_NOFAIL - Indicate that this allocation is in no way allowed to fail * (think twice before using). * @@ -173,24 +129,57 @@ static inline void *kcalloc(size_t n, size_t size, gfp_t flags) * %__GFP_NOWARN - If allocation fails, don't issue any warnings. * * %__GFP_REPEAT - If allocation fails initially, try once more before failing. + * + * There are other flags available as well, but these are not intended + * for general use, and so are not documented here. For a full list of + * potential flags, always refer to linux/gfp.h. */ -static inline void *kmalloc(size_t size, gfp_t flags) +static inline void *kcalloc(size_t n, size_t size, gfp_t flags) { - return __kmalloc(size, flags); + if (n != 0 && size > ULONG_MAX / n) + return NULL; + return __kzalloc(n * size, flags); } -/** - * kzalloc - allocate memory. The memory is set to zero. - * @size: how many bytes of memory are required. - * @flags: the type of memory to allocate (see kmalloc). +/* + * Allocator specific definitions. These are mainly used to establish optimized + * ways to convert kmalloc() calls to kmem_cache_alloc() invocations by + * selecting the appropriate general cache at compile time. + * + * Allocators must define at least: + * + * kmem_cache_alloc() + * __kmalloc() + * kmalloc() + * kzalloc() + * + * Those wishing to support NUMA must also define: + * + * kmem_cache_alloc_node() + * kmalloc_node() + * + * See each allocator definition file for additional comments and + * implementation notes. */ -static inline void *kzalloc(size_t size, gfp_t flags) -{ - return __kzalloc(size, flags); -} +#ifdef CONFIG_SLUB +#include <linux/slub_def.h> +#elif defined(CONFIG_SLOB) +#include <linux/slob_def.h> +#else +#include <linux/slab_def.h> #endif -#ifndef CONFIG_NUMA +#if !defined(CONFIG_NUMA) && !defined(CONFIG_SLOB) +/** + * kmalloc_node - allocate memory from a specific node + * @size: how many bytes of memory are required. + * @flags: the type of memory to allocate (see kcalloc). + * @node: node to allocate from. + * + * kmalloc() for non-local nodes, used to allocate from a specific node + * if available. Equivalent to kmalloc() in the non-NUMA single-node + * case. + */ static inline void *kmalloc_node(size_t size, gfp_t flags, int node) { return kmalloc(size, flags); @@ -200,7 +189,15 @@ static inline void *__kmalloc_node(size_t size, gfp_t flags, int node) { return __kmalloc(size, flags); } -#endif /* !CONFIG_NUMA */ + +void *kmem_cache_alloc(struct kmem_cache *, gfp_t); + +static inline void *kmem_cache_alloc_node(struct kmem_cache *cachep, + gfp_t flags, int node) +{ + return kmem_cache_alloc(cachep, flags); +} +#endif /* !CONFIG_NUMA && !CONFIG_SLOB */ /* * kmalloc_track_caller is a special version of kmalloc that records the @@ -247,4 +244,3 @@ extern void *__kmalloc_node_track_caller(size_t, gfp_t, int, void *); #endif /* __KERNEL__ */ #endif /* _LINUX_SLAB_H */ - diff --git a/include/linux/slab_def.h b/include/linux/slab_def.h index 8d81a60518e4..365d036c454a 100644 --- a/include/linux/slab_def.h +++ b/include/linux/slab_def.h @@ -25,6 +25,9 @@ struct cache_sizes { }; extern struct cache_sizes malloc_sizes[]; +void *kmem_cache_alloc(struct kmem_cache *, gfp_t); +void *__kmalloc(size_t size, gfp_t flags); + static inline void *kmalloc(size_t size, gfp_t flags) { if (__builtin_constant_p(size)) { @@ -79,6 +82,7 @@ found: #ifdef CONFIG_NUMA extern void *__kmalloc_node(size_t size, gfp_t flags, int node); +extern void *kmem_cache_alloc_node(struct kmem_cache *, gfp_t flags, int node); static inline void *kmalloc_node(size_t size, gfp_t flags, int node) { diff --git a/include/linux/slob_def.h b/include/linux/slob_def.h new file mode 100644 index 000000000000..a2daf2d418a9 --- /dev/null +++ b/include/linux/slob_def.h @@ -0,0 +1,46 @@ +#ifndef __LINUX_SLOB_DEF_H +#define __LINUX_SLOB_DEF_H + +void *kmem_cache_alloc_node(struct kmem_cache *, gfp_t flags, int node); + +static inline void *kmem_cache_alloc(struct kmem_cache *cachep, gfp_t flags) +{ + return kmem_cache_alloc_node(cachep, flags, -1); +} + +void *__kmalloc_node(size_t size, gfp_t flags, int node); + +static inline void *kmalloc_node(size_t size, gfp_t flags, int node) +{ + return __kmalloc_node(size, flags, node); +} + +/** + * kmalloc - allocate memory + * @size: how many bytes of memory are required. + * @flags: the type of memory to allocate (see kcalloc). + * + * kmalloc is the normal method of allocating memory + * in the kernel. + */ +static inline void *kmalloc(size_t size, gfp_t flags) +{ + return __kmalloc_node(size, flags, -1); +} + +static inline void *__kmalloc(size_t size, gfp_t flags) +{ + return kmalloc(size, flags); +} + +/** + * kzalloc - allocate memory. The memory is set to zero. + * @size: how many bytes of memory are required. + * @flags: the type of memory to allocate (see kcalloc). + */ +static inline void *kzalloc(size_t size, gfp_t flags) +{ + return __kzalloc(size, flags); +} + +#endif /* __LINUX_SLOB_DEF_H */ diff --git a/include/linux/slub_def.h b/include/linux/slub_def.h index 6207a3d8da71..a582f6771525 100644 --- a/include/linux/slub_def.h +++ b/include/linux/slub_def.h @@ -171,6 +171,9 @@ static inline struct kmem_cache *kmalloc_slab(size_t size) #define ZERO_SIZE_PTR ((void *)16) +void *kmem_cache_alloc(struct kmem_cache *, gfp_t); +void *__kmalloc(size_t size, gfp_t flags); + static inline void *kmalloc(size_t size, gfp_t flags) { if (__builtin_constant_p(size) && !(flags & SLUB_DMA)) { @@ -198,7 +201,8 @@ static inline void *kzalloc(size_t size, gfp_t flags) } #ifdef CONFIG_NUMA -extern void *__kmalloc_node(size_t size, gfp_t flags, int node); +void *__kmalloc_node(size_t size, gfp_t flags, int node); +void *kmem_cache_alloc_node(struct kmem_cache *, gfp_t flags, int node); static inline void *kmalloc_node(size_t size, gfp_t flags, int node) { diff --git a/include/linux/smp_lock.h b/include/linux/smp_lock.h index cf715a40d833..58962c51dee1 100644 --- a/include/linux/smp_lock.h +++ b/include/linux/smp_lock.h @@ -3,7 +3,6 @@ #ifdef CONFIG_LOCK_KERNEL #include <linux/sched.h> -#include <linux/spinlock.h> #define kernel_locked() (current->lock_depth >= 0) diff --git a/include/linux/socket.h b/include/linux/socket.h index 6e7c9483a6a6..f852e1afd65a 100644 --- a/include/linux/socket.h +++ b/include/linux/socket.h @@ -253,6 +253,9 @@ struct ucred { #define MSG_EOF MSG_FIN +#define MSG_CMSG_CLOEXEC 0x40000000 /* Set close_on_exit for file + descriptor received through + SCM_RIGHTS */ #if defined(CONFIG_COMPAT) #define MSG_CMSG_COMPAT 0x80000000 /* This message needs 32 bit fixups */ #else @@ -287,6 +290,7 @@ struct ucred { #define SOL_NETLINK 270 #define SOL_TIPC 271 #define SOL_RXRPC 272 +#define SOL_PPPOL2TP 273 /* IPX options */ #define IPX_TYPE 1 diff --git a/include/linux/sonypi.h b/include/linux/sonypi.h index 34d4b075f7b8..40c7b5d993b9 100644 --- a/include/linux/sonypi.h +++ b/include/linux/sonypi.h @@ -153,8 +153,6 @@ #define SONYPI_COMMAND_GETCAMERAROMVERSION 18 /* obsolete */ #define SONYPI_COMMAND_GETCAMERAREVISION 19 /* obsolete */ -int sonypi_camera_command(int command, u8 value); - #endif /* __KERNEL__ */ #endif /* _SONYPI_H_ */ diff --git a/include/linux/spinlock.h b/include/linux/spinlock.h index a946176db638..c376f3b36c89 100644 --- a/include/linux/spinlock.h +++ b/include/linux/spinlock.h @@ -282,6 +282,13 @@ do { \ 1 : ({ local_irq_restore(flags); 0; }); \ }) +#define write_trylock_irqsave(lock, flags) \ +({ \ + local_irq_save(flags); \ + write_trylock(lock) ? \ + 1 : ({ local_irq_restore(flags); 0; }); \ +}) + /* * Locks two spinlocks l1 and l2. * l1_first indicates if spinlock l1 should be taken first. diff --git a/include/linux/sunrpc/auth.h b/include/linux/sunrpc/auth.h index 534cdc7be58d..7a69ca3bebaf 100644 --- a/include/linux/sunrpc/auth.h +++ b/include/linux/sunrpc/auth.h @@ -16,6 +16,7 @@ #include <linux/sunrpc/xdr.h> #include <asm/atomic.h> +#include <linux/rcupdate.h> /* size of the nodename buffer */ #define UNX_MAXNODENAME 32 @@ -30,22 +31,28 @@ struct auth_cred { /* * Client user credentials */ +struct rpc_auth; +struct rpc_credops; struct rpc_cred { struct hlist_node cr_hash; /* hash chain */ - struct rpc_credops * cr_ops; - unsigned long cr_expire; /* when to gc */ - atomic_t cr_count; /* ref count */ - unsigned short cr_flags; /* various flags */ + struct list_head cr_lru; /* lru garbage collection */ + struct rcu_head cr_rcu; + struct rpc_auth * cr_auth; + const struct rpc_credops *cr_ops; #ifdef RPC_DEBUG unsigned long cr_magic; /* 0x0f4aa4f0 */ #endif + unsigned long cr_expire; /* when to gc */ + unsigned long cr_flags; /* various flags */ + atomic_t cr_count; /* ref count */ uid_t cr_uid; /* per-flavor data */ }; -#define RPCAUTH_CRED_NEW 0x0001 -#define RPCAUTH_CRED_UPTODATE 0x0002 +#define RPCAUTH_CRED_NEW 0 +#define RPCAUTH_CRED_UPTODATE 1 +#define RPCAUTH_CRED_HASHED 2 #define RPCAUTH_CRED_MAGIC 0x0f4aa4f0 @@ -56,10 +63,10 @@ struct rpc_cred { #define RPC_CREDCACHE_MASK (RPC_CREDCACHE_NR - 1) struct rpc_cred_cache { struct hlist_head hashtable[RPC_CREDCACHE_NR]; - unsigned long nextgc; /* next garbage collection */ - unsigned long expire; /* cache expiry interval */ + spinlock_t lock; }; +struct rpc_authops; struct rpc_auth { unsigned int au_cslack; /* call cred size estimate */ /* guess at number of u32's auth adds before @@ -69,7 +76,7 @@ struct rpc_auth { unsigned int au_verfsize; unsigned int au_flags; /* various flags */ - struct rpc_authops * au_ops; /* operations */ + const struct rpc_authops *au_ops; /* operations */ rpc_authflavor_t au_flavor; /* pseudoflavor (note may * differ from the flavor in * au_ops->au_flavor in gss @@ -115,17 +122,19 @@ struct rpc_credops { void *, __be32 *, void *); }; -extern struct rpc_authops authunix_ops; -extern struct rpc_authops authnull_ops; -#ifdef CONFIG_SUNRPC_SECURE -extern struct rpc_authops authdes_ops; -#endif +extern const struct rpc_authops authunix_ops; +extern const struct rpc_authops authnull_ops; + +void __init rpc_init_authunix(void); +void __init rpcauth_init_module(void); +void __exit rpcauth_remove_module(void); -int rpcauth_register(struct rpc_authops *); -int rpcauth_unregister(struct rpc_authops *); +int rpcauth_register(const struct rpc_authops *); +int rpcauth_unregister(const struct rpc_authops *); struct rpc_auth * rpcauth_create(rpc_authflavor_t, struct rpc_clnt *); -void rpcauth_destroy(struct rpc_auth *); +void rpcauth_release(struct rpc_auth *); struct rpc_cred * rpcauth_lookup_credcache(struct rpc_auth *, struct auth_cred *, int); +void rpcauth_init_cred(struct rpc_cred *, const struct auth_cred *, struct rpc_auth *, const struct rpc_credops *); struct rpc_cred * rpcauth_lookupcred(struct rpc_auth *, int); struct rpc_cred * rpcauth_bindcred(struct rpc_task *); void rpcauth_holdcred(struct rpc_task *); @@ -138,8 +147,9 @@ int rpcauth_unwrap_resp(struct rpc_task *task, kxdrproc_t decode, void *rqstp, int rpcauth_refreshcred(struct rpc_task *); void rpcauth_invalcred(struct rpc_task *); int rpcauth_uptodatecred(struct rpc_task *); -int rpcauth_init_credcache(struct rpc_auth *, unsigned long); -void rpcauth_free_credcache(struct rpc_auth *); +int rpcauth_init_credcache(struct rpc_auth *); +void rpcauth_destroy_credcache(struct rpc_auth *); +void rpcauth_clear_credcache(struct rpc_cred_cache *); static inline struct rpc_cred * get_rpccred(struct rpc_cred *cred) diff --git a/include/linux/sunrpc/auth_gss.h b/include/linux/sunrpc/auth_gss.h index 2db2fbf34947..67658e17a375 100644 --- a/include/linux/sunrpc/auth_gss.h +++ b/include/linux/sunrpc/auth_gss.h @@ -75,6 +75,7 @@ struct gss_cl_ctx { struct xdr_netobj gc_wire_ctx; u32 gc_win; unsigned long gc_expiry; + struct rcu_head gc_rcu; }; struct gss_upcall_msg; @@ -85,11 +86,6 @@ struct gss_cred { struct gss_upcall_msg *gc_upcall; }; -#define gc_uid gc_base.cr_uid -#define gc_count gc_base.cr_count -#define gc_flags gc_base.cr_flags -#define gc_expire gc_base.cr_expire - #endif /* __KERNEL__ */ #endif /* _LINUX_SUNRPC_AUTH_GSS_H */ diff --git a/include/linux/sunrpc/clnt.h b/include/linux/sunrpc/clnt.h index 66611423c8ee..c0d9d14983b3 100644 --- a/include/linux/sunrpc/clnt.h +++ b/include/linux/sunrpc/clnt.h @@ -24,8 +24,10 @@ struct rpc_inode; * The high-level client handle */ struct rpc_clnt { - atomic_t cl_count; /* Number of clones */ - atomic_t cl_users; /* number of references */ + struct kref cl_kref; /* Number of references */ + struct list_head cl_clients; /* Global list of clients */ + struct list_head cl_tasks; /* List of tasks */ + spinlock_t cl_lock; /* spinlock */ struct rpc_xprt * cl_xprt; /* transport */ struct rpc_procinfo * cl_procinfo; /* procedure info */ u32 cl_prog, /* RPC program number */ @@ -41,9 +43,7 @@ struct rpc_clnt { unsigned int cl_softrtry : 1,/* soft timeouts */ cl_intr : 1,/* interruptible */ cl_discrtry : 1,/* disconnect before retry */ - cl_autobind : 1,/* use getport() */ - cl_oneshot : 1,/* dispose after use */ - cl_dead : 1;/* abandoned */ + cl_autobind : 1;/* use getport() */ struct rpc_rtt * cl_rtt; /* RTO estimator data */ @@ -98,6 +98,7 @@ struct rpc_create_args { int protocol; struct sockaddr *address; size_t addrsize; + struct sockaddr *saddress; struct rpc_timeout *timeout; char *servername; struct rpc_program *program; @@ -110,20 +111,20 @@ struct rpc_create_args { #define RPC_CLNT_CREATE_HARDRTRY (1UL << 0) #define RPC_CLNT_CREATE_INTR (1UL << 1) #define RPC_CLNT_CREATE_AUTOBIND (1UL << 2) -#define RPC_CLNT_CREATE_ONESHOT (1UL << 3) -#define RPC_CLNT_CREATE_NONPRIVPORT (1UL << 4) -#define RPC_CLNT_CREATE_NOPING (1UL << 5) -#define RPC_CLNT_CREATE_DISCRTRY (1UL << 6) +#define RPC_CLNT_CREATE_NONPRIVPORT (1UL << 3) +#define RPC_CLNT_CREATE_NOPING (1UL << 4) +#define RPC_CLNT_CREATE_DISCRTRY (1UL << 5) struct rpc_clnt *rpc_create(struct rpc_create_args *args); struct rpc_clnt *rpc_bind_new_program(struct rpc_clnt *, struct rpc_program *, int); struct rpc_clnt *rpc_clone_client(struct rpc_clnt *); -int rpc_shutdown_client(struct rpc_clnt *); -int rpc_destroy_client(struct rpc_clnt *); +void rpc_shutdown_client(struct rpc_clnt *); void rpc_release_client(struct rpc_clnt *); + int rpcb_register(u32, u32, int, unsigned short, int *); -void rpcb_getport(struct rpc_task *); +int rpcb_getport_sync(struct sockaddr_in *, __u32, __u32, int); +void rpcb_getport_async(struct rpc_task *); void rpc_call_setup(struct rpc_task *, struct rpc_message *, int); @@ -132,20 +133,16 @@ int rpc_call_async(struct rpc_clnt *clnt, struct rpc_message *msg, void *calldata); int rpc_call_sync(struct rpc_clnt *clnt, struct rpc_message *msg, int flags); +struct rpc_task *rpc_call_null(struct rpc_clnt *clnt, struct rpc_cred *cred, + int flags); void rpc_restart_call(struct rpc_task *); void rpc_clnt_sigmask(struct rpc_clnt *clnt, sigset_t *oldset); void rpc_clnt_sigunmask(struct rpc_clnt *clnt, sigset_t *oldset); void rpc_setbufsize(struct rpc_clnt *, unsigned int, unsigned int); size_t rpc_max_payload(struct rpc_clnt *); void rpc_force_rebind(struct rpc_clnt *); -int rpc_ping(struct rpc_clnt *clnt, int flags); size_t rpc_peeraddr(struct rpc_clnt *, struct sockaddr *, size_t); char * rpc_peeraddr2str(struct rpc_clnt *, enum rpc_display_format_t); -/* - * Helper function for NFSroot support - */ -int rpcb_getport_external(struct sockaddr_in *, __u32, __u32, int); - #endif /* __KERNEL__ */ #endif /* _LINUX_SUNRPC_CLNT_H */ diff --git a/include/linux/sunrpc/gss_api.h b/include/linux/sunrpc/gss_api.h index 5eca9e442051..bbac101ac372 100644 --- a/include/linux/sunrpc/gss_api.h +++ b/include/linux/sunrpc/gss_api.h @@ -77,7 +77,7 @@ struct gss_api_mech { struct module *gm_owner; struct xdr_netobj gm_oid; char *gm_name; - struct gss_api_ops *gm_ops; + const struct gss_api_ops *gm_ops; /* pseudoflavors supported by this mechanism: */ int gm_pf_num; struct pf_desc * gm_pfs; diff --git a/include/linux/sunrpc/rpc_pipe_fs.h b/include/linux/sunrpc/rpc_pipe_fs.h index ad293760f6eb..51b977a4ca20 100644 --- a/include/linux/sunrpc/rpc_pipe_fs.h +++ b/include/linux/sunrpc/rpc_pipe_fs.h @@ -23,9 +23,11 @@ struct rpc_inode { void *private; struct list_head pipe; struct list_head in_upcall; + struct list_head in_downcall; int pipelen; int nreaders; int nwriters; + int nkern_readwriters; wait_queue_head_t waitq; #define RPC_PIPE_WAIT_FOR_OPEN 1 int flags; diff --git a/include/linux/sunrpc/sched.h b/include/linux/sunrpc/sched.h index 2047fb202a13..8ea077db0099 100644 --- a/include/linux/sunrpc/sched.h +++ b/include/linux/sunrpc/sched.h @@ -98,7 +98,6 @@ struct rpc_task { unsigned short tk_pid; /* debugging aid */ #endif }; -#define tk_auth tk_client->cl_auth #define tk_xprt tk_client->cl_xprt /* support walking a list of tasks on a wait queue */ @@ -110,11 +109,6 @@ struct rpc_task { if (!list_empty(head) && \ ((task=list_entry((head)->next, struct rpc_task, u.tk_wait.list)),1)) -/* .. and walking list of all tasks */ -#define alltask_for_each(task, pos, head) \ - list_for_each(pos, head) \ - if ((task=list_entry(pos, struct rpc_task, tk_task)),1) - typedef void (*rpc_action)(struct rpc_task *); struct rpc_call_ops { diff --git a/include/linux/sunrpc/svcsock.h b/include/linux/sunrpc/svcsock.h index e21dd93ac4b7..a53e0fa855d2 100644 --- a/include/linux/sunrpc/svcsock.h +++ b/include/linux/sunrpc/svcsock.h @@ -59,6 +59,7 @@ struct svc_sock { /* cache of various info for TCP sockets */ void *sk_info_authunix; + struct sockaddr_storage sk_local; /* local address */ struct sockaddr_storage sk_remote; /* remote peer's address */ int sk_remotelen; /* length of address */ }; diff --git a/include/linux/sunrpc/xprt.h b/include/linux/sunrpc/xprt.h index 34f7590506fa..d11cedd14f0f 100644 --- a/include/linux/sunrpc/xprt.h +++ b/include/linux/sunrpc/xprt.h @@ -17,6 +17,8 @@ #include <linux/sunrpc/xdr.h> #include <linux/sunrpc/msg_prot.h> +#ifdef __KERNEL__ + extern unsigned int xprt_udp_slot_table_entries; extern unsigned int xprt_tcp_slot_table_entries; @@ -194,7 +196,13 @@ struct rpc_xprt { char * address_strings[RPC_DISPLAY_MAX]; }; -#ifdef __KERNEL__ +struct rpc_xprtsock_create { + int proto; /* IPPROTO_UDP or IPPROTO_TCP */ + struct sockaddr * srcaddr; /* optional local address */ + struct sockaddr * dstaddr; /* remote peer address */ + size_t addrlen; + struct rpc_timeout * timeout; /* optional timeout parameters */ +}; /* * Transport operations used by ULPs @@ -204,7 +212,7 @@ void xprt_set_timeout(struct rpc_timeout *to, unsigned int retr, unsigned long /* * Generic internal transport functions */ -struct rpc_xprt * xprt_create_transport(int proto, struct sockaddr *addr, size_t size, struct rpc_timeout *toparms); +struct rpc_xprt * xprt_create_transport(struct rpc_xprtsock_create *args); void xprt_connect(struct rpc_task *task); void xprt_reserve(struct rpc_task *task); int xprt_reserve_xprt(struct rpc_task *task); @@ -242,8 +250,8 @@ void xprt_disconnect(struct rpc_xprt *xprt); /* * Socket transport setup operations */ -struct rpc_xprt * xs_setup_udp(struct sockaddr *addr, size_t addrlen, struct rpc_timeout *to); -struct rpc_xprt * xs_setup_tcp(struct sockaddr *addr, size_t addrlen, struct rpc_timeout *to); +struct rpc_xprt * xs_setup_udp(struct rpc_xprtsock_create *args); +struct rpc_xprt * xs_setup_tcp(struct rpc_xprtsock_create *args); int init_socket_xprt(void); void cleanup_socket_xprt(void); diff --git a/include/linux/sysdev.h b/include/linux/sysdev.h index e699ab279c2c..e285746588d6 100644 --- a/include/linux/sysdev.h +++ b/include/linux/sysdev.h @@ -101,8 +101,7 @@ struct sysdev_attribute { #define _SYSDEV_ATTR(_name,_mode,_show,_store) \ { \ - .attr = { .name = __stringify(_name), .mode = _mode, \ - .owner = THIS_MODULE }, \ + .attr = { .name = __stringify(_name), .mode = _mode }, \ .show = _show, \ .store = _store, \ } diff --git a/include/linux/sysfs.h b/include/linux/sysfs.h index 7d5d1ec95c2e..be8228e50a27 100644 --- a/include/linux/sysfs.h +++ b/include/linux/sysfs.h @@ -19,10 +19,15 @@ struct kobject; struct module; struct nameidata; struct dentry; +struct sysfs_dirent; +/* FIXME + * The *owner field is no longer used, but leave around + * until the tree gets cleaned up fully. + */ struct attribute { const char * name; - struct module * owner; + struct module * owner; mode_t mode; }; @@ -39,14 +44,14 @@ struct attribute_group { */ #define __ATTR(_name,_mode,_show,_store) { \ - .attr = {.name = __stringify(_name), .mode = _mode, .owner = THIS_MODULE }, \ + .attr = {.name = __stringify(_name), .mode = _mode }, \ .show = _show, \ .store = _store, \ } #define __ATTR_RO(_name) { \ - .attr = { .name = __stringify(_name), .mode = 0444, .owner = THIS_MODULE }, \ - .show = _name##_show, \ + .attr = { .name = __stringify(_name), .mode = 0444 }, \ + .show = _name##_show, \ } #define __ATTR_NULL { .attr = { .name = NULL } } @@ -59,8 +64,10 @@ struct bin_attribute { struct attribute attr; size_t size; void *private; - ssize_t (*read)(struct kobject *, char *, loff_t, size_t); - ssize_t (*write)(struct kobject *, char *, loff_t, size_t); + ssize_t (*read)(struct kobject *, struct bin_attribute *, + char *, loff_t, size_t); + ssize_t (*write)(struct kobject *, struct bin_attribute *, + char *, loff_t, size_t); int (*mmap)(struct kobject *, struct bin_attribute *attr, struct vm_area_struct *vma); }; @@ -70,12 +77,16 @@ struct sysfs_ops { ssize_t (*store)(struct kobject *,struct attribute *,const char *, size_t); }; +#define SYSFS_TYPE_MASK 0x00ff #define SYSFS_ROOT 0x0001 #define SYSFS_DIR 0x0002 #define SYSFS_KOBJ_ATTR 0x0004 #define SYSFS_KOBJ_BIN_ATTR 0x0008 #define SYSFS_KOBJ_LINK 0x0020 -#define SYSFS_NOT_PINNED (SYSFS_KOBJ_ATTR | SYSFS_KOBJ_BIN_ATTR | SYSFS_KOBJ_LINK) +#define SYSFS_COPY_NAME (SYSFS_DIR | SYSFS_KOBJ_LINK) + +#define SYSFS_FLAG_MASK ~SYSFS_TYPE_MASK +#define SYSFS_FLAG_REMOVED 0x0100 #ifdef CONFIG_SYSFS @@ -83,13 +94,14 @@ extern int sysfs_schedule_callback(struct kobject *kobj, void (*func)(void *), void *data, struct module *owner); extern int __must_check -sysfs_create_dir(struct kobject *, struct dentry *); +sysfs_create_dir(struct kobject *kobj, struct sysfs_dirent *shadow_parent_sd); extern void sysfs_remove_dir(struct kobject *); extern int __must_check -sysfs_rename_dir(struct kobject *, struct dentry *, const char *new_name); +sysfs_rename_dir(struct kobject *kobj, struct sysfs_dirent *new_parent_sd, + const char *new_name); extern int __must_check sysfs_move_dir(struct kobject *, struct kobject *); @@ -129,8 +141,8 @@ void sysfs_notify(struct kobject * k, char *dir, char *attr); extern int sysfs_make_shadowed_dir(struct kobject *kobj, void * (*follow_link)(struct dentry *, struct nameidata *)); -extern struct dentry *sysfs_create_shadow_dir(struct kobject *kobj); -extern void sysfs_remove_shadow_dir(struct dentry *dir); +extern struct sysfs_dirent *sysfs_create_shadow_dir(struct kobject *kobj); +extern void sysfs_remove_shadow_dir(struct sysfs_dirent *shadow_sd); extern int __must_check sysfs_init(void); @@ -142,7 +154,8 @@ static inline int sysfs_schedule_callback(struct kobject *kobj, return -ENOSYS; } -static inline int sysfs_create_dir(struct kobject * k, struct dentry *shadow) +static inline int sysfs_create_dir(struct kobject *kobj, + struct sysfs_dirent *shadow_parent_sd) { return 0; } @@ -152,9 +165,9 @@ static inline void sysfs_remove_dir(struct kobject * k) ; } -static inline int sysfs_rename_dir(struct kobject * k, - struct dentry *new_parent, - const char *new_name) +static inline int sysfs_rename_dir(struct kobject *kobj, + struct sysfs_dirent *new_parent_sd, + const char *new_name) { return 0; } diff --git a/include/linux/taskstats.h b/include/linux/taskstats.h index a46104a28f66..dce1ed204972 100644 --- a/include/linux/taskstats.h +++ b/include/linux/taskstats.h @@ -31,7 +31,7 @@ */ -#define TASKSTATS_VERSION 4 +#define TASKSTATS_VERSION 5 #define TS_COMM_LEN 32 /* should be >= TASK_COMM_LEN * in linux/sched.h */ @@ -149,6 +149,9 @@ struct taskstats { __u64 read_bytes; /* bytes of read I/O */ __u64 write_bytes; /* bytes of write I/O */ __u64 cancelled_write_bytes; /* bytes of cancelled write I/O */ + + __u64 nvcsw; /* voluntary_ctxt_switches */ + __u64 nivcsw; /* nonvoluntary_ctxt_switches */ }; diff --git a/include/linux/time.h b/include/linux/time.h index dda9be685ab6..4bb05a829be9 100644 --- a/include/linux/time.h +++ b/include/linux/time.h @@ -116,6 +116,8 @@ extern int do_setitimer(int which, struct itimerval *value, extern unsigned int alarm_setitimer(unsigned int seconds); extern int do_getitimer(int which, struct itimerval *value); extern void getnstimeofday(struct timespec *tv); +extern void getboottime(struct timespec *ts); +extern void monotonic_to_bootbased(struct timespec *ts); extern struct timespec timespec_trunc(struct timespec t, unsigned gran); extern int timekeeping_is_continuous(void); diff --git a/include/linux/timer.h b/include/linux/timer.h index c661710d3627..78cf899b4409 100644 --- a/include/linux/timer.h +++ b/include/linux/timer.h @@ -3,7 +3,6 @@ #include <linux/list.h> #include <linux/ktime.h> -#include <linux/spinlock.h> #include <linux/stddef.h> struct tvec_t_base_s; @@ -91,16 +90,13 @@ extern unsigned long get_next_timer_interrupt(unsigned long now); */ #ifdef CONFIG_TIMER_STATS +#define TIMER_STATS_FLAG_DEFERRABLE 0x1 + extern void init_timer_stats(void); extern void timer_stats_update_stats(void *timer, pid_t pid, void *startf, - void *timerf, char * comm); - -static inline void timer_stats_account_timer(struct timer_list *timer) -{ - timer_stats_update_stats(timer, timer->start_pid, timer->start_site, - timer->function, timer->start_comm); -} + void *timerf, char *comm, + unsigned int timer_flag); extern void __timer_stats_timer_set_start_info(struct timer_list *timer, void *addr); @@ -119,10 +115,6 @@ static inline void init_timer_stats(void) { } -static inline void timer_stats_account_timer(struct timer_list *timer) -{ -} - static inline void timer_stats_timer_set_start_info(struct timer_list *timer) { } diff --git a/include/linux/topology.h b/include/linux/topology.h index da6c39b2d051..d0890a7e5bab 100644 --- a/include/linux/topology.h +++ b/include/linux/topology.h @@ -50,10 +50,10 @@ for_each_online_node(node) \ if (nr_cpus_node(node)) -#ifndef node_distance /* Conform to ACPI 2.0 SLIT distance definitions */ #define LOCAL_DISTANCE 10 #define REMOTE_DISTANCE 20 +#ifndef node_distance #define node_distance(from,to) ((from) == (to) ? LOCAL_DISTANCE : REMOTE_DISTANCE) #endif #ifndef RECLAIM_DISTANCE diff --git a/include/linux/tty.h b/include/linux/tty.h index bb4576085203..691a1748d9d2 100644 --- a/include/linux/tty.h +++ b/include/linux/tty.h @@ -178,6 +178,7 @@ struct tty_bufhead { #define L_IEXTEN(tty) _L_FLAG((tty),IEXTEN) struct device; +struct signal_struct; /* * Where all of the state associated with a tty is kept while the tty * is open. Since the termios state should be kept even if the tty @@ -310,6 +311,7 @@ extern void tty_hangup(struct tty_struct * tty); extern void tty_vhangup(struct tty_struct * tty); extern void tty_unhangup(struct file *filp); extern int tty_hung_up_p(struct file * filp); +extern int is_tty(struct file *filp); extern void do_SAK(struct tty_struct *tty); extern void __do_SAK(struct tty_struct *tty); extern void disassociate_ctty(int priv); @@ -338,9 +340,46 @@ extern struct tty_struct *get_current_tty(void); extern struct mutex tty_mutex; +extern void tty_write_unlock(struct tty_struct *tty); +extern int tty_write_lock(struct tty_struct *tty, int ndelay); +#define tty_is_writelocked(tty) (mutex_is_locked(&tty->atomic_write_lock)) + + + /* n_tty.c */ extern struct tty_ldisc tty_ldisc_N_TTY; +/* tty_audit.c */ +#ifdef CONFIG_AUDIT +extern void tty_audit_add_data(struct tty_struct *tty, unsigned char *data, + size_t size); +extern void tty_audit_exit(void); +extern void tty_audit_fork(struct signal_struct *sig); +extern void tty_audit_push(struct tty_struct *tty); +extern void tty_audit_push_task(struct task_struct *tsk, uid_t loginuid); +extern void tty_audit_opening(void); +#else +static inline void tty_audit_add_data(struct tty_struct *tty, + unsigned char *data, size_t size) +{ +} +static inline void tty_audit_exit(void) +{ +} +static inline void tty_audit_fork(struct signal_struct *sig) +{ +} +static inline void tty_audit_push(struct tty_struct *tty) +{ +} +static inline void tty_audit_push_task(struct task_struct *tsk, uid_t loginuid) +{ +} +static inline void tty_audit_opening(void) +{ +} +#endif + /* tty_ioctl.c */ extern int n_tty_ioctl(struct tty_struct * tty, struct file * file, unsigned int cmd, unsigned long arg); diff --git a/include/linux/udp.h b/include/linux/udp.h index 6de445c31a64..8ec703f462da 100644 --- a/include/linux/udp.h +++ b/include/linux/udp.h @@ -42,6 +42,7 @@ static inline struct udphdr *udp_hdr(const struct sk_buff *skb) /* UDP encapsulation types */ #define UDP_ENCAP_ESPINUDP_NON_IKE 1 /* draft-ietf-ipsec-nat-t-ike-00/01 */ #define UDP_ENCAP_ESPINUDP 2 /* draft-ietf-ipsec-udp-encaps-06 */ +#define UDP_ENCAP_L2TPINUDP 3 /* rfc2661 */ #ifdef __KERNEL__ #include <linux/types.h> @@ -70,6 +71,11 @@ struct udp_sock { #define UDPLITE_SEND_CC 0x2 /* set via udplite setsockopt */ #define UDPLITE_RECV_CC 0x4 /* set via udplite setsocktopt */ __u8 pcflag; /* marks socket as UDP-Lite if > 0 */ + __u8 unused[3]; + /* + * For encapsulation sockets. + */ + int (*encap_rcv)(struct sock *sk, struct sk_buff *skb); }; static inline struct udp_sock *udp_sk(const struct sock *sk) diff --git a/include/linux/uio.h b/include/linux/uio.h index 9af8bbcd8963..b7fe13883bdb 100644 --- a/include/linux/uio.h +++ b/include/linux/uio.h @@ -13,10 +13,6 @@ * 2 of the License, or (at your option) any later version. */ - -/* A word of warning: Our uio structure will clash with the C library one (which is now obsolete). Remove the C - library one from sys/uio.h if you have a very old library set */ - struct iovec { void __user *iov_base; /* BSD uses caddr_t (1003.1g requires void *) */ @@ -38,11 +34,6 @@ struct kvec { #define UIO_FASTIOV 8 #define UIO_MAXIOV 1024 -#if 0 -#define UIO_MAXIOV 16 /* Maximum iovec's in one operation - 16 matches BSD */ - /* Beg pardon: BSD has 1024 --ANK */ -#endif /* * Total number of bytes covered by an iovec. diff --git a/include/linux/usb.h b/include/linux/usb.h index 56aa2ee21f1b..7a60946df3b6 100644 --- a/include/linux/usb.h +++ b/include/linux/usb.h @@ -146,6 +146,10 @@ struct usb_interface { * active alternate setting */ unsigned num_altsetting; /* number of alternate settings */ + /* If there is an interface association descriptor then it will list + * the associated interfaces */ + struct usb_interface_assoc_descriptor *intf_assoc; + int minor; /* minor number this interface is * bound to */ enum usb_interface_condition condition; /* state of binding */ @@ -175,6 +179,7 @@ void usb_put_intf(struct usb_interface *intf); /* this maximum is arbitrary */ #define USB_MAXINTERFACES 32 +#define USB_MAXIADS USB_MAXINTERFACES/2 /** * struct usb_interface_cache - long-term representation of a device interface @@ -245,6 +250,11 @@ struct usb_host_config { struct usb_config_descriptor desc; char *string; /* iConfiguration string, if present */ + + /* List of any Interface Association Descriptors in this + * configuration. */ + struct usb_interface_assoc_descriptor *intf_assoc[USB_MAXIADS]; + /* the interfaces associated with this configuration, * stored in no particular order */ struct usb_interface *interface[USB_MAXINTERFACES]; @@ -403,6 +413,8 @@ struct usb_device { unsigned auto_pm:1; /* autosuspend/resume in progress */ unsigned do_remote_wakeup:1; /* remote wakeup should be enabled */ + unsigned reset_resume:1; /* needs reset instead of resume */ + unsigned persist_enabled:1; /* USB_PERSIST enabled for this dev */ unsigned autosuspend_disabled:1; /* autosuspend and autoresume */ unsigned autoresume_disabled:1; /* disabled by the user */ #endif @@ -770,6 +782,28 @@ static inline int usb_endpoint_is_isoc_out(const struct usb_endpoint_descriptor .match_flags = USB_DEVICE_ID_MATCH_INT_INFO, .bInterfaceClass = (cl), \ .bInterfaceSubClass = (sc), .bInterfaceProtocol = (pr) +/** + * USB_DEVICE_AND_INTERFACE_INFO - macro used to describe a specific usb device + * with a class of usb interfaces + * @vend: the 16 bit USB Vendor ID + * @prod: the 16 bit USB Product ID + * @cl: bInterfaceClass value + * @sc: bInterfaceSubClass value + * @pr: bInterfaceProtocol value + * + * This macro is used to create a struct usb_device_id that matches a + * specific device with a specific class of interfaces. + * + * This is especially useful when explicitly matching devices that have + * vendor specific bDeviceClass values, but standards-compliant interfaces. + */ +#define USB_DEVICE_AND_INTERFACE_INFO(vend,prod,cl,sc,pr) \ + .match_flags = USB_DEVICE_ID_MATCH_INT_INFO \ + | USB_DEVICE_ID_MATCH_DEVICE, \ + .idVendor = (vend), .idProduct = (prod), \ + .bInterfaceClass = (cl), \ + .bInterfaceSubClass = (sc), .bInterfaceProtocol = (pr) + /* ----------------------------------------------------------------------- */ /* Stuff for dynamic usb ids */ @@ -816,10 +850,15 @@ struct usbdrv_wrap { * do (or don't) show up otherwise in the filesystem. * @suspend: Called when the device is going to be suspended by the system. * @resume: Called when the device is being resumed by the system. + * @reset_resume: Called when the suspended device has been reset instead + * of being resumed. * @pre_reset: Called by usb_reset_composite_device() when the device * is about to be reset. * @post_reset: Called by usb_reset_composite_device() after the device - * has been reset. + * has been reset, or in lieu of @resume following a reset-resume + * (i.e., the device is reset instead of being resumed, as might + * happen if power was lost). The second argument tells which is + * the reason. * @id_table: USB drivers use ID table to support hotplugging. * Export this with MODULE_DEVICE_TABLE(usb,...). This must be set * or your driver's probe function will never get called. @@ -859,9 +898,10 @@ struct usb_driver { int (*suspend) (struct usb_interface *intf, pm_message_t message); int (*resume) (struct usb_interface *intf); + int (*reset_resume)(struct usb_interface *intf); - void (*pre_reset) (struct usb_interface *intf); - void (*post_reset) (struct usb_interface *intf); + int (*pre_reset)(struct usb_interface *intf); + int (*post_reset)(struct usb_interface *intf); const struct usb_device_id *id_table; @@ -964,6 +1004,7 @@ extern int usb_disabled(void); #define URB_ZERO_PACKET 0x0040 /* Finish bulk OUT with short packet */ #define URB_NO_INTERRUPT 0x0080 /* HINT: no non-error interrupt * needed */ +#define URB_FREE_BUFFER 0x0100 /* Free transfer buffer with the URB */ struct usb_iso_packet_descriptor { unsigned int offset; @@ -974,11 +1015,26 @@ struct usb_iso_packet_descriptor { struct urb; +struct usb_anchor { + struct list_head urb_list; + wait_queue_head_t wait; + spinlock_t lock; +}; + +static inline void init_usb_anchor(struct usb_anchor *anchor) +{ + INIT_LIST_HEAD(&anchor->urb_list); + init_waitqueue_head(&anchor->wait); + spin_lock_init(&anchor->lock); +} + typedef void (*usb_complete_t)(struct urb *); /** * struct urb - USB Request Block * @urb_list: For use by current owner of the URB. + * @anchor_list: membership in the list of an anchor + * @anchor: to anchor URBs to a common mooring * @pipe: Holds endpoint number, direction, type, and more. * Create these values with the eight macros available; * usb_{snd,rcv}TYPEpipe(dev,endpoint), where the TYPE is "ctrl" @@ -1151,6 +1207,8 @@ struct urb /* public: documented fields in the urb that can be used by drivers */ struct list_head urb_list; /* list head for use by the urb's * current owner */ + struct list_head anchor_list; /* the URB may be anchored by the driver */ + struct usb_anchor *anchor; struct usb_device *dev; /* (in) pointer to associated device */ unsigned int pipe; /* (in) pipe information */ int status; /* (return) non-ISO status */ @@ -1286,6 +1344,11 @@ extern struct urb *usb_get_urb(struct urb *urb); extern int usb_submit_urb(struct urb *urb, gfp_t mem_flags); extern int usb_unlink_urb(struct urb *urb); extern void usb_kill_urb(struct urb *urb); +extern void usb_kill_anchored_urbs(struct usb_anchor *anchor); +extern void usb_anchor_urb(struct urb *urb, struct usb_anchor *anchor); +extern void usb_unanchor_urb(struct urb *urb); +extern int usb_wait_anchor_empty_timeout(struct usb_anchor *anchor, + unsigned int timeout); void *usb_buffer_alloc (struct usb_device *dev, size_t size, gfp_t mem_flags, dma_addr_t *dma); diff --git a/include/linux/usb/Kbuild b/include/linux/usb/Kbuild index 43f160cfe003..6ce42bf9f743 100644 --- a/include/linux/usb/Kbuild +++ b/include/linux/usb/Kbuild @@ -1,5 +1,6 @@ unifdef-y += audio.h unifdef-y += cdc.h unifdef-y += ch9.h +unifdef-y += gadgetfs.h unifdef-y += midi.h diff --git a/include/linux/usb_gadgetfs.h b/include/linux/usb/gadgetfs.h index 8086d5a9b94e..e8654c338729 100644 --- a/include/linux/usb_gadgetfs.h +++ b/include/linux/usb/gadgetfs.h @@ -1,3 +1,5 @@ +#ifndef __LINUX_USB_GADGETFS_H +#define __LINUX_USB_GADGETFS_H #include <asm/types.h> #include <asm/ioctl.h> @@ -7,11 +9,12 @@ /* * Filesystem based user-mode API to USB Gadget controller hardware * - * Almost everything can be done with only read and write operations, + * Other than ep0 operations, most things are done by read() and write() * on endpoint files found in one directory. They are configured by * writing descriptors, and then may be used for normal stream style * i/o requests. When ep0 is configured, the device can enumerate; - * when it's closed, the device disconnects from usb. + * when it's closed, the device disconnects from usb. Operations on + * ep0 require ioctl() operations. * * Configuration and device descriptors get written to /dev/gadget/$CHIP, * which may then be used to read usb_gadgetfs_event structs. The driver @@ -21,9 +24,9 @@ */ /* - * Events are delivered on the ep0 file descriptor, if the user mode driver + * Events are delivered on the ep0 file descriptor, when the user mode driver * reads from this file descriptor after writing the descriptors. Don't - * stop polling this descriptor, if you write that kind of driver. + * stop polling this descriptor. */ enum usb_gadgetfs_event_type { @@ -36,8 +39,10 @@ enum usb_gadgetfs_event_type { // and likely more ! }; +/* NOTE: this structure must stay the same size and layout on + * both 32-bit and 64-bit kernels. + */ struct usb_gadgetfs_event { - enum usb_gadgetfs_event_type type; union { // NOP, DISCONNECT, SUSPEND: nothing // ... some hardware can't report disconnection @@ -46,19 +51,20 @@ struct usb_gadgetfs_event { enum usb_device_speed speed; // SETUP: packet; DATA phase i/o precedes next event - // (setup.bmRequestType & USB_DIR_IN) flags direction + // (setup.bmRequestType & USB_DIR_IN) flags direction // ... includes SET_CONFIGURATION, SET_INTERFACE struct usb_ctrlrequest setup; } u; + enum usb_gadgetfs_event_type type; }; /* endpoint ioctls */ /* IN transfers may be reported to the gadget driver as complete - * when the fifo is loaded, before the host reads the data; + * when the fifo is loaded, before the host reads the data; * OUT transfers may be reported to the host's "client" driver as - * complete when they're sitting in the FIFO unread. + * complete when they're sitting in the FIFO unread. * THIS returns how many bytes are "unclaimed" in the endpoint fifo * (needed for precise fault handling, when the hardware allows it) */ @@ -72,4 +78,4 @@ struct usb_gadgetfs_event { */ #define GADGETFS_CLEAR_HALT _IO('g',3) - +#endif /* __LINUX_USB_GADGETFS_H */ diff --git a/include/linux/usb/quirks.h b/include/linux/usb/quirks.h index 6bac8faacbc6..8da374caf582 100644 --- a/include/linux/usb/quirks.h +++ b/include/linux/usb/quirks.h @@ -9,3 +9,6 @@ /* string descriptors must not be fetched using a 255-byte read */ #define USB_QUIRK_STRING_FETCH_255 0x00000002 + +/* device can't resume correctly so reset it instead */ +#define USB_QUIRK_RESET_RESUME 0x00000004 diff --git a/include/linux/usb/serial.h b/include/linux/usb/serial.h index 32acbae28d24..e8b8928232c8 100644 --- a/include/linux/usb/serial.h +++ b/include/linux/usb/serial.h @@ -221,6 +221,9 @@ struct usb_serial_driver { int (*port_probe) (struct usb_serial_port *port); int (*port_remove) (struct usb_serial_port *port); + int (*suspend) (struct usb_serial *serial, pm_message_t message); + int (*resume) (struct usb_serial *serial); + /* serial function calls */ int (*open) (struct usb_serial_port *port, struct file * filp); void (*close) (struct usb_serial_port *port, struct file * filp); @@ -249,6 +252,9 @@ extern void usb_serial_port_softint(struct usb_serial_port *port); extern int usb_serial_probe(struct usb_interface *iface, const struct usb_device_id *id); extern void usb_serial_disconnect(struct usb_interface *iface); +extern int usb_serial_suspend(struct usb_interface *intf, pm_message_t message); +extern int usb_serial_resume(struct usb_interface *intf); + extern int ezusb_writememory (struct usb_serial *serial, int address, unsigned char *data, int length, __u8 bRequest); extern int ezusb_set_reset (struct usb_serial *serial, unsigned char reset_bit); @@ -269,6 +275,7 @@ extern void usb_serial_put(struct usb_serial *serial); extern int usb_serial_generic_open (struct usb_serial_port *port, struct file *filp); extern int usb_serial_generic_write (struct usb_serial_port *port, const unsigned char *buf, int count); extern void usb_serial_generic_close (struct usb_serial_port *port, struct file *filp); +extern int usb_serial_generic_resume (struct usb_serial *serial); extern int usb_serial_generic_write_room (struct usb_serial_port *port); extern int usb_serial_generic_chars_in_buffer (struct usb_serial_port *port); extern void usb_serial_generic_read_bulk_callback (struct urb *urb); diff --git a/include/linux/usb_gadget.h b/include/linux/usb_gadget.h index e17186dbcdca..4f59b2aa8a9e 100644 --- a/include/linux/usb_gadget.h +++ b/include/linux/usb_gadget.h @@ -110,13 +110,6 @@ struct usb_ep_ops { gfp_t gfp_flags); void (*free_request) (struct usb_ep *ep, struct usb_request *req); - void *(*alloc_buffer) (struct usb_ep *ep, unsigned bytes, - dma_addr_t *dma, gfp_t gfp_flags); - void (*free_buffer) (struct usb_ep *ep, void *buf, dma_addr_t dma, - unsigned bytes); - // NOTE: on 2.6, drivers may also use dma_map() and - // dma_sync_single_*() to directly manage dma overhead. - int (*queue) (struct usb_ep *ep, struct usb_request *req, gfp_t gfp_flags); int (*dequeue) (struct usb_ep *ep, struct usb_request *req); @@ -235,47 +228,6 @@ usb_ep_free_request (struct usb_ep *ep, struct usb_request *req) } /** - * usb_ep_alloc_buffer - allocate an I/O buffer - * @ep:the endpoint associated with the buffer - * @len:length of the desired buffer - * @dma:pointer to the buffer's DMA address; must be valid - * @gfp_flags:GFP_* flags to use - * - * Returns a new buffer, or null if one could not be allocated. - * The buffer is suitably aligned for dma, if that endpoint uses DMA, - * and the caller won't have to care about dma-inconsistency - * or any hidden "bounce buffer" mechanism. No additional per-request - * DMA mapping will be required for such buffers. - * Free it later with usb_ep_free_buffer(). - * - * You don't need to use this call to allocate I/O buffers unless you - * want to make sure drivers don't incur costs for such "bounce buffer" - * copies or per-request DMA mappings. - */ -static inline void * -usb_ep_alloc_buffer (struct usb_ep *ep, unsigned len, dma_addr_t *dma, - gfp_t gfp_flags) -{ - return ep->ops->alloc_buffer (ep, len, dma, gfp_flags); -} - -/** - * usb_ep_free_buffer - frees an i/o buffer - * @ep:the endpoint associated with the buffer - * @buf:CPU view address of the buffer - * @dma:the buffer's DMA address - * @len:length of the buffer - * - * reverses the effect of usb_ep_alloc_buffer(). - * caller guarantees the buffer will no longer be accessed - */ -static inline void -usb_ep_free_buffer (struct usb_ep *ep, void *buf, dma_addr_t dma, unsigned len) -{ - ep->ops->free_buffer (ep, buf, dma, len); -} - -/** * usb_ep_queue - queues (submits) an I/O request to an endpoint. * @ep:the endpoint associated with the request * @req:the request being submitted diff --git a/include/linux/user_namespace.h b/include/linux/user_namespace.h new file mode 100644 index 000000000000..bb320573bb9e --- /dev/null +++ b/include/linux/user_namespace.h @@ -0,0 +1,61 @@ +#ifndef _LINUX_USER_NAMESPACE_H +#define _LINUX_USER_NAMESPACE_H + +#include <linux/kref.h> +#include <linux/nsproxy.h> +#include <linux/sched.h> +#include <linux/err.h> + +#define UIDHASH_BITS (CONFIG_BASE_SMALL ? 3 : 8) +#define UIDHASH_SZ (1 << UIDHASH_BITS) + +struct user_namespace { + struct kref kref; + struct list_head uidhash_table[UIDHASH_SZ]; + struct user_struct *root_user; +}; + +extern struct user_namespace init_user_ns; + +#ifdef CONFIG_USER_NS + +static inline struct user_namespace *get_user_ns(struct user_namespace *ns) +{ + if (ns) + kref_get(&ns->kref); + return ns; +} + +extern struct user_namespace *copy_user_ns(int flags, + struct user_namespace *old_ns); +extern void free_user_ns(struct kref *kref); + +static inline void put_user_ns(struct user_namespace *ns) +{ + if (ns) + kref_put(&ns->kref, free_user_ns); +} + +#else + +static inline struct user_namespace *get_user_ns(struct user_namespace *ns) +{ + return &init_user_ns; +} + +static inline struct user_namespace *copy_user_ns(int flags, + struct user_namespace *old_ns) +{ + if (flags & CLONE_NEWUSER) + return ERR_PTR(-EINVAL); + + return NULL; +} + +static inline void put_user_ns(struct user_namespace *ns) +{ +} + +#endif + +#endif /* _LINUX_USER_H */ diff --git a/include/linux/utsname.h b/include/linux/utsname.h index f8d3b326e93a..923db99175f2 100644 --- a/include/linux/utsname.h +++ b/include/linux/utsname.h @@ -48,26 +48,14 @@ static inline void get_uts_ns(struct uts_namespace *ns) kref_get(&ns->kref); } -#ifdef CONFIG_UTS_NS -extern struct uts_namespace *copy_utsname(int flags, struct uts_namespace *ns); +extern struct uts_namespace *copy_utsname(unsigned long flags, + struct uts_namespace *ns); extern void free_uts_ns(struct kref *kref); static inline void put_uts_ns(struct uts_namespace *ns) { kref_put(&ns->kref, free_uts_ns); } -#else -static inline struct uts_namespace *copy_utsname(int flags, - struct uts_namespace *ns) -{ - return ns; -} - -static inline void put_uts_ns(struct uts_namespace *ns) -{ -} -#endif - static inline struct new_utsname *utsname(void) { return ¤t->nsproxy->uts_ns->name; diff --git a/include/linux/workqueue.h b/include/linux/workqueue.h index ce0719a2cfeb..ce6badc98f6d 100644 --- a/include/linux/workqueue.h +++ b/include/linux/workqueue.h @@ -148,7 +148,7 @@ extern int keventd_up(void); extern void init_workqueues(void); int execute_in_process_context(work_func_t fn, struct execute_work *); -extern void cancel_work_sync(struct work_struct *work); +extern int cancel_work_sync(struct work_struct *work); /* * Kill off a pending schedule_delayed_work(). Note that the work callback @@ -166,14 +166,21 @@ static inline int cancel_delayed_work(struct delayed_work *work) return ret; } -extern void cancel_rearming_delayed_work(struct delayed_work *work); +extern int cancel_delayed_work_sync(struct delayed_work *work); -/* Obsolete. use cancel_rearming_delayed_work() */ +/* Obsolete. use cancel_delayed_work_sync() */ static inline void cancel_rearming_delayed_workqueue(struct workqueue_struct *wq, struct delayed_work *work) { - cancel_rearming_delayed_work(work); + cancel_delayed_work_sync(work); +} + +/* Obsolete. use cancel_delayed_work_sync() */ +static inline +void cancel_rearming_delayed_work(struct delayed_work *work) +{ + cancel_delayed_work_sync(work); } #endif diff --git a/include/net/9p/9p.h b/include/net/9p/9p.h new file mode 100644 index 000000000000..88884d39f28f --- /dev/null +++ b/include/net/9p/9p.h @@ -0,0 +1,417 @@ +/* + * include/net/9p/9p.h + * + * 9P protocol definitions. + * + * Copyright (C) 2005 by Latchesar Ionkov <lucho@ionkov.net> + * Copyright (C) 2004 by Eric Van Hensbergen <ericvh@gmail.com> + * Copyright (C) 2002 by Ron Minnich <rminnich@lanl.gov> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to: + * Free Software Foundation + * 51 Franklin Street, Fifth Floor + * Boston, MA 02111-1301 USA + * + */ + +#ifndef NET_9P_H +#define NET_9P_H + +#ifdef CONFIG_NET_9P_DEBUG + +#define P9_DEBUG_ERROR (1<<0) +#define P9_DEBUG_9P (1<<2) +#define P9_DEBUG_VFS (1<<3) +#define P9_DEBUG_CONV (1<<4) +#define P9_DEBUG_MUX (1<<5) +#define P9_DEBUG_TRANS (1<<6) +#define P9_DEBUG_SLABS (1<<7) +#define P9_DEBUG_FCALL (1<<8) + +extern unsigned int p9_debug_level; + +#define P9_DPRINTK(level, format, arg...) \ +do { \ + if ((p9_debug_level & level) == level) \ + printk(KERN_NOTICE "-- %s (%d): " \ + format , __FUNCTION__, current->pid , ## arg); \ +} while (0) + +#define PRINT_FCALL_ERROR(s, fcall) P9_DPRINTK(P9_DEBUG_ERROR, \ + "%s: %.*s\n", s, fcall?fcall->params.rerror.error.len:0, \ + fcall?fcall->params.rerror.error.str:""); + +#else +#define P9_DPRINTK(level, format, arg...) do { } while (0) +#define PRINT_FCALL_ERROR(s, fcall) do { } while (0) +#endif + +#define P9_EPRINTK(level, format, arg...) \ +do { \ + printk(level "9p: %s (%d): " \ + format , __FUNCTION__, current->pid , ## arg); \ +} while (0) + + +/* Message Types */ +enum { + P9_TVERSION = 100, + P9_RVERSION, + P9_TAUTH = 102, + P9_RAUTH, + P9_TATTACH = 104, + P9_RATTACH, + P9_TERROR = 106, + P9_RERROR, + P9_TFLUSH = 108, + P9_RFLUSH, + P9_TWALK = 110, + P9_RWALK, + P9_TOPEN = 112, + P9_ROPEN, + P9_TCREATE = 114, + P9_RCREATE, + P9_TREAD = 116, + P9_RREAD, + P9_TWRITE = 118, + P9_RWRITE, + P9_TCLUNK = 120, + P9_RCLUNK, + P9_TREMOVE = 122, + P9_RREMOVE, + P9_TSTAT = 124, + P9_RSTAT, + P9_TWSTAT = 126, + P9_RWSTAT, +}; + +/* open modes */ +enum { + P9_OREAD = 0x00, + P9_OWRITE = 0x01, + P9_ORDWR = 0x02, + P9_OEXEC = 0x03, + P9_OEXCL = 0x04, + P9_OTRUNC = 0x10, + P9_OREXEC = 0x20, + P9_ORCLOSE = 0x40, + P9_OAPPEND = 0x80, +}; + +/* permissions */ +enum { + P9_DMDIR = 0x80000000, + P9_DMAPPEND = 0x40000000, + P9_DMEXCL = 0x20000000, + P9_DMMOUNT = 0x10000000, + P9_DMAUTH = 0x08000000, + P9_DMTMP = 0x04000000, + P9_DMSYMLINK = 0x02000000, + P9_DMLINK = 0x01000000, + /* 9P2000.u extensions */ + P9_DMDEVICE = 0x00800000, + P9_DMNAMEDPIPE = 0x00200000, + P9_DMSOCKET = 0x00100000, + P9_DMSETUID = 0x00080000, + P9_DMSETGID = 0x00040000, +}; + +/* qid.types */ +enum { + P9_QTDIR = 0x80, + P9_QTAPPEND = 0x40, + P9_QTEXCL = 0x20, + P9_QTMOUNT = 0x10, + P9_QTAUTH = 0x08, + P9_QTTMP = 0x04, + P9_QTSYMLINK = 0x02, + P9_QTLINK = 0x01, + P9_QTFILE = 0x00, +}; + +#define P9_NOTAG (u16)(~0) +#define P9_NOFID (u32)(~0) +#define P9_MAXWELEM 16 + +/* ample room for Twrite/Rread header */ +#define P9_IOHDRSZ 24 + +struct p9_str { + u16 len; + char *str; +}; + +/* qids are the unique ID for a file (like an inode */ +struct p9_qid { + u8 type; + u32 version; + u64 path; +}; + +/* Plan 9 file metadata (stat) structure */ +struct p9_stat { + u16 size; + u16 type; + u32 dev; + struct p9_qid qid; + u32 mode; + u32 atime; + u32 mtime; + u64 length; + struct p9_str name; + struct p9_str uid; + struct p9_str gid; + struct p9_str muid; + struct p9_str extension; /* 9p2000.u extensions */ + u32 n_uid; /* 9p2000.u extensions */ + u32 n_gid; /* 9p2000.u extensions */ + u32 n_muid; /* 9p2000.u extensions */ +}; + +/* file metadata (stat) structure used to create Twstat message + The is similar to p9_stat, but the strings don't point to + the same memory block and should be freed separately +*/ +struct p9_wstat { + u16 size; + u16 type; + u32 dev; + struct p9_qid qid; + u32 mode; + u32 atime; + u32 mtime; + u64 length; + char *name; + char *uid; + char *gid; + char *muid; + char *extension; /* 9p2000.u extensions */ + u32 n_uid; /* 9p2000.u extensions */ + u32 n_gid; /* 9p2000.u extensions */ + u32 n_muid; /* 9p2000.u extensions */ +}; + +/* Structures for Protocol Operations */ +struct p9_tversion { + u32 msize; + struct p9_str version; +}; + +struct p9_rversion { + u32 msize; + struct p9_str version; +}; + +struct p9_tauth { + u32 afid; + struct p9_str uname; + struct p9_str aname; +}; + +struct p9_rauth { + struct p9_qid qid; +}; + +struct p9_rerror { + struct p9_str error; + u32 errno; /* 9p2000.u extension */ +}; + +struct p9_tflush { + u16 oldtag; +}; + +struct p9_rflush { +}; + +struct p9_tattach { + u32 fid; + u32 afid; + struct p9_str uname; + struct p9_str aname; +}; + +struct p9_rattach { + struct p9_qid qid; +}; + +struct p9_twalk { + u32 fid; + u32 newfid; + u16 nwname; + struct p9_str wnames[16]; +}; + +struct p9_rwalk { + u16 nwqid; + struct p9_qid wqids[16]; +}; + +struct p9_topen { + u32 fid; + u8 mode; +}; + +struct p9_ropen { + struct p9_qid qid; + u32 iounit; +}; + +struct p9_tcreate { + u32 fid; + struct p9_str name; + u32 perm; + u8 mode; + struct p9_str extension; +}; + +struct p9_rcreate { + struct p9_qid qid; + u32 iounit; +}; + +struct p9_tread { + u32 fid; + u64 offset; + u32 count; +}; + +struct p9_rread { + u32 count; + u8 *data; +}; + +struct p9_twrite { + u32 fid; + u64 offset; + u32 count; + u8 *data; +}; + +struct p9_rwrite { + u32 count; +}; + +struct p9_tclunk { + u32 fid; +}; + +struct p9_rclunk { +}; + +struct p9_tremove { + u32 fid; +}; + +struct p9_rremove { +}; + +struct p9_tstat { + u32 fid; +}; + +struct p9_rstat { + struct p9_stat stat; +}; + +struct p9_twstat { + u32 fid; + struct p9_stat stat; +}; + +struct p9_rwstat { +}; + +/* + * fcall is the primary packet structure + * + */ + +struct p9_fcall { + u32 size; + u8 id; + u16 tag; + void *sdata; + + union { + struct p9_tversion tversion; + struct p9_rversion rversion; + struct p9_tauth tauth; + struct p9_rauth rauth; + struct p9_rerror rerror; + struct p9_tflush tflush; + struct p9_rflush rflush; + struct p9_tattach tattach; + struct p9_rattach rattach; + struct p9_twalk twalk; + struct p9_rwalk rwalk; + struct p9_topen topen; + struct p9_ropen ropen; + struct p9_tcreate tcreate; + struct p9_rcreate rcreate; + struct p9_tread tread; + struct p9_rread rread; + struct p9_twrite twrite; + struct p9_rwrite rwrite; + struct p9_tclunk tclunk; + struct p9_rclunk rclunk; + struct p9_tremove tremove; + struct p9_rremove rremove; + struct p9_tstat tstat; + struct p9_rstat rstat; + struct p9_twstat twstat; + struct p9_rwstat rwstat; + } params; +}; + +struct p9_idpool; + +int p9_deserialize_stat(void *buf, u32 buflen, struct p9_stat *stat, + int dotu); +int p9_deserialize_fcall(void *buf, u32 buflen, struct p9_fcall *fc, int dotu); +void p9_set_tag(struct p9_fcall *fc, u16 tag); +struct p9_fcall *p9_create_tversion(u32 msize, char *version); +struct p9_fcall *p9_create_tattach(u32 fid, u32 afid, char *uname, + char *aname); +struct p9_fcall *p9_create_tauth(u32 afid, char *uname, char *aname); +struct p9_fcall *p9_create_tflush(u16 oldtag); +struct p9_fcall *p9_create_twalk(u32 fid, u32 newfid, u16 nwname, + char **wnames); +struct p9_fcall *p9_create_topen(u32 fid, u8 mode); +struct p9_fcall *p9_create_tcreate(u32 fid, char *name, u32 perm, u8 mode, + char *extension, int dotu); +struct p9_fcall *p9_create_tread(u32 fid, u64 offset, u32 count); +struct p9_fcall *p9_create_twrite(u32 fid, u64 offset, u32 count, + const char *data); +struct p9_fcall *p9_create_twrite_u(u32 fid, u64 offset, u32 count, + const char __user *data); +struct p9_fcall *p9_create_tclunk(u32 fid); +struct p9_fcall *p9_create_tremove(u32 fid); +struct p9_fcall *p9_create_tstat(u32 fid); +struct p9_fcall *p9_create_twstat(u32 fid, struct p9_wstat *wstat, + int dotu); + +int p9_printfcall(char *buf, int buflen, struct p9_fcall *fc, int dotu); +int p9_errstr2errno(char *errstr, int len); + +struct p9_idpool *p9_idpool_create(void); +void p9_idpool_destroy(struct p9_idpool *); +int p9_idpool_get(struct p9_idpool *p); +void p9_idpool_put(int id, struct p9_idpool *p); +int p9_idpool_check(int id, struct p9_idpool *p); + +int p9_error_init(void); +int p9_errstr2errno(char *, int); +int __init p9_sysctl_register(void); +void __exit p9_sysctl_unregister(void); +#endif /* NET_9P_H */ diff --git a/include/net/9p/client.h b/include/net/9p/client.h new file mode 100644 index 000000000000..d65ed7c69063 --- /dev/null +++ b/include/net/9p/client.h @@ -0,0 +1,80 @@ +/* + * include/net/9p/client.h + * + * 9P Client Definitions + * + * Copyright (C) 2007 by Latchesar Ionkov <lucho@ionkov.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to: + * Free Software Foundation + * 51 Franklin Street, Fifth Floor + * Boston, MA 02111-1301 USA + * + */ + +#ifndef NET_9P_CLIENT_H +#define NET_9P_CLIENT_H + +struct p9_client { + spinlock_t lock; /* protect client structure */ + int msize; + unsigned char dotu; + struct p9_transport *trans; + struct p9_conn *conn; + + struct p9_idpool *fidpool; + struct list_head fidlist; +}; + +struct p9_fid { + struct p9_client *clnt; + u32 fid; + int mode; + struct p9_qid qid; + u32 iounit; + uid_t uid; + void *aux; + + int rdir_fpos; + int rdir_pos; + struct p9_fcall *rdir_fcall; + struct list_head flist; + struct list_head dlist; /* list of all fids attached to a dentry */ +}; + +struct p9_client *p9_client_create(struct p9_transport *trans, int msize, + int dotu); +void p9_client_destroy(struct p9_client *clnt); +void p9_client_disconnect(struct p9_client *clnt); +struct p9_fid *p9_client_attach(struct p9_client *clnt, struct p9_fid *afid, + char *uname, char *aname); +struct p9_fid *p9_client_auth(struct p9_client *clnt, char *uname, char *aname); +struct p9_fid *p9_client_walk(struct p9_fid *oldfid, int nwname, char **wnames, + int clone); +int p9_client_open(struct p9_fid *fid, int mode); +int p9_client_fcreate(struct p9_fid *fid, char *name, u32 perm, int mode, + char *extension); +int p9_client_clunk(struct p9_fid *fid); +int p9_client_remove(struct p9_fid *fid); +int p9_client_read(struct p9_fid *fid, char *data, u64 offset, u32 count); +int p9_client_readn(struct p9_fid *fid, char *data, u64 offset, u32 count); +int p9_client_write(struct p9_fid *fid, char *data, u64 offset, u32 count); +int p9_client_uread(struct p9_fid *fid, char __user *data, u64 offset, + u32 count); +int p9_client_uwrite(struct p9_fid *fid, const char __user *data, u64 offset, + u32 count); +struct p9_stat *p9_client_stat(struct p9_fid *fid); +int p9_client_wstat(struct p9_fid *fid, struct p9_wstat *wst); +struct p9_stat *p9_client_dirread(struct p9_fid *fid, u64 offset); + +#endif /* NET_9P_CLIENT_H */ diff --git a/include/net/9p/conn.h b/include/net/9p/conn.h new file mode 100644 index 000000000000..583b6a2cb3df --- /dev/null +++ b/include/net/9p/conn.h @@ -0,0 +1,57 @@ +/* + * include/net/9p/conn.h + * + * Connection Definitions + * + * Copyright (C) 2005 by Latchesar Ionkov <lucho@ionkov.net> + * Copyright (C) 2004 by Eric Van Hensbergen <ericvh@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to: + * Free Software Foundation + * 51 Franklin Street, Fifth Floor + * Boston, MA 02111-1301 USA + * + */ + +#ifndef NET_9P_CONN_H +#define NET_9P_CONN_H + +#undef P9_NONBLOCK + +struct p9_conn; +struct p9_req; + +/** + * p9_mux_req_callback - callback function that is called when the + * response of a request is received. The callback is called from + * a workqueue and shouldn't block. + * + * @req - request + * @a - the pointer that was specified when the request was send to be + * passed to the callback + */ +typedef void (*p9_conn_req_callback)(struct p9_req *req, void *a); + +struct p9_conn *p9_conn_create(struct p9_transport *trans, int msize, + unsigned char *dotu); +void p9_conn_destroy(struct p9_conn *); +int p9_conn_rpc(struct p9_conn *m, struct p9_fcall *tc, struct p9_fcall **rc); + +#ifdef P9_NONBLOCK +int p9_conn_rpcnb(struct p9_conn *m, struct p9_fcall *tc, + p9_conn_req_callback cb, void *a); +#endif /* P9_NONBLOCK */ + +void p9_conn_cancel(struct p9_conn *m, int err); + +#endif /* NET_9P_CONN_H */ diff --git a/include/net/9p/transport.h b/include/net/9p/transport.h new file mode 100644 index 000000000000..462d42279fb0 --- /dev/null +++ b/include/net/9p/transport.h @@ -0,0 +1,49 @@ +/* + * include/net/9p/transport.h + * + * Transport Definition + * + * Copyright (C) 2005 by Latchesar Ionkov <lucho@ionkov.net> + * Copyright (C) 2004 by Eric Van Hensbergen <ericvh@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to: + * Free Software Foundation + * 51 Franklin Street, Fifth Floor + * Boston, MA 02111-1301 USA + * + */ + +#ifndef NET_9P_TRANSPORT_H +#define NET_9P_TRANSPORT_H + +enum p9_transport_status { + Connected, + Disconnected, + Hung, +}; + +struct p9_transport { + enum p9_transport_status status; + void *priv; + + int (*write) (struct p9_transport *, void *, int); + int (*read) (struct p9_transport *, void *, int); + void (*close) (struct p9_transport *); + unsigned int (*poll)(struct p9_transport *, struct poll_table_struct *); +}; + +struct p9_transport *p9_trans_create_tcp(const char *addr, int port); +struct p9_transport *p9_trans_create_unix(const char *addr); +struct p9_transport *p9_trans_create_fd(int rfd, int wfd); + +#endif /* NET_9P_TRANSPORT_H */ diff --git a/include/net/act_api.h b/include/net/act_api.h index 8b06c2f3657f..68b4eaf7719d 100644 --- a/include/net/act_api.h +++ b/include/net/act_api.h @@ -19,7 +19,6 @@ struct tcf_common { struct gnet_stats_basic tcfc_bstats; struct gnet_stats_queue tcfc_qstats; struct gnet_stats_rate_est tcfc_rate_est; - spinlock_t *tcfc_stats_lock; spinlock_t tcfc_lock; }; #define tcf_next common.tcfc_next @@ -32,7 +31,6 @@ struct tcf_common { #define tcf_bstats common.tcfc_bstats #define tcf_qstats common.tcfc_qstats #define tcf_rate_est common.tcfc_rate_est -#define tcf_stats_lock common.tcfc_stats_lock #define tcf_lock common.tcfc_lock struct tcf_police { @@ -123,34 +121,4 @@ extern int tcf_action_dump_old(struct sk_buff *skb, struct tc_action *a, int, in extern int tcf_action_dump_1(struct sk_buff *skb, struct tc_action *a, int, int); extern int tcf_action_copy_stats (struct sk_buff *,struct tc_action *, int); #endif /* CONFIG_NET_CLS_ACT */ - -extern int tcf_police(struct sk_buff *skb, struct tcf_police *p); -extern void tcf_police_destroy(struct tcf_police *p); -extern struct tcf_police * tcf_police_locate(struct rtattr *rta, struct rtattr *est); -extern int tcf_police_dump(struct sk_buff *skb, struct tcf_police *p); -extern int tcf_police_dump_stats(struct sk_buff *skb, struct tcf_police *p); - -static inline int -tcf_police_release(struct tcf_police *p, int bind) -{ - int ret = 0; -#ifdef CONFIG_NET_CLS_ACT - if (p) { - if (bind) - p->tcf_bindcnt--; - - p->tcf_refcnt--; - if (p->tcf_refcnt <= 0 && !p->tcf_bindcnt) { - tcf_police_destroy(p); - ret = 1; - } - } -#else - if (p && --p->tcf_refcnt == 0) - tcf_police_destroy(p); - -#endif /* CONFIG_NET_CLS_ACT */ - return ret; -} - #endif diff --git a/include/net/addrconf.h b/include/net/addrconf.h index f3531d0bcd05..33b593e17441 100644 --- a/include/net/addrconf.h +++ b/include/net/addrconf.h @@ -61,7 +61,7 @@ extern int addrconf_set_dstaddr(void __user *arg); extern int ipv6_chk_addr(struct in6_addr *addr, struct net_device *dev, int strict); -#ifdef CONFIG_IPV6_MIP6 +#if defined(CONFIG_IPV6_MIP6) || defined(CONFIG_IPV6_MIP6_MODULE) extern int ipv6_chk_home_addr(struct in6_addr *addr); #endif extern struct inet6_ifaddr * ipv6_get_ifaddr(struct in6_addr *addr, diff --git a/include/net/af_unix.h b/include/net/af_unix.h index 65f49fd7deff..6de1e9e35c73 100644 --- a/include/net/af_unix.h +++ b/include/net/af_unix.h @@ -79,9 +79,10 @@ struct unix_sock { struct mutex readlock; struct sock *peer; struct sock *other; - struct sock *gc_tree; + struct list_head link; atomic_t inflight; spinlock_t lock; + unsigned int gc_candidate : 1; wait_queue_head_t peer_wait; }; #define unix_sk(__sk) ((struct unix_sock *)__sk) diff --git a/include/net/bluetooth/hci.h b/include/net/bluetooth/hci.h index 93ce272a5d27..ebfb96b41106 100644 --- a/include/net/bluetooth/hci.h +++ b/include/net/bluetooth/hci.h @@ -107,14 +107,14 @@ enum { #define HCI_IDLE_TIMEOUT (6000) /* 6 seconds */ #define HCI_INIT_TIMEOUT (10000) /* 10 seconds */ -/* HCI Packet types */ +/* HCI data types */ #define HCI_COMMAND_PKT 0x01 #define HCI_ACLDATA_PKT 0x02 #define HCI_SCODATA_PKT 0x03 #define HCI_EVENT_PKT 0x04 #define HCI_VENDOR_PKT 0xff -/* HCI Packet types */ +/* HCI packet types */ #define HCI_DM1 0x0008 #define HCI_DM3 0x0400 #define HCI_DM5 0x4000 @@ -129,6 +129,14 @@ enum { #define SCO_PTYPE_MASK (HCI_HV1 | HCI_HV2 | HCI_HV3) #define ACL_PTYPE_MASK (~SCO_PTYPE_MASK) +/* eSCO packet types */ +#define ESCO_HV1 0x0001 +#define ESCO_HV2 0x0002 +#define ESCO_HV3 0x0004 +#define ESCO_EV3 0x0008 +#define ESCO_EV4 0x0010 +#define ESCO_EV5 0x0020 + /* ACL flags */ #define ACL_CONT 0x01 #define ACL_START 0x02 @@ -138,6 +146,7 @@ enum { /* Baseband links */ #define SCO_LINK 0x00 #define ACL_LINK 0x01 +#define ESCO_LINK 0x02 /* LMP features */ #define LMP_3SLOT 0x01 @@ -162,6 +171,11 @@ enum { #define LMP_PSCHEME 0x02 #define LMP_PCONTROL 0x04 +#define LMP_ESCO 0x80 + +#define LMP_EV4 0x01 +#define LMP_EV5 0x02 + #define LMP_SNIFF_SUBR 0x02 /* Connection modes */ diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h index c0fc39620f36..8f67c8a7169b 100644 --- a/include/net/bluetooth/hci_core.h +++ b/include/net/bluetooth/hci_core.h @@ -78,6 +78,7 @@ struct hci_dev { __u16 voice_setting; __u16 pkt_type; + __u16 esco_type; __u16 link_policy; __u16 link_mode; @@ -109,6 +110,7 @@ struct hci_dev { struct sk_buff_head cmd_q; struct sk_buff *sent_cmd; + struct sk_buff *reassembly[3]; struct semaphore req_lock; wait_queue_head_t req_wait_q; @@ -437,6 +439,8 @@ static inline int hci_recv_frame(struct sk_buff *skb) return 0; } +int hci_recv_fragment(struct hci_dev *hdev, int type, void *data, int count); + int hci_register_sysfs(struct hci_dev *hdev); void hci_unregister_sysfs(struct hci_dev *hdev); void hci_conn_add_sysfs(struct hci_conn *conn); @@ -449,6 +453,7 @@ void hci_conn_del_sysfs(struct hci_conn *conn); #define lmp_encrypt_capable(dev) ((dev)->features[0] & LMP_ENCRYPT) #define lmp_sniff_capable(dev) ((dev)->features[0] & LMP_SNIFF) #define lmp_sniffsubr_capable(dev) ((dev)->features[5] & LMP_SNIFF_SUBR) +#define lmp_esco_capable(dev) ((dev)->features[3] & LMP_ESCO) /* ----- HCI protocols ----- */ struct hci_proto { diff --git a/include/net/bluetooth/rfcomm.h b/include/net/bluetooth/rfcomm.h index 3c563f02907c..25aa575db807 100644 --- a/include/net/bluetooth/rfcomm.h +++ b/include/net/bluetooth/rfcomm.h @@ -323,6 +323,7 @@ int rfcomm_connect_ind(struct rfcomm_session *s, u8 channel, struct rfcomm_dlc #define RFCOMM_RELEASE_ONHUP 1 #define RFCOMM_HANGUP_NOW 2 #define RFCOMM_TTY_ATTACHED 3 +#define RFCOMM_TTY_RELEASED 4 struct rfcomm_dev_req { s16 dev_id; diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h index 88171f8ce58a..7edaef6b29d6 100644 --- a/include/net/cfg80211.h +++ b/include/net/cfg80211.h @@ -11,6 +11,44 @@ * Copyright 2006 Johannes Berg <johannes@sipsolutions.net> */ + +/* Radiotap header iteration + * implemented in net/wireless/radiotap.c + * docs in Documentation/networking/radiotap-headers.txt + */ +/** + * struct ieee80211_radiotap_iterator - tracks walk thru present radiotap args + * @rtheader: pointer to the radiotap header we are walking through + * @max_length: length of radiotap header in cpu byte ordering + * @this_arg_index: IEEE80211_RADIOTAP_... index of current arg + * @this_arg: pointer to current radiotap arg + * @arg_index: internal next argument index + * @arg: internal next argument pointer + * @next_bitmap: internal pointer to next present u32 + * @bitmap_shifter: internal shifter for curr u32 bitmap, b0 set == arg present + */ + +struct ieee80211_radiotap_iterator { + struct ieee80211_radiotap_header *rtheader; + int max_length; + int this_arg_index; + u8 *this_arg; + + int arg_index; + u8 *arg; + __le32 *next_bitmap; + u32 bitmap_shifter; +}; + +extern int ieee80211_radiotap_iterator_init( + struct ieee80211_radiotap_iterator *iterator, + struct ieee80211_radiotap_header *radiotap_header, + int max_length); + +extern int ieee80211_radiotap_iterator_next( + struct ieee80211_radiotap_iterator *iterator); + + /* from net/wireless.h */ struct wiphy; diff --git a/include/net/dn.h b/include/net/dn.h index ac4ce9091747..627778384c84 100644 --- a/include/net/dn.h +++ b/include/net/dn.h @@ -3,7 +3,6 @@ #include <linux/dn.h> #include <net/sock.h> -#include <net/tcp.h> #include <asm/byteorder.h> #define dn_ntohs(x) le16_to_cpu(x) diff --git a/include/net/dst.h b/include/net/dst.h index 82270f9332db..e9ff4a4caef9 100644 --- a/include/net/dst.h +++ b/include/net/dst.h @@ -47,7 +47,6 @@ struct dst_entry #define DST_NOXFRM 2 #define DST_NOPOLICY 4 #define DST_NOHASH 8 -#define DST_BALANCED 0x10 unsigned long expires; unsigned short header_len; /* more space at head required */ diff --git a/include/net/flow.h b/include/net/flow.h index f3cc1f812619..af59fa5cc1f8 100644 --- a/include/net/flow.h +++ b/include/net/flow.h @@ -67,20 +67,16 @@ struct flowi { __be32 spi; -#ifdef CONFIG_IPV6_MIP6 struct { __u8 type; } mht; -#endif } uli_u; #define fl_ip_sport uli_u.ports.sport #define fl_ip_dport uli_u.ports.dport #define fl_icmp_type uli_u.icmpt.type #define fl_icmp_code uli_u.icmpt.code #define fl_ipsec_spi uli_u.spi -#ifdef CONFIG_IPV6_MIP6 #define fl_mh_type uli_u.mht.type -#endif __u32 secid; /* used by xfrm; see secid.txt */ } __attribute__((__aligned__(BITS_PER_LONG/8))); diff --git a/include/net/inet_timewait_sock.h b/include/net/inet_timewait_sock.h index 09a2532699b2..47d52b2414db 100644 --- a/include/net/inet_timewait_sock.h +++ b/include/net/inet_timewait_sock.h @@ -209,9 +209,6 @@ static inline void inet_twsk_put(struct inet_timewait_sock *tw) extern struct inet_timewait_sock *inet_twsk_alloc(const struct sock *sk, const int state); -extern void __inet_twsk_kill(struct inet_timewait_sock *tw, - struct inet_hashinfo *hashinfo); - extern void __inet_twsk_hashdance(struct inet_timewait_sock *tw, struct sock *sk, struct inet_hashinfo *hashinfo); diff --git a/include/net/ip_fib.h b/include/net/ip_fib.h index 69252cbe05b0..8cadc77c7df4 100644 --- a/include/net/ip_fib.h +++ b/include/net/ip_fib.h @@ -39,7 +39,6 @@ struct fib_config { int fc_mx_len; int fc_mp_len; u32 fc_flow; - u32 fc_mp_alg; u32 fc_nlflags; struct nl_info fc_nlinfo; }; @@ -86,9 +85,6 @@ struct fib_info { #ifdef CONFIG_IP_ROUTE_MULTIPATH int fib_power; #endif -#ifdef CONFIG_IP_ROUTE_MULTIPATH_CACHED - u32 fib_mp_alg; -#endif struct fib_nh fib_nh[0]; #define fib_dev fib_nh[0].nh_dev }; @@ -103,10 +99,6 @@ struct fib_result { unsigned char nh_sel; unsigned char type; unsigned char scope; -#ifdef CONFIG_IP_ROUTE_MULTIPATH_CACHED - __be32 network; - __be32 netmask; -#endif struct fib_info *fi; #ifdef CONFIG_IP_MULTIPLE_TABLES struct fib_rule *r; @@ -145,14 +137,6 @@ struct fib_result_nl { #define FIB_RES_DEV(res) (FIB_RES_NH(res).nh_dev) #define FIB_RES_OIF(res) (FIB_RES_NH(res).nh_oif) -#ifdef CONFIG_IP_ROUTE_MULTIPATH_CACHED -#define FIB_RES_NETWORK(res) ((res).network) -#define FIB_RES_NETMASK(res) ((res).netmask) -#else /* CONFIG_IP_ROUTE_MULTIPATH_CACHED */ -#define FIB_RES_NETWORK(res) (0) -#define FIB_RES_NETMASK(res) (0) -#endif /* CONFIG_IP_ROUTE_MULTIPATH_WRANDOM */ - struct fib_table { struct hlist_node tb_hlist; u32 tb_id; diff --git a/include/net/ip_mp_alg.h b/include/net/ip_mp_alg.h deleted file mode 100644 index 25b56571e54b..000000000000 --- a/include/net/ip_mp_alg.h +++ /dev/null @@ -1,96 +0,0 @@ -/* ip_mp_alg.h: IPV4 multipath algorithm support. - * - * Copyright (C) 2004, 2005 Einar Lueck <elueck@de.ibm.com> - * Copyright (C) 2005 David S. Miller <davem@davemloft.net> - */ - -#ifndef _NET_IP_MP_ALG_H -#define _NET_IP_MP_ALG_H - -#include <linux/ip_mp_alg.h> -#include <net/flow.h> -#include <net/route.h> - -struct fib_nh; - -struct ip_mp_alg_ops { - void (*mp_alg_select_route)(const struct flowi *flp, - struct rtable *rth, struct rtable **rp); - void (*mp_alg_flush)(void); - void (*mp_alg_set_nhinfo)(__be32 network, __be32 netmask, - unsigned char prefixlen, - const struct fib_nh *nh); - void (*mp_alg_remove)(struct rtable *rth); -}; - -extern int multipath_alg_register(struct ip_mp_alg_ops *, enum ip_mp_alg); -extern void multipath_alg_unregister(struct ip_mp_alg_ops *, enum ip_mp_alg); - -extern struct ip_mp_alg_ops *ip_mp_alg_table[]; - -static inline int multipath_select_route(const struct flowi *flp, - struct rtable *rth, - struct rtable **rp) -{ -#ifdef CONFIG_IP_ROUTE_MULTIPATH_CACHED - struct ip_mp_alg_ops *ops = ip_mp_alg_table[rth->rt_multipath_alg]; - - /* mp_alg_select_route _MUST_ be implemented */ - if (ops && (rth->u.dst.flags & DST_BALANCED)) { - ops->mp_alg_select_route(flp, rth, rp); - return 1; - } -#endif - return 0; -} - -static inline void multipath_flush(void) -{ -#ifdef CONFIG_IP_ROUTE_MULTIPATH_CACHED - int i; - - for (i = IP_MP_ALG_NONE; i <= IP_MP_ALG_MAX; i++) { - struct ip_mp_alg_ops *ops = ip_mp_alg_table[i]; - - if (ops && ops->mp_alg_flush) - ops->mp_alg_flush(); - } -#endif -} - -static inline void multipath_set_nhinfo(struct rtable *rth, - __be32 network, __be32 netmask, - unsigned char prefixlen, - const struct fib_nh *nh) -{ -#ifdef CONFIG_IP_ROUTE_MULTIPATH_CACHED - struct ip_mp_alg_ops *ops = ip_mp_alg_table[rth->rt_multipath_alg]; - - if (ops && ops->mp_alg_set_nhinfo) - ops->mp_alg_set_nhinfo(network, netmask, prefixlen, nh); -#endif -} - -static inline void multipath_remove(struct rtable *rth) -{ -#ifdef CONFIG_IP_ROUTE_MULTIPATH_CACHED - struct ip_mp_alg_ops *ops = ip_mp_alg_table[rth->rt_multipath_alg]; - - if (ops && ops->mp_alg_remove && - (rth->u.dst.flags & DST_BALANCED)) - ops->mp_alg_remove(rth); -#endif -} - -static inline int multipath_comparekeys(const struct flowi *flp1, - const struct flowi *flp2) -{ - return flp1->fl4_dst == flp2->fl4_dst && - flp1->fl4_src == flp2->fl4_src && - flp1->oif == flp2->oif && - flp1->mark == flp2->mark && - !((flp1->fl4_tos ^ flp2->fl4_tos) & - (IPTOS_RT_MASK | RTO_ONLINK)); -} - -#endif /* _NET_IP_MP_ALG_H */ diff --git a/include/net/ipv6.h b/include/net/ipv6.h index 78a0d06d98d5..46b9dce82f6e 100644 --- a/include/net/ipv6.h +++ b/include/net/ipv6.h @@ -512,10 +512,6 @@ extern int ipv6_ext_hdr(u8 nexthdr); extern int ipv6_find_tlv(struct sk_buff *skb, int offset, int type); -extern struct ipv6_txoptions * ipv6_invert_rthdr(struct sock *sk, - struct ipv6_rt_hdr *hdr); - - /* * socket options (ipv6_sockglue.c) */ diff --git a/include/net/irda/irda.h b/include/net/irda/irda.h index 36bee441aa56..08387553b57e 100644 --- a/include/net/irda/irda.h +++ b/include/net/irda/irda.h @@ -125,6 +125,9 @@ extern void irda_sysctl_unregister(void); extern int irsock_init(void); extern void irsock_cleanup(void); +extern int irda_nl_register(void); +extern void irda_nl_unregister(void); + extern int irlap_driver_rcv(struct sk_buff *skb, struct net_device *dev, struct packet_type *ptype, struct net_device *orig_dev); diff --git a/include/net/irda/irlap.h b/include/net/irda/irlap.h index a3d370efb903..9d0c78ea92f5 100644 --- a/include/net/irda/irlap.h +++ b/include/net/irda/irlap.h @@ -208,6 +208,8 @@ struct irlap_cb { int xbofs_delay; /* Nr of XBOF's used to MTT */ int bofs_count; /* Negotiated extra BOFs */ int next_bofs; /* Negotiated extra BOFs after next frame */ + + int mode; /* IrLAP mode (primary, secondary or monitor) */ }; /* diff --git a/include/net/iucv/af_iucv.h b/include/net/iucv/af_iucv.h index f9bd11be1891..b6c468cd7f5b 100644 --- a/include/net/iucv/af_iucv.h +++ b/include/net/iucv/af_iucv.h @@ -60,6 +60,7 @@ struct iucv_sock { char dst_user_id[8]; char dst_name[8]; struct list_head accept_q; + spinlock_t accept_q_lock; struct sock *parent; struct iucv_path *path; struct sk_buff_head send_skb_q; diff --git a/include/net/mac80211.h b/include/net/mac80211.h index a7f122b79948..c34fd9a6160a 100644 --- a/include/net/mac80211.h +++ b/include/net/mac80211.h @@ -347,9 +347,16 @@ enum ieee80211_if_types { * @mac_addr: pointer to MAC address of the interface. This pointer is valid * until the interface is removed (i.e. it cannot be used after * remove_interface() callback was called for this interface). + * This pointer will be %NULL for monitor interfaces, be careful. * * This structure is used in add_interface() and remove_interface() * callbacks of &struct ieee80211_hw. + * + * When you allow multiple interfaces to be added to your PHY, take care + * that the hardware can actually handle multiple MAC addresses. However, + * also take care that when there's no interface left with mac_addr != %NULL + * you remove the MAC address from the device to avoid acknowledging packets + * in pure monitor mode. */ struct ieee80211_if_init_conf { int if_id; @@ -574,10 +581,11 @@ struct ieee80211_ops { * to returning zero. By returning non-zero addition of the interface * is inhibited. Unless monitor_during_oper is set, it is guaranteed * that monitor interfaces and normal interfaces are mutually - * exclusive. The open() handler is called after add_interface() - * if this is the first device added. At least one of the open() - * open() and add_interface() callbacks has to be assigned. If - * add_interface() is NULL, one STA interface is permitted only. */ + * exclusive. If assigned, the open() handler is called after + * add_interface() if this is the first device added. The + * add_interface() callback has to be assigned because it is the only + * way to obtain the requested MAC address for any interface. + */ int (*add_interface)(struct ieee80211_hw *hw, struct ieee80211_if_init_conf *conf); @@ -921,12 +929,6 @@ struct sk_buff * ieee80211_get_buffered_bc(struct ieee80211_hw *hw, int if_id, struct ieee80211_tx_control *control); -/* Low level drivers that have their own MLME and MAC indicate - * the aid for an associating station with this call */ -int ieee80211_set_aid_for_sta(struct ieee80211_hw *hw, - u8 *peer_address, u16 aid); - - /* Given an sk_buff with a raw 802.11 header at the data pointer this function * returns the 802.11 header length in bytes (not including encryption * headers). If the data in the sk_buff is too short to contain a valid 802.11 diff --git a/include/net/mip6.h b/include/net/mip6.h index 68263c6d9996..63272610a24a 100644 --- a/include/net/mip6.h +++ b/include/net/mip6.h @@ -54,8 +54,4 @@ struct ip6_mh { #define IP6_MH_TYPE_BERROR 7 /* Binding Error */ #define IP6_MH_TYPE_MAX IP6_MH_TYPE_BERROR -extern int mip6_init(void); -extern void mip6_fini(void); -extern int mip6_mh_filter(struct sock *sk, struct sk_buff *skb); - #endif diff --git a/include/net/netfilter/ipv4/nf_conntrack_ipv4.h b/include/net/netfilter/ipv4/nf_conntrack_ipv4.h index 1401ccc051c4..7a671603fca6 100644 --- a/include/net/netfilter/ipv4/nf_conntrack_ipv4.h +++ b/include/net/netfilter/ipv4/nf_conntrack_ipv4.h @@ -9,29 +9,10 @@ #ifndef _NF_CONNTRACK_IPV4_H #define _NF_CONNTRACK_IPV4_H -#ifdef CONFIG_NF_NAT_NEEDED -#include <net/netfilter/nf_nat.h> -#include <linux/netfilter/nf_conntrack_pptp.h> - -/* per conntrack: nat application helper private data */ -union nf_conntrack_nat_help { - /* insert nat helper private data here */ - struct nf_nat_pptp nat_pptp_info; -}; - -struct nf_conn_nat { - struct nf_nat_info info; - union nf_conntrack_nat_help help; -#if defined(CONFIG_IP_NF_TARGET_MASQUERADE) || \ - defined(CONFIG_IP_NF_TARGET_MASQUERADE_MODULE) - int masq_index; -#endif -}; -#endif /* CONFIG_NF_NAT_NEEDED */ - /* Returns new sk_buff, or NULL */ -struct sk_buff * -nf_ct_ipv4_ct_gather_frags(struct sk_buff *skb); +struct sk_buff *nf_ct_ipv4_ct_gather_frags(struct sk_buff *skb); + +extern struct nf_conntrack_l3proto nf_conntrack_l3proto_ipv4; extern struct nf_conntrack_l4proto nf_conntrack_l4proto_tcp4; extern struct nf_conntrack_l4proto nf_conntrack_l4proto_udp4; diff --git a/include/net/netfilter/ipv6/nf_conntrack_ipv6.h b/include/net/netfilter/ipv6/nf_conntrack_ipv6.h index b4b6049e01fa..5a8965904377 100644 --- a/include/net/netfilter/ipv6/nf_conntrack_ipv6.h +++ b/include/net/netfilter/ipv6/nf_conntrack_ipv6.h @@ -7,7 +7,7 @@ extern struct nf_conntrack_l4proto nf_conntrack_l4proto_tcp6; extern struct nf_conntrack_l4proto nf_conntrack_l4proto_udp6; extern struct nf_conntrack_l4proto nf_conntrack_l4proto_icmpv6; -extern int nf_ct_ipv6_skip_exthdr(struct sk_buff *skb, int start, +extern int nf_ct_ipv6_skip_exthdr(const struct sk_buff *skb, int start, u8 *nexthdrp, int len); extern int nf_ct_frag6_init(void); diff --git a/include/net/netfilter/nf_conntrack.h b/include/net/netfilter/nf_conntrack.h index 4732432f8eb0..810020ec345d 100644 --- a/include/net/netfilter/nf_conntrack.h +++ b/include/net/netfilter/nf_conntrack.h @@ -82,6 +82,8 @@ struct nf_conn_help { union nf_conntrack_help help; + struct hlist_head expectations; + /* Current number of expected connections */ unsigned int expecting; }; @@ -117,9 +119,6 @@ struct nf_conn /* Unique ID that identifies this conntrack*/ unsigned int id; - /* features - nat, helper, ... used by allocating system */ - u_int32_t features; - #if defined(CONFIG_NF_CONNTRACK_MARK) u_int32_t mark; #endif @@ -131,8 +130,8 @@ struct nf_conn /* Storage reserved for other modules: */ union nf_conntrack_proto proto; - /* features dynamically at the end: helper, nat (both optional) */ - char data[0]; + /* Extensions */ + struct nf_ct_ext *ext; }; static inline struct nf_conn * @@ -175,6 +174,10 @@ static inline void nf_ct_put(struct nf_conn *ct) extern int nf_ct_l3proto_try_module_get(unsigned short l3proto); extern void nf_ct_l3proto_module_put(unsigned short l3proto); +extern struct hlist_head *nf_ct_alloc_hashtable(int *sizep, int *vmalloced); +extern void nf_ct_free_hashtable(struct hlist_head *hash, int vmalloced, + int size); + extern struct nf_conntrack_tuple_hash * __nf_conntrack_find(const struct nf_conntrack_tuple *tuple, const struct nf_conn *ignored_conntrack); @@ -183,6 +186,10 @@ extern void nf_conntrack_hash_insert(struct nf_conn *ct); extern void nf_conntrack_flush(void); +extern int nf_ct_get_tuplepr(const struct sk_buff *skb, + unsigned int nhoff, + u_int16_t l3num, + struct nf_conntrack_tuple *tuple); extern int nf_ct_invert_tuplepr(struct nf_conntrack_tuple *inverse, const struct nf_conntrack_tuple *orig); @@ -216,9 +223,6 @@ extern void nf_conntrack_tcp_update(struct sk_buff *skb, struct nf_conn *conntrack, int dir); -/* Call me when a conntrack is destroyed. */ -extern void (*nf_conntrack_destroyed)(struct nf_conn *conntrack); - /* Fake conntrack entry for untracked connections */ extern struct nf_conn nf_conntrack_untracked; @@ -262,60 +266,10 @@ do { \ local_bh_enable(); \ } while (0) -/* no helper, no nat */ -#define NF_CT_F_BASIC 0 -/* for helper */ -#define NF_CT_F_HELP 1 -/* for nat. */ -#define NF_CT_F_NAT 2 -#define NF_CT_F_NUM 4 - extern int nf_conntrack_register_cache(u_int32_t features, const char *name, size_t size); extern void nf_conntrack_unregister_cache(u_int32_t features); -/* valid combinations: - * basic: nf_conn, nf_conn .. nf_conn_help - * nat: nf_conn .. nf_conn_nat, nf_conn .. nf_conn_nat .. nf_conn help - */ -#ifdef CONFIG_NF_NAT_NEEDED -static inline struct nf_conn_nat *nfct_nat(const struct nf_conn *ct) -{ - unsigned int offset = sizeof(struct nf_conn); - - if (!(ct->features & NF_CT_F_NAT)) - return NULL; - - offset = ALIGN(offset, __alignof__(struct nf_conn_nat)); - return (struct nf_conn_nat *) ((void *)ct + offset); -} - -static inline struct nf_conn_help *nfct_help(const struct nf_conn *ct) -{ - unsigned int offset = sizeof(struct nf_conn); - - if (!(ct->features & NF_CT_F_HELP)) - return NULL; - if (ct->features & NF_CT_F_NAT) { - offset = ALIGN(offset, __alignof__(struct nf_conn_nat)); - offset += sizeof(struct nf_conn_nat); - } - - offset = ALIGN(offset, __alignof__(struct nf_conn_help)); - return (struct nf_conn_help *) ((void *)ct + offset); -} -#else /* No NAT */ -static inline struct nf_conn_help *nfct_help(const struct nf_conn *ct) -{ - unsigned int offset = sizeof(struct nf_conn); - - if (!(ct->features & NF_CT_F_HELP)) - return NULL; - - offset = ALIGN(offset, __alignof__(struct nf_conn_help)); - return (struct nf_conn_help *) ((void *)ct + offset); -} -#endif /* CONFIG_NF_NAT_NEEDED */ #endif /* __KERNEL__ */ #endif /* _NF_CONNTRACK_H */ diff --git a/include/net/netfilter/nf_conntrack_core.h b/include/net/netfilter/nf_conntrack_core.h index 9fb906688ffa..4056f5f08da1 100644 --- a/include/net/netfilter/nf_conntrack_core.h +++ b/include/net/netfilter/nf_conntrack_core.h @@ -30,6 +30,9 @@ extern void nf_conntrack_cleanup(void); extern int nf_conntrack_proto_init(void); extern void nf_conntrack_proto_fini(void); +extern int nf_conntrack_helper_init(void); +extern void nf_conntrack_helper_fini(void); + struct nf_conntrack_l3proto; extern struct nf_conntrack_l3proto *nf_ct_find_l3proto(u_int16_t pf); /* Like above, but you already have conntrack read lock. */ @@ -55,8 +58,7 @@ nf_ct_invert_tuple(struct nf_conntrack_tuple *inverse, /* Find a connection corresponding to a tuple. */ extern struct nf_conntrack_tuple_hash * -nf_conntrack_find_get(const struct nf_conntrack_tuple *tuple, - const struct nf_conn *ignored_conntrack); +nf_conntrack_find_get(const struct nf_conntrack_tuple *tuple); extern int __nf_conntrack_confirm(struct sk_buff **pskb); @@ -81,9 +83,8 @@ print_tuple(struct seq_file *s, const struct nf_conntrack_tuple *tuple, struct nf_conntrack_l3proto *l3proto, struct nf_conntrack_l4proto *proto); -extern struct list_head *nf_conntrack_hash; -extern struct list_head nf_conntrack_expect_list; +extern struct hlist_head *nf_conntrack_hash; extern rwlock_t nf_conntrack_lock ; -extern struct list_head unconfirmed; +extern struct hlist_head unconfirmed; #endif /* _NF_CONNTRACK_CORE_H */ diff --git a/include/net/netfilter/nf_conntrack_ecache.h b/include/net/netfilter/nf_conntrack_ecache.h index 811c9073c532..f0b9078235c9 100644 --- a/include/net/netfilter/nf_conntrack_ecache.h +++ b/include/net/netfilter/nf_conntrack_ecache.h @@ -49,15 +49,15 @@ static inline void nf_conntrack_event(enum ip_conntrack_events event, atomic_notifier_call_chain(&nf_conntrack_chain, event, ct); } -extern struct atomic_notifier_head nf_conntrack_expect_chain; -extern int nf_conntrack_expect_register_notifier(struct notifier_block *nb); -extern int nf_conntrack_expect_unregister_notifier(struct notifier_block *nb); +extern struct atomic_notifier_head nf_ct_expect_chain; +extern int nf_ct_expect_register_notifier(struct notifier_block *nb); +extern int nf_ct_expect_unregister_notifier(struct notifier_block *nb); static inline void -nf_conntrack_expect_event(enum ip_conntrack_expect_events event, - struct nf_conntrack_expect *exp) +nf_ct_expect_event(enum ip_conntrack_expect_events event, + struct nf_conntrack_expect *exp) { - atomic_notifier_call_chain(&nf_conntrack_expect_chain, event, exp); + atomic_notifier_call_chain(&nf_ct_expect_chain, event, exp); } #else /* CONFIG_NF_CONNTRACK_EVENTS */ @@ -67,9 +67,8 @@ static inline void nf_conntrack_event_cache(enum ip_conntrack_events event, static inline void nf_conntrack_event(enum ip_conntrack_events event, struct nf_conn *ct) {} static inline void nf_ct_deliver_cached_events(const struct nf_conn *ct) {} -static inline void -nf_conntrack_expect_event(enum ip_conntrack_expect_events event, - struct nf_conntrack_expect *exp) {} +static inline void nf_ct_expect_event(enum ip_conntrack_expect_events event, + struct nf_conntrack_expect *exp) {} static inline void nf_ct_event_cache_flush(void) {} #endif /* CONFIG_NF_CONNTRACK_EVENTS */ diff --git a/include/net/netfilter/nf_conntrack_expect.h b/include/net/netfilter/nf_conntrack_expect.h index 173c7c1eff23..cae1a0dce365 100644 --- a/include/net/netfilter/nf_conntrack_expect.h +++ b/include/net/netfilter/nf_conntrack_expect.h @@ -6,17 +6,21 @@ #define _NF_CONNTRACK_EXPECT_H #include <net/netfilter/nf_conntrack.h> -extern struct list_head nf_conntrack_expect_list; -extern struct kmem_cache *nf_conntrack_expect_cachep; -extern const struct file_operations exp_file_ops; +extern struct hlist_head *nf_ct_expect_hash; +extern unsigned int nf_ct_expect_hsize; +extern unsigned int nf_ct_expect_max; struct nf_conntrack_expect { - /* Internal linked list (global expectation list) */ - struct list_head list; + /* Conntrack expectation list member */ + struct hlist_node lnode; + + /* Hash member */ + struct hlist_node hnode; /* We expect this tuple, with the following mask */ - struct nf_conntrack_tuple tuple, mask; + struct nf_conntrack_tuple tuple; + struct nf_conntrack_tuple_mask mask; /* Function to call after setup and insertion */ void (*expectfn)(struct nf_conn *new, @@ -52,29 +56,31 @@ struct nf_conntrack_expect #define NF_CT_EXPECT_PERMANENT 0x1 +int nf_conntrack_expect_init(void); +void nf_conntrack_expect_fini(void); struct nf_conntrack_expect * -__nf_conntrack_expect_find(const struct nf_conntrack_tuple *tuple); +__nf_ct_expect_find(const struct nf_conntrack_tuple *tuple); struct nf_conntrack_expect * -nf_conntrack_expect_find_get(const struct nf_conntrack_tuple *tuple); +nf_ct_expect_find_get(const struct nf_conntrack_tuple *tuple); struct nf_conntrack_expect * -find_expectation(const struct nf_conntrack_tuple *tuple); +nf_ct_find_expectation(const struct nf_conntrack_tuple *tuple); void nf_ct_unlink_expect(struct nf_conntrack_expect *exp); void nf_ct_remove_expectations(struct nf_conn *ct); -void nf_conntrack_unexpect_related(struct nf_conntrack_expect *exp); +void nf_ct_unexpect_related(struct nf_conntrack_expect *exp); /* Allocate space for an expectation: this is mandatory before calling - nf_conntrack_expect_related. You will have to call put afterwards. */ -struct nf_conntrack_expect *nf_conntrack_expect_alloc(struct nf_conn *me); -void nf_conntrack_expect_init(struct nf_conntrack_expect *, int, - union nf_conntrack_address *, - union nf_conntrack_address *, - u_int8_t, __be16 *, __be16 *); -void nf_conntrack_expect_put(struct nf_conntrack_expect *exp); -int nf_conntrack_expect_related(struct nf_conntrack_expect *expect); + nf_ct_expect_related. You will have to call put afterwards. */ +struct nf_conntrack_expect *nf_ct_expect_alloc(struct nf_conn *me); +void nf_ct_expect_init(struct nf_conntrack_expect *, int, + union nf_conntrack_address *, + union nf_conntrack_address *, + u_int8_t, __be16 *, __be16 *); +void nf_ct_expect_put(struct nf_conntrack_expect *exp); +int nf_ct_expect_related(struct nf_conntrack_expect *expect); #endif /*_NF_CONNTRACK_EXPECT_H*/ diff --git a/include/net/netfilter/nf_conntrack_extend.h b/include/net/netfilter/nf_conntrack_extend.h new file mode 100644 index 000000000000..73b5711faf32 --- /dev/null +++ b/include/net/netfilter/nf_conntrack_extend.h @@ -0,0 +1,85 @@ +#ifndef _NF_CONNTRACK_EXTEND_H +#define _NF_CONNTRACK_EXTEND_H + +#include <net/netfilter/nf_conntrack.h> + +enum nf_ct_ext_id +{ + NF_CT_EXT_HELPER, + NF_CT_EXT_NAT, + NF_CT_EXT_NUM, +}; + +#define NF_CT_EXT_HELPER_TYPE struct nf_conn_help +#define NF_CT_EXT_NAT_TYPE struct nf_conn_nat + +/* Extensions: optional stuff which isn't permanently in struct. */ +struct nf_ct_ext { + u8 offset[NF_CT_EXT_NUM]; + u8 len; + u8 real_len; + char data[0]; +}; + +static inline int nf_ct_ext_exist(const struct nf_conn *ct, u8 id) +{ + return (ct->ext && ct->ext->offset[id]); +} + +static inline void *__nf_ct_ext_find(const struct nf_conn *ct, u8 id) +{ + if (!nf_ct_ext_exist(ct, id)) + return NULL; + + return (void *)ct->ext + ct->ext->offset[id]; +} +#define nf_ct_ext_find(ext, id) \ + ((id##_TYPE *)__nf_ct_ext_find((ext), (id))) + +/* Destroy all relationships */ +extern void __nf_ct_ext_destroy(struct nf_conn *ct); +static inline void nf_ct_ext_destroy(struct nf_conn *ct) +{ + if (ct->ext) + __nf_ct_ext_destroy(ct); +} + +/* Free operation. If you want to free a object referred from private area, + * please implement __nf_ct_ext_free() and call it. + */ +static inline void nf_ct_ext_free(struct nf_conn *ct) +{ + if (ct->ext) + kfree(ct->ext); +} + +/* Add this type, returns pointer to data or NULL. */ +void * +__nf_ct_ext_add(struct nf_conn *ct, enum nf_ct_ext_id id, gfp_t gfp); +#define nf_ct_ext_add(ct, id, gfp) \ + ((id##_TYPE *)__nf_ct_ext_add((ct), (id), (gfp))) + +#define NF_CT_EXT_F_PREALLOC 0x0001 + +struct nf_ct_ext_type +{ + /* Destroys relationships (can be NULL). */ + void (*destroy)(struct nf_conn *ct); + /* Called when realloacted (can be NULL). + Contents has already been moved. */ + void (*move)(struct nf_conn *ct, void *old); + + enum nf_ct_ext_id id; + + unsigned int flags; + + /* Length and min alignment. */ + u8 len; + u8 align; + /* initial size of nf_ct_ext. */ + u8 alloc_size; +}; + +int nf_ct_extend_register(struct nf_ct_ext_type *type); +void nf_ct_extend_unregister(struct nf_ct_ext_type *type); +#endif /* _NF_CONNTRACK_EXTEND_H */ diff --git a/include/net/netfilter/nf_conntrack_helper.h b/include/net/netfilter/nf_conntrack_helper.h index 8c72ac9f0ab8..d04f99964d94 100644 --- a/include/net/netfilter/nf_conntrack_helper.h +++ b/include/net/netfilter/nf_conntrack_helper.h @@ -10,12 +10,13 @@ #ifndef _NF_CONNTRACK_HELPER_H #define _NF_CONNTRACK_HELPER_H #include <net/netfilter/nf_conntrack.h> +#include <net/netfilter/nf_conntrack_extend.h> struct module; struct nf_conntrack_helper -{ - struct list_head list; /* Internal use. */ +{ + struct hlist_node hnode; /* Internal use. */ const char *name; /* name of the module */ struct module *me; /* pointer to self */ @@ -23,10 +24,9 @@ struct nf_conntrack_helper * expected connections */ unsigned int timeout; /* timeout for expecteds */ - /* Mask of things we will help (compared against server response) */ + /* Tuple of things we will help (compared against server response) */ struct nf_conntrack_tuple tuple; - struct nf_conntrack_tuple mask; - + /* Function to call when data passes; return verdict, or -1 to invalidate. */ int (*help)(struct sk_buff **pskb, @@ -52,4 +52,10 @@ extern void nf_ct_helper_put(struct nf_conntrack_helper *helper); extern int nf_conntrack_helper_register(struct nf_conntrack_helper *); extern void nf_conntrack_helper_unregister(struct nf_conntrack_helper *); +extern struct nf_conn_help *nf_ct_helper_ext_add(struct nf_conn *ct, gfp_t gfp); + +static inline struct nf_conn_help *nfct_help(const struct nf_conn *ct) +{ + return nf_ct_ext_find(ct, NF_CT_EXT_HELPER); +} #endif /*_NF_CONNTRACK_HELPER_H*/ diff --git a/include/net/netfilter/nf_conntrack_l3proto.h b/include/net/netfilter/nf_conntrack_l3proto.h index 96a58d8e1d3f..3c58a2c4df28 100644 --- a/include/net/netfilter/nf_conntrack_l3proto.h +++ b/include/net/netfilter/nf_conntrack_l3proto.h @@ -58,13 +58,11 @@ struct nf_conntrack_l3proto /* * Called before tracking. - * *dataoff: offset of protocol header (TCP, UDP,...) in *pskb + * *dataoff: offset of protocol header (TCP, UDP,...) in skb * *protonum: protocol number */ - int (*prepare)(struct sk_buff **pskb, unsigned int hooknum, - unsigned int *dataoff, u_int8_t *protonum); - - u_int32_t (*get_features)(const struct nf_conntrack_tuple *tuple); + int (*get_l4proto)(const struct sk_buff *skb, unsigned int nhoff, + unsigned int *dataoff, u_int8_t *protonum); int (*tuple_to_nfattr)(struct sk_buff *skb, const struct nf_conntrack_tuple *t); @@ -91,8 +89,6 @@ extern struct nf_conntrack_l3proto *nf_ct_l3proto_find_get(u_int16_t l3proto); extern void nf_ct_l3proto_put(struct nf_conntrack_l3proto *p); /* Existing built-in protocols */ -extern struct nf_conntrack_l3proto nf_conntrack_l3proto_ipv4; -extern struct nf_conntrack_l3proto nf_conntrack_l3proto_ipv6; extern struct nf_conntrack_l3proto nf_conntrack_l3proto_generic; static inline struct nf_conntrack_l3proto * diff --git a/include/net/netfilter/nf_conntrack_tuple.h b/include/net/netfilter/nf_conntrack_tuple.h index 5d72b16e876f..040dae5f0c9e 100644 --- a/include/net/netfilter/nf_conntrack_tuple.h +++ b/include/net/netfilter/nf_conntrack_tuple.h @@ -100,6 +100,14 @@ struct nf_conntrack_tuple } dst; }; +struct nf_conntrack_tuple_mask +{ + struct { + union nf_conntrack_address u3; + union nf_conntrack_man_proto u; + } src; +}; + /* This is optimized opposed to a memset of the whole structure. Everything we * really care about is the source/destination unions */ #define NF_CT_TUPLE_U_BLANK(tuple) \ @@ -112,11 +120,11 @@ struct nf_conntrack_tuple #ifdef __KERNEL__ -#define NF_CT_DUMP_TUPLE(tp) \ -DEBUGP("tuple %p: %u %u " NIP6_FMT " %hu -> " NIP6_FMT " %hu\n", \ - (tp), (tp)->src.l3num, (tp)->dst.protonum, \ - NIP6(*(struct in6_addr *)(tp)->src.u3.all), ntohs((tp)->src.u.all), \ - NIP6(*(struct in6_addr *)(tp)->dst.u3.all), ntohs((tp)->dst.u.all)) +#define NF_CT_DUMP_TUPLE(tp) \ +pr_debug("tuple %p: %u %u " NIP6_FMT " %hu -> " NIP6_FMT " %hu\n", \ + (tp), (tp)->src.l3num, (tp)->dst.protonum, \ + NIP6(*(struct in6_addr *)(tp)->src.u3.all), ntohs((tp)->src.u.all), \ + NIP6(*(struct in6_addr *)(tp)->dst.u3.all), ntohs((tp)->dst.u.all)) /* If we're the first tuple, it's the original dir. */ #define NF_CT_DIRECTION(h) \ @@ -125,8 +133,7 @@ DEBUGP("tuple %p: %u %u " NIP6_FMT " %hu -> " NIP6_FMT " %hu\n", \ /* Connections have two entries in the hash table: one for each way */ struct nf_conntrack_tuple_hash { - struct list_head list; - + struct hlist_node hnode; struct nf_conntrack_tuple tuple; }; @@ -162,31 +169,44 @@ static inline int nf_ct_tuple_equal(const struct nf_conntrack_tuple *t1, return nf_ct_tuple_src_equal(t1, t2) && nf_ct_tuple_dst_equal(t1, t2); } +static inline int nf_ct_tuple_mask_equal(const struct nf_conntrack_tuple_mask *m1, + const struct nf_conntrack_tuple_mask *m2) +{ + return (m1->src.u3.all[0] == m2->src.u3.all[0] && + m1->src.u3.all[1] == m2->src.u3.all[1] && + m1->src.u3.all[2] == m2->src.u3.all[2] && + m1->src.u3.all[3] == m2->src.u3.all[3] && + m1->src.u.all == m2->src.u.all); +} + +static inline int nf_ct_tuple_src_mask_cmp(const struct nf_conntrack_tuple *t1, + const struct nf_conntrack_tuple *t2, + const struct nf_conntrack_tuple_mask *mask) +{ + int count; + + for (count = 0; count < NF_CT_TUPLE_L3SIZE; count++) { + if ((t1->src.u3.all[count] ^ t2->src.u3.all[count]) & + mask->src.u3.all[count]) + return 0; + } + + if ((t1->src.u.all ^ t2->src.u.all) & mask->src.u.all) + return 0; + + if (t1->src.l3num != t2->src.l3num || + t1->dst.protonum != t2->dst.protonum) + return 0; + + return 1; +} + static inline int nf_ct_tuple_mask_cmp(const struct nf_conntrack_tuple *t, const struct nf_conntrack_tuple *tuple, - const struct nf_conntrack_tuple *mask) + const struct nf_conntrack_tuple_mask *mask) { - int count = 0; - - for (count = 0; count < NF_CT_TUPLE_L3SIZE; count++){ - if ((t->src.u3.all[count] ^ tuple->src.u3.all[count]) & - mask->src.u3.all[count]) - return 0; - } - - for (count = 0; count < NF_CT_TUPLE_L3SIZE; count++){ - if ((t->dst.u3.all[count] ^ tuple->dst.u3.all[count]) & - mask->dst.u3.all[count]) - return 0; - } - - if ((t->src.u.all ^ tuple->src.u.all) & mask->src.u.all || - (t->dst.u.all ^ tuple->dst.u.all) & mask->dst.u.all || - (t->src.l3num ^ tuple->src.l3num) & mask->src.l3num || - (t->dst.protonum ^ tuple->dst.protonum) & mask->dst.protonum) - return 0; - - return 1; + return nf_ct_tuple_src_mask_cmp(t, tuple, mask) && + nf_ct_tuple_dst_equal(t, tuple); } #endif /* _NF_CONNTRACK_TUPLE_H */ diff --git a/include/net/netfilter/nf_nat.h b/include/net/netfilter/nf_nat.h index bc57dd7b9b5c..6ae52f7c9f55 100644 --- a/include/net/netfilter/nf_nat.h +++ b/include/net/netfilter/nf_nat.h @@ -51,16 +51,31 @@ struct nf_nat_multi_range_compat #ifdef __KERNEL__ #include <linux/list.h> +#include <linux/netfilter/nf_conntrack_pptp.h> +#include <net/netfilter/nf_conntrack_extend.h> -/* The structure embedded in the conntrack structure. */ -struct nf_nat_info +/* per conntrack: nat application helper private data */ +union nf_conntrack_nat_help { - struct list_head bysource; - struct nf_nat_seq seq[IP_CT_DIR_MAX]; + /* insert nat helper private data here */ + struct nf_nat_pptp nat_pptp_info; }; struct nf_conn; +/* The structure embedded in the conntrack structure. */ +struct nf_conn_nat +{ + struct hlist_node bysource; + struct nf_nat_seq seq[IP_CT_DIR_MAX]; + struct nf_conn *ct; + union nf_conntrack_nat_help help; +#if defined(CONFIG_IP_NF_TARGET_MASQUERADE) || \ + defined(CONFIG_IP_NF_TARGET_MASQUERADE_MODULE) + int masq_index; +#endif +}; + /* Set up the info structure to map into this range. */ extern unsigned int nf_nat_setup_info(struct nf_conn *ct, const struct nf_nat_range *range, @@ -70,7 +85,10 @@ extern unsigned int nf_nat_setup_info(struct nf_conn *ct, extern int nf_nat_used_tuple(const struct nf_conntrack_tuple *tuple, const struct nf_conn *ignored_conntrack); -extern int nf_nat_module_is_loaded; +static inline struct nf_conn_nat *nfct_nat(const struct nf_conn *ct) +{ + return nf_ct_ext_find(ct, NF_CT_EXT_NAT); +} #else /* !__KERNEL__: iptables wants this to compile. */ #define nf_nat_multi_range nf_nat_multi_range_compat diff --git a/include/net/netfilter/nf_nat_core.h b/include/net/netfilter/nf_nat_core.h index 9778ffa93440..c3cd127ba4bb 100644 --- a/include/net/netfilter/nf_nat_core.h +++ b/include/net/netfilter/nf_nat_core.h @@ -2,6 +2,7 @@ #define _NF_NAT_CORE_H #include <linux/list.h> #include <net/netfilter/nf_conntrack.h> +#include <net/netfilter/nf_nat.h> /* This header used to share core functionality between the standalone NAT module, and the compatibility layer's use of NAT for masquerading. */ diff --git a/include/net/netlink.h b/include/net/netlink.h index 7b510a9edb91..d7b824be5422 100644 --- a/include/net/netlink.h +++ b/include/net/netlink.h @@ -118,6 +118,9 @@ * Nested Attributes Construction: * nla_nest_start(skb, type) start a nested attribute * nla_nest_end(skb, nla) finalize a nested attribute + * nla_nest_compat_start(skb, type, start a nested compat attribute + * len, data) + * nla_nest_compat_end(skb, type) finalize a nested compat attribute * nla_nest_cancel(skb, nla) cancel nested attribute construction * * Attribute Length Calculations: @@ -152,6 +155,7 @@ * nla_find_nested() find attribute in nested attributes * nla_parse() parse and validate stream of attrs * nla_parse_nested() parse nested attribuets + * nla_parse_nested_compat() parse nested compat attributes * nla_for_each_attr() loop over all attributes * nla_for_each_nested() loop over the nested attributes *========================================================================= @@ -170,6 +174,7 @@ enum { NLA_FLAG, NLA_MSECS, NLA_NESTED, + NLA_NESTED_COMPAT, NLA_NUL_STRING, NLA_BINARY, __NLA_TYPE_MAX, @@ -190,6 +195,7 @@ enum { * NLA_NUL_STRING Maximum length of string (excluding NUL) * NLA_FLAG Unused * NLA_BINARY Maximum length of attribute payload + * NLA_NESTED_COMPAT Exact length of structure payload * All other Exact length of attribute payload * * Example: @@ -733,6 +739,39 @@ static inline int nla_parse_nested(struct nlattr *tb[], int maxtype, { return nla_parse(tb, maxtype, nla_data(nla), nla_len(nla), policy); } + +/** + * nla_parse_nested_compat - parse nested compat attributes + * @tb: destination array with maxtype+1 elements + * @maxtype: maximum attribute type to be expected + * @nla: attribute containing the nested attributes + * @data: pointer to point to contained structure + * @len: length of contained structure + * @policy: validation policy + * + * Parse a nested compat attribute. The compat attribute contains a structure + * and optionally a set of nested attributes. On success the data pointer + * points to the nested data and tb contains the parsed attributes + * (see nla_parse). + */ +static inline int __nla_parse_nested_compat(struct nlattr *tb[], int maxtype, + struct nlattr *nla, + const struct nla_policy *policy, + int len) +{ + if (nla_len(nla) < len) + return -1; + if (nla_len(nla) >= NLA_ALIGN(len) + sizeof(struct nlattr)) + return nla_parse_nested(tb, maxtype, + nla_data(nla) + NLA_ALIGN(len), + policy); + memset(tb, 0, sizeof(struct nlattr *) * (maxtype + 1)); + return 0; +} + +#define nla_parse_nested_compat(tb, maxtype, nla, policy, data, len) \ +({ data = nla_len(nla) >= len ? nla_data(nla) : NULL; \ + __nla_parse_nested_compat(tb, maxtype, nla, policy, len); }) /** * nla_put_u8 - Add a u16 netlink attribute to a socket buffer * @skb: socket buffer to add attribute to @@ -965,6 +1004,51 @@ static inline int nla_nest_end(struct sk_buff *skb, struct nlattr *start) } /** + * nla_nest_compat_start - Start a new level of nested compat attributes + * @skb: socket buffer to add attributes to + * @attrtype: attribute type of container + * @attrlen: length of structure + * @data: pointer to structure + * + * Start a nested compat attribute that contains both a structure and + * a set of nested attributes. + * + * Returns the container attribute + */ +static inline struct nlattr *nla_nest_compat_start(struct sk_buff *skb, + int attrtype, int attrlen, + const void *data) +{ + struct nlattr *start = (struct nlattr *)skb_tail_pointer(skb); + + if (nla_put(skb, attrtype, attrlen, data) < 0) + return NULL; + if (nla_nest_start(skb, attrtype) == NULL) { + nlmsg_trim(skb, start); + return NULL; + } + return start; +} + +/** + * nla_nest_compat_end - Finalize nesting of compat attributes + * @skb: socket buffer the attribtues are stored in + * @start: container attribute + * + * Corrects the container attribute header to include the all + * appeneded attributes. + * + * Returns the total data length of the skb. + */ +static inline int nla_nest_compat_end(struct sk_buff *skb, struct nlattr *start) +{ + struct nlattr *nest = (void *)start + NLMSG_ALIGN(start->nla_len); + + start->nla_len = skb_tail_pointer(skb) - (unsigned char *)start; + return nla_nest_end(skb, nest); +} + +/** * nla_nest_cancel - Cancel nesting of attributes * @skb: socket buffer the message is stored in * @start: container attribute diff --git a/include/net/pkt_cls.h b/include/net/pkt_cls.h index 4129df708079..7968b1d66369 100644 --- a/include/net/pkt_cls.h +++ b/include/net/pkt_cls.h @@ -65,8 +65,6 @@ struct tcf_exts { #ifdef CONFIG_NET_CLS_ACT struct tc_action *action; -#elif defined CONFIG_NET_CLS_POLICE - struct tcf_police *police; #endif }; @@ -91,8 +89,6 @@ tcf_exts_is_predicative(struct tcf_exts *exts) { #ifdef CONFIG_NET_CLS_ACT return !!exts->action; -#elif defined CONFIG_NET_CLS_POLICE - return !!exts->police; #else return 0; #endif @@ -129,11 +125,7 @@ tcf_exts_exec(struct sk_buff *skb, struct tcf_exts *exts, #ifdef CONFIG_NET_CLS_ACT if (exts->action) return tcf_action_exec(skb, exts->action, res); -#elif defined CONFIG_NET_CLS_POLICE - if (exts->police) - return tcf_police(skb, exts->police); #endif - return 0; } @@ -306,6 +298,8 @@ static inline int tcf_em_tree_match(struct sk_buff *skb, return 1; } +#define MODULE_ALIAS_TCF_EMATCH(kind) MODULE_ALIAS("ematch-kind-" __stringify(kind)) + #else /* CONFIG_NET_EMATCH */ struct tcf_ematch_tree diff --git a/include/net/pkt_sched.h b/include/net/pkt_sched.h index 5754d53d9efc..9e22526e80e7 100644 --- a/include/net/pkt_sched.h +++ b/include/net/pkt_sched.h @@ -89,8 +89,10 @@ static inline void qdisc_run(struct net_device *dev) __qdisc_run(dev); } +extern int tc_classify_compat(struct sk_buff *skb, struct tcf_proto *tp, + struct tcf_result *res); extern int tc_classify(struct sk_buff *skb, struct tcf_proto *tp, - struct tcf_result *res); + struct tcf_result *res); /* Calculate maximal size of packet seen by hard_start_xmit routine of this device. diff --git a/include/net/rawv6.h b/include/net/rawv6.h index af8960878ef4..a5819891d525 100644 --- a/include/net/rawv6.h +++ b/include/net/rawv6.h @@ -3,6 +3,8 @@ #ifdef __KERNEL__ +#include <net/protocol.h> + #define RAWV6_HTABLE_SIZE MAX_INET_PROTOS extern struct hlist_head raw_v6_htable[RAWV6_HTABLE_SIZE]; extern rwlock_t raw_v6_lock; @@ -23,6 +25,13 @@ extern void rawv6_err(struct sock *sk, int type, int code, int offset, __be32 info); +#if defined(CONFIG_IPV6_MIP6) || defined(CONFIG_IPV6_MIP6_MODULE) +int rawv6_mh_filter_register(int (*filter)(struct sock *sock, + struct sk_buff *skb)); +int rawv6_mh_filter_unregister(int (*filter)(struct sock *sock, + struct sk_buff *skb)); +#endif + #endif #endif diff --git a/include/net/route.h b/include/net/route.h index 749e4dfe5ff3..f7ce6259f86f 100644 --- a/include/net/route.h +++ b/include/net/route.h @@ -62,7 +62,6 @@ struct rtable unsigned rt_flags; __u16 rt_type; - __u16 rt_multipath_alg; __be32 rt_dst; /* Path destination */ __be32 rt_src; /* Path source */ @@ -136,7 +135,7 @@ static inline void ip_rt_put(struct rtable * rt) #define IPTOS_RT_MASK (IPTOS_TOS_MASK & ~3) -extern __u8 ip_tos2prio[16]; +extern const __u8 ip_tos2prio[16]; static inline char rt_tos2priority(u8 tos) { diff --git a/include/net/rtnetlink.h b/include/net/rtnetlink.h index 3b3d4745618d..3861c05cdf0f 100644 --- a/include/net/rtnetlink.h +++ b/include/net/rtnetlink.h @@ -22,4 +22,62 @@ static inline int rtnl_msg_family(struct nlmsghdr *nlh) return AF_UNSPEC; } +/** + * struct rtnl_link_ops - rtnetlink link operations + * + * @list: Used internally + * @kind: Identifier + * @maxtype: Highest device specific netlink attribute number + * @policy: Netlink policy for device specific attribute validation + * @validate: Optional validation function for netlink/changelink parameters + * @priv_size: sizeof net_device private space + * @setup: net_device setup function + * @newlink: Function for configuring and registering a new device + * @changelink: Function for changing parameters of an existing device + * @dellink: Function to remove a device + * @get_size: Function to calculate required room for dumping device + * specific netlink attributes + * @fill_info: Function to dump device specific netlink attributes + * @get_xstats_size: Function to calculate required room for dumping devic + * specific statistics + * @fill_xstats: Function to dump device specific statistics + */ +struct rtnl_link_ops { + struct list_head list; + + const char *kind; + + size_t priv_size; + void (*setup)(struct net_device *dev); + + int maxtype; + const struct nla_policy *policy; + int (*validate)(struct nlattr *tb[], + struct nlattr *data[]); + + int (*newlink)(struct net_device *dev, + struct nlattr *tb[], + struct nlattr *data[]); + int (*changelink)(struct net_device *dev, + struct nlattr *tb[], + struct nlattr *data[]); + void (*dellink)(struct net_device *dev); + + size_t (*get_size)(const struct net_device *dev); + int (*fill_info)(struct sk_buff *skb, + const struct net_device *dev); + + size_t (*get_xstats_size)(const struct net_device *dev); + int (*fill_xstats)(struct sk_buff *skb, + const struct net_device *dev); +}; + +extern int __rtnl_link_register(struct rtnl_link_ops *ops); +extern void __rtnl_link_unregister(struct rtnl_link_ops *ops); + +extern int rtnl_link_register(struct rtnl_link_ops *ops); +extern void rtnl_link_unregister(struct rtnl_link_ops *ops); + +#define MODULE_ALIAS_RTNL_LINK(kind) MODULE_ALIAS("rtnl-link-" kind) + #endif diff --git a/include/net/sch_generic.h b/include/net/sch_generic.h index 1b8e35197ebe..8a67f24cbe02 100644 --- a/include/net/sch_generic.h +++ b/include/net/sch_generic.h @@ -290,7 +290,7 @@ static inline int qdisc_reshape_fail(struct sk_buff *skb, struct Qdisc *sch) { sch->qstats.drops++; -#ifdef CONFIG_NET_CLS_POLICE +#ifdef CONFIG_NET_CLS_ACT if (sch->reshape_fail == NULL || sch->reshape_fail(skb, sch)) goto drop; diff --git a/include/net/tipc/tipc_port.h b/include/net/tipc/tipc_port.h index 333bba6dc522..cfc4ba46de8f 100644 --- a/include/net/tipc/tipc_port.h +++ b/include/net/tipc/tipc_port.h @@ -1,8 +1,8 @@ /* * include/net/tipc/tipc_port.h: Include file for privileged access to TIPC ports * - * Copyright (c) 1994-2006, Ericsson AB - * Copyright (c) 2005, Wind River Systems + * Copyright (c) 1994-2007, Ericsson AB + * Copyright (c) 2005-2007, Wind River Systems * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -55,6 +55,7 @@ * @conn_unacked: number of unacknowledged messages received from peer port * @published: non-zero if port has one or more associated names * @congested: non-zero if cannot send because of link or port congestion + * @max_pkt: maximum packet size "hint" used when building messages sent by port * @ref: unique reference to port in TIPC object registry * @phdr: preformatted message header used when sending messages */ @@ -68,6 +69,7 @@ struct tipc_port { u32 conn_unacked; int published; u32 congested; + u32 max_pkt; u32 ref; struct tipc_msg phdr; }; diff --git a/include/net/xfrm.h b/include/net/xfrm.h index 311f25af5e1a..ae959e950174 100644 --- a/include/net/xfrm.h +++ b/include/net/xfrm.h @@ -19,9 +19,19 @@ #include <net/ipv6.h> #include <net/ip6_fib.h> +#define XFRM_PROTO_ESP 50 +#define XFRM_PROTO_AH 51 +#define XFRM_PROTO_COMP 108 +#define XFRM_PROTO_IPIP 4 +#define XFRM_PROTO_IPV6 41 +#define XFRM_PROTO_ROUTING IPPROTO_ROUTING +#define XFRM_PROTO_DSTOPTS IPPROTO_DSTOPTS + #define XFRM_ALIGN8(len) (((len) + 7) & ~7) #define MODULE_ALIAS_XFRM_MODE(family, encap) \ MODULE_ALIAS("xfrm-mode-" __stringify(family) "-" __stringify(encap)) +#define MODULE_ALIAS_XFRM_TYPE(family, proto) \ + MODULE_ALIAS("xfrm-type-" __stringify(family) "-" __stringify(proto)) extern struct sock *xfrm_nl; extern u32 sysctl_xfrm_aevent_etime; @@ -509,11 +519,9 @@ __be16 xfrm_flowi_sport(struct flowi *fl) case IPPROTO_ICMPV6: port = htons(fl->fl_icmp_type); break; -#ifdef CONFIG_IPV6_MIP6 case IPPROTO_MH: port = htons(fl->fl_mh_type); break; -#endif default: port = 0; /*XXX*/ } @@ -920,6 +928,10 @@ extern struct xfrm_state *xfrm_state_find(xfrm_address_t *daddr, xfrm_address_t struct flowi *fl, struct xfrm_tmpl *tmpl, struct xfrm_policy *pol, int *err, unsigned short family); +extern struct xfrm_state * xfrm_stateonly_find(xfrm_address_t *daddr, + xfrm_address_t *saddr, + unsigned short family, + u8 mode, u8 proto, u32 reqid); extern int xfrm_state_check_expire(struct xfrm_state *x); extern void xfrm_state_insert(struct xfrm_state *x); extern int xfrm_state_add(struct xfrm_state *x); @@ -991,7 +1003,7 @@ extern int xfrm6_find_1stfragopt(struct xfrm_state *x, struct sk_buff *skb, u8 **prevhdr); #ifdef CONFIG_XFRM -extern int xfrm4_rcv_encap(struct sk_buff *skb, __u16 encap_type); +extern int xfrm4_udp_encap_rcv(struct sock *sk, struct sk_buff *skb); extern int xfrm_user_policy(struct sock *sk, int optname, u8 __user *optval, int optlen); extern int xfrm_dst_lookup(struct xfrm_dst **dst, struct flowi *fl, unsigned short family); #else @@ -1000,12 +1012,13 @@ static inline int xfrm_user_policy(struct sock *sk, int optname, u8 __user *optv return -ENOPROTOOPT; } -static inline int xfrm4_rcv_encap(struct sk_buff *skb, __u16 encap_type) +static inline int xfrm4_udp_encap_rcv(struct sock *sk, struct sk_buff *skb) { /* should not happen */ kfree_skb(skb); return 0; } + static inline int xfrm_dst_lookup(struct xfrm_dst **dst, struct flowi *fl, unsigned short family) { return -EINVAL; diff --git a/include/rdma/ib_cm.h b/include/rdma/ib_cm.h index 5c070176d9ab..12243e80c706 100644 --- a/include/rdma/ib_cm.h +++ b/include/rdma/ib_cm.h @@ -385,7 +385,6 @@ struct ib_cm_rep_param { u8 private_data_len; u8 responder_resources; u8 initiator_depth; - u8 target_ack_delay; u8 failover_accepted; u8 flow_control; u8 rnr_retry_count; diff --git a/include/rdma/ib_mad.h b/include/rdma/ib_mad.h index 739fa4d0e539..30712ddd8a5e 100644 --- a/include/rdma/ib_mad.h +++ b/include/rdma/ib_mad.h @@ -111,6 +111,9 @@ #define IB_QP1_QKEY 0x80010000 #define IB_QP_SET_QKEY 0x80000000 +#define IB_DEFAULT_PKEY_PARTIAL 0x7FFF +#define IB_DEFAULT_PKEY_FULL 0xFFFF + enum { IB_MGMT_MAD_HDR = 24, IB_MGMT_MAD_DATA = 232, diff --git a/include/scsi/iscsi_if.h b/include/scsi/iscsi_if.h index 55ebf035e620..50e907f42048 100644 --- a/include/scsi/iscsi_if.h +++ b/include/scsi/iscsi_if.h @@ -48,6 +48,7 @@ enum iscsi_uevent_e { ISCSI_UEVENT_TRANSPORT_EP_DISCONNECT = UEVENT_BASE + 14, ISCSI_UEVENT_TGT_DSCVR = UEVENT_BASE + 15, + ISCSI_UEVENT_SET_HOST_PARAM = UEVENT_BASE + 16, /* up events */ ISCSI_KEVENT_RECV_PDU = KEVENT_BASE + 1, @@ -71,6 +72,8 @@ struct iscsi_uevent { /* messages u -> k */ struct msg_create_session { uint32_t initial_cmdsn; + uint16_t cmds_max; + uint16_t queue_depth; } c_session; struct msg_destroy_session { uint32_t sid; @@ -136,6 +139,11 @@ struct iscsi_uevent { */ uint32_t enable; } tgt_dscvr; + struct msg_set_host_param { + uint32_t host_no; + uint32_t param; /* enum iscsi_host_param */ + uint32_t len; + } set_host_param; } u; union { /* messages k -> u */ @@ -223,6 +231,11 @@ enum iscsi_param { ISCSI_PARAM_CONN_PORT, ISCSI_PARAM_CONN_ADDRESS, + ISCSI_PARAM_USERNAME, + ISCSI_PARAM_USERNAME_IN, + ISCSI_PARAM_PASSWORD, + ISCSI_PARAM_PASSWORD_IN, + /* must always be last */ ISCSI_PARAM_MAX, }; @@ -249,6 +262,24 @@ enum iscsi_param { #define ISCSI_SESS_RECOVERY_TMO (1 << ISCSI_PARAM_SESS_RECOVERY_TMO) #define ISCSI_CONN_PORT (1 << ISCSI_PARAM_CONN_PORT) #define ISCSI_CONN_ADDRESS (1 << ISCSI_PARAM_CONN_ADDRESS) +#define ISCSI_USERNAME (1 << ISCSI_PARAM_USERNAME) +#define ISCSI_USERNAME_IN (1 << ISCSI_PARAM_USERNAME_IN) +#define ISCSI_PASSWORD (1 << ISCSI_PARAM_PASSWORD) +#define ISCSI_PASSWORD_IN (1 << ISCSI_PARAM_PASSWORD_IN) + +/* iSCSI HBA params */ +enum iscsi_host_param { + ISCSI_HOST_PARAM_HWADDRESS, + ISCSI_HOST_PARAM_INITIATOR_NAME, + ISCSI_HOST_PARAM_NETDEV_NAME, + ISCSI_HOST_PARAM_IPADDRESS, + ISCSI_HOST_PARAM_MAX, +}; + +#define ISCSI_HOST_HWADDRESS (1 << ISCSI_HOST_PARAM_HWADDRESS) +#define ISCSI_HOST_INITIATOR_NAME (1 << ISCSI_HOST_PARAM_INITIATOR_NAME) +#define ISCSI_HOST_NETDEV_NAME (1 << ISCSI_HOST_PARAM_NETDEV_NAME) +#define ISCSI_HOST_IPADDRESS (1 << ISCSI_HOST_PARAM_IPADDRESS) #define iscsi_ptr(_handle) ((void*)(unsigned long)_handle) #define iscsi_handle(_ptr) ((uint64_t)(unsigned long)_ptr) @@ -272,6 +303,9 @@ enum iscsi_param { #define CAP_MULTI_CONN 0x40 #define CAP_TEXT_NEGO 0x80 #define CAP_MARKERS 0x100 +#define CAP_FW_DB 0x200 +#define CAP_SENDTARGETS_OFFLOAD 0x400 +#define CAP_DATA_PATH_OFFLOAD 0x800 /* * These flags describes reason of stop_conn() call diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h index ea0816d4904d..3f631b08a1ab 100644 --- a/include/scsi/libiscsi.h +++ b/include/scsi/libiscsi.h @@ -48,9 +48,8 @@ struct iscsi_nopin; #define debug_scsi(fmt...) #endif -#define ISCSI_XMIT_CMDS_MAX 128 /* must be power of 2 */ -#define ISCSI_MGMT_CMDS_MAX 32 /* must be power of 2 */ -#define ISCSI_CONN_MAX 1 +#define ISCSI_DEF_XMIT_CMDS_MAX 128 /* must be power of 2 */ +#define ISCSI_MGMT_CMDS_MAX 16 /* must be power of 2 */ #define ISCSI_MGMT_ITT_OFFSET 0xa00 @@ -73,6 +72,8 @@ struct iscsi_nopin; #define ISCSI_AGE_SHIFT 28 #define ISCSI_AGE_MASK (0xf << ISCSI_AGE_SHIFT) +#define ISCSI_ADDRESS_BUF_LEN 64 + struct iscsi_mgmt_task { /* * Becuae LLDs allocate their hdr differently, this is a pointer to @@ -80,7 +81,7 @@ struct iscsi_mgmt_task { */ struct iscsi_hdr *hdr; char *data; /* mgmt payload */ - int data_count; /* counts data to be sent */ + unsigned data_count; /* counts data to be sent */ uint32_t itt; /* this ITT */ void *dd_data; /* driver/transport data */ struct list_head running; @@ -90,6 +91,7 @@ enum { ISCSI_TASK_COMPLETED, ISCSI_TASK_PENDING, ISCSI_TASK_RUNNING, + ISCSI_TASK_ABORTING, }; struct iscsi_cmd_task { @@ -99,16 +101,14 @@ struct iscsi_cmd_task { */ struct iscsi_cmd *hdr; int itt; /* this ITT */ - int datasn; /* DataSN */ uint32_t unsol_datasn; - int imm_count; /* imm-data (bytes) */ - int unsol_count; /* unsolicited (bytes)*/ + unsigned imm_count; /* imm-data (bytes) */ + unsigned unsol_count; /* unsolicited (bytes)*/ /* offset in unsolicited stream (bytes); */ - int unsol_offset; - int data_count; /* remaining Data-Out */ + unsigned unsol_offset; + unsigned data_count; /* remaining Data-Out */ struct scsi_cmnd *sc; /* associated SCSI cmd*/ - int total_length; struct iscsi_conn *conn; /* used connection */ struct iscsi_mgmt_task *mtask; /* tmf mtask in progr */ @@ -152,18 +152,11 @@ struct iscsi_conn { struct iscsi_cmd_task *ctask; /* xmit ctask in progress */ /* xmit */ - struct kfifo *immqueue; /* immediate xmit queue */ struct kfifo *mgmtqueue; /* mgmt (control) xmit queue */ struct list_head mgmt_run_list; /* list of control tasks */ struct list_head xmitqueue; /* data-path cmd queue */ struct list_head run_list; /* list of cmds in progress */ struct work_struct xmitwork; /* per-conn. xmit workqueue */ - /* - * serializes connection xmit, access to kfifos: - * xmitqueue, immqueue, mgmtqueue - */ - struct mutex xmitmutex; - unsigned long suspend_tx; /* suspend Tx */ unsigned long suspend_rx; /* suspend Rx */ @@ -174,8 +167,8 @@ struct iscsi_conn { int tmabort_state; /* see TMABORT_INITIAL, etc.*/ /* negotiated params */ - int max_recv_dlength; /* initiator_max_recv_dsl*/ - int max_xmit_dlength; /* target_max_recv_dsl */ + unsigned max_recv_dlength; /* initiator_max_recv_dsl*/ + unsigned max_xmit_dlength; /* target_max_recv_dsl */ int hdrdgst_en; int datadgst_en; int ifmarker_en; @@ -183,6 +176,12 @@ struct iscsi_conn { /* values userspace uses to id a conn */ int persistent_port; char *persistent_address; + /* remote portal currently connected to */ + int portal_port; + char portal_address[ISCSI_ADDRESS_BUF_LEN]; + /* local address */ + int local_port; + char local_address[ISCSI_ADDRESS_BUF_LEN]; /* MIB-statistics */ uint64_t txdata_octets; @@ -213,18 +212,25 @@ struct iscsi_session { /* configuration */ int initial_r2t_en; - int max_r2t; + unsigned max_r2t; int imm_data_en; - int first_burst; - int max_burst; + unsigned first_burst; + unsigned max_burst; int time2wait; int time2retain; int pdu_inorder_en; int dataseq_inorder_en; int erl; int tpgt; + char *username; + char *username_in; + char *password; + char *password_in; char *targetname; - + char *initiatorname; + /* hw address or netdev iscsi connection is bound to */ + char *hwaddress; + char *netdev; /* control data */ struct iscsi_transport *tt; struct Scsi_Host *host; @@ -255,12 +261,22 @@ extern int iscsi_eh_host_reset(struct scsi_cmnd *sc); extern int iscsi_queuecommand(struct scsi_cmnd *sc, void (*done)(struct scsi_cmnd *)); + +/* + * iSCSI host helpers. + */ +extern int iscsi_host_set_param(struct Scsi_Host *shost, + enum iscsi_host_param param, char *buf, + int buflen); +extern int iscsi_host_get_param(struct Scsi_Host *shost, + enum iscsi_host_param param, char *buf); + /* * session management */ extern struct iscsi_cls_session * iscsi_session_setup(struct iscsi_transport *, struct scsi_transport_template *, - int, int, uint32_t, uint32_t *); + uint16_t, uint16_t, int, int, uint32_t, uint32_t *); extern void iscsi_session_teardown(struct iscsi_cls_session *); extern struct iscsi_session *class_to_transport_session(struct iscsi_cls_session *); extern void iscsi_session_recovery_timedout(struct iscsi_cls_session *); @@ -289,8 +305,7 @@ extern int iscsi_conn_get_param(struct iscsi_cls_conn *cls_conn, /* * pdu and task processing */ -extern int iscsi_check_assign_cmdsn(struct iscsi_session *, - struct iscsi_nopin *); +extern void iscsi_update_cmdsn(struct iscsi_session *, struct iscsi_nopin *); extern void iscsi_prep_unsolicit_data_pdu(struct iscsi_cmd_task *, struct iscsi_data *hdr); extern int iscsi_conn_send_pdu(struct iscsi_cls_conn *, struct iscsi_hdr *, diff --git a/include/scsi/scsi_cmnd.h b/include/scsi/scsi_cmnd.h index a2e0c1032491..53e170586c26 100644 --- a/include/scsi/scsi_cmnd.h +++ b/include/scsi/scsi_cmnd.h @@ -135,4 +135,24 @@ extern void scsi_kunmap_atomic_sg(void *virt); extern struct scatterlist *scsi_alloc_sgtable(struct scsi_cmnd *, gfp_t); extern void scsi_free_sgtable(struct scatterlist *, int); +extern int scsi_dma_map(struct scsi_cmnd *cmd); +extern void scsi_dma_unmap(struct scsi_cmnd *cmd); + +#define scsi_sg_count(cmd) ((cmd)->use_sg) +#define scsi_sglist(cmd) ((struct scatterlist *)(cmd)->request_buffer) +#define scsi_bufflen(cmd) ((cmd)->request_bufflen) + +static inline void scsi_set_resid(struct scsi_cmnd *cmd, int resid) +{ + cmd->resid = resid; +} + +static inline int scsi_get_resid(struct scsi_cmnd *cmd) +{ + return cmd->resid; +} + +#define scsi_for_each_sg(cmd, sg, nseg, __i) \ + for (__i = 0, sg = scsi_sglist(cmd); __i < (nseg); __i++, (sg)++) + #endif /* _SCSI_SCSI_CMND_H */ diff --git a/include/scsi/scsi_device.h b/include/scsi/scsi_device.h index 2f3c5b8b1d6a..d5057bc338ff 100644 --- a/include/scsi/scsi_device.h +++ b/include/scsi/scsi_device.h @@ -209,7 +209,6 @@ extern struct scsi_device *__scsi_add_device(struct Scsi_Host *, extern int scsi_add_device(struct Scsi_Host *host, uint channel, uint target, uint lun); extern void scsi_remove_device(struct scsi_device *); -extern int scsi_device_cancel(struct scsi_device *, int); extern int scsi_device_get(struct scsi_device *); extern void scsi_device_put(struct scsi_device *); @@ -287,6 +286,7 @@ extern void scsi_target_block(struct device *); extern void scsi_target_unblock(struct device *); extern void scsi_remove_target(struct device *); extern void int_to_scsilun(unsigned int, struct scsi_lun *); +extern int scsilun_to_int(struct scsi_lun *); extern const char *scsi_device_state_name(enum scsi_device_state); extern int scsi_is_sdev_device(const struct device *); extern int scsi_is_target_device(const struct device *); diff --git a/include/scsi/scsi_host.h b/include/scsi/scsi_host.h index 68f461b7a835..ba07cf7c04ba 100644 --- a/include/scsi/scsi_host.h +++ b/include/scsi/scsi_host.h @@ -339,12 +339,6 @@ struct scsi_host_template { enum scsi_eh_timer_return (* eh_timed_out)(struct scsi_cmnd *); /* - * suspend support - */ - int (*resume)(struct scsi_device *); - int (*suspend)(struct scsi_device *, pm_message_t state); - - /* * Name of proc directory */ char *proc_name; @@ -677,6 +671,10 @@ struct Scsi_Host { #define shost_printk(prefix, shost, fmt, a...) \ dev_printk(prefix, &(shost)->shost_gendev, fmt, ##a) +static inline void *shost_priv(struct Scsi_Host *shost) +{ + return (void *)shost->hostdata; +} int scsi_is_host_device(const struct device *); diff --git a/include/scsi/scsi_transport_fc.h b/include/scsi/scsi_transport_fc.h index 1e797308640a..a0d80bcaa93d 100644 --- a/include/scsi/scsi_transport_fc.h +++ b/include/scsi/scsi_transport_fc.h @@ -1,4 +1,4 @@ -/* +/* * FiberChannel transport specific attributes exported to sysfs. * * Copyright (c) 2003 Silicon Graphics, Inc. All rights reserved. @@ -19,7 +19,7 @@ * * ======== * - * Copyright (C) 2004-2005 James Smart, Emulex Corporation + * Copyright (C) 2004-2007 James Smart, Emulex Corporation * Rewrite for host, target, device, and remote port attributes, * statistics, and service functions... * @@ -62,8 +62,10 @@ enum fc_port_type { FC_PORTTYPE_NLPORT, /* (Public) Loop w/ FLPort */ FC_PORTTYPE_LPORT, /* (Private) Loop w/o FLPort */ FC_PORTTYPE_PTP, /* Point to Point w/ another NPort */ + FC_PORTTYPE_NPIV, /* VPORT based on NPIV */ }; + /* * fc_port_state: If you alter this, you also need to alter scsi_transport_fc.c * (for the ascii descriptions). @@ -83,7 +85,26 @@ enum fc_port_state { }; -/* +/* + * fc_vport_state: If you alter this, you also need to alter + * scsi_transport_fc.c (for the ascii descriptions). + */ +enum fc_vport_state { + FC_VPORT_UNKNOWN, + FC_VPORT_ACTIVE, + FC_VPORT_DISABLED, + FC_VPORT_LINKDOWN, + FC_VPORT_INITIALIZING, + FC_VPORT_NO_FABRIC_SUPP, + FC_VPORT_NO_FABRIC_RSCS, + FC_VPORT_FABRIC_LOGOUT, + FC_VPORT_FABRIC_REJ_WWN, + FC_VPORT_FAILED, +}; + + + +/* * FC Classes of Service * Note: values are not enumerated, as they can be "or'd" together * for reporting (e.g. report supported_classes). If you alter this list, @@ -96,7 +117,7 @@ enum fc_port_state { #define FC_COS_CLASS4 0x10 #define FC_COS_CLASS6 0x40 -/* +/* * FC Port Speeds * Note: values are not enumerated, as they can be "or'd" together * for reporting (e.g. report supported_speeds). If you alter this list, @@ -124,16 +145,114 @@ enum fc_tgtid_binding_type { }; /* - * FC Remote Port Roles + * FC Port Roles * Note: values are not enumerated, as they can be "or'd" together * for reporting (e.g. report roles). If you alter this list, * you also need to alter scsi_transport_fc.c (for the ascii descriptions). */ -#define FC_RPORT_ROLE_UNKNOWN 0x00 -#define FC_RPORT_ROLE_FCP_TARGET 0x01 -#define FC_RPORT_ROLE_FCP_INITIATOR 0x02 -#define FC_RPORT_ROLE_IP_PORT 0x04 +#define FC_PORT_ROLE_UNKNOWN 0x00 +#define FC_PORT_ROLE_FCP_TARGET 0x01 +#define FC_PORT_ROLE_FCP_INITIATOR 0x02 +#define FC_PORT_ROLE_IP_PORT 0x04 + +/* The following are for compatibility */ +#define FC_RPORT_ROLE_UNKNOWN FC_PORT_ROLE_UNKNOWN +#define FC_RPORT_ROLE_FCP_TARGET FC_PORT_ROLE_FCP_TARGET +#define FC_RPORT_ROLE_FCP_INITIATOR FC_PORT_ROLE_FCP_INITIATOR +#define FC_RPORT_ROLE_IP_PORT FC_PORT_ROLE_IP_PORT + + +/* Macro for use in defining Virtual Port attributes */ +#define FC_VPORT_ATTR(_name,_mode,_show,_store) \ +struct class_device_attribute class_device_attr_vport_##_name = \ + __ATTR(_name,_mode,_show,_store) + + +/* + * FC Virtual Port Attributes + * + * This structure exists for each FC port is a virtual FC port. Virtual + * ports share the physical link with the Physical port. Each virtual + * ports has a unique presense on the SAN, and may be instantiated via + * NPIV, Virtual Fabrics, or via additional ALPAs. As the vport is a + * unique presense, each vport has it's own view of the fabric, + * authentication priviledge, and priorities. + * + * A virtual port may support 1 or more FC4 roles. Typically it is a + * FCP Initiator. It could be a FCP Target, or exist sole for an IP over FC + * roles. FC port attributes for the vport will be reported on any + * fc_host class object allocated for an FCP Initiator. + * + * -- + * + * Fixed attributes are not expected to change. The driver is + * expected to set these values after receiving the fc_vport structure + * via the vport_create() call from the transport. + * The transport fully manages all get functions w/o driver interaction. + * + * Dynamic attributes are expected to change. The driver participates + * in all get/set operations via functions provided by the driver. + * + * Private attributes are transport-managed values. They are fully + * managed by the transport w/o driver interaction. + */ +#define FC_VPORT_SYMBOLIC_NAMELEN 64 +struct fc_vport { + /* Fixed Attributes */ + + /* Dynamic Attributes */ + + /* Private (Transport-managed) Attributes */ + enum fc_vport_state vport_state; + enum fc_vport_state vport_last_state; + u64 node_name; + u64 port_name; + u32 roles; + u32 vport_id; /* Admin Identifier for the vport */ + enum fc_port_type vport_type; + char symbolic_name[FC_VPORT_SYMBOLIC_NAMELEN]; + + /* exported data */ + void *dd_data; /* Used for driver-specific storage */ + + /* internal data */ + struct Scsi_Host *shost; /* Physical Port Parent */ + unsigned int channel; + u32 number; + u8 flags; + struct list_head peers; + struct device dev; + struct work_struct vport_delete_work; +} __attribute__((aligned(sizeof(unsigned long)))); + +/* bit field values for struct fc_vport "flags" field: */ +#define FC_VPORT_CREATING 0x01 +#define FC_VPORT_DELETING 0x02 +#define FC_VPORT_DELETED 0x04 +#define FC_VPORT_DEL 0x06 /* Any DELETE state */ + +#define dev_to_vport(d) \ + container_of(d, struct fc_vport, dev) +#define transport_class_to_vport(classdev) \ + dev_to_vport(classdev->dev) +#define vport_to_shost(v) \ + (v->shost) +#define vport_to_shost_channel(v) \ + (v->channel) +#define vport_to_parent(v) \ + (v->dev.parent) + + +/* Error return codes for vport_create() callback */ +#define VPCERR_UNSUPPORTED -ENOSYS /* no driver/adapter + support */ +#define VPCERR_BAD_WWN -ENOTUNIQ /* driver validation + of WWNs failed */ +#define VPCERR_NO_FABRIC_SUPP -EOPNOTSUPP /* Fabric connection + is loop or the + Fabric Port does + not support NPIV */ /* * fc_rport_identifiers: This set of data contains all elements @@ -149,6 +268,7 @@ struct fc_rport_identifiers { u32 roles; }; + /* Macro for use in defining Remote Port attributes */ #define FC_RPORT_ATTR(_name,_mode,_show,_store) \ struct class_device_attribute class_device_attr_rport_##_name = \ @@ -278,7 +398,7 @@ struct fc_host_statistics { u64 prim_seq_protocol_err_count; u64 invalid_tx_word_count; u64 invalid_crc_count; - + /* fc4 statistics (only FCP supported currently) */ u64 fcp_input_requests; u64 fcp_output_requests; @@ -343,6 +463,7 @@ struct fc_host_attrs { u8 supported_fc4s[FC_FC4_LIST_SIZE]; u32 supported_speeds; u32 maxframe_size; + u16 max_npiv_vports; char serial_number[FC_SERIAL_NUMBER_SIZE]; /* Dynamic Attributes */ @@ -361,8 +482,11 @@ struct fc_host_attrs { /* internal data */ struct list_head rports; struct list_head rport_bindings; + struct list_head vports; u32 next_rport_number; u32 next_target_id; + u32 next_vport_number; + u16 npiv_vports_inuse; /* work queues for rport state manipulation */ char work_q_name[KOBJ_NAME_LEN]; @@ -388,6 +512,8 @@ struct fc_host_attrs { (((struct fc_host_attrs *)(x)->shost_data)->supported_speeds) #define fc_host_maxframe_size(x) \ (((struct fc_host_attrs *)(x)->shost_data)->maxframe_size) +#define fc_host_max_npiv_vports(x) \ + (((struct fc_host_attrs *)(x)->shost_data)->max_npiv_vports) #define fc_host_serial_number(x) \ (((struct fc_host_attrs *)(x)->shost_data)->serial_number) #define fc_host_port_id(x) \ @@ -412,10 +538,16 @@ struct fc_host_attrs { (((struct fc_host_attrs *)(x)->shost_data)->rports) #define fc_host_rport_bindings(x) \ (((struct fc_host_attrs *)(x)->shost_data)->rport_bindings) +#define fc_host_vports(x) \ + (((struct fc_host_attrs *)(x)->shost_data)->vports) #define fc_host_next_rport_number(x) \ (((struct fc_host_attrs *)(x)->shost_data)->next_rport_number) #define fc_host_next_target_id(x) \ (((struct fc_host_attrs *)(x)->shost_data)->next_target_id) +#define fc_host_next_vport_number(x) \ + (((struct fc_host_attrs *)(x)->shost_data)->next_vport_number) +#define fc_host_npiv_vports_inuse(x) \ + (((struct fc_host_attrs *)(x)->shost_data)->npiv_vports_inuse) #define fc_host_work_q_name(x) \ (((struct fc_host_attrs *)(x)->shost_data)->work_q_name) #define fc_host_work_q(x) \ @@ -452,14 +584,20 @@ struct fc_function_template { void (*dev_loss_tmo_callbk)(struct fc_rport *); void (*terminate_rport_io)(struct fc_rport *); + void (*set_vport_symbolic_name)(struct fc_vport *); + int (*vport_create)(struct fc_vport *, bool); + int (*vport_disable)(struct fc_vport *, bool); + int (*vport_delete)(struct fc_vport *); + /* allocation lengths for host-specific data */ u32 dd_fcrport_size; + u32 dd_fcvport_size; - /* + /* * The driver sets these to tell the transport class it * wants the attributes displayed in sysfs. If the show_ flag * is not set, the attribute will be private to the transport - * class + * class */ /* remote port fixed attributes */ @@ -512,7 +650,7 @@ fc_remote_port_chkready(struct fc_rport *rport) switch (rport->port_state) { case FC_PORTSTATE_ONLINE: - if (rport->roles & FC_RPORT_ROLE_FCP_TARGET) + if (rport->roles & FC_PORT_ROLE_FCP_TARGET) result = 0; else if (rport->flags & FC_RPORT_DEVLOSS_PENDING) result = DID_IMM_RETRY << 16; @@ -549,6 +687,27 @@ static inline void u64_to_wwn(u64 inm, u8 *wwn) wwn[7] = inm & 0xff; } +/** + * fc_vport_set_state() - called to set a vport's state. Saves the old state, + * excepting the transitory states of initializing and sending the ELS + * traffic to instantiate the vport on the link. + * + * Assumes the driver has surrounded this with the proper locking to ensure + * a coherent state change. + * + * @vport: virtual port whose state is changing + * @new_state: new state + **/ +static inline void +fc_vport_set_state(struct fc_vport *vport, enum fc_vport_state new_state) +{ + if ((new_state != FC_VPORT_UNKNOWN) && + (new_state != FC_VPORT_INITIALIZING)) + vport->vport_last_state = vport->vport_state; + vport->vport_state = new_state; +} + + struct scsi_transport_template *fc_attach_transport( struct fc_function_template *); void fc_release_transport(struct scsi_transport_template *); @@ -567,5 +726,6 @@ void fc_host_post_vendor_event(struct Scsi_Host *shost, u32 event_number, * be sure to read the Vendor Type and ID formatting requirements * specified in scsi_netlink.h */ +int fc_vport_terminate(struct fc_vport *vport); #endif /* SCSI_TRANSPORT_FC_H */ diff --git a/include/scsi/scsi_transport_iscsi.h b/include/scsi/scsi_transport_iscsi.h index d5c218ddc527..706c0cd36c14 100644 --- a/include/scsi/scsi_transport_iscsi.h +++ b/include/scsi/scsi_transport_iscsi.h @@ -79,7 +79,8 @@ struct iscsi_transport { char *name; unsigned int caps; /* LLD sets this to indicate what values it can export to sysfs */ - unsigned int param_mask; + uint64_t param_mask; + uint64_t host_param_mask; struct scsi_host_template *host_template; /* LLD connection data size */ int conndata_size; @@ -89,7 +90,8 @@ struct iscsi_transport { unsigned int max_conn; unsigned int max_cmd_len; struct iscsi_cls_session *(*create_session) (struct iscsi_transport *it, - struct scsi_transport_template *t, uint32_t sn, uint32_t *hn); + struct scsi_transport_template *t, uint16_t, uint16_t, + uint32_t sn, uint32_t *hn); void (*destroy_session) (struct iscsi_cls_session *session); struct iscsi_cls_conn *(*create_conn) (struct iscsi_cls_session *sess, uint32_t cid); @@ -105,14 +107,18 @@ struct iscsi_transport { enum iscsi_param param, char *buf); int (*get_session_param) (struct iscsi_cls_session *session, enum iscsi_param param, char *buf); + int (*get_host_param) (struct Scsi_Host *shost, + enum iscsi_host_param param, char *buf); + int (*set_host_param) (struct Scsi_Host *shost, + enum iscsi_host_param param, char *buf, + int buflen); int (*send_pdu) (struct iscsi_cls_conn *conn, struct iscsi_hdr *hdr, char *data, uint32_t data_size); void (*get_stats) (struct iscsi_cls_conn *conn, struct iscsi_stats *stats); void (*init_cmd_task) (struct iscsi_cmd_task *ctask); void (*init_mgmt_task) (struct iscsi_conn *conn, - struct iscsi_mgmt_task *mtask, - char *data, uint32_t data_size); + struct iscsi_mgmt_task *mtask); int (*xmit_cmd_task) (struct iscsi_conn *conn, struct iscsi_cmd_task *ctask); void (*cleanup_cmd_task) (struct iscsi_conn *conn, @@ -124,7 +130,7 @@ struct iscsi_transport { uint64_t *ep_handle); int (*ep_poll) (uint64_t ep_handle, int timeout_ms); void (*ep_disconnect) (uint64_t ep_handle); - int (*tgt_dscvr) (enum iscsi_tgt_dscvr type, uint32_t host_no, + int (*tgt_dscvr) (struct Scsi_Host *shost, enum iscsi_tgt_dscvr type, uint32_t enable, struct sockaddr *dst_addr); }; |