diff options
Diffstat (limited to 'include')
80 files changed, 1735 insertions, 881 deletions
diff --git a/include/asm-arm/arch-at91/at91_ecc.h b/include/asm-arm/arch-at91/at91_ecc.h index ff93df516d6d..1e5a8caca2d1 100644 --- a/include/asm-arm/arch-at91/at91_ecc.h +++ b/include/asm-arm/arch-at91/at91_ecc.h @@ -13,26 +13,26 @@ #ifndef AT91_ECC_H #define AT91_ECC_H -#define AT91_ECC_CR (AT91_ECC + 0x00) /* Control register */ +#define AT91_ECC_CR 0x00 /* Control register */ #define AT91_ECC_RST (1 << 0) /* Reset parity */ -#define AT91_ECC_MR (AT91_ECC + 0x04) /* Mode register */ +#define AT91_ECC_MR 0x04 /* Mode register */ #define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */ #define AT91_ECC_PAGESIZE_528 (0) #define AT91_ECC_PAGESIZE_1056 (1) #define AT91_ECC_PAGESIZE_2112 (2) #define AT91_ECC_PAGESIZE_4224 (3) -#define AT91_ECC_SR (AT91_ECC + 0x08) /* Status register */ +#define AT91_ECC_SR 0x08 /* Status register */ #define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */ #define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */ #define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */ -#define AT91_ECC_PR (AT91_ECC + 0x0c) /* Parity register */ +#define AT91_ECC_PR 0x0c /* Parity register */ #define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */ #define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */ -#define AT91_ECC_NPR (AT91_ECC + 0x10) /* NParity register */ +#define AT91_ECC_NPR 0x10 /* NParity register */ #define AT91_ECC_NPARITY (0xffff << 0) /* NParity */ #endif diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h index 52cd8e5dabc9..c2b13c280155 100644 --- a/include/asm-arm/arch-at91/at91_pmc.h +++ b/include/asm-arm/arch-at91/at91_pmc.h @@ -76,10 +76,17 @@ #define AT91_PMC_PRES_32 (5 << 2) #define AT91_PMC_PRES_64 (6 << 2) #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ -#define AT91_PMC_MDIV_1 (0 << 8) -#define AT91_PMC_MDIV_2 (1 << 8) -#define AT91_PMC_MDIV_3 (2 << 8) -#define AT91_PMC_MDIV_4 (3 << 8) +#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ +#define AT91RM9200_PMC_MDIV_2 (1 << 8) +#define AT91RM9200_PMC_MDIV_3 (2 << 8) +#define AT91RM9200_PMC_MDIV_4 (3 << 8) +#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ +#define AT91SAM9_PMC_MDIV_2 (1 << 8) +#define AT91SAM9_PMC_MDIV_4 (2 << 8) +#define AT91SAM9_PMC_MDIV_6 (3 << 8) +#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ +#define AT91_PMC_PDIV_1 (0 << 12) +#define AT91_PMC_PDIV_2 (1 << 12) #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ diff --git a/include/asm-arm/arch-at91/at91_shdwc.h b/include/asm-arm/arch-at91/at91_shdwc.h index 01b433de2272..581fa41d90e8 100644 --- a/include/asm-arm/arch-at91/at91_shdwc.h +++ b/include/asm-arm/arch-at91/at91_shdwc.h @@ -24,10 +24,12 @@ #define AT91_SHDW_WKMODE0_LOW 2 #define AT91_SHDW_WKMODE0_ANYLEVEL 3 #define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */ +#define AT91_SHDW_CPTWK0_(x) ((x) << 4) #define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */ #define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */ #define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */ #define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */ +#define AT91_SHDW_RTCWK (1 << 17) /* Real-time Clock Wake-up [SAM9RL] */ #endif diff --git a/include/asm-arm/arch-at91/at91cap9_ddrsdr.h b/include/asm-arm/arch-at91/at91cap9_ddrsdr.h new file mode 100644 index 000000000000..efdb23af1ee4 --- /dev/null +++ b/include/asm-arm/arch-at91/at91cap9_ddrsdr.h @@ -0,0 +1,100 @@ +/* + * include/asm-arm/arch-at91/at91cap9_ddrsdr.h + * + * DDR/SDR Controller (DDRSDRC) - System peripherals registers. + * Based on AT91CAP9 datasheet revision B. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91CAP9_DDRSDR_H +#define AT91CAP9_DDRSDR_H + +#define AT91_DDRSDRC_MR (AT91_DDRSDRC + 0x00) /* Mode Register */ +#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */ +#define AT91_DDRSDRC_MODE_NORMAL 0 +#define AT91_DDRSDRC_MODE_NOP 1 +#define AT91_DDRSDRC_MODE_PRECHARGE 2 +#define AT91_DDRSDRC_MODE_LMR 3 +#define AT91_DDRSDRC_MODE_REFRESH 4 +#define AT91_DDRSDRC_MODE_EXT_LMR 5 +#define AT91_DDRSDRC_MODE_DEEP 6 + +#define AT91_DDRSDRC_RTR (AT91_DDRSDRC + 0x04) /* Refresh Timer Register */ +#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */ + +#define AT91_DDRSDRC_CR (AT91_DDRSDRC + 0x08) /* Configuration Register */ +#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */ +#define AT91_DDRSDRC_NC_SDR8 (0 << 0) +#define AT91_DDRSDRC_NC_SDR9 (1 << 0) +#define AT91_DDRSDRC_NC_SDR10 (2 << 0) +#define AT91_DDRSDRC_NC_SDR11 (3 << 0) +#define AT91_DDRSDRC_NC_DDR9 (0 << 0) +#define AT91_DDRSDRC_NC_DDR10 (1 << 0) +#define AT91_DDRSDRC_NC_DDR11 (2 << 0) +#define AT91_DDRSDRC_NC_DDR12 (3 << 0) +#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */ +#define AT91_DDRSDRC_NR_11 (0 << 2) +#define AT91_DDRSDRC_NR_12 (1 << 2) +#define AT91_DDRSDRC_NR_13 (2 << 2) +#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */ +#define AT91_DDRSDRC_CAS_2 (2 << 4) +#define AT91_DDRSDRC_CAS_3 (3 << 4) +#define AT91_DDRSDRC_CAS_25 (6 << 4) +#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */ +#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ + +#define AT91_DDRSDRC_T0PR (AT91_DDRSDRC + 0x0C) /* Timing 0 Register */ +#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ +#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */ +#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */ +#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */ +#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ +#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ +#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */ +#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ + +#define AT91_DDRSDRC_T1PR (AT91_DDRSDRC + 0x10) /* Timing 1 Register */ +#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */ +#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */ +#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ +#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ + +#define AT91_DDRSDRC_LPR (AT91_DDRSDRC + 0x18) /* Low Power Register */ +#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ +#define AT91_DDRSDRC_LPCB_DISABLE 0 +#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 +#define AT91_DDRSDRC_LPCB_POWER_DOWN 2 +#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3 +#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */ +#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */ +#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ +#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */ +#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ +#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12) +#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12) +#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12) + +#define AT91_DDRSDRC_MDR (AT91_DDRSDRC + 0x1C) /* Memory Device Register */ +#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ +#define AT91_DDRSDRC_MD_SDR 0 +#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 +#define AT91_DDRSDRC_MD_DDR 2 +#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 + +#define AT91_DDRSDRC_DLLR (AT91_DDRSDRC + 0x20) /* DLL Information Register */ +#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ +#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ +#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ +#define AT91_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */ +#define AT91_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */ +#define AT91_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */ +#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ +#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */ +#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */ + + +#endif diff --git a/include/asm-arm/arch-at91/at91sam926x_mc.h b/include/asm-arm/arch-at91/at91sam9_sdramc.h index d82631c251f1..d3b8b3da6b4d 100644 --- a/include/asm-arm/arch-at91/at91sam926x_mc.h +++ b/include/asm-arm/arch-at91/at91sam9_sdramc.h @@ -1,7 +1,7 @@ /* - * include/asm-arm/arch-at91/at91sam926x_mc.h + * include/asm-arm/arch-at91/at91sam9_sdramc.h * - * Memory Controllers (SMC, SDRAMC) - System peripherals registers. + * SDRAM Controllers (SDRAMC) - System peripherals registers. * Based on AT91SAM9261 datasheet revision D. * * This program is free software; you can redistribute it and/or modify @@ -10,8 +10,8 @@ * (at your option) any later version. */ -#ifndef AT91SAM926x_MC_H -#define AT91SAM926x_MC_H +#ifndef AT91SAM9_SDRAMC_H +#define AT91SAM9_SDRAMC_H /* SDRAM Controller (SDRAMC) registers */ #define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ @@ -62,7 +62,7 @@ #define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */ #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ -#define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */ +#define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */ #define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ #define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) #define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) @@ -80,62 +80,4 @@ #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 -/* Static Memory Controller (SMC) registers */ -#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ -#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ -#define AT91_SMC_NWESETUP_(x) ((x) << 0) -#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ -#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) -#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ -#define AT91_SMC_NRDSETUP_(x) ((x) << 16) -#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ -#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) - -#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ -#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ -#define AT91_SMC_NWEPULSE_(x) ((x) << 0) -#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ -#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) -#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ -#define AT91_SMC_NRDPULSE_(x) ((x) << 16) -#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ -#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) - -#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ -#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ -#define AT91_SMC_NWECYCLE_(x) ((x) << 0) -#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ -#define AT91_SMC_NRDCYCLE_(x) ((x) << 16) - -#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ -#define AT91_SMC_READMODE (1 << 0) /* Read Mode */ -#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ -#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ -#define AT91_SMC_EXNWMODE_DISABLE (0 << 4) -#define AT91_SMC_EXNWMODE_FROZEN (2 << 4) -#define AT91_SMC_EXNWMODE_READY (3 << 4) -#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ -#define AT91_SMC_BAT_SELECT (0 << 8) -#define AT91_SMC_BAT_WRITE (1 << 8) -#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ -#define AT91_SMC_DBW_8 (0 << 12) -#define AT91_SMC_DBW_16 (1 << 12) -#define AT91_SMC_DBW_32 (2 << 12) -#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ -#define AT91_SMC_TDF_(x) ((x) << 16) -#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ -#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ -#define AT91_SMC_PS (3 << 28) /* Page Size */ -#define AT91_SMC_PS_4 (0 << 28) -#define AT91_SMC_PS_8 (1 << 28) -#define AT91_SMC_PS_16 (2 << 28) -#define AT91_SMC_PS_32 (3 << 28) - -#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */ -#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ -#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ -#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ -#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ -#endif - #endif diff --git a/include/asm-arm/arch-at91/at91sam9_smc.h b/include/asm-arm/arch-at91/at91sam9_smc.h new file mode 100644 index 000000000000..9e49eed31e50 --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9_smc.h @@ -0,0 +1,73 @@ +/* + * include/asm-arm/arch-at91/at91sam9_smc.h + * + * Static Memory Controllers (SMC) - System peripherals registers. + * Based on AT91SAM9261 datasheet revision D. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9_SMC_H +#define AT91SAM9_SMC_H + +#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ +#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ +#define AT91_SMC_NWESETUP_(x) ((x) << 0) +#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ +#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) +#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ +#define AT91_SMC_NRDSETUP_(x) ((x) << 16) +#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ +#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) + +#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ +#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ +#define AT91_SMC_NWEPULSE_(x) ((x) << 0) +#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ +#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) +#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ +#define AT91_SMC_NRDPULSE_(x) ((x) << 16) +#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ +#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) + +#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ +#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ +#define AT91_SMC_NWECYCLE_(x) ((x) << 0) +#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ +#define AT91_SMC_NRDCYCLE_(x) ((x) << 16) + +#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ +#define AT91_SMC_READMODE (1 << 0) /* Read Mode */ +#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ +#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ +#define AT91_SMC_EXNWMODE_DISABLE (0 << 4) +#define AT91_SMC_EXNWMODE_FROZEN (2 << 4) +#define AT91_SMC_EXNWMODE_READY (3 << 4) +#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ +#define AT91_SMC_BAT_SELECT (0 << 8) +#define AT91_SMC_BAT_WRITE (1 << 8) +#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ +#define AT91_SMC_DBW_8 (0 << 12) +#define AT91_SMC_DBW_16 (1 << 12) +#define AT91_SMC_DBW_32 (2 << 12) +#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ +#define AT91_SMC_TDF_(x) ((x) << 16) +#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ +#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ +#define AT91_SMC_PS (3 << 28) /* Page Size */ +#define AT91_SMC_PS_4 (0 << 28) +#define AT91_SMC_PS_8 (1 << 28) +#define AT91_SMC_PS_16 (2 << 28) +#define AT91_SMC_PS_32 (3 << 28) + +#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */ +#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ +#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ +#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ +#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ +#endif + +#endif diff --git a/include/asm-arm/arch-ep93xx/gpio.h b/include/asm-arm/arch-ep93xx/gpio.h index 9b1864bbd9a8..186e7c715f8a 100644 --- a/include/asm-arm/arch-ep93xx/gpio.h +++ b/include/asm-arm/arch-ep93xx/gpio.h @@ -101,30 +101,17 @@ /* new generic GPIO API - see Documentation/gpio.txt */ -static inline int gpio_request(unsigned gpio, const char *label) -{ - if (gpio > EP93XX_GPIO_LINE_MAX) - return -EINVAL; - return 0; -} +#include <asm-generic/gpio.h> -static inline void gpio_free(unsigned gpio) -{ -} - -int gpio_direction_input(unsigned gpio); -int gpio_direction_output(unsigned gpio, int value); -int gpio_get_value(unsigned gpio); -void gpio_set_value(unsigned gpio, int value); - -#include <asm-generic/gpio.h> /* cansleep wrappers */ +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep /* * Map GPIO A0..A7 (0..7) to irq 64..71, * B0..B7 (7..15) to irq 72..79, and * F0..F7 (16..24) to irq 80..87. */ - static inline int gpio_to_irq(unsigned gpio) { if (gpio <= EP93XX_GPIO_LINE_MAX_IRQ) diff --git a/include/asm-arm/arch-ks8695/devices.h b/include/asm-arm/arch-ks8695/devices.h index b0364dce463f..7ad2c656e162 100644 --- a/include/asm-arm/arch-ks8695/devices.h +++ b/include/asm-arm/arch-ks8695/devices.h @@ -18,6 +18,11 @@ extern void __init ks8695_add_device_wan(void); extern void __init ks8695_add_device_lan(void); extern void __init ks8695_add_device_hpna(void); + /* LEDs */ +extern short ks8695_leds_cpu; +extern short ks8695_leds_timer; +extern void __init ks8695_init_leds(u8 cpu_led, u8 timer_led); + /* PCI */ #define KS8695_MODE_PCI 0 #define KS8695_MODE_MINIPCI 1 diff --git a/include/asm-arm/arch-mxc/board-mx31ads.h b/include/asm-arm/arch-mxc/board-mx31ads.h index be29b83ad4ae..8590127760a8 100644 --- a/include/asm-arm/arch-mxc/board-mx31ads.h +++ b/include/asm-arm/arch-mxc/board-mx31ads.h @@ -11,107 +11,77 @@ #ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ #define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ -/*! - * @name PBC Controller parameters - */ -/*! @{ */ -/*! - * Base address of PBC controller - */ +/* Base address of PBC controller */ #define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) /* Offsets for the PBC Controller register */ -/*! - * PBC Board status register offset - */ + +/* PBC Board status register offset */ #define PBC_BSTAT 0x000002 -/*! - * PBC Board control register 1 set address. - */ + +/* PBC Board control register 1 set address */ #define PBC_BCTRL1_SET 0x000004 -/*! - * PBC Board control register 1 clear address. - */ + +/* PBC Board control register 1 clear address */ #define PBC_BCTRL1_CLEAR 0x000006 -/*! - * PBC Board control register 2 set address. - */ + +/* PBC Board control register 2 set address */ #define PBC_BCTRL2_SET 0x000008 -/*! - * PBC Board control register 2 clear address. - */ + +/* PBC Board control register 2 clear address */ #define PBC_BCTRL2_CLEAR 0x00000A -/*! - * PBC Board control register 3 set address. - */ + +/* PBC Board control register 3 set address */ #define PBC_BCTRL3_SET 0x00000C -/*! - * PBC Board control register 3 clear address. - */ + +/* PBC Board control register 3 clear address */ #define PBC_BCTRL3_CLEAR 0x00000E -/*! - * PBC Board control register 4 set address. - */ + +/* PBC Board control register 4 set address */ #define PBC_BCTRL4_SET 0x000010 -/*! - * PBC Board control register 4 clear address. - */ + +/* PBC Board control register 4 clear address */ #define PBC_BCTRL4_CLEAR 0x000012 -/*! - * PBC Board status register 1. - */ + +/* PBC Board status register 1 */ #define PBC_BSTAT1 0x000014 -/*! - * PBC Board interrupt status register. - */ + +/* PBC Board interrupt status register */ #define PBC_INTSTATUS 0x000016 -/*! - * PBC Board interrupt current status register. - */ + +/* PBC Board interrupt current status register */ #define PBC_INTCURR_STATUS 0x000018 -/*! - * PBC Interrupt mask register set address. - */ + +/* PBC Interrupt mask register set address */ #define PBC_INTMASK_SET 0x00001A -/*! - * PBC Interrupt mask register clear address. - */ + +/* PBC Interrupt mask register clear address */ #define PBC_INTMASK_CLEAR 0x00001C -/*! - * External UART A. - */ +/* External UART A */ #define PBC_SC16C652_UARTA 0x010000 -/*! - * External UART B. - */ + +/* External UART B */ #define PBC_SC16C652_UARTB 0x010010 -/*! - * Ethernet Controller IO base address. - */ + +/* Ethernet Controller IO base address */ #define PBC_CS8900A_IOBASE 0x020000 -/*! - * Ethernet Controller Memory base address. - */ + +/* Ethernet Controller Memory base address */ #define PBC_CS8900A_MEMBASE 0x021000 -/*! - * Ethernet Controller DMA base address. - */ + +/* Ethernet Controller DMA base address */ #define PBC_CS8900A_DMABASE 0x022000 -/*! - * External chip select 0. - */ + +/* External chip select 0 */ #define PBC_XCS0 0x040000 -/*! - * LCD Display enable. - */ + +/* LCD Display enable */ #define PBC_LCD_EN_B 0x060000 -/*! - * Code test debug enable. - */ + +/* Code test debug enable */ #define PBC_CODE_B 0x070000 -/*! - * PSRAM memory select. - */ + +/* PSRAM memory select */ #define PBC_PSRAM_B 0x5000000 #define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS) @@ -139,4 +109,4 @@ #define MXC_MAX_EXP_IO_LINES 16 -#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ +#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ diff --git a/include/asm-arm/arch-mxc/dma.h b/include/asm-arm/arch-mxc/dma.h index 65e639d51d2b..c822d569a05e 100644 --- a/include/asm-arm/arch-mxc/dma.h +++ b/include/asm-arm/arch-mxc/dma.h @@ -11,11 +11,4 @@ #ifndef __ASM_ARCH_MXC_DMA_H__ #define __ASM_ARCH_MXC_DMA_H__ -/*! - * @file dma.h - * @brief This file contains Unified DMA API for all MXC platforms. - * The API is platform independent. - * - * @ingroup SDMA - */ #endif diff --git a/include/asm-arm/arch-mxc/hardware.h b/include/asm-arm/arch-mxc/hardware.h index 3c09b92fef0d..e87ff0679d5e 100644 --- a/include/asm-arm/arch-mxc/hardware.h +++ b/include/asm-arm/arch-mxc/hardware.h @@ -8,45 +8,24 @@ * published by the Free Software Foundation. */ -/*! - * @file hardware.h - * @brief This file contains the hardware definitions of the board. - * - * @ingroup System - */ #ifndef __ASM_ARCH_MXC_HARDWARE_H__ #define __ASM_ARCH_MXC_HARDWARE_H__ #include <asm/sizes.h> -#include <asm/arch/mx31.h> +#ifdef CONFIG_ARCH_MX3 +# include <asm/arch/mx31.h> +#endif #include <asm/arch/mxc.h> -#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM) - /* * --------------------------------------------------------------------------- * Board specific defines * --------------------------------------------------------------------------- */ -#define MXC_EXP_IO_BASE (MXC_GPIO_INT_BASE + MXC_MAX_GPIO_LINES) - -#include <asm/arch/board-mx31ads.h> - -#ifndef MXC_MAX_EXP_IO_LINES -#define MXC_MAX_EXP_IO_LINES 0 +#ifdef CONFIG_MACH_MX31ADS +# include <asm/arch/board-mx31ads.h> #endif -#define MXC_MAX_VIRTUAL_INTS 16 -#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES) -#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE -#define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1) -#define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2) - -#define MXC_MAX_INTS (MXC_MAX_INT_LINES + \ - MXC_MAX_GPIO_LINES + \ - MXC_MAX_EXP_IO_LINES + \ - MXC_MAX_VIRTUAL_INTS) - -#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ +#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ diff --git a/include/asm-arm/arch-mxc/io.h b/include/asm-arm/arch-mxc/io.h index cf6c83a4b9f7..65b6810124c1 100644 --- a/include/asm-arm/arch-mxc/io.h +++ b/include/asm-arm/arch-mxc/io.h @@ -8,24 +8,13 @@ * published by the Free Software Foundation. */ -/*! - * @file io.h - * @brief This file contains some memory mapping macros. - * @note There is no real ISA or PCI buses. But have to define these macros - * for some drivers to compile. - * - * @ingroup System - */ - #ifndef __ASM_ARCH_MXC_IO_H__ #define __ASM_ARCH_MXC_IO_H__ -/*! Allow IO space to be anywhere in the memory */ +/* Allow IO space to be anywhere in the memory */ #define IO_SPACE_LIMIT 0xffffffff -/*! - * io address mapping macro - */ +/* io address mapping macro */ #define __io(a) ((void __iomem *)(a)) #define __mem_pci(a) (a) diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h index e4686c6bc4bf..b2c5205e1962 100644 --- a/include/asm-arm/arch-mxc/irqs.h +++ b/include/asm-arm/arch-mxc/irqs.h @@ -13,26 +13,17 @@ #include <asm/hardware.h> -/*! - * @file irqs.h - * @brief This file defines the number of normal interrupts and fast interrupts - * - * @ingroup Interrupt - */ - #define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) #define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_GPIO_INT_BASE) #define MXC_GPIO_TO_IRQ(x) (MXC_GPIO_INT_BASE + x) -/*! - * Number of normal interrupts - */ -#define NR_IRQS MXC_MAX_INTS +/* Number of normal interrupts */ +#define NR_IRQS (MXC_MAX_INT_LINES + \ + MXC_MAX_GPIO_LINES + \ + MXC_MAX_VIRTUAL_INTS) -/*! - * Number of fast interrupts - */ +/* Number of fast interrupts */ #define NR_FIQS MXC_MAX_INTS -#endif /* __ASM_ARCH_MXC_IRQS_H__ */ +#endif /* __ASM_ARCH_MXC_IRQS_H__ */ diff --git a/include/asm-arm/arch-mxc/memory.h b/include/asm-arm/arch-mxc/memory.h index c89aac83a407..059f83023a10 100644 --- a/include/asm-arm/arch-mxc/memory.h +++ b/include/asm-arm/arch-mxc/memory.h @@ -13,24 +13,17 @@ #include <asm/hardware.h> -/*! - * @file memory.h - * @brief This file contains macros needed by the Linux kernel and drivers. - * - * @ingroup Memory - */ - -/*! +/* * Virtual view <-> DMA view memory address translations * This macro is used to translate the virtual address to an address * suitable to be passed to set_dma_addr() */ #define __virt_to_bus(a) __virt_to_phys(a) -/*! +/* * Used to convert an address for DMA operations to an address that the * kernel can use. */ #define __bus_to_virt(a) __phys_to_virt(a) -#endif /* __ASM_ARCH_MXC_MEMORY_H__ */ +#endif /* __ASM_ARCH_MXC_MEMORY_H__ */ diff --git a/include/asm-arm/arch-mxc/mx31.h b/include/asm-arm/arch-mxc/mx31.h index 85c49c9e5d15..36a1af495bb3 100644 --- a/include/asm-arm/arch-mxc/mx31.h +++ b/include/asm-arm/arch-mxc/mx31.h @@ -317,6 +317,8 @@ #define MXC_MAX_INT_LINES 64 #define MXC_GPIO_INT_BASE MXC_MAX_INT_LINES +#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM) +#define MXC_MAX_VIRTUAL_INTS 16 /*! * Number of GPIO port as defined in the IC Spec @@ -329,7 +331,33 @@ #define PROD_SIGNATURE 0x1 /* For MX31 */ +/* silicon revisions specific to i.MX31 */ +#define CHIP_REV_1_0 0x10 +#define CHIP_REV_1_1 0x11 +#define CHIP_REV_1_2 0x12 +#define CHIP_REV_1_3 0x13 +#define CHIP_REV_2_0 0x20 +#define CHIP_REV_2_1 0x21 +#define CHIP_REV_2_2 0x22 +#define CHIP_REV_2_3 0x23 +#define CHIP_REV_3_0 0x30 +#define CHIP_REV_3_1 0x31 +#define CHIP_REV_3_2 0x32 + #define SYSTEM_REV_MIN CHIP_REV_1_0 #define SYSTEM_REV_NUM 3 -#endif /* __ASM_ARCH_MXC_MX31_H__ */ +#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) + +/* this is a i.MX31 CPU */ +#define cpu_is_mx31() (1) + +extern unsigned int system_rev; + +static inline int mx31_revision(void) +{ + return system_rev; +} +#endif + +#endif /* __ASM_ARCH_MXC_MX31_H__ */ diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h index 0837f1f9ca31..146d3f60951a 100644 --- a/include/asm-arm/arch-mxc/mxc.h +++ b/include/asm-arm/arch-mxc/mxc.h @@ -15,6 +15,11 @@ #error "Do not include directly." #endif +/* clean up all things that are not used */ +#ifndef CONFIG_ARCH_MX3 +# define cpu_is_mx31() (0) +#endif + /* ***************************************** * GPT Register definitions * @@ -31,9 +36,7 @@ #define MXC_GPT_GPTICR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x20) #define MXC_GPT_GPTCNT IO_ADDRESS(GPT1_BASE_ADDR + 0x24) -/*! - * GPT Control register bit definitions - */ +/* GPT Control register bit definitions */ #define GPTCR_FO3 (1 << 31) #define GPTCR_FO2 (1 << 30) #define GPTCR_FO1 (1 << 29) @@ -146,4 +149,4 @@ #define IIM_PROD_REV_SH 3 #define IIM_PROD_REV_LEN 5 -#endif /* __ASM_ARCH_MXC_H__ */ +#endif /* __ASM_ARCH_MXC_H__ */ diff --git a/include/asm-arm/arch-mxc/system.h b/include/asm-arm/arch-mxc/system.h index 109956b41aca..bbfc37465fc5 100644 --- a/include/asm-arm/arch-mxc/system.h +++ b/include/asm-arm/arch-mxc/system.h @@ -21,30 +21,14 @@ #ifndef __ASM_ARCH_MXC_SYSTEM_H__ #define __ASM_ARCH_MXC_SYSTEM_H__ -/*! - * @file system.h - * @brief This file contains idle and reset functions. - * - * @ingroup System - */ - -/*! - * This function puts the CPU into idle mode. It is called by default_idle() - * in process.c file. - */ static inline void arch_idle(void) { cpu_do_idle(); } -/* - * This function resets the system. It is called by machine_restart(). - * - * @param mode indicates different kinds of resets - */ static inline void arch_reset(char mode) { cpu_reset(0); } -#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */ +#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */ diff --git a/include/asm-arm/arch-mxc/vmalloc.h b/include/asm-arm/arch-mxc/vmalloc.h index 83a73da895eb..62d97623412f 100644 --- a/include/asm-arm/arch-mxc/vmalloc.h +++ b/include/asm-arm/arch-mxc/vmalloc.h @@ -20,17 +20,7 @@ #ifndef __ASM_ARCH_MXC_VMALLOC_H__ #define __ASM_ARCH_MXC_VMALLOC_H__ -/*! - * @file vmalloc.h - * - * @brief This file contains platform specific macros for vmalloc. - * - * @ingroup System - */ - -/*! - * vmalloc ending address - */ +/* vmalloc ending address */ #define VMALLOC_END 0xF4000000 -#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */ +#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */ diff --git a/include/asm-arm/arch-ns9xxx/board.h b/include/asm-arm/arch-ns9xxx/board.h index 716f34fdb716..e57443bdbbd9 100644 --- a/include/asm-arm/arch-ns9xxx/board.h +++ b/include/asm-arm/arch-ns9xxx/board.h @@ -1,7 +1,7 @@ /* * include/asm-arm/arch-ns9xxx/board.h * - * Copyright (C) 2006 by Digi International Inc. + * Copyright (C) 2006,2007 by Digi International Inc. * All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -13,8 +13,30 @@ #include <asm/mach-types.h> -#define board_is_a9m9750dev() (machine_is_cc9p9360dev()) +#define board_is_a9m9750dev() (0 \ + || machine_is_cc9p9360dev() \ + || machine_is_cc9p9750dev() \ + ) -#define board_is_jscc9p9360() (machine_is_cc9p9360js()) +#define board_is_a9mvali() (0 \ + || machine_is_cc9p9360val() \ + || machine_is_cc9p9750val() \ + ) + +#define board_is_jscc9p9210() (0 \ + || machine_is_cc9p9210js() \ + ) + +#define board_is_jscc9p9215() (0 \ + || machine_is_cc9p9215js() \ + ) + +#define board_is_jscc9p9360() (0 \ + || machine_is_cc9p9360js() \ + ) + +#define board_is_uncbas() (0 \ + || machine_is_cc7ucamry() \ + ) #endif /* ifndef __ASM_ARCH_BOARD_H */ diff --git a/include/asm-arm/arch-ns9xxx/clock.h b/include/asm-arm/arch-ns9xxx/clock.h deleted file mode 100644 index b943d3a92a1d..000000000000 --- a/include/asm-arm/arch-ns9xxx/clock.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * include/asm-arm/arch-ns9xxx/clock.h - * - * Copyright (C) 2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#include <asm/arch-ns9xxx/regs-sys.h> - -#define CRYSTAL 29491200 /* Hz */ - -/* The HRM calls this value f_vco */ -static inline u32 ns9xxx_systemclock(void) __attribute__((const)); -static inline u32 ns9xxx_systemclock(void) -{ - u32 pll = __raw_readl(SYS_PLL); - - /* - * The system clock should be a multiple of HZ * TIMERCLOCKSELECT (in - * time.c). - * - * The following values are given: - * - TIMERCLOCKSELECT == 2^i for an i in {0 .. 6} - * - CRYSTAL == 29491200 == 2^17 * 3^2 * 5^2 - * - ND in {0 .. 31} - * - FS in {0 .. 3} - * - * Assuming the worst, we consider: - * - TIMERCLOCKSELECT == 64 - * - ND == 0 - * - FS == 3 - * - * So HZ should be a divisor of: - * (CRYSTAL * (ND + 1) >> FS) / TIMERCLOCKSELECT - * == (2^17 * 3^2 * 5^2 * 1 >> 3) / 64 - * == 2^8 * 3^2 * 5^2 - * == 57600 - * - * Currently HZ is defined to be 100 for this platform. - * - * Fine. - */ - return CRYSTAL * (REGGETIM(pll, SYS_PLL, ND) + 1) - >> REGGETIM(pll, SYS_PLL, FS); -} - -static inline u32 ns9xxx_cpuclock(void) __attribute__((const)); -static inline u32 ns9xxx_cpuclock(void) -{ - return ns9xxx_systemclock() / 2; -} - -static inline u32 ns9xxx_ahbclock(void) __attribute__((const)); -static inline u32 ns9xxx_ahbclock(void) -{ - return ns9xxx_systemclock() / 4; -} - -static inline u32 ns9xxx_bbusclock(void) __attribute__((const)); -static inline u32 ns9xxx_bbusclock(void) -{ - return ns9xxx_systemclock() / 8; -} - -#endif /* ifndef __ASM_ARCH_CLOCK_H */ diff --git a/include/asm-arm/arch-ns9xxx/entry-macro.S b/include/asm-arm/arch-ns9xxx/entry-macro.S index 86aec87303e4..89a21c530468 100644 --- a/include/asm-arm/arch-ns9xxx/entry-macro.S +++ b/include/asm-arm/arch-ns9xxx/entry-macro.S @@ -1,7 +1,7 @@ /* * include/asm-arm/arch-ns9xxx/entry-macro.S * - * Copyright (C) 2006 by Digi International Inc. + * Copyright (C) 2006,2007 by Digi International Inc. * All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -9,16 +9,16 @@ * the Free Software Foundation. */ #include <asm/hardware.h> -#include <asm/arch-ns9xxx/regs-sys.h> +#include <asm/arch-ns9xxx/regs-sys-common.h> .macro get_irqnr_preamble, base, tmp + ldr \base, =SYS_ISRADDR .endm .macro arch_ret_to_user, tmp1, tmp2 .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =SYS_ISRADDR ldr \irqstat, [\base, #(SYS_ISA - SYS_ISRADDR)] cmp \irqstat, #0 ldrne \irqnr, [\base] diff --git a/include/asm-arm/arch-ns9xxx/irqs.h b/include/asm-arm/arch-ns9xxx/irqs.h index 25d8d28b27f3..e83d48ec42c9 100644 --- a/include/asm-arm/arch-ns9xxx/irqs.h +++ b/include/asm-arm/arch-ns9xxx/irqs.h @@ -1,7 +1,7 @@ /* * include/asm-arm/arch-ns9xxx/irqs.h * - * Copyright (C) 2006 by Digi International Inc. + * Copyright (C) 2006,2007 by Digi International Inc. * All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -11,38 +11,39 @@ #ifndef __ASM_ARCH_IRQS_H #define __ASM_ARCH_IRQS_H -#define IRQ_WATCHDOG 0 -#define IRQ_AHBBUSERR 1 -#define IRQ_BBUSAGG 2 +/* NetSilicon 9360 */ +#define IRQ_NS9XXX_WATCHDOG 0 +#define IRQ_NS9XXX_AHBBUSERR 1 +#define IRQ_NS9360_BBUSAGG 2 /* irq 3 is reserved for NS9360 */ -#define IRQ_ETHRX 4 -#define IRQ_ETHTX 5 -#define IRQ_ETHPHY 6 -#define IRQ_LCD 7 -#define IRQ_SERBRX 8 -#define IRQ_SERBTX 9 -#define IRQ_SERARX 10 -#define IRQ_SERATX 11 -#define IRQ_SERCRX 12 -#define IRQ_SERCTX 13 -#define IRQ_I2C 14 -#define IRQ_BBUSDMA 15 -#define IRQ_TIMER0 16 -#define IRQ_TIMER1 17 -#define IRQ_TIMER2 18 -#define IRQ_TIMER3 19 -#define IRQ_TIMER4 20 -#define IRQ_TIMER5 21 -#define IRQ_TIMER6 22 -#define IRQ_TIMER7 23 -#define IRQ_RTC 24 -#define IRQ_USBHOST 25 -#define IRQ_USBDEVICE 26 -#define IRQ_IEEE1284 27 -#define IRQ_EXT0 28 -#define IRQ_EXT1 29 -#define IRQ_EXT2 30 -#define IRQ_EXT3 31 +#define IRQ_NS9XXX_ETHRX 4 +#define IRQ_NS9XXX_ETHTX 5 +#define IRQ_NS9XXX_ETHPHY 6 +#define IRQ_NS9360_LCD 7 +#define IRQ_NS9360_SERBRX 8 +#define IRQ_NS9360_SERBTX 9 +#define IRQ_NS9360_SERARX 10 +#define IRQ_NS9360_SERATX 11 +#define IRQ_NS9360_SERCRX 12 +#define IRQ_NS9360_SERCTX 13 +#define IRQ_NS9360_I2C 14 +#define IRQ_NS9360_BBUSDMA 15 +#define IRQ_NS9360_TIMER0 16 +#define IRQ_NS9360_TIMER1 17 +#define IRQ_NS9360_TIMER2 18 +#define IRQ_NS9360_TIMER3 19 +#define IRQ_NS9360_TIMER4 20 +#define IRQ_NS9360_TIMER5 21 +#define IRQ_NS9360_TIMER6 22 +#define IRQ_NS9360_TIMER7 23 +#define IRQ_NS9360_RTC 24 +#define IRQ_NS9360_USBHOST 25 +#define IRQ_NS9360_USBDEVICE 26 +#define IRQ_NS9360_IEEE1284 27 +#define IRQ_NS9XXX_EXT0 28 +#define IRQ_NS9XXX_EXT1 29 +#define IRQ_NS9XXX_EXT2 30 +#define IRQ_NS9XXX_EXT3 31 #define BBUS_IRQ(irq) (32 + irq) @@ -67,7 +68,7 @@ /* * these Interrupts are specific for the a9m9750dev board. * They are generated by an FPGA that interrupts the CPU on - * IRQ_EXT2 + * IRQ_NS9360_EXT2 */ #define FPGA_IRQ(irq) (64 + irq) diff --git a/include/asm-arm/arch-ns9xxx/module.h b/include/asm-arm/arch-ns9xxx/module.h new file mode 100644 index 000000000000..ac08a31111e4 --- /dev/null +++ b/include/asm-arm/arch-ns9xxx/module.h @@ -0,0 +1,60 @@ +/* + * include/asm-arm/arch-ns9xxx/module.h + * + * Copyright (C) 2007 by Digi International Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ +#ifndef __ASM_ARCH_MODULE_H +#define __ASM_ARCH_MODULE_H + +#include <asm/mach-types.h> + +#define module_is_cc7ucamry() (0 \ + || machine_is_cc7ucamry() \ + ) + +#define module_is_cc9c() (0 \ + || machine_is_cc9c() \ + ) + +#define module_is_cc9p9210() (0 \ + || machine_is_cc9p9210() \ + || machine_is_cc9p9210js() \ + ) + +#define module_is_cc9p9215() (0 \ + || machine_is_cc9p9215() \ + || machine_is_cc9p9215js() \ + ) + +#define module_is_cc9p9360() (0 \ + || machine_is_a9m9360() \ + || machine_is_cc9p9360dev() \ + || machine_is_cc9p9360js() \ + || machine_is_cc9p9360val() \ + ) + +#define module_is_cc9p9750() (0 \ + || machine_is_a9m9750() \ + || machine_is_cc9p9750dev() \ + || machine_is_cc9p9750js() \ + || machine_is_cc9p9750val() \ + ) + +#define module_is_ccw9c() (0 \ + || machine_is_ccw9c() \ + ) + +#define module_is_inc20otter() (0 \ + || machine_is_inc20otter() \ + ) + +#define module_is_otter() (0 \ + || machine_is_otter() \ + ) + +#endif /* ifndef __ASM_ARCH_MODULE_H */ diff --git a/include/asm-arm/arch-ns9xxx/processor-ns9360.h b/include/asm-arm/arch-ns9xxx/processor-ns9360.h new file mode 100644 index 000000000000..f3aa6c50dbe5 --- /dev/null +++ b/include/asm-arm/arch-ns9xxx/processor-ns9360.h @@ -0,0 +1,32 @@ +/* + * include/asm-arm/arch-ns9xxx/processor-ns9360.h + * + * Copyright (C) 2007 by Digi International Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ +#ifndef __ASM_ARCH_PROCESSORNS9360_H +#define __ASM_ARCH_PROCESSORNS9360_H + +#include <linux/init.h> + +void ns9360_reset(char mode); + +unsigned long ns9360_systemclock(void) __attribute__((const)); + +static inline unsigned long ns9360_cpuclock(void) __attribute__((const)); +static inline unsigned long ns9360_cpuclock(void) +{ + return ns9360_systemclock() / 2; +} + +void __init ns9360_map_io(void); + +extern struct sys_timer ns9360_timer; + +int ns9360_gpio_configure(unsigned gpio, int inv, int func); + +#endif /* ifndef __ASM_ARCH_PROCESSORNS9360_H */ diff --git a/include/asm-arm/arch-ns9xxx/processor.h b/include/asm-arm/arch-ns9xxx/processor.h index 223e51b8e104..f7b53b65de81 100644 --- a/include/asm-arm/arch-ns9xxx/processor.h +++ b/include/asm-arm/arch-ns9xxx/processor.h @@ -1,7 +1,7 @@ /* * include/asm-arm/arch-ns9xxx/processor.h * - * Copyright (C) 2006 by Digi International Inc. + * Copyright (C) 2006,2007 by Digi International Inc. * All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -11,9 +11,32 @@ #ifndef __ASM_ARCH_PROCESSOR_H #define __ASM_ARCH_PROCESSOR_H -#include <asm/mach-types.h> +#include <asm/arch-ns9xxx/module.h> -#define processor_is_ns9360() (machine_is_cc9p9360dev() \ - || machine_is_cc9p9360js()) +#define processor_is_ns9210() (0 \ + || module_is_cc7ucamry() \ + || module_is_cc9p9210() \ + || module_is_inc20otter() \ + || module_is_otter() \ + ) + +#define processor_is_ns9215() (0 \ + || module_is_cc9p9215() \ + ) + +#define processor_is_ns9360() (0 \ + || module_is_cc9p9360() \ + || module_is_cc9c() \ + || module_is_ccw9c() \ + ) + +#define processor_is_ns9750() (0 \ + || module_is_cc9p9750() \ + ) + +#define processor_is_ns921x() (0 \ + || processor_is_ns9210() \ + || processor_is_ns9215() \ + ) #endif /* ifndef __ASM_ARCH_PROCESSOR_H */ diff --git a/include/asm-arm/arch-ns9xxx/regs-sys-common.h b/include/asm-arm/arch-ns9xxx/regs-sys-common.h new file mode 100644 index 000000000000..956c57cb781f --- /dev/null +++ b/include/asm-arm/arch-ns9xxx/regs-sys-common.h @@ -0,0 +1,31 @@ +/* + * include/asm-arm/arch-ns9xxx/regs-sys-common.h + * + * Copyright (C) 2007 by Digi International Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_REGSSYSCOMMON_H +#define __ASM_ARCH_REGSSYSCOMMON_H +#include <asm/hardware.h> + +/* Interrupt Vector Address Register Level x */ +#define SYS_IVA(x) __REG2(0xa09000c4, (x)) + +/* Interrupt Configuration registers */ +#define SYS_IC(x) __REG2(0xa0900144, (x)) + +/* ISRADDR */ +#define SYS_ISRADDR __REG(0xa0900164) + +/* Interrupt Status Active */ +#define SYS_ISA __REG(0xa0900168) + +/* Interrupt Status Raw */ +#define SYS_ISR __REG(0xa090016c) + +#endif /* ifndef __ASM_ARCH_REGSSYSCOMMON_H */ diff --git a/include/asm-arm/arch-ns9xxx/regs-sys.h b/include/asm-arm/arch-ns9xxx/regs-sys-ns9360.h index 749262f86204..318b6945afb6 100644 --- a/include/asm-arm/arch-ns9xxx/regs-sys.h +++ b/include/asm-arm/arch-ns9xxx/regs-sys-ns9360.h @@ -1,15 +1,15 @@ /* - * include/asm-arm/arch-ns9xxx/regs-sys.h + * include/asm-arm/arch-ns9xxx/regs-sys-ns9360.h * - * Copyright (C) 2006 by Digi International Inc. + * Copyright (C) 2006,2007 by Digi International Inc. * All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published by * the Free Software Foundation. */ -#ifndef __ASM_ARCH_REGSSYS_H -#define __ASM_ARCH_REGSSYS_H +#ifndef __ASM_ARCH_REGSSYSNS9360_H +#define __ASM_ARCH_REGSSYSNS9360_H #include <asm/hardware.h> @@ -27,21 +27,6 @@ /* Timer x Read register */ #define SYS_TR(x) __REG2(0xa0900084, (x)) -/* Interrupt Vector Address Register Level x */ -#define SYS_IVA(x) __REG2(0xa09000c4, (x)) - -/* Interrupt Configuration registers */ -#define SYS_IC(x) __REG2(0xa0900144, (x)) - -/* ISRADDR */ -#define SYS_ISRADDR __REG(0xa0900164) - -/* Interrupt Status Active */ -#define SYS_ISA __REG(0xa0900168) - -/* Interrupt Status Raw */ -#define SYS_ISR __REG(0xa090016c) - /* Timer Interrupt Status register */ #define SYS_TIS __REG(0xa0900170) @@ -160,4 +145,4 @@ #define SYS_EIC_LVEDG_LEVEL __REGVAL(SYS_EIC_LVEDG, 0) #define SYS_EIC_LVEDG_EDGE __REGVAL(SYS_EIC_LVEDG, 1) -#endif /* ifndef __ASM_ARCH_REGSSYS_H */ +#endif /* ifndef __ASM_ARCH_REGSSYSNS9360_H */ diff --git a/include/asm-arm/arch-ns9xxx/system.h b/include/asm-arm/arch-ns9xxx/system.h index c1082bd8977c..1348073afe48 100644 --- a/include/asm-arm/arch-ns9xxx/system.h +++ b/include/asm-arm/arch-ns9xxx/system.h @@ -1,7 +1,7 @@ /* * include/asm-arm/arch-ns9xxx/system.h * - * Copyright (C) 2006 by Digi International Inc. + * Copyright (C) 2006,2007 by Digi International Inc. * All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -12,8 +12,8 @@ #define __ASM_ARCH_SYSTEM_H #include <asm/proc-fns.h> -#include <asm/arch-ns9xxx/regs-sys.h> -#include <asm/mach-types.h> +#include <asm/arch-ns9xxx/processor.h> +#include <asm/arch-ns9xxx/processor-ns9360.h> static inline void arch_idle(void) { @@ -22,11 +22,12 @@ static inline void arch_idle(void) static inline void arch_reset(char mode) { - u32 reg; - - reg = __raw_readl(SYS_PLL) >> 16; - REGSET(reg, SYS_PLL, SWC, YES); - __raw_writel(reg, SYS_PLL); +#ifdef CONFIG_PROCESSOR_NS9360 + if (processor_is_ns9360()) + ns9360_reset(mode); + else +#endif + BUG(); BUG(); } diff --git a/include/asm-arm/arch-ns9xxx/uncompress.h b/include/asm-arm/arch-ns9xxx/uncompress.h index 961ca7dc9954..71066baceab7 100644 --- a/include/asm-arm/arch-ns9xxx/uncompress.h +++ b/include/asm-arm/arch-ns9xxx/uncompress.h @@ -11,20 +11,149 @@ #ifndef __ASM_ARCH_UNCOMPRESS_H #define __ASM_ARCH_UNCOMPRESS_H -static void putc(char c) +#include <asm/io.h> + +#define __REG(x) ((void __iomem __force *)(x)) + +static void putc_dummy(char c, void __iomem *base) { - volatile u8 *base = (volatile u8 *)0x40000000; - int t = 0x10000; + /* nothing */ +} +static void putc_ns9360(char c, void __iomem *base) +{ + static int t = 0x10000; + do { + if (t) + --t; + + if (__raw_readl(base + 8) & (1 << 3)) { + __raw_writeb(c, base + 16); + t = 0x10000; + break; + } + } while (t); +} + +static void putc_a9m9750dev(char c, void __iomem *base) +{ + static int t = 0x10000; + do { + if (t) + --t; + + if (__raw_readb(base + 5) & (1 << 5)) { + __raw_writeb(c, base); + t = 0x10000; + break; + } + } while (t); + +} + +static void putc_ns921x(char c, void __iomem *base) +{ + static int t = 0x10000; do { - if (base[5] & 0x20) { - base[0] = c; + if (t) + --t; + + if (!(__raw_readl(base) & (1 << 11))) { + __raw_writeb(c, base + 0x0028); + t = 0x10000; break; } - } while (--t); + } while (t); } -#define arch_decomp_setup() +#define MSCS __REG(0xA0900184) + +#define NS9360_UARTA __REG(0x90200040) +#define NS9360_UARTB __REG(0x90200000) +#define NS9360_UARTC __REG(0x90300000) +#define NS9360_UARTD __REG(0x90300040) + +#define NS9360_UART_ENABLED(base) \ + (__raw_readl(NS9360_UARTA) & (1 << 31)) + +#define A9M9750DEV_UARTA __REG(0x40000000) + +#define NS921XSYS_CLOCK __REG(0xa090017c) +#define NS921X_UARTA __REG(0x90010000) +#define NS921X_UARTB __REG(0x90018000) +#define NS921X_UARTC __REG(0x90020000) +#define NS921X_UARTD __REG(0x90028000) + +#define NS921X_UART_ENABLED(base) \ + (__raw_readl((base) + 0x1000) & (1 << 29)) + +static void autodetect(void (**putc)(char, void __iomem *), void __iomem **base) +{ + if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x00) { + /* ns9360 or ns9750 */ + if (NS9360_UART_ENABLED(NS9360_UARTA)) { + *putc = putc_ns9360; + *base = NS9360_UARTA; + return; + } else if (NS9360_UART_ENABLED(NS9360_UARTB)) { + *putc = putc_ns9360; + *base = NS9360_UARTB; + return; + } else if (NS9360_UART_ENABLED(NS9360_UARTC)) { + *putc = putc_ns9360; + *base = NS9360_UARTC; + return; + } else if (NS9360_UART_ENABLED(NS9360_UARTD)) { + *putc = putc_ns9360; + *base = NS9360_UARTD; + return; + } else if (__raw_readl(__REG(0xa09001f4)) == 0xfffff001) { + *putc = putc_a9m9750dev; + *base = A9M9750DEV_UARTA; + return; + } + } else if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x02) { + /* ns921x */ + u32 clock = __raw_readl(NS921XSYS_CLOCK); + + if ((clock & (1 << 1)) && + NS921X_UART_ENABLED(NS921X_UARTA)) { + *putc = putc_ns921x; + *base = NS921X_UARTA; + return; + } else if ((clock & (1 << 2)) && + NS921X_UART_ENABLED(NS921X_UARTB)) { + *putc = putc_ns921x; + *base = NS921X_UARTB; + return; + } else if ((clock & (1 << 3)) && + NS921X_UART_ENABLED(NS921X_UARTC)) { + *putc = putc_ns921x; + *base = NS921X_UARTC; + return; + } else if ((clock & (1 << 4)) && + NS921X_UART_ENABLED(NS921X_UARTD)) { + *putc = putc_ns921x; + *base = NS921X_UARTD; + return; + } + } + + *putc = putc_dummy; +} + +void (*myputc)(char, void __iomem *); +void __iomem *base; + +static void putc(char c) +{ + myputc(c, base); +} + +static void arch_decomp_setup(void) +{ + autodetect(&myputc, &base); +} #define arch_decomp_wdog() static void flush(void) diff --git a/include/asm-arm/arch-orion/io.h b/include/asm-arm/arch-orion/io.h deleted file mode 100644 index e0b8c39b9167..000000000000 --- a/include/asm-arm/arch-orion/io.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * include/asm-arm/arch-orion/io.h - * - * Tzachi Perelstein <tzachi@marvell.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#include "orion.h" - -#define IO_SPACE_LIMIT 0xffffffff -#define IO_SPACE_REMAP ORION_PCI_SYS_IO_BASE - -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)addr; -} - -#define __io(a) __io(a) -#define __mem_pci(a) (a) - -#endif diff --git a/include/asm-arm/arch-orion/irqs.h b/include/asm-arm/arch-orion/irqs.h deleted file mode 100644 index eea65ca6076a..000000000000 --- a/include/asm-arm/arch-orion/irqs.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * include/asm-arm/arch-orion/irqs.h - * - * IRQ definitions for Orion SoC - * - * Maintainer: Tzachi Perelstein <tzachi@marvell.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IRQS_H__ -#define __ASM_ARCH_IRQS_H__ - -#include "orion.h" /* need GPIO_MAX */ - -/* - * Orion Main Interrupt Controller - */ -#define IRQ_ORION_BRIDGE 0 -#define IRQ_ORION_DOORBELL_H2C 1 -#define IRQ_ORION_DOORBELL_C2H 2 -#define IRQ_ORION_UART0 3 -#define IRQ_ORION_UART1 4 -#define IRQ_ORION_I2C 5 -#define IRQ_ORION_GPIO_0_7 6 -#define IRQ_ORION_GPIO_8_15 7 -#define IRQ_ORION_GPIO_16_23 8 -#define IRQ_ORION_GPIO_24_31 9 -#define IRQ_ORION_PCIE0_ERR 10 -#define IRQ_ORION_PCIE0_INT 11 -#define IRQ_ORION_USB1_CTRL 12 -#define IRQ_ORION_DEV_BUS_ERR 14 -#define IRQ_ORION_PCI_ERR 15 -#define IRQ_ORION_USB_BR_ERR 16 -#define IRQ_ORION_USB0_CTRL 17 -#define IRQ_ORION_ETH_RX 18 -#define IRQ_ORION_ETH_TX 19 -#define IRQ_ORION_ETH_MISC 20 -#define IRQ_ORION_ETH_SUM 21 -#define IRQ_ORION_ETH_ERR 22 -#define IRQ_ORION_IDMA_ERR 23 -#define IRQ_ORION_IDMA_0 24 -#define IRQ_ORION_IDMA_1 25 -#define IRQ_ORION_IDMA_2 26 -#define IRQ_ORION_IDMA_3 27 -#define IRQ_ORION_CESA 28 -#define IRQ_ORION_SATA 29 -#define IRQ_ORION_XOR0 30 -#define IRQ_ORION_XOR1 31 - -/* - * Orion General Purpose Pins - */ -#define IRQ_ORION_GPIO_START 32 -#define NR_GPIO_IRQS GPIO_MAX - -#define NR_IRQS (IRQ_ORION_GPIO_START + NR_GPIO_IRQS) - -#endif /* __ASM_ARCH_IRQS_H__ */ diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h deleted file mode 100644 index 673a418a7419..000000000000 --- a/include/asm-arm/arch-orion/orion.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * include/asm-arm/arch-orion/orion.h - * - * Generic definitions of Orion SoC flavors: - * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2. - * - * Maintainer: Tzachi Perelstein <tzachi@marvell.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_ORION_H__ -#define __ASM_ARCH_ORION_H__ - -/***************************************************************************** - * Orion Address Map - * - * virt phys size - * fdd00000 f1000000 1M on-chip peripheral registers - * fde00000 f2000000 1M PCIe I/O space - * fdf00000 f2100000 1M PCI I/O space - * fe000000 f0000000 16M PCIe WA space (Orion-NAS only) - ****************************************************************************/ -#define ORION_REGS_PHYS_BASE 0xf1000000 -#define ORION_REGS_VIRT_BASE 0xfdd00000 -#define ORION_REGS_SIZE SZ_1M - -#define ORION_PCIE_IO_PHYS_BASE 0xf2000000 -#define ORION_PCIE_IO_VIRT_BASE 0xfde00000 -#define ORION_PCIE_IO_BUS_BASE 0x00000000 -#define ORION_PCIE_IO_SIZE SZ_1M - -#define ORION_PCI_IO_PHYS_BASE 0xf2100000 -#define ORION_PCI_IO_VIRT_BASE 0xfdf00000 -#define ORION_PCI_IO_BUS_BASE 0x00100000 -#define ORION_PCI_IO_SIZE SZ_1M - -/* Relevant only for Orion-NAS */ -#define ORION_PCIE_WA_PHYS_BASE 0xf0000000 -#define ORION_PCIE_WA_VIRT_BASE 0xfe000000 -#define ORION_PCIE_WA_SIZE SZ_16M - -#define ORION_PCIE_MEM_PHYS_BASE 0xe0000000 -#define ORION_PCIE_MEM_SIZE SZ_128M - -#define ORION_PCI_MEM_PHYS_BASE 0xe8000000 -#define ORION_PCI_MEM_SIZE SZ_128M - -/******************************************************************************* - * Supported Devices & Revisions - ******************************************************************************/ -/* Orion-1 (88F5181) */ -#define MV88F5181_DEV_ID 0x5181 -#define MV88F5181_REV_B1 3 -/* Orion-NAS (88F5182) */ -#define MV88F5182_DEV_ID 0x5182 -#define MV88F5182_REV_A2 2 -/* Orion-2 (88F5281) */ -#define MV88F5281_DEV_ID 0x5281 -#define MV88F5281_REV_D1 5 -#define MV88F5281_REV_D2 6 - -/******************************************************************************* - * Orion Registers Map - ******************************************************************************/ -#define ORION_DDR_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x00000) -#define ORION_DDR_REG(x) (ORION_DDR_VIRT_BASE | (x)) - -#define ORION_DEV_BUS_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x10000) -#define ORION_DEV_BUS_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x10000) -#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_VIRT_BASE | (x)) -#define I2C_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x1000) -#define UART0_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2000) -#define UART0_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2000) -#define UART1_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2100) -#define UART1_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2100) - -#define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000) -#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x)) - -#define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000) -#define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x)) - -#define ORION_PCIE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x40000) -#define ORION_PCIE_REG(x) (ORION_PCIE_VIRT_BASE | (x)) - -#define ORION_USB0_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x50000) -#define ORION_USB0_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x50000) -#define ORION_USB0_REG(x) (ORION_USB0_VIRT_BASE | (x)) - -#define ORION_ETH_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x70000) -#define ORION_ETH_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x70000) -#define ORION_ETH_REG(x) (ORION_ETH_VIRT_BASE | (x)) - -#define ORION_SATA_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x80000) -#define ORION_SATA_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x80000) -#define ORION_SATA_REG(x) (ORION_SATA_VIRT_BASE | (x)) - -#define ORION_USB1_PHYS_BASE (ORION_REGS_PHYS_BASE | 0xa0000) -#define ORION_USB1_VIRT_BASE (ORION_REGS_VIRT_BASE | 0xa0000) -#define ORION_USB1_REG(x) (ORION_USB1_VIRT_BASE | (x)) - -/******************************************************************************* - * Device Bus Registers - ******************************************************************************/ -#define MPP_0_7_CTRL ORION_DEV_BUS_REG(0x000) -#define MPP_8_15_CTRL ORION_DEV_BUS_REG(0x004) -#define MPP_16_19_CTRL ORION_DEV_BUS_REG(0x050) -#define MPP_DEV_CTRL ORION_DEV_BUS_REG(0x008) -#define MPP_RESET_SAMPLE ORION_DEV_BUS_REG(0x010) -#define GPIO_OUT ORION_DEV_BUS_REG(0x100) -#define GPIO_IO_CONF ORION_DEV_BUS_REG(0x104) -#define GPIO_BLINK_EN ORION_DEV_BUS_REG(0x108) -#define GPIO_IN_POL ORION_DEV_BUS_REG(0x10c) -#define GPIO_DATA_IN ORION_DEV_BUS_REG(0x110) -#define GPIO_EDGE_CAUSE ORION_DEV_BUS_REG(0x114) -#define GPIO_EDGE_MASK ORION_DEV_BUS_REG(0x118) -#define GPIO_LEVEL_MASK ORION_DEV_BUS_REG(0x11c) -#define DEV_BANK_0_PARAM ORION_DEV_BUS_REG(0x45c) -#define DEV_BANK_1_PARAM ORION_DEV_BUS_REG(0x460) -#define DEV_BANK_2_PARAM ORION_DEV_BUS_REG(0x464) -#define DEV_BANK_BOOT_PARAM ORION_DEV_BUS_REG(0x46c) -#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0) -#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0) -#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4) -#define GPIO_MAX 32 - -/*************************************************************************** - * Orion CPU Bridge Registers - **************************************************************************/ -#define CPU_CONF ORION_BRIDGE_REG(0x100) -#define CPU_CTRL ORION_BRIDGE_REG(0x104) -#define CPU_RESET_MASK ORION_BRIDGE_REG(0x108) -#define CPU_SOFT_RESET ORION_BRIDGE_REG(0x10c) -#define POWER_MNG_CTRL_REG ORION_BRIDGE_REG(0x11C) -#define BRIDGE_CAUSE ORION_BRIDGE_REG(0x110) -#define BRIDGE_MASK ORION_BRIDGE_REG(0x114) -#define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200) -#define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204) -#define TIMER_CTRL ORION_BRIDGE_REG(0x300) -#define TIMER_VAL(x) ORION_BRIDGE_REG(0x314 + ((x) * 8)) -#define TIMER_VAL_RELOAD(x) ORION_BRIDGE_REG(0x310 + ((x) * 8)) - -#ifndef __ASSEMBLY__ - -/******************************************************************************* - * Helpers to access Orion registers - ******************************************************************************/ -#include <asm/types.h> -#include <asm/io.h> - -#define orion_read(r) __raw_readl(r) -#define orion_write(r, val) __raw_writel(val, r) - -/* - * These are not preempt safe. Locks, if needed, must be taken care by caller. - */ -#define orion_setbits(r, mask) orion_write((r), orion_read(r) | (mask)) -#define orion_clrbits(r, mask) orion_write((r), orion_read(r) & ~(mask)) - -#endif /* __ASSEMBLY__ */ - -#endif /* __ASM_ARCH_ORION_H__ */ diff --git a/include/asm-arm/arch-orion/timex.h b/include/asm-arm/arch-orion/timex.h deleted file mode 100644 index 26c2c91eecf0..000000000000 --- a/include/asm-arm/arch-orion/timex.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * include/asm-arm/arch-orion/timex.h - * - * Tzachi Perelstein <tzachi@marvell.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#define ORION_TCLK 166666667 -#define CLOCK_TICK_RATE ORION_TCLK diff --git a/include/asm-arm/arch-orion/debug-macro.S b/include/asm-arm/arch-orion5x/debug-macro.S index 2746220f5d85..4f98f3ba2929 100644 --- a/include/asm-arm/arch-orion/debug-macro.S +++ b/include/asm-arm/arch-orion5x/debug-macro.S @@ -1,5 +1,5 @@ /* - * linux/include/asm-arm/arch-orion/debug-macro.S + * include/asm-arm/arch-orion5x/debug-macro.S * * Debugging macro include header * @@ -8,13 +8,13 @@ * published by the Free Software Foundation. */ -#include <asm/arch/orion.h> +#include <asm/arch/orion5x.h> .macro addruart,rx mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? - ldreq \rx, =ORION_REGS_PHYS_BASE - ldrne \rx, =ORION_REGS_VIRT_BASE + ldreq \rx, =ORION5X_REGS_PHYS_BASE + ldrne \rx, =ORION5X_REGS_VIRT_BASE orr \rx, \rx, #0x00012000 .endm diff --git a/include/asm-arm/arch-orion/dma.h b/include/asm-arm/arch-orion5x/dma.h index 40a8c178f10d..40a8c178f10d 100644 --- a/include/asm-arm/arch-orion/dma.h +++ b/include/asm-arm/arch-orion5x/dma.h diff --git a/include/asm-arm/arch-orion/entry-macro.S b/include/asm-arm/arch-orion5x/entry-macro.S index cda096b2acfd..d8ef54c0ee9a 100644 --- a/include/asm-arm/arch-orion/entry-macro.S +++ b/include/asm-arm/arch-orion5x/entry-macro.S @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/entry-macro.S + * include/asm-arm/arch-orion5x/entry-macro.S * * Low-level IRQ helper macros for Orion platforms * @@ -8,7 +8,7 @@ * warranty of any kind, whether express or implied. */ -#include <asm/arch/orion.h> +#include <asm/arch/orion5x.h> .macro disable_fiq .endm diff --git a/include/asm-arm/arch-orion/gpio.h b/include/asm-arm/arch-orion5x/gpio.h index d66284f9a14c..c85e498388b6 100644 --- a/include/asm-arm/arch-orion/gpio.h +++ b/include/asm-arm/arch-orion5x/gpio.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/gpio.h + * include/asm-arm/arch-orion5x/gpio.h * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any @@ -12,17 +12,17 @@ extern int gpio_direction_input(unsigned pin); extern int gpio_direction_output(unsigned pin, int value); extern int gpio_get_value(unsigned pin); extern void gpio_set_value(unsigned pin, int value); -extern void orion_gpio_set_blink(unsigned pin, int blink); +extern void orion5x_gpio_set_blink(unsigned pin, int blink); extern void gpio_display(void); /* debug */ static inline int gpio_to_irq(int pin) { - return pin + IRQ_ORION_GPIO_START; + return pin + IRQ_ORION5X_GPIO_START; } static inline int irq_to_gpio(int irq) { - return irq - IRQ_ORION_GPIO_START; + return irq - IRQ_ORION5X_GPIO_START; } #include <asm-generic/gpio.h> /* cansleep wrappers */ diff --git a/include/asm-arm/arch-orion/hardware.h b/include/asm-arm/arch-orion5x/hardware.h index 65da374de735..5d2d8e0b5630 100644 --- a/include/asm-arm/arch-orion/hardware.h +++ b/include/asm-arm/arch-orion5x/hardware.h @@ -1,21 +1,21 @@ /* - * include/asm-arm/arch-orion/hardware.h + * include/asm-arm/arch-orion5x/hardware.h * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#ifndef __ASM_ARCH_HARDWARE_H__ -#define __ASM_ARCH_HARDWARE_H__ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H -#include "orion.h" +#include "orion5x.h" #define pcibios_assign_all_busses() 1 #define PCIBIOS_MIN_IO 0x00001000 #define PCIBIOS_MIN_MEM 0x01000000 -#define PCIMEM_BASE ORION_PCIE_MEM_PHYS_BASE +#define PCIMEM_BASE ORION5X_PCIE_MEM_PHYS_BASE #endif diff --git a/include/asm-arm/arch-orion5x/io.h b/include/asm-arm/arch-orion5x/io.h new file mode 100644 index 000000000000..5148ab7ad1f8 --- /dev/null +++ b/include/asm-arm/arch-orion5x/io.h @@ -0,0 +1,68 @@ +/* + * include/asm-arm/arch-orion5x/io.h + * + * Tzachi Perelstein <tzachi@marvell.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#include "orion5x.h" + +#define IO_SPACE_LIMIT 0xffffffff +#define IO_SPACE_REMAP ORION5X_PCI_SYS_IO_BASE + +static inline void __iomem * +__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype) +{ + void __iomem *retval; + + if (mtype == MT_DEVICE && size && paddr >= ORION5X_REGS_PHYS_BASE && + paddr + size <= ORION5X_REGS_PHYS_BASE + ORION5X_REGS_SIZE) { + retval = (void __iomem *)ORION5X_REGS_VIRT_BASE + + (paddr - ORION5X_REGS_PHYS_BASE); + } else { + retval = __arm_ioremap(paddr, size, mtype); + } + + return retval; +} + +static inline void +__arch_iounmap(void __iomem *addr) +{ + if (addr < (void __iomem *)ORION5X_REGS_VIRT_BASE || + addr >= (void __iomem *)(ORION5X_REGS_VIRT_BASE + ORION5X_REGS_SIZE)) + __iounmap(addr); +} + +static inline void __iomem *__io(unsigned long addr) +{ + return (void __iomem *)addr; +} + +#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m) +#define __arch_iounmap(a) __arch_iounmap(a) +#define __io(a) __io(a) +#define __mem_pci(a) (a) + + +/***************************************************************************** + * Helpers to access Orion registers + ****************************************************************************/ +#define orion5x_read(r) __raw_readl(r) +#define orion5x_write(r, val) __raw_writel(val, r) + +/* + * These are not preempt-safe. Locks, if needed, must be taken + * care of by the caller. + */ +#define orion5x_setbits(r, mask) orion5x_write((r), orion5x_read(r) | (mask)) +#define orion5x_clrbits(r, mask) orion5x_write((r), orion5x_read(r) & ~(mask)) + + +#endif diff --git a/include/asm-arm/arch-orion5x/irqs.h b/include/asm-arm/arch-orion5x/irqs.h new file mode 100644 index 000000000000..abdd61a4833a --- /dev/null +++ b/include/asm-arm/arch-orion5x/irqs.h @@ -0,0 +1,62 @@ +/* + * include/asm-arm/arch-orion5x/irqs.h + * + * IRQ definitions for Orion SoC + * + * Maintainer: Tzachi Perelstein <tzachi@marvell.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +#include "orion5x.h" /* need GPIO_MAX */ + +/* + * Orion Main Interrupt Controller + */ +#define IRQ_ORION5X_BRIDGE 0 +#define IRQ_ORION5X_DOORBELL_H2C 1 +#define IRQ_ORION5X_DOORBELL_C2H 2 +#define IRQ_ORION5X_UART0 3 +#define IRQ_ORION5X_UART1 4 +#define IRQ_ORION5X_I2C 5 +#define IRQ_ORION5X_GPIO_0_7 6 +#define IRQ_ORION5X_GPIO_8_15 7 +#define IRQ_ORION5X_GPIO_16_23 8 +#define IRQ_ORION5X_GPIO_24_31 9 +#define IRQ_ORION5X_PCIE0_ERR 10 +#define IRQ_ORION5X_PCIE0_INT 11 +#define IRQ_ORION5X_USB1_CTRL 12 +#define IRQ_ORION5X_DEV_BUS_ERR 14 +#define IRQ_ORION5X_PCI_ERR 15 +#define IRQ_ORION5X_USB_BR_ERR 16 +#define IRQ_ORION5X_USB0_CTRL 17 +#define IRQ_ORION5X_ETH_RX 18 +#define IRQ_ORION5X_ETH_TX 19 +#define IRQ_ORION5X_ETH_MISC 20 +#define IRQ_ORION5X_ETH_SUM 21 +#define IRQ_ORION5X_ETH_ERR 22 +#define IRQ_ORION5X_IDMA_ERR 23 +#define IRQ_ORION5X_IDMA_0 24 +#define IRQ_ORION5X_IDMA_1 25 +#define IRQ_ORION5X_IDMA_2 26 +#define IRQ_ORION5X_IDMA_3 27 +#define IRQ_ORION5X_CESA 28 +#define IRQ_ORION5X_SATA 29 +#define IRQ_ORION5X_XOR0 30 +#define IRQ_ORION5X_XOR1 31 + +/* + * Orion General Purpose Pins + */ +#define IRQ_ORION5X_GPIO_START 32 +#define NR_GPIO_IRQS GPIO_MAX + +#define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) + + +#endif diff --git a/include/asm-arm/arch-orion/memory.h b/include/asm-arm/arch-orion5x/memory.h index d954dba87ced..80053a7afc7a 100644 --- a/include/asm-arm/arch-orion/memory.h +++ b/include/asm-arm/arch-orion5x/memory.h @@ -1,15 +1,16 @@ /* - * include/asm-arm/arch-orion/memory.h + * include/asm-arm/arch-orion5x/memory.h * * Marvell Orion memory definitions */ -#ifndef __ASM_ARCH_MMU_H -#define __ASM_ARCH_MMU_H +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H #define PHYS_OFFSET UL(0x00000000) #define __virt_to_bus(x) __virt_to_phys(x) #define __bus_to_virt(x) __phys_to_virt(x) + #endif diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h new file mode 100644 index 000000000000..206ddd71e193 --- /dev/null +++ b/include/asm-arm/arch-orion5x/orion5x.h @@ -0,0 +1,159 @@ +/* + * include/asm-arm/arch-orion5x/orion5x.h + * + * Generic definitions of Orion SoC flavors: + * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2. + * + * Maintainer: Tzachi Perelstein <tzachi@marvell.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_ORION5X_H +#define __ASM_ARCH_ORION5X_H + +/***************************************************************************** + * Orion Address Maps + * + * phys + * e0000000 PCIe MEM space + * e8000000 PCI MEM space + * f0000000 PCIe WA space (Orion-1/Orion-NAS only) + * f1000000 on-chip peripheral registers + * f2000000 PCIe I/O space + * f2100000 PCI I/O space + * f4000000 device bus mappings (boot) + * fa000000 device bus mappings (cs0) + * fa800000 device bus mappings (cs2) + * fc000000 device bus mappings (cs0/cs1) + * + * virt phys size + * fdd00000 f1000000 1M on-chip peripheral registers + * fde00000 f2000000 1M PCIe I/O space + * fdf00000 f2100000 1M PCI I/O space + * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) + ****************************************************************************/ +#define ORION5X_REGS_PHYS_BASE 0xf1000000 +#define ORION5X_REGS_VIRT_BASE 0xfdd00000 +#define ORION5X_REGS_SIZE SZ_1M + +#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 +#define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000 +#define ORION5X_PCIE_IO_BUS_BASE 0x00000000 +#define ORION5X_PCIE_IO_SIZE SZ_1M + +#define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 +#define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000 +#define ORION5X_PCI_IO_BUS_BASE 0x00100000 +#define ORION5X_PCI_IO_SIZE SZ_1M + +/* Relevant only for Orion-1/Orion-NAS */ +#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 +#define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000 +#define ORION5X_PCIE_WA_SIZE SZ_16M + +#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 +#define ORION5X_PCIE_MEM_SIZE SZ_128M + +#define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000 +#define ORION5X_PCI_MEM_SIZE SZ_128M + +/******************************************************************************* + * Supported Devices & Revisions + ******************************************************************************/ +/* Orion-1 (88F5181) */ +#define MV88F5181_DEV_ID 0x5181 +#define MV88F5181_REV_B1 3 +/* Orion-NAS (88F5182) */ +#define MV88F5182_DEV_ID 0x5182 +#define MV88F5182_REV_A2 2 +/* Orion-2 (88F5281) */ +#define MV88F5281_DEV_ID 0x5281 +#define MV88F5281_REV_D1 5 +#define MV88F5281_REV_D2 6 + +/******************************************************************************* + * Orion Registers Map + ******************************************************************************/ +#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) +#define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x)) + +#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) +#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) +#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) +#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000) +#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000) +#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000) +#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100) +#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100) + +#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000) +#define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x)) +#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300) + +#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000) +#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) + +#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000) +#define ORION5X_PCIE_REG(x) (ORION5X_PCIE_VIRT_BASE | (x)) + +#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000) +#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000) +#define ORION5X_USB0_REG(x) (ORION5X_USB0_VIRT_BASE | (x)) + +#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000) +#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000) +#define ORION5X_ETH_REG(x) (ORION5X_ETH_VIRT_BASE | (x)) + +#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) +#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) +#define ORION5X_SATA_REG(x) (ORION5X_SATA_VIRT_BASE | (x)) + +#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) +#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) +#define ORION5X_USB1_REG(x) (ORION5X_USB1_VIRT_BASE | (x)) + +/******************************************************************************* + * Device Bus Registers + ******************************************************************************/ +#define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000) +#define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004) +#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050) +#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008) +#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010) +#define GPIO_OUT ORION5X_DEV_BUS_REG(0x100) +#define GPIO_IO_CONF ORION5X_DEV_BUS_REG(0x104) +#define GPIO_BLINK_EN ORION5X_DEV_BUS_REG(0x108) +#define GPIO_IN_POL ORION5X_DEV_BUS_REG(0x10c) +#define GPIO_DATA_IN ORION5X_DEV_BUS_REG(0x110) +#define GPIO_EDGE_CAUSE ORION5X_DEV_BUS_REG(0x114) +#define GPIO_EDGE_MASK ORION5X_DEV_BUS_REG(0x118) +#define GPIO_LEVEL_MASK ORION5X_DEV_BUS_REG(0x11c) +#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c) +#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460) +#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464) +#define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c) +#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0) +#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0) +#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4) +#define GPIO_MAX 32 + +/*************************************************************************** + * Orion CPU Bridge Registers + **************************************************************************/ +#define CPU_CONF ORION5X_BRIDGE_REG(0x100) +#define CPU_CTRL ORION5X_BRIDGE_REG(0x104) +#define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108) +#define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c) +#define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C) +#define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110) +#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114) +#define BRIDGE_INT_TIMER0 0x0002 +#define BRIDGE_INT_TIMER1 0x0004 +#define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200) +#define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204) + + +#endif diff --git a/include/asm-arm/arch-orion/system.h b/include/asm-arm/arch-orion5x/system.h index 17704c68f90e..3f1d1e2d38f8 100644 --- a/include/asm-arm/arch-orion/system.h +++ b/include/asm-arm/arch-orion5x/system.h @@ -1,10 +1,10 @@ /* - * include/asm-arm/arch-orion/system.h + * include/asm-arm/arch-orion5x/system.h * * Tzachi Perelstein <tzachi@marvell.com> * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ @@ -12,7 +12,7 @@ #define __ASM_ARCH_SYSTEM_H #include <asm/arch/hardware.h> -#include <asm/arch/orion.h> +#include <asm/arch/orion5x.h> static inline void arch_idle(void) { @@ -24,8 +24,9 @@ static inline void arch_reset(char mode) /* * Enable and issue soft reset */ - orion_setbits(CPU_RESET_MASK, (1 << 2)); - orion_setbits(CPU_SOFT_RESET, 1); + orion5x_setbits(CPU_RESET_MASK, (1 << 2)); + orion5x_setbits(CPU_SOFT_RESET, 1); } + #endif diff --git a/include/asm-arm/arch-orion5x/timex.h b/include/asm-arm/arch-orion5x/timex.h new file mode 100644 index 000000000000..31c568e28cc3 --- /dev/null +++ b/include/asm-arm/arch-orion5x/timex.h @@ -0,0 +1,13 @@ +/* + * include/asm-arm/arch-orion5x/timex.h + * + * Tzachi Perelstein <tzachi@marvell.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define CLOCK_TICK_RATE (100 * HZ) + +#define ORION5X_TCLK 166666667 diff --git a/include/asm-arm/arch-orion/uncompress.h b/include/asm-arm/arch-orion5x/uncompress.h index 59f44039909a..5c13d4fafb4e 100644 --- a/include/asm-arm/arch-orion/uncompress.h +++ b/include/asm-arm/arch-orion5x/uncompress.h @@ -1,14 +1,14 @@ /* - * include/asm-arm/arch-orion/uncompress.h + * include/asm-arm/arch-orion5x/uncompress.h * * Tzachi Perelstein <tzachi@marvell.com> * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#include <asm/arch/orion.h> +#include <asm/arch/orion5x.h> #define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0)) #define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14)) diff --git a/include/asm-arm/arch-orion/vmalloc.h b/include/asm-arm/arch-orion5x/vmalloc.h index 9d580278d2bc..2b3061e90dc1 100644 --- a/include/asm-arm/arch-orion/vmalloc.h +++ b/include/asm-arm/arch-orion5x/vmalloc.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/vmalloc.h + * include/asm-arm/arch-orion5x/vmalloc.h */ #define VMALLOC_END 0xfd800000 diff --git a/include/asm-arm/arch-realview/board-eb.h b/include/asm-arm/arch-realview/board-eb.h index 3e437b7f425a..206f7a752882 100644 --- a/include/asm-arm/arch-realview/board-eb.h +++ b/include/asm-arm/arch-realview/board-eb.h @@ -26,6 +26,26 @@ /* * RealView EB + ARM11MPCore peripheral addresses */ +#define REALVIEW_EB_UART0_BASE 0x10009000 /* UART 0 */ +#define REALVIEW_EB_UART1_BASE 0x1000A000 /* UART 1 */ +#define REALVIEW_EB_UART2_BASE 0x1000B000 /* UART 2 */ +#define REALVIEW_EB_UART3_BASE 0x1000C000 /* UART 3 */ +#define REALVIEW_EB_SSP_BASE 0x1000D000 /* Synchronous Serial Port */ +#define REALVIEW_EB_WATCHDOG_BASE 0x10010000 /* watchdog interface */ +#define REALVIEW_EB_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */ +#define REALVIEW_EB_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */ +#define REALVIEW_EB_GPIO0_BASE 0x10013000 /* GPIO port 0 */ +#define REALVIEW_EB_RTC_BASE 0x10017000 /* Real Time Clock */ +#define REALVIEW_EB_CLCD_BASE 0x10020000 /* CLCD */ +#define REALVIEW_EB_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */ +#define REALVIEW_EB_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */ +#define REALVIEW_EB_SMC_BASE 0x10080000 /* Static memory controller */ + +#define REALVIEW_EB_FLASH_BASE 0x40000000 +#define REALVIEW_EB_FLASH_SIZE SZ_64M +#define REALVIEW_EB_ETH_BASE 0x4E000000 /* Ethernet */ +#define REALVIEW_EB_USB_BASE 0x4F000000 /* USB */ + #ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB #define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */ #define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */ diff --git a/include/asm-arm/arch-realview/board-pb1176.h b/include/asm-arm/arch-realview/board-pb1176.h new file mode 100644 index 000000000000..48ce9c833705 --- /dev/null +++ b/include/asm-arm/arch-realview/board-pb1176.h @@ -0,0 +1,152 @@ +/* + * include/asm-arm/arch-realview/board-pb1176.h + * + * Copyright (C) 2008 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_BOARD_PB1176_H +#define __ASM_ARCH_BOARD_PB1176_H + +#include <asm/arch/platform.h> + +/* + * Peripheral addresses + */ +#define REALVIEW_PB1176_SCTL_BASE 0x10100000 /* System controller */ +#define REALVIEW_PB1176_SMC_BASE 0x10111000 /* SMC */ +#define REALVIEW_PB1176_DMC_BASE 0x10109000 /* DMC configuration */ +#define REALVIEW_PB1176_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */ +#define REALVIEW_PB1176_FLASH_BASE 0x30000000 +#define REALVIEW_PB1176_FLASH_SIZE SZ_64M + +#define REALVIEW_PB1176_TIMER0_1_BASE 0x10104000 /* Timer 0 and 1 */ +#define REALVIEW_PB1176_TIMER2_3_BASE 0x10105000 /* Timer 2 and 3 */ +#define REALVIEW_PB1176_TIMER4_5_BASE 0x10106000 /* Timer 4 and 5 */ +#define REALVIEW_PB1176_WATCHDOG_BASE 0x10107000 /* watchdog interface */ +#define REALVIEW_PB1176_RTC_BASE 0x10108000 /* Real Time Clock */ +#define REALVIEW_PB1176_GPIO0_BASE 0x1010A000 /* GPIO port 0 */ +#define REALVIEW_PB1176_SSP_BASE 0x1010B000 /* Synchronous Serial Port */ +#define REALVIEW_PB1176_UART0_BASE 0x1010C000 /* UART 0 */ +#define REALVIEW_PB1176_UART1_BASE 0x1010D000 /* UART 1 */ +#define REALVIEW_PB1176_UART2_BASE 0x1010E000 /* UART 2 */ +#define REALVIEW_PB1176_UART3_BASE 0x1010F000 /* UART 3 */ +#define REALVIEW_PB1176_CLCD_BASE 0x10112000 /* CLCD */ +#define REALVIEW_PB1176_ETH_BASE 0x3A000000 /* Ethernet */ +#define REALVIEW_PB1176_USB_BASE 0x3B000000 /* USB */ + +/* + * PCI regions + */ +#define REALVIEW_PB1176_PCI_BASE 0x60000000 /* PCI self config */ +#define REALVIEW_PB1176_PCI_CFG_BASE 0x61000000 /* PCI config */ +#define REALVIEW_PB1176_PCI_IO_BASE0 0x62000000 /* PCI IO region */ +#define REALVIEW_PB1176_PCI_MEM_BASE0 0x63000000 /* Memory region 1 */ +#define REALVIEW_PB1176_PCI_MEM_BASE1 0x64000000 /* Memory region 2 */ +#define REALVIEW_PB1176_PCI_MEM_BASE2 0x68000000 /* Memory region 3 */ + +#define REALVIEW_PB1176_PCI_BASE_SIZE 0x01000000 /* 16MB */ +#define REALVIEW_PB1176_PCI_CFG_BASE_SIZE 0x01000000 /* 16MB */ +#define REALVIEW_PB1176_PCI_IO_BASE0_SIZE 0x01000000 /* 16MB */ +#define REALVIEW_PB1176_PCI_MEM_BASE0_SIZE 0x01000000 /* 16MB */ +#define REALVIEW_PB1176_PCI_MEM_BASE1_SIZE 0x04000000 /* 64MB */ +#define REALVIEW_PB1176_PCI_MEM_BASE2_SIZE 0x08000000 /* 128MB */ + +#define REALVIEW_DC1176_GIC_CPU_BASE 0x10120000 /* GIC CPU interface, on devchip */ +#define REALVIEW_DC1176_GIC_DIST_BASE 0x10121000 /* GIC distributor, on devchip */ +#define REALVIEW_PB1176_GIC_CPU_BASE 0x10040000 /* GIC CPU interface, on FPGA */ +#define REALVIEW_PB1176_GIC_DIST_BASE 0x10041000 /* GIC distributor, on FPGA */ +#define REALVIEW_PB1176_L220_BASE 0x10110000 /* L220 registers */ + +/* + * Irqs + */ +#define IRQ_DC1176_GIC_START 32 +#define IRQ_PB1176_GIC_START 64 + +/* + * ARM1176 DevChip interrupt sources (primary GIC) + */ +#define IRQ_DC1176_WATCHDOG (IRQ_DC1176_GIC_START + 0) /* Watchdog timer */ +#define IRQ_DC1176_SOFTINT (IRQ_DC1176_GIC_START + 1) /* Software interrupt */ +#define IRQ_DC1176_COMMRx (IRQ_DC1176_GIC_START + 2) /* Debug Comm Rx interrupt */ +#define IRQ_DC1176_COMMTx (IRQ_DC1176_GIC_START + 3) /* Debug Comm Tx interrupt */ +#define IRQ_DC1176_TIMER0 (IRQ_DC1176_GIC_START + 8) /* Timer 0 */ +#define IRQ_DC1176_TIMER1 (IRQ_DC1176_GIC_START + 9) /* Timer 1 */ +#define IRQ_DC1176_TIMER2 (IRQ_DC1176_GIC_START + 10) /* Timer 2 */ +#define IRQ_DC1176_APC (IRQ_DC1176_GIC_START + 11) +#define IRQ_DC1176_IEC (IRQ_DC1176_GIC_START + 12) +#define IRQ_DC1176_L2CC (IRQ_DC1176_GIC_START + 13) +#define IRQ_DC1176_RTC (IRQ_DC1176_GIC_START + 14) +#define IRQ_DC1176_CLCD (IRQ_DC1176_GIC_START + 15) /* CLCD controller */ +#define IRQ_DC1176_UART0 (IRQ_DC1176_GIC_START + 18) /* UART 0 on development chip */ +#define IRQ_DC1176_UART1 (IRQ_DC1176_GIC_START + 19) /* UART 1 on development chip */ +#define IRQ_DC1176_UART2 (IRQ_DC1176_GIC_START + 20) /* UART 2 on development chip */ +#define IRQ_DC1176_UART3 (IRQ_DC1176_GIC_START + 21) /* UART 3 on development chip */ + +#define IRQ_DC1176_PB_IRQ2 (IRQ_DC1176_GIC_START + 30) /* tile GIC */ +#define IRQ_DC1176_PB_IRQ1 (IRQ_DC1176_GIC_START + 31) /* main GIC */ + +/* + * RealView PB1176 interrupt sources (secondary GIC) + */ +#define IRQ_PB1176_MMCI0A (IRQ_PB1176_GIC_START + 1) /* Multimedia Card 0A */ +#define IRQ_PB1176_MMCI0B (IRQ_PB1176_GIC_START + 2) /* Multimedia Card 0A */ +#define IRQ_PB1176_KMI0 (IRQ_PB1176_GIC_START + 3) /* Keyboard/Mouse port 0 */ +#define IRQ_PB1176_KMI1 (IRQ_PB1176_GIC_START + 4) /* Keyboard/Mouse port 1 */ +#define IRQ_PB1176_SCI (IRQ_PB1176_GIC_START + 5) +#define IRQ_PB1176_UART4 (IRQ_PB1176_GIC_START + 6) /* UART 4 on baseboard */ +#define IRQ_PB1176_CHARLCD (IRQ_PB1176_GIC_START + 7) /* Character LCD */ +#define IRQ_PB1176_GPIO1 (IRQ_PB1176_GIC_START + 8) +#define IRQ_PB1176_GPIO2 (IRQ_PB1176_GIC_START + 9) +#define IRQ_PB1176_ETH (IRQ_PB1176_GIC_START + 10) /* Ethernet controller */ +#define IRQ_PB1176_USB (IRQ_PB1176_GIC_START + 11) /* USB controller */ + +#define IRQ_PB1176_PISMO (IRQ_PB1176_GIC_START + 16) + +#define IRQ_PB1176_AACI (IRQ_PB1176_GIC_START + 19) /* Audio Codec */ + +#define IRQ_PB1176_TIMER0_1 (IRQ_PB1176_GIC_START + 22) +#define IRQ_PB1176_TIMER2_3 (IRQ_PB1176_GIC_START + 23) +#define IRQ_PB1176_DMAC (IRQ_PB1176_GIC_START + 24) /* DMA controller */ +#define IRQ_PB1176_RTC (IRQ_PB1176_GIC_START + 25) /* Real Time Clock */ + +#define IRQ_PB1176_GPIO0 -1 +#define IRQ_PB1176_SSP -1 +#define IRQ_PB1176_SCTL -1 + +#define NR_GIC_PB1176 2 + +/* + * Only define NR_IRQS if less than NR_IRQS_PB1176 + */ +#define NR_IRQS_PB1176 (IRQ_DC1176_GIC_START + 96) + +#if defined(CONFIG_MACH_REALVIEW_PB1176) + +#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB1176) +#undef NR_IRQS +#define NR_IRQS NR_IRQS_PB1176 +#endif + +#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB1176) +#undef MAX_GIC_NR +#define MAX_GIC_NR NR_GIC_PB1176 +#endif + +#endif /* CONFIG_MACH_REALVIEW_PB1176 */ + +#endif /* __ASM_ARCH_BOARD_PB1176_H */ diff --git a/include/asm-arm/arch-realview/board-pb11mp.h b/include/asm-arm/arch-realview/board-pb11mp.h new file mode 100644 index 000000000000..a1294d915fa8 --- /dev/null +++ b/include/asm-arm/arch-realview/board-pb11mp.h @@ -0,0 +1,186 @@ +/* + * include/asm-arm/arch-realview/board-pb11mp.h + * + * Copyright (C) 2008 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_BOARD_PB11MP_H +#define __ASM_ARCH_BOARD_PB11MP_H + +#include <asm/arch/platform.h> + +/* + * Peripheral addresses + */ +#define REALVIEW_PB11MP_UART0_BASE 0x10009000 /* UART 0 */ +#define REALVIEW_PB11MP_UART1_BASE 0x1000A000 /* UART 1 */ +#define REALVIEW_PB11MP_UART2_BASE 0x1000B000 /* UART 2 */ +#define REALVIEW_PB11MP_UART3_BASE 0x1000C000 /* UART 3 */ +#define REALVIEW_PB11MP_SSP_BASE 0x1000D000 /* Synchronous Serial Port */ +#define REALVIEW_PB11MP_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */ +#define REALVIEW_PB11MP_WATCHDOG_BASE 0x10010000 /* watchdog interface */ +#define REALVIEW_PB11MP_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */ +#define REALVIEW_PB11MP_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */ +#define REALVIEW_PB11MP_GPIO0_BASE 0x10013000 /* GPIO port 0 */ +#define REALVIEW_PB11MP_RTC_BASE 0x10017000 /* Real Time Clock */ +#define REALVIEW_PB11MP_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */ +#define REALVIEW_PB11MP_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */ +#define REALVIEW_PB11MP_SCTL_BASE 0x1001A000 /* System Controller */ +#define REALVIEW_PB11MP_CLCD_BASE 0x10020000 /* CLCD */ +#define REALVIEW_PB11MP_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */ +#define REALVIEW_PB11MP_DMC_BASE 0x100E0000 /* DMC configuration */ +#define REALVIEW_PB11MP_SMC_BASE 0x100E1000 /* SMC configuration */ +#define REALVIEW_PB11MP_CAN_BASE 0x100E2000 /* CAN bus */ +#define REALVIEW_PB11MP_CF_BASE 0x18000000 /* Compact flash */ +#define REALVIEW_PB11MP_CF_MEM_BASE 0x18003000 /* SMC for Compact flash */ +#define REALVIEW_PB11MP_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */ +#define REALVIEW_PB11MP_FLASH0_BASE 0x40000000 +#define REALVIEW_PB11MP_FLASH0_SIZE SZ_64M +#define REALVIEW_PB11MP_FLASH1_BASE 0x44000000 +#define REALVIEW_PB11MP_FLASH1_SIZE SZ_64M +#define REALVIEW_PB11MP_ETH_BASE 0x4E000000 /* Ethernet */ +#define REALVIEW_PB11MP_USB_BASE 0x4F000000 /* USB */ +#define REALVIEW_PB11MP_GIC_DIST_BASE 0x1E001000 /* Generic interrupt controller distributor */ +#define REALVIEW_PB11MP_LT_BASE 0xC0000000 /* Logic Tile expansion */ +#define REALVIEW_PB11MP_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */ +#define REALVIEW_PB11MP_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */ + +#define REALVIEW_PB11MP_SYS_PLD_CTRL1 0x74 + +/* + * PB11MPCore PCI regions + */ +#define REALVIEW_PB11MP_PCI_BASE 0x90040000 /* PCI-X Unit base */ +#define REALVIEW_PB11MP_PCI_IO_BASE 0x90050000 /* IO Region on AHB */ +#define REALVIEW_PB11MP_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */ + +#define REALVIEW_PB11MP_PCI_BASE_SIZE 0x10000 /* 16 Kb */ +#define REALVIEW_PB11MP_PCI_IO_SIZE 0x1000 /* 4 Kb */ +#define REALVIEW_PB11MP_PCI_MEM_SIZE 0x20000000 /* 512 MB */ + +/* + * Testchip peripheral and fpga gic regions + */ +#define REALVIEW_TC11MP_SCU_BASE 0x1F000000 /* IRQ, Test chip */ +#define REALVIEW_TC11MP_GIC_CPU_BASE 0x1F000100 /* Test chip interrupt controller CPU interface */ +#define REALVIEW_TC11MP_TWD_BASE 0x1F000700 +#define REALVIEW_TC11MP_TWD_SIZE 0x00000100 +#define REALVIEW_TC11MP_GIC_DIST_BASE 0x1F001000 /* Test chip interrupt controller distributor */ +#define REALVIEW_TC11MP_L220_BASE 0x1F002000 /* L220 registers */ + +/* + * Irqs + */ +#define IRQ_TC11MP_GIC_START 32 +#define IRQ_PB11MP_GIC_START 64 + +/* + * ARM11MPCore test chip interrupt sources (primary GIC on the test chip) + */ +#define IRQ_TC11MP_AACI (IRQ_TC11MP_GIC_START + 0) +#define IRQ_TC11MP_TIMER0_1 (IRQ_TC11MP_GIC_START + 1) +#define IRQ_TC11MP_TIMER2_3 (IRQ_TC11MP_GIC_START + 2) +#define IRQ_TC11MP_USB (IRQ_TC11MP_GIC_START + 3) +#define IRQ_TC11MP_UART0 (IRQ_TC11MP_GIC_START + 4) +#define IRQ_TC11MP_UART1 (IRQ_TC11MP_GIC_START + 5) +#define IRQ_TC11MP_RTC (IRQ_TC11MP_GIC_START + 6) +#define IRQ_TC11MP_KMI0 (IRQ_TC11MP_GIC_START + 7) +#define IRQ_TC11MP_KMI1 (IRQ_TC11MP_GIC_START + 8) +#define IRQ_TC11MP_ETH (IRQ_TC11MP_GIC_START + 9) +#define IRQ_TC11MP_PB_IRQ1 (IRQ_TC11MP_GIC_START + 10) /* main GIC */ +#define IRQ_TC11MP_PB_IRQ2 (IRQ_TC11MP_GIC_START + 11) /* tile GIC */ +#define IRQ_TC11MP_PB_FIQ1 (IRQ_TC11MP_GIC_START + 12) /* main GIC */ +#define IRQ_TC11MP_PB_FIQ2 (IRQ_TC11MP_GIC_START + 13) /* tile GIC */ +#define IRQ_TC11MP_MMCI0A (IRQ_TC11MP_GIC_START + 14) +#define IRQ_TC11MP_MMCI0B (IRQ_TC11MP_GIC_START + 15) + +#define IRQ_TC11MP_PMU_CPU0 (IRQ_TC11MP_GIC_START + 17) +#define IRQ_TC11MP_PMU_CPU1 (IRQ_TC11MP_GIC_START + 18) +#define IRQ_TC11MP_PMU_CPU2 (IRQ_TC11MP_GIC_START + 19) +#define IRQ_TC11MP_PMU_CPU3 (IRQ_TC11MP_GIC_START + 20) +#define IRQ_TC11MP_PMU_SCU0 (IRQ_TC11MP_GIC_START + 21) +#define IRQ_TC11MP_PMU_SCU1 (IRQ_TC11MP_GIC_START + 22) +#define IRQ_TC11MP_PMU_SCU2 (IRQ_TC11MP_GIC_START + 23) +#define IRQ_TC11MP_PMU_SCU3 (IRQ_TC11MP_GIC_START + 24) +#define IRQ_TC11MP_PMU_SCU4 (IRQ_TC11MP_GIC_START + 25) +#define IRQ_TC11MP_PMU_SCU5 (IRQ_TC11MP_GIC_START + 26) +#define IRQ_TC11MP_PMU_SCU6 (IRQ_TC11MP_GIC_START + 27) +#define IRQ_TC11MP_PMU_SCU7 (IRQ_TC11MP_GIC_START + 28) + +#define IRQ_TC11MP_L220_EVENT (IRQ_TC11MP_GIC_START + 29) +#define IRQ_TC11MP_L220_SLAVE (IRQ_TC11MP_GIC_START + 30) +#define IRQ_TC11MP_L220_DECODE (IRQ_TC11MP_GIC_START + 31) + +/* + * RealView PB11MPCore GIC interrupt sources (secondary GIC on the board) + */ +#define IRQ_PB11MP_WATCHDOG (IRQ_PB11MP_GIC_START + 0) /* Watchdog timer */ +#define IRQ_PB11MP_SOFT (IRQ_PB11MP_GIC_START + 1) /* Software interrupt */ +#define IRQ_PB11MP_COMMRx (IRQ_PB11MP_GIC_START + 2) /* Debug Comm Rx interrupt */ +#define IRQ_PB11MP_COMMTx (IRQ_PB11MP_GIC_START + 3) /* Debug Comm Tx interrupt */ +#define IRQ_PB11MP_GPIO0 (IRQ_PB11MP_GIC_START + 6) /* GPIO 0 */ +#define IRQ_PB11MP_GPIO1 (IRQ_PB11MP_GIC_START + 7) /* GPIO 1 */ +#define IRQ_PB11MP_GPIO2 (IRQ_PB11MP_GIC_START + 8) /* GPIO 2 */ + /* 9 reserved */ +#define IRQ_PB11MP_RTC_GIC1 (IRQ_PB11MP_GIC_START + 10) /* Real Time Clock */ +#define IRQ_PB11MP_SSP (IRQ_PB11MP_GIC_START + 11) /* Synchronous Serial Port */ +#define IRQ_PB11MP_UART0_GIC1 (IRQ_PB11MP_GIC_START + 12) /* UART 0 on development chip */ +#define IRQ_PB11MP_UART1_GIC1 (IRQ_PB11MP_GIC_START + 13) /* UART 1 on development chip */ +#define IRQ_PB11MP_UART2 (IRQ_PB11MP_GIC_START + 14) /* UART 2 on development chip */ +#define IRQ_PB11MP_UART3 (IRQ_PB11MP_GIC_START + 15) /* UART 3 on development chip */ +#define IRQ_PB11MP_SCI (IRQ_PB11MP_GIC_START + 16) /* Smart Card Interface */ +#define IRQ_PB11MP_MMCI0A_GIC1 (IRQ_PB11MP_GIC_START + 17) /* Multimedia Card 0A */ +#define IRQ_PB11MP_MMCI0B_GIC1 (IRQ_PB11MP_GIC_START + 18) /* Multimedia Card 0B */ +#define IRQ_PB11MP_AACI_GIC1 (IRQ_PB11MP_GIC_START + 19) /* Audio Codec */ +#define IRQ_PB11MP_KMI0_GIC1 (IRQ_PB11MP_GIC_START + 20) /* Keyboard/Mouse port 0 */ +#define IRQ_PB11MP_KMI1_GIC1 (IRQ_PB11MP_GIC_START + 21) /* Keyboard/Mouse port 1 */ +#define IRQ_PB11MP_CHARLCD (IRQ_PB11MP_GIC_START + 22) /* Character LCD */ +#define IRQ_PB11MP_CLCD (IRQ_PB11MP_GIC_START + 23) /* CLCD controller */ +#define IRQ_PB11MP_DMAC (IRQ_PB11MP_GIC_START + 24) /* DMA controller */ +#define IRQ_PB11MP_PWRFAIL (IRQ_PB11MP_GIC_START + 25) /* Power failure */ +#define IRQ_PB11MP_PISMO (IRQ_PB11MP_GIC_START + 26) /* PISMO interface */ +#define IRQ_PB11MP_DoC (IRQ_PB11MP_GIC_START + 27) /* Disk on Chip memory controller */ +#define IRQ_PB11MP_ETH_GIC1 (IRQ_PB11MP_GIC_START + 28) /* Ethernet controller */ +#define IRQ_PB11MP_USB_GIC1 (IRQ_PB11MP_GIC_START + 29) /* USB controller */ +#define IRQ_PB11MP_TSPEN (IRQ_PB11MP_GIC_START + 30) /* Touchscreen pen */ +#define IRQ_PB11MP_TSKPAD (IRQ_PB11MP_GIC_START + 31) /* Touchscreen keypad */ + +#define IRQ_PB11MP_SMC -1 +#define IRQ_PB11MP_SCTL -1 + +#define NR_GIC_PB11MP 2 + +/* + * Only define NR_IRQS if less than NR_IRQS_PB11MP + */ +#define NR_IRQS_PB11MP (IRQ_TC11MP_GIC_START + 96) + +#if defined(CONFIG_MACH_REALVIEW_PB11MP) + +#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB11MP) +#undef NR_IRQS +#define NR_IRQS NR_IRQS_PB11MP +#endif + +#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB11MP) +#undef MAX_GIC_NR +#define MAX_GIC_NR NR_GIC_PB11MP +#endif + +#endif /* CONFIG_MACH_REALVIEW_PB11MP */ + +#endif /* __ASM_ARCH_BOARD_PB11MP_H */ diff --git a/include/asm-arm/arch-realview/debug-macro.S b/include/asm-arm/arch-realview/debug-macro.S index f17efc65518a..c8c860c3c26e 100644 --- a/include/asm-arm/arch-realview/debug-macro.S +++ b/include/asm-arm/arch-realview/debug-macro.S @@ -15,7 +15,7 @@ mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? moveq \rx, #0x10000000 - movne \rx, #0xf1000000 @ virtual base + movne \rx, #0xf0000000 @ virtual base orr \rx, \rx, #0x00009000 .endm diff --git a/include/asm-arm/arch-realview/hardware.h b/include/asm-arm/arch-realview/hardware.h index bad8d7ce9bfe..1ee8313ceb6a 100644 --- a/include/asm-arm/arch-realview/hardware.h +++ b/include/asm-arm/arch-realview/hardware.h @@ -25,7 +25,7 @@ #include <asm/sizes.h> /* macro to get at IO space when running virtually */ -#define IO_ADDRESS(x) ((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000) +#define IO_ADDRESS(x) (((x) & 0x0fffffff) + 0xf0000000) #define __io_address(n) __io(IO_ADDRESS(n)) #endif diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h index ad0c911002fc..ccbac59235c6 100644 --- a/include/asm-arm/arch-realview/irqs.h +++ b/include/asm-arm/arch-realview/irqs.h @@ -23,6 +23,8 @@ #define __ASM_ARCH_IRQS_H #include <asm/arch/board-eb.h> +#include <asm/arch/board-pb11mp.h> +#include <asm/arch/board-pb1176.h> #define IRQ_LOCALTIMER 29 #define IRQ_LOCALWDOG 30 diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h index 4fd351b5e4a2..424c0aaf46a0 100644 --- a/include/asm-arm/arch-realview/platform.h +++ b/include/asm-arm/arch-realview/platform.h @@ -32,9 +32,6 @@ #define REALVIEW_SSRAM_BASE /* REALVIEW_SSMC_BASE ? */ #define REALVIEW_SSRAM_SIZE SZ_2M -#define REALVIEW_FLASH_BASE 0x40000000 -#define REALVIEW_FLASH_SIZE SZ_64M - /* * SDRAM */ @@ -175,42 +172,20 @@ #define REALVIEW_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */ /* - * REALVIEW peripheral addresses + * RealView common peripheral addresses */ #define REALVIEW_SCTL_BASE 0x10001000 /* System controller */ #define REALVIEW_I2C_BASE 0x10002000 /* I2C control */ - /* Reserved 0x10003000 */ #define REALVIEW_AACI_BASE 0x10004000 /* Audio */ #define REALVIEW_MMCI0_BASE 0x10005000 /* MMC interface */ #define REALVIEW_KMI0_BASE 0x10006000 /* KMI interface */ #define REALVIEW_KMI1_BASE 0x10007000 /* KMI 2nd interface */ #define REALVIEW_CHAR_LCD_BASE 0x10008000 /* Character LCD */ -#define REALVIEW_UART0_BASE 0x10009000 /* UART 0 */ -#define REALVIEW_UART1_BASE 0x1000A000 /* UART 1 */ -#define REALVIEW_UART2_BASE 0x1000B000 /* UART 2 */ -#define REALVIEW_UART3_BASE 0x1000C000 /* UART 3 */ -#define REALVIEW_SSP_BASE 0x1000D000 /* Synchronous Serial Port */ #define REALVIEW_SCI_BASE 0x1000E000 /* Smart card controller */ - /* Reserved 0x1000F000 */ -#define REALVIEW_WATCHDOG_BASE 0x10010000 /* watchdog interface */ -#define REALVIEW_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */ -#define REALVIEW_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */ -#define REALVIEW_GPIO0_BASE 0x10013000 /* GPIO port 0 */ #define REALVIEW_GPIO1_BASE 0x10014000 /* GPIO port 1 */ #define REALVIEW_GPIO2_BASE 0x10015000 /* GPIO port 2 */ - /* Reserved 0x10016000 */ -#define REALVIEW_RTC_BASE 0x10017000 /* Real Time Clock */ #define REALVIEW_DMC_BASE 0x10018000 /* DMC configuration */ -#define REALVIEW_PCI_CORE_BASE 0x10019000 /* PCI configuration */ - /* Reserved 0x1001A000 - 0x1001FFFF */ -#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */ #define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */ -#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */ -#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */ -#define REALVIEW_SMC_BASE 0x10080000 /* SMC */ - /* Reserved 0x10090000 - 0x100EFFFF */ - -#define REALVIEW_ETH_BASE 0x4E000000 /* Ethernet */ /* PCI space */ #define REALVIEW_PCI_BASE 0x41000000 /* PCI Interface */ diff --git a/include/asm-arm/arch-realview/scu.h b/include/asm-arm/arch-realview/scu.h index 08b3db883c36..d55802d645af 100644 --- a/include/asm-arm/arch-realview/scu.h +++ b/include/asm-arm/arch-realview/scu.h @@ -1,8 +1,13 @@ #ifndef __ASMARM_ARCH_SCU_H #define __ASMARM_ARCH_SCU_H -#include <asm/arch/board-eb.h> - -#define SCU_BASE REALVIEW_EB11MP_SCU_BASE +/* + * SCU registers + */ +#define SCU_CTRL 0x00 +#define SCU_CONFIG 0x04 +#define SCU_CPU_STATUS 0x08 +#define SCU_INVALIDATE 0x0c +#define SCU_FPGA_REVISION 0x10 #endif diff --git a/include/asm-arm/arch-realview/uncompress.h b/include/asm-arm/arch-realview/uncompress.h index 3d5c2db07a26..4c905d7a13a1 100644 --- a/include/asm-arm/arch-realview/uncompress.h +++ b/include/asm-arm/arch-realview/uncompress.h @@ -18,28 +18,50 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <asm/hardware.h> +#include <asm/mach-types.h> -#include <asm/arch/platform.h> +#include <asm/arch/board-eb.h> +#include <asm/arch/board-pb11mp.h> +#include <asm/arch/board-pb1176.h> -#define AMBA_UART_DR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00)) -#define AMBA_UART_LCRH (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c)) -#define AMBA_UART_CR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30)) -#define AMBA_UART_FR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x18)) +#define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00)) +#define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c)) +#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30)) +#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18)) + +/* + * Return the UART base address + */ +static inline unsigned long get_uart_base(void) +{ + if (machine_is_realview_eb()) + return REALVIEW_EB_UART0_BASE; + else if (machine_is_realview_pb11mp()) + return REALVIEW_PB11MP_UART0_BASE; + else if (machine_is_realview_pb1176()) + return REALVIEW_PB1176_UART0_BASE; + else + return 0; +} /* * This does not append a newline */ static inline void putc(int c) { - while (AMBA_UART_FR & (1 << 5)) + unsigned long base = get_uart_base(); + + while (AMBA_UART_FR(base) & (1 << 5)) barrier(); - AMBA_UART_DR = c; + AMBA_UART_DR(base) = c; } static inline void flush(void) { - while (AMBA_UART_FR & (1 << 3)) + unsigned long base = get_uart_base(); + + while (AMBA_UART_FR(base) & (1 << 3)) barrier(); } diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h index dba9df9d8713..ecae9e7f5e45 100644 --- a/include/asm-arm/arch-s3c2410/regs-clock.h +++ b/include/asm-arm/arch-s3c2410/regs-clock.h @@ -137,7 +137,7 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk) #define S3C2412_CLKDIVN_PDIVN (1<<2) #define S3C2412_CLKDIVN_HDIVN_MASK (3<<0) -#define S3C2421_CLKDIVN_ARMDIVN (1<<3) +#define S3C2412_CLKDIVN_ARMDIVN (1<<3) #define S3C2412_CLKDIVN_DVSEN (1<<4) #define S3C2412_CLKDIVN_HALFHCLK (1<<5) #define S3C2412_CLKDIVN_USB48DIV (1<<6) diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h index 0ad75d716ded..497dd06e2c99 100644 --- a/include/asm-arm/arch-s3c2410/regs-gpio.h +++ b/include/asm-arm/arch-s3c2410/regs-gpio.h @@ -529,11 +529,13 @@ #define S3C2410_GPD14_INP (0x00 << 28) #define S3C2410_GPD14_OUTP (0x01 << 28) #define S3C2410_GPD14_VD22 (0x02 << 28) +#define S3C2410_GPD14_nSS1 (0x03 << 28) #define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15) #define S3C2410_GPD15_INP (0x00 << 30) #define S3C2410_GPD15_OUTP (0x01 << 30) #define S3C2410_GPD15_VD23 (0x02 << 30) +#define S3C2410_GPD15_nSS0 (0x03 << 30) #define S3C2410_GPD_PUPDIS(x) (1<<(x)) @@ -801,12 +803,14 @@ #define S3C2410_GPG2_INP (0x00 << 4) #define S3C2410_GPG2_OUTP (0x01 << 4) #define S3C2410_GPG2_EINT10 (0x02 << 4) +#define S3C2410_GPG2_nSS0 (0x03 << 4) #define S3C2400_GPG2_CDCLK (0x02 << 4) #define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3) #define S3C2410_GPG3_INP (0x00 << 6) #define S3C2410_GPG3_OUTP (0x01 << 6) #define S3C2410_GPG3_EINT11 (0x02 << 6) +#define S3C2410_GPG3_nSS1 (0x03 << 6) #define S3C2400_GPG3_I2SSDO (0x02 << 6) #define S3C2400_GPG3_I2SSDI (0x03 << 6) diff --git a/include/asm-arm/arch-s3c2410/regs-s3c2412-mem.h b/include/asm-arm/arch-s3c2410/regs-s3c2412-mem.h new file mode 100644 index 000000000000..c8c793e78936 --- /dev/null +++ b/include/asm-arm/arch-s3c2410/regs-s3c2412-mem.h @@ -0,0 +1,29 @@ +/* linux/include/asm-arm/arch-s3c2410/regs-s3c2412-mem.h + * + * Copyright (c) 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C2412 memory register definitions +*/ + +#ifndef __ASM_ARM_REGS_S3C2412_MEM +#define __ASM_ARM_REGS_S3C2412_MEM + +#ifndef S3C2412_MEMREG +#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) +#endif + +#define S3C2412_BANKCFG S3C2412_MEMREG(0x00) +#define S3C2412_BANKCON1 S3C2412_MEMREG(0x04) +#define S3C2412_BANKCON2 S3C2412_MEMREG(0x08) +#define S3C2412_BANKCON3 S3C2412_MEMREG(0x0C) + +#define S3C2412_REFRESH S3C2412_MEMREG(0x10) +#define S3C2412_TIMEOUT S3C2412_MEMREG(0x14) + +#endif /* __ASM_ARM_REGS_S3C2412_MEM */ diff --git a/include/asm-arm/arch-s3c2410/system-reset.h b/include/asm-arm/arch-s3c2410/system-reset.h new file mode 100644 index 000000000000..1615bce0c026 --- /dev/null +++ b/include/asm-arm/arch-s3c2410/system-reset.h @@ -0,0 +1,64 @@ +/* linux/include/asm-arm/arch-s3c2410/system-reset.h + * + * Copyright (c) 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * S3C2410 - System define for arch_reset() function + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <asm/hardware.h> +#include <asm/io.h> + +#include <asm/plat-s3c/regs-watchdog.h> +#include <asm/arch/regs-clock.h> + +#include <linux/clk.h> +#include <linux/err.h> + +extern void (*s3c24xx_reset_hook)(void); + +static void +arch_reset(char mode) +{ + struct clk *wdtclk; + + if (mode == 's') { + cpu_reset(0); + } + + if (s3c24xx_reset_hook) + s3c24xx_reset_hook(); + + printk("arch_reset: attempting watchdog reset\n"); + + __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ + + wdtclk = clk_get(NULL, "watchdog"); + if (!IS_ERR(wdtclk)) { + clk_enable(wdtclk); + } else + printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__); + + /* put initial values into count and data */ + __raw_writel(0x80, S3C2410_WTCNT); + __raw_writel(0x80, S3C2410_WTDAT); + + /* set the watchdog to go and reset... */ + __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN | + S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON); + + /* wait for reset to assert... */ + mdelay(500); + + printk(KERN_ERR "Watchdog reset failed to assert reset\n"); + + /* delay to allow the serial port to show the message */ + mdelay(50); + + /* we'll take a jump through zero as a poor second */ + cpu_reset(0); +} diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h index 14de4e596f87..ad258085e53b 100644 --- a/include/asm-arm/arch-s3c2410/system.h +++ b/include/asm-arm/arch-s3c2410/system.h @@ -17,12 +17,8 @@ #include <asm/arch/idle.h> #include <asm/arch/reset.h> -#include <asm/plat-s3c/regs-watchdog.h> #include <asm/arch/regs-clock.h> -#include <linux/clk.h> -#include <linux/err.h> - void (*s3c24xx_idle)(void); void (*s3c24xx_reset_hook)(void); @@ -59,44 +55,4 @@ static void arch_idle(void) s3c24xx_default_idle(); } -static void -arch_reset(char mode) -{ - struct clk *wdtclk; - - if (mode == 's') { - cpu_reset(0); - } - - if (s3c24xx_reset_hook) - s3c24xx_reset_hook(); - - printk("arch_reset: attempting watchdog reset\n"); - - __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ - - wdtclk = clk_get(NULL, "watchdog"); - if (!IS_ERR(wdtclk)) { - clk_enable(wdtclk); - } else - printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__); - - /* put initial values into count and data */ - __raw_writel(0x80, S3C2410_WTCNT); - __raw_writel(0x80, S3C2410_WTDAT); - - /* set the watchdog to go and reset... */ - __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN | - S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON); - - /* wait for reset to assert... */ - mdelay(500); - - printk(KERN_ERR "Watchdog reset failed to assert reset\n"); - - /* delay to allow the serial port to show the message */ - mdelay(50); - - /* we'll take a jump through zero as a poor second */ - cpu_reset(0); -} +#include <asm/arch/system-reset.h> diff --git a/include/asm-arm/arch-sa1100/gpio.h b/include/asm-arm/arch-sa1100/gpio.h index e7a9d26e22a8..93d3395b102d 100644 --- a/include/asm-arm/arch-sa1100/gpio.h +++ b/include/asm-arm/arch-sa1100/gpio.h @@ -26,35 +26,28 @@ #include <asm/hardware.h> #include <asm/irq.h> - -static inline int gpio_request(unsigned gpio, const char *label) -{ - return 0; -} - -static inline void gpio_free(unsigned gpio) -{ - return; -} - -extern int gpio_direction_input(unsigned gpio); -extern int gpio_direction_output(unsigned gpio, int value); - +#include <asm-generic/gpio.h> static inline int gpio_get_value(unsigned gpio) { - return GPLR & GPIO_GPIO(gpio); + if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX)) + return GPLR & GPIO_GPIO(gpio); + else + return __gpio_get_value(gpio); } static inline void gpio_set_value(unsigned gpio, int value) { - if (value) - GPSR = GPIO_GPIO(gpio); + if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX)) + if (value) + GPSR = GPIO_GPIO(gpio); + else + GPCR = GPIO_GPIO(gpio); else - GPCR = GPIO_GPIO(gpio); + __gpio_set_value(gpio, value); } -#include <asm-generic/gpio.h> /* cansleep wrappers */ +#define gpio_cansleep __gpio_cansleep static inline unsigned gpio_to_irq(unsigned gpio) { diff --git a/include/asm-arm/cpu-multi32.h b/include/asm-arm/cpu-multi32.h index 715e18a4add1..3479de9266e5 100644 --- a/include/asm-arm/cpu-multi32.h +++ b/include/asm-arm/cpu-multi32.h @@ -21,6 +21,10 @@ extern struct processor { */ void (*_data_abort)(unsigned long pc); /* + * Retrieve prefetch fault address + */ + unsigned long (*_prefetch_abort)(unsigned long lr); + /* * Set up any processor specifics */ void (*_proc_init)(void); diff --git a/include/asm-arm/glue.h b/include/asm-arm/glue.h index 22274ce81375..a97a182ba287 100644 --- a/include/asm-arm/glue.h +++ b/include/asm-arm/glue.h @@ -40,83 +40,110 @@ * v6_early - ARMv6 generic early abort handler * v7_early - ARMv7 generic early abort handler */ -#undef CPU_ABORT_HANDLER -#undef MULTI_ABORT +#undef CPU_DABORT_HANDLER +#undef MULTI_DABORT #if defined(CONFIG_CPU_ARM610) -# ifdef CPU_ABORT_HANDLER -# define MULTI_ABORT 1 +# ifdef CPU_DABORT_HANDLER +# define MULTI_DABORT 1 # else -# define CPU_ABORT_HANDLER cpu_arm6_data_abort +# define CPU_DABORT_HANDLER cpu_arm6_data_abort # endif #endif #if defined(CONFIG_CPU_ARM710) -# ifdef CPU_ABORT_HANDLER -# define MULTI_ABORT 1 +# ifdef CPU_DABORT_HANDLER +# define MULTI_DABORT 1 # else -# define CPU_ABORT_HANDLER cpu_arm7_data_abort +# define CPU_DABORT_HANDLER cpu_arm7_data_abort # endif #endif #ifdef CONFIG_CPU_ABRT_LV4T -# ifdef CPU_ABORT_HANDLER -# define MULTI_ABORT 1 +# ifdef CPU_DABORT_HANDLER +# define MULTI_DABORT 1 # else -# define CPU_ABORT_HANDLER v4t_late_abort +# define CPU_DABORT_HANDLER v4t_late_abort # endif #endif #ifdef CONFIG_CPU_ABRT_EV4 -# ifdef CPU_ABORT_HANDLER -# define MULTI_ABORT 1 +# ifdef CPU_DABORT_HANDLER +# define MULTI_DABORT 1 # else -# define CPU_ABORT_HANDLER v4_early_abort +# define CPU_DABORT_HANDLER v4_early_abort # endif #endif #ifdef CONFIG_CPU_ABRT_EV4T -# ifdef CPU_ABORT_HANDLER -# define MULTI_ABORT 1 +# ifdef CPU_DABORT_HANDLER +# define MULTI_DABORT 1 # else -# define CPU_ABORT_HANDLER v4t_early_abort +# define CPU_DABORT_HANDLER v4t_early_abort # endif #endif #ifdef CONFIG_CPU_ABRT_EV5TJ -# ifdef CPU_ABORT_HANDLER -# define MULTI_ABORT 1 +# ifdef CPU_DABORT_HANDLER +# define MULTI_DABORT 1 # else -# define CPU_ABORT_HANDLER v5tj_early_abort +# define CPU_DABORT_HANDLER v5tj_early_abort # endif #endif #ifdef CONFIG_CPU_ABRT_EV5T -# ifdef CPU_ABORT_HANDLER -# define MULTI_ABORT 1 +# ifdef CPU_DABORT_HANDLER +# define MULTI_DABORT 1 # else -# define CPU_ABORT_HANDLER v5t_early_abort +# define CPU_DABORT_HANDLER v5t_early_abort # endif #endif #ifdef CONFIG_CPU_ABRT_EV6 -# ifdef CPU_ABORT_HANDLER -# define MULTI_ABORT 1 +# ifdef CPU_DABORT_HANDLER +# define MULTI_DABORT 1 # else -# define CPU_ABORT_HANDLER v6_early_abort +# define CPU_DABORT_HANDLER v6_early_abort # endif #endif #ifdef CONFIG_CPU_ABRT_EV7 -# ifdef CPU_ABORT_HANDLER -# define MULTI_ABORT 1 +# ifdef CPU_DABORT_HANDLER +# define MULTI_DABORT 1 # else -# define CPU_ABORT_HANDLER v7_early_abort +# define CPU_DABORT_HANDLER v7_early_abort # endif #endif -#ifndef CPU_ABORT_HANDLER +#ifndef CPU_DABORT_HANDLER #error Unknown data abort handler type #endif +/* + * Prefetch abort handler. If the CPU has an IFAR use that, otherwise + * use the address of the aborted instruction + */ +#undef CPU_PABORT_HANDLER +#undef MULTI_PABORT + +#ifdef CONFIG_CPU_PABRT_IFAR +# ifdef CPU_PABORT_HANDLER +# define MULTI_PABORT 1 +# else +# define CPU_PABORT_HANDLER(reg, insn) mrc p15, 0, reg, cr6, cr0, 2 +# endif +#endif + +#ifdef CONFIG_CPU_PABRT_NOIFAR +# ifdef CPU_PABORT_HANDLER +# define MULTI_PABORT 1 +# else +# define CPU_PABORT_HANDLER(reg, insn) mov reg, insn +# endif +#endif + +#ifndef CPU_PABORT_HANDLER +#error Unknown prefetch abort handler type +#endif + #endif diff --git a/include/asm-arm/hardware/arm_scu.h b/include/asm-arm/hardware/arm_scu.h deleted file mode 100644 index 7d28eb5a1758..000000000000 --- a/include/asm-arm/hardware/arm_scu.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef ASMARM_HARDWARE_ARM_SCU_H -#define ASMARM_HARDWARE_ARM_SCU_H - -#include <asm/arch/scu.h> - -/* - * SCU registers - */ -#define SCU_CTRL 0x00 -#define SCU_CONFIG 0x04 -#define SCU_CPU_STATUS 0x08 -#define SCU_INVALIDATE 0x0c -#define SCU_FPGA_REVISION 0x10 - -#endif diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h index ede377ec9147..18f6937f5010 100644 --- a/include/asm-arm/hardware/iop3xx.h +++ b/include/asm-arm/hardware/iop3xx.h @@ -29,6 +29,7 @@ extern void gpio_line_config(int line, int direction); extern int gpio_line_get(int line); extern void gpio_line_set(int line, int value); extern int init_atu; +extern int iop3xx_get_init_atu(void); #endif @@ -112,14 +113,6 @@ extern int init_atu; #define IOP3XX_INIT_ATU_DISABLE -1 #define IOP3XX_INIT_ATU_ENABLE 1 -#ifdef CONFIG_IOP3XX_ATU -#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\ - IOP3XX_INIT_ATU_ENABLE : init_atu) -#else -#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\ - IOP3XX_INIT_ATU_DISABLE : init_atu) -#endif - /* Messaging Unit */ #define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310) #define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314) diff --git a/include/asm-arm/hardware/scoop.h b/include/asm-arm/hardware/scoop.h index d37bf7443264..dfb8330599f9 100644 --- a/include/asm-arm/hardware/scoop.h +++ b/include/asm-arm/hardware/scoop.h @@ -40,6 +40,7 @@ struct scoop_config { unsigned short io_dir; unsigned short suspend_clr; unsigned short suspend_set; + int gpio_base; }; /* Structure for linking scoop devices to PCMCIA sockets */ @@ -62,7 +63,7 @@ struct scoop_pcmcia_config { extern struct scoop_pcmcia_config *platform_scoop_config; void reset_scoop(struct device *dev); -unsigned short set_scoop_gpio(struct device *dev, unsigned short bit); -unsigned short reset_scoop_gpio(struct device *dev, unsigned short bit); +unsigned short __deprecated set_scoop_gpio(struct device *dev, unsigned short bit); +unsigned short __deprecated reset_scoop_gpio(struct device *dev, unsigned short bit); unsigned short read_scoop_reg(struct device *dev, unsigned short reg); void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data); diff --git a/include/asm-arm/hwcap.h b/include/asm-arm/hwcap.h index 01a1391d3014..81f4c899a555 100644 --- a/include/asm-arm/hwcap.h +++ b/include/asm-arm/hwcap.h @@ -15,6 +15,7 @@ #define HWCAP_JAVA 256 #define HWCAP_IWMMXT 512 #define HWCAP_CRUNCH 1024 +#define HWCAP_THUMBEE 2048 #if defined(__KERNEL__) && !defined(__ASSEMBLY__) /* diff --git a/include/asm-arm/mach/pci.h b/include/asm-arm/mach/pci.h index 24621c49a0c7..9d4f6b5ea419 100644 --- a/include/asm-arm/mach/pci.h +++ b/include/asm-arm/mach/pci.h @@ -55,6 +55,7 @@ void pci_common_init(struct hw_pci *); extern int iop3xx_pci_setup(int nr, struct pci_sys_data *); extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *); extern void iop3xx_pci_preinit(void); +extern void iop3xx_pci_preinit_cond(void); extern int dc21285_setup(int nr, struct pci_sys_data *); extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *); diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h index d9bfb39adabf..9ba4d7136e6b 100644 --- a/include/asm-arm/memory.h +++ b/include/asm-arm/memory.h @@ -217,7 +217,10 @@ static inline __deprecated void *bus_to_virt(unsigned long x) #ifndef CONFIG_DISCONTIGMEM #define ARCH_PFN_OFFSET PHYS_PFN_OFFSET + +#ifndef CONFIG_SPARSEMEM #define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr)) +#endif #define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) #define virt_addr_valid(kaddr) ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory) diff --git a/include/asm-arm/plat-orion/ehci-orion.h b/include/asm-arm/plat-orion/ehci-orion.h new file mode 100644 index 000000000000..785705651e24 --- /dev/null +++ b/include/asm-arm/plat-orion/ehci-orion.h @@ -0,0 +1,19 @@ +/* + * include/asm-arm/plat-orion/ehci-orion.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_PLAT_ORION_EHCI_ORION_H +#define __ASM_PLAT_ORION_EHCI_ORION_H + +#include <linux/mbus.h> + +struct orion_ehci_data { + struct mbus_dram_target_info *dram; +}; + + +#endif diff --git a/include/asm-arm/plat-orion/irq.h b/include/asm-arm/plat-orion/irq.h new file mode 100644 index 000000000000..94aeed919d5b --- /dev/null +++ b/include/asm-arm/plat-orion/irq.h @@ -0,0 +1,17 @@ +/* + * include/asm-arm/plat-orion/irq.h + * + * Marvell Orion SoC IRQ handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_PLAT_ORION_IRQ_H +#define __ASM_PLAT_ORION_IRQ_H + +void orion_irq_init(unsigned int irq_start, void __iomem *maskaddr); + + +#endif diff --git a/include/asm-arm/arch-orion/platform.h b/include/asm-arm/plat-orion/orion_nand.h index 143c38e2fa0b..ffd3852a0dd7 100644 --- a/include/asm-arm/arch-orion/platform.h +++ b/include/asm-arm/plat-orion/orion_nand.h @@ -1,15 +1,13 @@ /* - * asm-arm/arch-orion/platform.h - * - * Tzachi Perelstein <tzachi@marvell.com> + * include/asm-arm/plat-orion/orion_nand.h * * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#ifndef __ASM_ARCH_PLATFORM_H__ -#define __ASM_ARCH_PLATFORM_H__ +#ifndef __ASM_PLAT_ORION_ORION_NAND_H +#define __ASM_PLAT_ORION_ORION_NAND_H /* * Device bus NAND private data @@ -22,4 +20,5 @@ struct orion_nand_data { u8 width; /* buswidth */ }; + #endif diff --git a/include/asm-arm/plat-orion/pcie.h b/include/asm-arm/plat-orion/pcie.h new file mode 100644 index 000000000000..6434ac685d21 --- /dev/null +++ b/include/asm-arm/plat-orion/pcie.h @@ -0,0 +1,31 @@ +/* + * include/asm-arm/plat-orion/pcie.h + * + * Marvell Orion SoC PCIe handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_PLAT_ORION_PCIE_H +#define __ASM_PLAT_ORION_PCIE_H + +u32 orion_pcie_dev_id(void __iomem *base); +u32 orion_pcie_rev(void __iomem *base); +int orion_pcie_link_up(void __iomem *base); +int orion_pcie_get_local_bus_nr(void __iomem *base); +void orion_pcie_set_local_bus_nr(void __iomem *base, int nr); +void orion_pcie_setup(void __iomem *base, + struct mbus_dram_target_info *dram); +int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, + u32 devfn, int where, int size, u32 *val); +int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus, + u32 devfn, int where, int size, u32 *val); +int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus, + u32 devfn, int where, int size, u32 *val); +int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus, + u32 devfn, int where, int size, u32 val); + + +#endif diff --git a/include/asm-arm/plat-orion/time.h b/include/asm-arm/plat-orion/time.h new file mode 100644 index 000000000000..0e85cc8f44d9 --- /dev/null +++ b/include/asm-arm/plat-orion/time.h @@ -0,0 +1,17 @@ +/* + * include/asm-arm/plat-orion/time.h + * + * Marvell Orion SoC time handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_PLAT_ORION_TIME_H +#define __ASM_PLAT_ORION_TIME_H + +void orion_time_init(unsigned int irq, unsigned int tclk); + + +#endif diff --git a/include/asm-arm/sparsemem.h b/include/asm-arm/sparsemem.h new file mode 100644 index 000000000000..277158191a0d --- /dev/null +++ b/include/asm-arm/sparsemem.h @@ -0,0 +1,10 @@ +#ifndef ASMARM_SPARSEMEM_H +#define ASMARM_SPARSEMEM_H + +#include <asm/memory.h> + +#define MAX_PHYSADDR_BITS 32 +#define MAX_PHYSMEM_BITS 32 +#define SECTION_SIZE_BITS NODE_MEM_SIZE_BITS + +#endif diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h index 41784357a204..f5a664786311 100644 --- a/include/asm-arm/thread_info.h +++ b/include/asm-arm/thread_info.h @@ -62,6 +62,9 @@ struct thread_info { struct crunch_state crunchstate; union fp_state fpstate __attribute__((aligned(8))); union vfp_state vfpstate; +#ifdef CONFIG_ARM_THUMBEE + unsigned long thumbee_state; /* ThumbEE Handler Base register */ +#endif struct restart_block restart_block; }; diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h index 88e868b7aae0..7c570082b1e0 100644 --- a/include/asm-arm/unistd.h +++ b/include/asm-arm/unistd.h @@ -376,9 +376,11 @@ #define __NR_kexec_load (__NR_SYSCALL_BASE+347) #define __NR_utimensat (__NR_SYSCALL_BASE+348) #define __NR_signalfd (__NR_SYSCALL_BASE+349) -#define __NR_timerfd (__NR_SYSCALL_BASE+350) +#define __NR_timerfd_create (__NR_SYSCALL_BASE+350) #define __NR_eventfd (__NR_SYSCALL_BASE+351) #define __NR_fallocate (__NR_SYSCALL_BASE+352) +#define __NR_timerfd_settime (__NR_SYSCALL_BASE+353) +#define __NR_timerfd_gettime (__NR_SYSCALL_BASE+354) /* * The following SWIs are ARM private. diff --git a/include/linux/ata_platform.h b/include/linux/ata_platform.h index b856a2a590d9..9a26c83a2c9e 100644 --- a/include/linux/ata_platform.h +++ b/include/linux/ata_platform.h @@ -27,7 +27,10 @@ extern int __devexit __pata_platform_remove(struct device *dev); /* * Marvell SATA private data */ +struct mbus_dram_target_info; + struct mv_sata_platform_data { + struct mbus_dram_target_info *dram; int n_ports; /* number of sata ports */ }; diff --git a/include/linux/mbus.h b/include/linux/mbus.h new file mode 100644 index 000000000000..c11ff2932549 --- /dev/null +++ b/include/linux/mbus.h @@ -0,0 +1,36 @@ +/* + * Marvell MBUS common definitions. + * + * Copyright (C) 2008 Marvell Semiconductor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __LINUX_MBUS_H +#define __LINUX_MBUS_H + +struct mbus_dram_target_info +{ + /* + * The 4-bit MBUS target ID of the DRAM controller. + */ + u8 mbus_dram_target_id; + + /* + * The base address, size, and MBUS attribute ID for each + * of the possible DRAM chip selects. Peripherals are + * required to support at least 4 decode windows. + */ + int num_cs; + struct mbus_dram_window { + u8 cs_index; + u8 mbus_attr; + u32 base; + u32 size; + } cs[4]; +}; + + +#endif diff --git a/include/linux/sched.h b/include/linux/sched.h index fed07d03364e..6a1e7afb099b 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -1541,6 +1541,12 @@ static inline void idle_task_exit(void) {} extern void sched_idle_next(void); +#if defined(CONFIG_NO_HZ) && defined(CONFIG_SMP) +extern void wake_up_idle_cpu(int cpu); +#else +static inline void wake_up_idle_cpu(int cpu) { } +#endif + #ifdef CONFIG_SCHED_DEBUG extern unsigned int sysctl_sched_latency; extern unsigned int sysctl_sched_min_granularity; |