diff options
Diffstat (limited to 'include')
153 files changed, 6222 insertions, 2472 deletions
diff --git a/include/acpi/acbuffer.h b/include/acpi/acbuffer.h new file mode 100644 index 000000000000..a1e45cdd729a --- /dev/null +++ b/include/acpi/acbuffer.h @@ -0,0 +1,235 @@ +/****************************************************************************** + * + * Name: acbuffer.h - Support for buffers returned by ACPI predefined names + * + *****************************************************************************/ + +/* + * Copyright (C) 2000 - 2012, Intel Corp. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * substantially similar to the "NO WARRANTY" disclaimer below + * ("Disclaimer") and any redistribution must be conditioned upon + * including a substantially similar Disclaimer requirement for further + * binary redistribution. + * 3. Neither the names of the above-listed copyright holders nor the names + * of any contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGES. + */ + +#ifndef __ACBUFFER_H__ +#define __ACBUFFER_H__ + +/* + * Contains buffer structures for these predefined names: + * _FDE, _GRT, _GTM, _PLD, _SRT + */ + +/* + * Note: C bitfields are not used for this reason: + * + * "Bitfields are great and easy to read, but unfortunately the C language + * does not specify the layout of bitfields in memory, which means they are + * essentially useless for dealing with packed data in on-disk formats or + * binary wire protocols." (Or ACPI tables and buffers.) "If you ask me, + * this decision was a design error in C. Ritchie could have picked an order + * and stuck with it." Norman Ramsey. + * See http://stackoverflow.com/a/1053662/41661 + */ + +/* _FDE return value */ + +struct acpi_fde_info { + u32 floppy0; + u32 floppy1; + u32 floppy2; + u32 floppy3; + u32 tape; +}; + +/* + * _GRT return value + * _SRT input value + */ +struct acpi_grt_info { + u16 year; + u8 month; + u8 day; + u8 hour; + u8 minute; + u8 second; + u8 valid; + u16 milliseconds; + u16 timezone; + u8 daylight; + u8 reserved[3]; +}; + +/* _GTM return value */ + +struct acpi_gtm_info { + u32 pio_speed0; + u32 dma_speed0; + u32 pio_speed1; + u32 dma_speed1; + u32 flags; +}; + +/* + * Formatted _PLD return value. The minimum size is a package containing + * one buffer. + * Revision 1: Buffer is 16 bytes (128 bits) + * Revision 2: Buffer is 20 bytes (160 bits) + * + * Note: This structure is returned from the acpi_decode_pld_buffer + * interface. + */ +struct acpi_pld_info { + u8 revision; + u8 ignore_color; + u32 color; + u16 width; + u16 height; + u8 user_visible; + u8 dock; + u8 lid; + u8 panel; + u8 vertical_position; + u8 horizontal_position; + u8 shape; + u8 group_orientation; + u8 group_token; + u8 group_position; + u8 bay; + u8 ejectable; + u8 ospm_eject_required; + u8 cabinet_number; + u8 card_cage_number; + u8 reference; + u8 rotation; + u8 order; + u8 reserved; + u16 vertical_offset; + u16 horizontal_offset; +}; + +/* + * Macros to: + * 1) Convert a _PLD buffer to internal struct acpi_pld_info format - ACPI_PLD_GET* + * (Used by acpi_decode_pld_buffer) + * 2) Construct a _PLD buffer - ACPI_PLD_SET* + * (Intended for BIOS use only) + */ +#define ACPI_PLD_REV1_BUFFER_SIZE 16 /* For Revision 1 of the buffer (From ACPI spec) */ +#define ACPI_PLD_BUFFER_SIZE 20 /* For Revision 2 of the buffer (From ACPI spec) */ + +/* First 32-bit dword, bits 0:32 */ + +#define ACPI_PLD_GET_REVISION(dword) ACPI_GET_BITS (dword, 0, ACPI_7BIT_MASK) +#define ACPI_PLD_SET_REVISION(dword,value) ACPI_SET_BITS (dword, 0, ACPI_7BIT_MASK, value) /* Offset 0, Len 7 */ + +#define ACPI_PLD_GET_IGNORE_COLOR(dword) ACPI_GET_BITS (dword, 7, ACPI_1BIT_MASK) +#define ACPI_PLD_SET_IGNORE_COLOR(dword,value) ACPI_SET_BITS (dword, 7, ACPI_1BIT_MASK, value) /* Offset 7, Len 1 */ + +#define ACPI_PLD_GET_COLOR(dword) ACPI_GET_BITS (dword, 8, ACPI_24BIT_MASK) +#define ACPI_PLD_SET_COLOR(dword,value) ACPI_SET_BITS (dword, 8, ACPI_24BIT_MASK, value) /* Offset 8, Len 24 */ + +/* Second 32-bit dword, bits 33:63 */ + +#define ACPI_PLD_GET_WIDTH(dword) ACPI_GET_BITS (dword, 0, ACPI_16BIT_MASK) +#define ACPI_PLD_SET_WIDTH(dword,value) ACPI_SET_BITS (dword, 0, ACPI_16BIT_MASK, value) /* Offset 32+0=32, Len 16 */ + +#define ACPI_PLD_GET_HEIGHT(dword) ACPI_GET_BITS (dword, 16, ACPI_16BIT_MASK) +#define ACPI_PLD_SET_HEIGHT(dword,value) ACPI_SET_BITS (dword, 16, ACPI_16BIT_MASK, value) /* Offset 32+16=48, Len 16 */ + +/* Third 32-bit dword, bits 64:95 */ + +#define ACPI_PLD_GET_USER_VISIBLE(dword) ACPI_GET_BITS (dword, 0, ACPI_1BIT_MASK) +#define ACPI_PLD_SET_USER_VISIBLE(dword,value) ACPI_SET_BITS (dword, 0, ACPI_1BIT_MASK, value) /* Offset 64+0=64, Len 1 */ + +#define ACPI_PLD_GET_DOCK(dword) ACPI_GET_BITS (dword, 1, ACPI_1BIT_MASK) +#define ACPI_PLD_SET_DOCK(dword,value) ACPI_SET_BITS (dword, 1, ACPI_1BIT_MASK, value) /* Offset 64+1=65, Len 1 */ + +#define ACPI_PLD_GET_LID(dword) ACPI_GET_BITS (dword, 2, ACPI_1BIT_MASK) +#define ACPI_PLD_SET_LID(dword,value) ACPI_SET_BITS (dword, 2, ACPI_1BIT_MASK, value) /* Offset 64+2=66, Len 1 */ + +#define ACPI_PLD_GET_PANEL(dword) ACPI_GET_BITS (dword, 3, ACPI_3BIT_MASK) +#define ACPI_PLD_SET_PANEL(dword,value) ACPI_SET_BITS (dword, 3, ACPI_3BIT_MASK, value) /* Offset 64+3=67, Len 3 */ + +#define ACPI_PLD_GET_VERTICAL(dword) ACPI_GET_BITS (dword, 6, ACPI_2BIT_MASK) +#define ACPI_PLD_SET_VERTICAL(dword,value) ACPI_SET_BITS (dword, 6, ACPI_2BIT_MASK, value) /* Offset 64+6=70, Len 2 */ + +#define ACPI_PLD_GET_HORIZONTAL(dword) ACPI_GET_BITS (dword, 8, ACPI_2BIT_MASK) +#define ACPI_PLD_SET_HORIZONTAL(dword,value) ACPI_SET_BITS (dword, 8, ACPI_2BIT_MASK, value) /* Offset 64+8=72, Len 2 */ + +#define ACPI_PLD_GET_SHAPE(dword) ACPI_GET_BITS (dword, 10, ACPI_4BIT_MASK) +#define ACPI_PLD_SET_SHAPE(dword,value) ACPI_SET_BITS (dword, 10, ACPI_4BIT_MASK, value) /* Offset 64+10=74, Len 4 */ + +#define ACPI_PLD_GET_ORIENTATION(dword) ACPI_GET_BITS (dword, 14, ACPI_1BIT_MASK) +#define ACPI_PLD_SET_ORIENTATION(dword,value) ACPI_SET_BITS (dword, 14, ACPI_1BIT_MASK, value) /* Offset 64+14=78, Len 1 */ + +#define ACPI_PLD_GET_TOKEN(dword) ACPI_GET_BITS (dword, 15, ACPI_8BIT_MASK) +#define ACPI_PLD_SET_TOKEN(dword,value) ACPI_SET_BITS (dword, 15, ACPI_8BIT_MASK, value) /* Offset 64+15=79, Len 8 */ + +#define ACPI_PLD_GET_POSITION(dword) ACPI_GET_BITS (dword, 23, ACPI_8BIT_MASK) +#define ACPI_PLD_SET_POSITION(dword,value) ACPI_SET_BITS (dword, 23, ACPI_8BIT_MASK, value) /* Offset 64+23=87, Len 8 */ + +#define ACPI_PLD_GET_BAY(dword) ACPI_GET_BITS (dword, 31, ACPI_1BIT_MASK) +#define ACPI_PLD_SET_BAY(dword,value) ACPI_SET_BITS (dword, 31, ACPI_1BIT_MASK, value) /* Offset 64+31=95, Len 1 */ + +/* Fourth 32-bit dword, bits 96:127 */ + +#define ACPI_PLD_GET_EJECTABLE(dword) ACPI_GET_BITS (dword, 0, ACPI_1BIT_MASK) +#define ACPI_PLD_SET_EJECTABLE(dword,value) ACPI_SET_BITS (dword, 0, ACPI_1BIT_MASK, value) /* Offset 96+0=96, Len 1 */ + +#define ACPI_PLD_GET_OSPM_EJECT(dword) ACPI_GET_BITS (dword, 1, ACPI_1BIT_MASK) +#define ACPI_PLD_SET_OSPM_EJECT(dword,value) ACPI_SET_BITS (dword, 1, ACPI_1BIT_MASK, value) /* Offset 96+1=97, Len 1 */ + +#define ACPI_PLD_GET_CABINET(dword) ACPI_GET_BITS (dword, 2, ACPI_8BIT_MASK) +#define ACPI_PLD_SET_CABINET(dword,value) ACPI_SET_BITS (dword, 2, ACPI_8BIT_MASK, value) /* Offset 96+2=98, Len 8 */ + +#define ACPI_PLD_GET_CARD_CAGE(dword) ACPI_GET_BITS (dword, 10, ACPI_8BIT_MASK) +#define ACPI_PLD_SET_CARD_CAGE(dword,value) ACPI_SET_BITS (dword, 10, ACPI_8BIT_MASK, value) /* Offset 96+10=106, Len 8 */ + +#define ACPI_PLD_GET_REFERENCE(dword) ACPI_GET_BITS (dword, 18, ACPI_1BIT_MASK) +#define ACPI_PLD_SET_REFERENCE(dword,value) ACPI_SET_BITS (dword, 18, ACPI_1BIT_MASK, value) /* Offset 96+18=114, Len 1 */ + +#define ACPI_PLD_GET_ROTATION(dword) ACPI_GET_BITS (dword, 19, ACPI_4BIT_MASK) +#define ACPI_PLD_SET_ROTATION(dword,value) ACPI_SET_BITS (dword, 19, ACPI_4BIT_MASK, value) /* Offset 96+19=115, Len 4 */ + +#define ACPI_PLD_GET_ORDER(dword) ACPI_GET_BITS (dword, 23, ACPI_5BIT_MASK) +#define ACPI_PLD_SET_ORDER(dword,value) ACPI_SET_BITS (dword, 23, ACPI_5BIT_MASK, value) /* Offset 96+23=119, Len 5 */ + +/* Fifth 32-bit dword, bits 128:159 (Revision 2 of _PLD only) */ + +#define ACPI_PLD_GET_VERT_OFFSET(dword) ACPI_GET_BITS (dword, 0, ACPI_16BIT_MASK) +#define ACPI_PLD_SET_VERT_OFFSET(dword,value) ACPI_SET_BITS (dword, 0, ACPI_16BIT_MASK, value) /* Offset 128+0=128, Len 16 */ + +#define ACPI_PLD_GET_HORIZ_OFFSET(dword) ACPI_GET_BITS (dword, 16, ACPI_16BIT_MASK) +#define ACPI_PLD_SET_HORIZ_OFFSET(dword,value) ACPI_SET_BITS (dword, 16, ACPI_16BIT_MASK, value) /* Offset 128+16=144, Len 16 */ + +#endif /* ACBUFFER_H */ diff --git a/include/acpi/acnames.h b/include/acpi/acnames.h index d988ac54f41e..745dd24e3cb5 100644 --- a/include/acpi/acnames.h +++ b/include/acpi/acnames.h @@ -63,11 +63,10 @@ #define METHOD_NAME__PRW "_PRW" #define METHOD_NAME__SRS "_SRS" #define METHOD_NAME__CBA "_CBA" +#define METHOD_NAME__PLD "_PLD" /* Method names - these methods must appear at the namespace root */ -#define METHOD_PATHNAME__BFS "\\_BFS" -#define METHOD_PATHNAME__GTS "\\_GTS" #define METHOD_PATHNAME__PTS "\\_PTS" #define METHOD_PATHNAME__SST "\\_SI._SST" #define METHOD_PATHNAME__WAK "\\_WAK" diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index bde976ee068d..0daa0fbd8654 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -54,37 +54,8 @@ acpi_status acpi_evaluate_hotplug_ost(acpi_handle handle, u32 source_event, u32 status_code, struct acpi_buffer *status_buf); -struct acpi_pld { - unsigned int revision:7; /* 0 */ - unsigned int ignore_colour:1; /* 7 */ - unsigned int colour:24; /* 8 */ - unsigned int width:16; /* 32 */ - unsigned int height:16; /* 48 */ - unsigned int user_visible:1; /* 64 */ - unsigned int dock:1; /* 65 */ - unsigned int lid:1; /* 66 */ - unsigned int panel:3; /* 67 */ - unsigned int vertical_pos:2; /* 70 */ - unsigned int horizontal_pos:2; /* 72 */ - unsigned int shape:4; /* 74 */ - unsigned int group_orientation:1; /* 78 */ - unsigned int group_token:8; /* 79 */ - unsigned int group_position:8; /* 87 */ - unsigned int bay:1; /* 95 */ - unsigned int ejectable:1; /* 96 */ - unsigned int ospm_eject_required:1; /* 97 */ - unsigned int cabinet_number:8; /* 98 */ - unsigned int card_cage_number:8; /* 106 */ - unsigned int reference:1; /* 114 */ - unsigned int rotation:4; /* 115 */ - unsigned int order:5; /* 119 */ - unsigned int reserved:4; /* 124 */ - unsigned int vertical_offset:16; /* 128 */ - unsigned int horizontal_offset:16; /* 144 */ -} __attribute__((__packed__)); - acpi_status -acpi_get_physical_device_location(acpi_handle handle, struct acpi_pld *pld); +acpi_get_physical_device_location(acpi_handle handle, struct acpi_pld_info **pld); #ifdef CONFIG_ACPI #include <linux/proc_fs.h> @@ -208,6 +179,7 @@ struct acpi_device_pnp { struct list_head ids; /* _HID and _CIDs */ acpi_device_name device_name; /* Driver-determined */ acpi_device_class device_class; /* " */ + union acpi_object *str_obj; /* unicode string for _STR method */ }; #define acpi_device_bid(d) ((d)->pnp.bus_id) @@ -282,8 +254,16 @@ struct acpi_device_wakeup { int prepare_count; }; -/* Device */ +struct acpi_device_physical_node { + u8 node_id; + struct list_head node; + struct device *dev; +}; + +/* set maximum of physical nodes to 32 for expansibility */ +#define ACPI_MAX_PHYSICAL_NODE 32 +/* Device */ struct acpi_device { int device_type; acpi_handle handle; /* no handle for fixed hardware */ @@ -304,6 +284,10 @@ struct acpi_device { struct device dev; struct acpi_bus_ops bus_ops; /* workaround for different code path for hotplug */ enum acpi_bus_removal_type removal_type; /* indicate for different removal type */ + u8 physical_node_count; + struct list_head physical_node_list; + struct mutex physical_node_lock; + DECLARE_BITMAP(physical_node_id_bitmap, ACPI_MAX_PHYSICAL_NODE); }; static inline void *acpi_driver_data(struct acpi_device *d) @@ -381,6 +365,19 @@ int acpi_match_device_ids(struct acpi_device *device, int acpi_create_dir(struct acpi_device *); void acpi_remove_dir(struct acpi_device *); + +/** + * module_acpi_driver(acpi_driver) - Helper macro for registering an ACPI driver + * @__acpi_driver: acpi_driver struct + * + * Helper macro for ACPI drivers which do not do anything special in module + * init/exit. This eliminates a lot of boilerplate. Each module may only + * use this macro once, and calling it replaces module_init() and module_exit() + */ +#define module_acpi_driver(__acpi_driver) \ + module_driver(__acpi_driver, acpi_bus_register_driver, \ + acpi_bus_unregister_driver) + /* * Bind physical devices with ACPI devices */ @@ -394,7 +391,6 @@ struct acpi_bus_type { }; int register_acpi_bus_type(struct acpi_bus_type *); int unregister_acpi_bus_type(struct acpi_bus_type *); -struct device *acpi_get_physical_device(acpi_handle); struct acpi_pci_root { struct list_head node; diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h index 51405d32ac64..8b891dbead66 100644 --- a/include/acpi/acpixf.h +++ b/include/acpi/acpixf.h @@ -47,11 +47,12 @@ /* Current ACPICA subsystem version in YYYYMMDD format */ -#define ACPI_CA_VERSION 0x20120711 +#define ACPI_CA_VERSION 0x20120913 #include <acpi/acconfig.h> #include <acpi/actypes.h> #include <acpi/actbl.h> +#include <acpi/acbuffer.h> extern u8 acpi_gbl_permanent_mmap; @@ -144,6 +145,10 @@ acpi_check_address_range(acpi_adr_space_type space_id, acpi_physical_address address, acpi_size length, u8 warn); +acpi_status +acpi_decode_pld_buffer(u8 *in_buffer, + acpi_size length, struct acpi_pld_info **return_buffer); + /* * ACPI Memory management */ diff --git a/include/acpi/actbl.h b/include/acpi/actbl.h index 59a73e1b2845..4f94b1d812d5 100644 --- a/include/acpi/actbl.h +++ b/include/acpi/actbl.h @@ -79,9 +79,15 @@ #pragma pack(1) /* - * Note about bitfields: The u8 type is used for bitfields in ACPI tables. - * This is the only type that is even remotely portable. Anything else is not - * portable, so do not use any other bitfield types. + * Note: C bitfields are not used for this reason: + * + * "Bitfields are great and easy to read, but unfortunately the C language + * does not specify the layout of bitfields in memory, which means they are + * essentially useless for dealing with packed data in on-disk formats or + * binary wire protocols." (Or ACPI tables and buffers.) "If you ask me, + * this decision was a design error in C. Ritchie could have picked an order + * and stuck with it." Norman Ramsey. + * See http://stackoverflow.com/a/1053662/41661 */ /******************************************************************************* @@ -94,7 +100,7 @@ struct acpi_table_header { char signature[ACPI_NAME_SIZE]; /* ASCII table signature */ u32 length; /* Length of table in bytes, including this header */ - u8 revision; /* ACPI Specification minor version # */ + u8 revision; /* ACPI Specification minor version number */ u8 checksum; /* To make sum of entire table == 0 */ char oem_id[ACPI_OEM_ID_SIZE]; /* ASCII OEM identification */ char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; /* ASCII OEM table identification */ @@ -108,7 +114,7 @@ struct acpi_table_header { * GAS - Generic Address Structure (ACPI 2.0+) * * Note: Since this structure is used in the ACPI tables, it is byte aligned. - * If misaliged access is not supported by the hardware, accesses to the + * If misaligned access is not supported by the hardware, accesses to the * 64-bit Address field must be performed with care. * ******************************************************************************/ @@ -210,18 +216,18 @@ struct acpi_table_fadt { u8 preferred_profile; /* Conveys preferred power management profile to OSPM. */ u16 sci_interrupt; /* System vector of SCI interrupt */ u32 smi_command; /* 32-bit Port address of SMI command port */ - u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */ - u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */ - u8 s4_bios_request; /* Value to write to SMI CMD to enter S4BIOS state */ + u8 acpi_enable; /* Value to write to SMI_CMD to enable ACPI */ + u8 acpi_disable; /* Value to write to SMI_CMD to disable ACPI */ + u8 s4_bios_request; /* Value to write to SMI_CMD to enter S4BIOS state */ u8 pstate_control; /* Processor performance state control */ - u32 pm1a_event_block; /* 32-bit Port address of Power Mgt 1a Event Reg Blk */ - u32 pm1b_event_block; /* 32-bit Port address of Power Mgt 1b Event Reg Blk */ - u32 pm1a_control_block; /* 32-bit Port address of Power Mgt 1a Control Reg Blk */ - u32 pm1b_control_block; /* 32-bit Port address of Power Mgt 1b Control Reg Blk */ - u32 pm2_control_block; /* 32-bit Port address of Power Mgt 2 Control Reg Blk */ - u32 pm_timer_block; /* 32-bit Port address of Power Mgt Timer Ctrl Reg Blk */ - u32 gpe0_block; /* 32-bit Port address of General Purpose Event 0 Reg Blk */ - u32 gpe1_block; /* 32-bit Port address of General Purpose Event 1 Reg Blk */ + u32 pm1a_event_block; /* 32-bit port address of Power Mgt 1a Event Reg Blk */ + u32 pm1b_event_block; /* 32-bit port address of Power Mgt 1b Event Reg Blk */ + u32 pm1a_control_block; /* 32-bit port address of Power Mgt 1a Control Reg Blk */ + u32 pm1b_control_block; /* 32-bit port address of Power Mgt 1b Control Reg Blk */ + u32 pm2_control_block; /* 32-bit port address of Power Mgt 2 Control Reg Blk */ + u32 pm_timer_block; /* 32-bit port address of Power Mgt Timer Ctrl Reg Blk */ + u32 gpe0_block; /* 32-bit port address of General Purpose Event 0 Reg Blk */ + u32 gpe1_block; /* 32-bit port address of General Purpose Event 1 Reg Blk */ u8 pm1_event_length; /* Byte Length of ports at pm1x_event_block */ u8 pm1_control_length; /* Byte Length of ports at pm1x_control_block */ u8 pm2_control_length; /* Byte Length of ports at pm2_control_block */ @@ -229,12 +235,12 @@ struct acpi_table_fadt { u8 gpe0_block_length; /* Byte Length of ports at gpe0_block */ u8 gpe1_block_length; /* Byte Length of ports at gpe1_block */ u8 gpe1_base; /* Offset in GPE number space where GPE1 events start */ - u8 cst_control; /* Support for the _CST object and C States change notification */ + u8 cst_control; /* Support for the _CST object and C-States change notification */ u16 c2_latency; /* Worst case HW latency to enter/exit C2 state */ u16 c3_latency; /* Worst case HW latency to enter/exit C3 state */ - u16 flush_size; /* Processor's memory cache line width, in bytes */ + u16 flush_size; /* Processor memory cache line width, in bytes */ u16 flush_stride; /* Number of flush strides that need to be read */ - u8 duty_offset; /* Processor duty cycle index in processor's P_CNT reg */ + u8 duty_offset; /* Processor duty cycle index in processor P_CNT reg */ u8 duty_width; /* Processor duty cycle value bit width in P_CNT register */ u8 day_alarm; /* Index to day-of-month alarm in RTC CMOS RAM */ u8 month_alarm; /* Index to month-of-year alarm in RTC CMOS RAM */ @@ -255,11 +261,11 @@ struct acpi_table_fadt { struct acpi_generic_address xpm_timer_block; /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */ struct acpi_generic_address xgpe0_block; /* 64-bit Extended General Purpose Event 0 Reg Blk address */ struct acpi_generic_address xgpe1_block; /* 64-bit Extended General Purpose Event 1 Reg Blk address */ - struct acpi_generic_address sleep_control; /* 64-bit Sleep Control register */ - struct acpi_generic_address sleep_status; /* 64-bit Sleep Status register */ + struct acpi_generic_address sleep_control; /* 64-bit Sleep Control register (ACPI 5.0) */ + struct acpi_generic_address sleep_status; /* 64-bit Sleep Status register (ACPI 5.0) */ }; -/* Masks for FADT Boot Architecture Flags (boot_flags) */ +/* Masks for FADT Boot Architecture Flags (boot_flags) [Vx]=Introduced in this FADT revision */ #define ACPI_FADT_LEGACY_DEVICES (1) /* 00: [V2] System has LPC or ISA bus devices */ #define ACPI_FADT_8042 (1<<1) /* 01: [V3] System has an 8042 controller on port 60/64 */ @@ -272,13 +278,13 @@ struct acpi_table_fadt { /* Masks for FADT flags */ -#define ACPI_FADT_WBINVD (1) /* 00: [V1] The wbinvd instruction works properly */ -#define ACPI_FADT_WBINVD_FLUSH (1<<1) /* 01: [V1] wbinvd flushes but does not invalidate caches */ +#define ACPI_FADT_WBINVD (1) /* 00: [V1] The WBINVD instruction works properly */ +#define ACPI_FADT_WBINVD_FLUSH (1<<1) /* 01: [V1] WBINVD flushes but does not invalidate caches */ #define ACPI_FADT_C1_SUPPORTED (1<<2) /* 02: [V1] All processors support C1 state */ #define ACPI_FADT_C2_MP_SUPPORTED (1<<3) /* 03: [V1] C2 state works on MP system */ #define ACPI_FADT_POWER_BUTTON (1<<4) /* 04: [V1] Power button is handled as a control method device */ #define ACPI_FADT_SLEEP_BUTTON (1<<5) /* 05: [V1] Sleep button is handled as a control method device */ -#define ACPI_FADT_FIXED_RTC (1<<6) /* 06: [V1] RTC wakeup status not in fixed register space */ +#define ACPI_FADT_FIXED_RTC (1<<6) /* 06: [V1] RTC wakeup status is not in fixed register space */ #define ACPI_FADT_S4_RTC_WAKE (1<<7) /* 07: [V1] RTC alarm can wake system from S4 */ #define ACPI_FADT_32BIT_TIMER (1<<8) /* 08: [V1] ACPI timer width is 32-bit (0=24-bit) */ #define ACPI_FADT_DOCKING_SUPPORTED (1<<9) /* 09: [V1] Docking supported */ @@ -297,7 +303,7 @@ struct acpi_table_fadt { /* Values for preferred_profile (Preferred Power Management Profiles) */ -enum acpi_prefered_pm_profiles { +enum acpi_preferred_pm_profiles { PM_UNSPECIFIED = 0, PM_DESKTOP = 1, PM_MOBILE = 2, @@ -335,7 +341,7 @@ union acpi_name_union { struct acpi_table_desc { acpi_physical_address address; struct acpi_table_header *pointer; - u32 length; /* Length fixed at 32 bits */ + u32 length; /* Length fixed at 32 bits (fixed in table header) */ union acpi_name_union signature; acpi_owner_id owner_id; u8 flags; diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 300d14e7c5d5..280fc45b59dd 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -79,9 +79,15 @@ #pragma pack(1) /* - * Note about bitfields: The u8 type is used for bitfields in ACPI tables. - * This is the only type that is even remotely portable. Anything else is not - * portable, so do not use any other bitfield types. + * Note: C bitfields are not used for this reason: + * + * "Bitfields are great and easy to read, but unfortunately the C language + * does not specify the layout of bitfields in memory, which means they are + * essentially useless for dealing with packed data in on-disk formats or + * binary wire protocols." (Or ACPI tables and buffers.) "If you ask me, + * this decision was a design error in C. Ritchie could have picked an order + * and stuck with it." Norman Ramsey. + * See http://stackoverflow.com/a/1053662/41661 */ /******************************************************************************* @@ -489,7 +495,9 @@ enum acpi_hest_notify_types { ACPI_HEST_NOTIFY_LOCAL = 2, ACPI_HEST_NOTIFY_SCI = 3, ACPI_HEST_NOTIFY_NMI = 4, - ACPI_HEST_NOTIFY_RESERVED = 5 /* 5 and greater are reserved */ + ACPI_HEST_NOTIFY_CMCI = 5, /* ACPI 5.0 */ + ACPI_HEST_NOTIFY_MCE = 6, /* ACPI 5.0 */ + ACPI_HEST_NOTIFY_RESERVED = 7 /* 7 and greater are reserved */ }; /* Values for config_write_enable bitfield above */ diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index d9ceb3d31629..1b2b356486d1 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -63,6 +63,8 @@ */ #define ACPI_SIG_ASF "ASF!" /* Alert Standard Format table */ #define ACPI_SIG_BOOT "BOOT" /* Simple Boot Flag Table */ +#define ACPI_SIG_CSRT "CSRT" /* Core System Resource Table */ +#define ACPI_SIG_DBG2 "DBG2" /* Debug Port table type 2 */ #define ACPI_SIG_DBGP "DBGP" /* Debug Port table */ #define ACPI_SIG_DMAR "DMAR" /* DMA Remapping table */ #define ACPI_SIG_HPET "HPET" /* High Precision Event Timer table */ @@ -96,9 +98,15 @@ #pragma pack(1) /* - * Note about bitfields: The u8 type is used for bitfields in ACPI tables. - * This is the only type that is even remotely portable. Anything else is not - * portable, so do not use any other bitfield types. + * Note: C bitfields are not used for this reason: + * + * "Bitfields are great and easy to read, but unfortunately the C language + * does not specify the layout of bitfields in memory, which means they are + * essentially useless for dealing with packed data in on-disk formats or + * binary wire protocols." (Or ACPI tables and buffers.) "If you ask me, + * this decision was a design error in C. Ritchie could have picked an order + * and stuck with it." Norman Ramsey. + * See http://stackoverflow.com/a/1053662/41661 */ /******************************************************************************* @@ -232,6 +240,115 @@ struct acpi_table_boot { /******************************************************************************* * + * CSRT - Core System Resource Table + * Version 0 + * + * Conforms to the "Core System Resource Table (CSRT)", November 14, 2011 + * + ******************************************************************************/ + +struct acpi_table_csrt { + struct acpi_table_header header; /* Common ACPI table header */ +}; + +/* Resource Group subtable */ + +struct acpi_csrt_group { + u32 length; + u32 vendor_id; + u32 subvendor_id; + u16 device_id; + u16 subdevice_id; + u16 revision; + u16 reserved; + u32 info_length; + + /* Shared data (length = info_length) immediately follows */ +}; + +/* Resource Descriptor subtable */ + +struct acpi_csrt_descriptor { + u32 length; + u16 type; + u16 subtype; + u32 uid; + + /* Resource-specific information immediately follows */ +}; + +/* Resource Types */ + +#define ACPI_CSRT_TYPE_INTERRUPT 0x0001 +#define ACPI_CSRT_TYPE_TIMER 0x0002 +#define ACPI_CSRT_TYPE_DMA 0x0003 + +/* Resource Subtypes */ + +#define ACPI_CSRT_XRUPT_LINE 0x0000 +#define ACPI_CSRT_XRUPT_CONTROLLER 0x0001 +#define ACPI_CSRT_TIMER 0x0000 +#define ACPI_CSRT_DMA_CHANNEL 0x0000 +#define ACPI_CSRT_DMA_CONTROLLER 0x0001 + +/******************************************************************************* + * + * DBG2 - Debug Port Table 2 + * Version 0 (Both main table and subtables) + * + * Conforms to "Microsoft Debug Port Table 2 (DBG2)", May 22 2012. + * + ******************************************************************************/ + +struct acpi_table_dbg2 { + struct acpi_table_header header; /* Common ACPI table header */ + u32 info_offset; + u32 info_count; +}; + +/* Debug Device Information Subtable */ + +struct acpi_dbg2_device { + u8 revision; + u16 length; + u8 register_count; /* Number of base_address registers */ + u16 namepath_length; + u16 namepath_offset; + u16 oem_data_length; + u16 oem_data_offset; + u16 port_type; + u16 port_subtype; + u16 reserved; + u16 base_address_offset; + u16 address_size_offset; + /* + * Data that follows: + * base_address (required) - Each in 12-byte Generic Address Structure format. + * address_size (required) - Array of u32 sizes corresponding to each base_address register. + * Namepath (required) - Null terminated string. Single dot if not supported. + * oem_data (optional) - Length is oem_data_length. + */ +}; + +/* Types for port_type field above */ + +#define ACPI_DBG2_SERIAL_PORT 0x8000 +#define ACPI_DBG2_1394_PORT 0x8001 +#define ACPI_DBG2_USB_PORT 0x8002 +#define ACPI_DBG2_NET_PORT 0x8003 + +/* Subtypes for port_subtype field above */ + +#define ACPI_DBG2_16550_COMPATIBLE 0x0000 +#define ACPI_DBG2_16550_SUBSET 0x0001 + +#define ACPI_DBG2_1394_STANDARD 0x0000 + +#define ACPI_DBG2_USB_XHCI 0x0000 +#define ACPI_DBG2_USB_EHCI 0x0001 + +/******************************************************************************* + * * DBGP - Debug Port table * Version 1 * diff --git a/include/acpi/actbl3.h b/include/acpi/actbl3.h index f65a0ed869eb..8c61b5fe42a4 100644 --- a/include/acpi/actbl3.h +++ b/include/acpi/actbl3.h @@ -75,7 +75,6 @@ /* Reserved table signatures */ #define ACPI_SIG_CSRT "CSRT" /* Core System Resources Table */ -#define ACPI_SIG_DBG2 "DBG2" /* Debug Port table 2 */ #define ACPI_SIG_MATR "MATR" /* Memory Address Translation Table */ #define ACPI_SIG_MSDM "MSDM" /* Microsoft Data Management Table */ #define ACPI_SIG_WPBT "WPBT" /* Windows Platform Binary Table */ @@ -87,9 +86,15 @@ #pragma pack(1) /* - * Note about bitfields: The u8 type is used for bitfields in ACPI tables. - * This is the only type that is even remotely portable. Anything else is not - * portable, so do not use any other bitfield types. + * Note: C bitfields are not used for this reason: + * + * "Bitfields are great and easy to read, but unfortunately the C language + * does not specify the layout of bitfields in memory, which means they are + * essentially useless for dealing with packed data in on-disk formats or + * binary wire protocols." (Or ACPI tables and buffers.) "If you ask me, + * this decision was a design error in C. Ritchie could have picked an order + * and stuck with it." Norman Ramsey. + * See http://stackoverflow.com/a/1053662/41661 */ /******************************************************************************* diff --git a/include/acpi/actypes.h b/include/acpi/actypes.h index 3d00bd5bd7e3..a85bae968262 100644 --- a/include/acpi/actypes.h +++ b/include/acpi/actypes.h @@ -519,13 +519,6 @@ typedef u64 acpi_integer; #define ACPI_SLEEP_TYPE_INVALID 0xFF /* - * Sleep/Wake flags - */ -#define ACPI_NO_OPTIONAL_METHODS 0x00 /* Do not execute any optional methods */ -#define ACPI_EXECUTE_GTS 0x01 /* For enter sleep interface */ -#define ACPI_EXECUTE_BFS 0x02 /* For leave sleep prep interface */ - -/* * Standard notify values */ #define ACPI_NOTIFY_BUS_CHECK (u8) 0x00 diff --git a/include/asm-generic/unistd.h b/include/asm-generic/unistd.h index 3748ec92dcbc..cf22fae8cae1 100644 --- a/include/asm-generic/unistd.h +++ b/include/asm-generic/unistd.h @@ -1,6 +1,3 @@ -#if !defined(_ASM_GENERIC_UNISTD_H) || defined(__SYSCALL) -#define _ASM_GENERIC_UNISTD_H - #include <asm/bitsperlong.h> /* @@ -930,4 +927,3 @@ __SYSCALL(__NR_fork, sys_ni_syscall) #endif #endif /* __KERNEL__ */ -#endif /* _ASM_GENERIC_UNISTD_H */ diff --git a/include/drm/Kbuild b/include/drm/Kbuild index 1e38a19d68f6..e69de29bb2d1 100644 --- a/include/drm/Kbuild +++ b/include/drm/Kbuild @@ -1,15 +0,0 @@ -header-y += drm.h -header-y += drm_fourcc.h -header-y += drm_mode.h -header-y += drm_sarea.h -header-y += exynos_drm.h -header-y += i810_drm.h -header-y += i915_drm.h -header-y += mga_drm.h -header-y += nouveau_drm.h -header-y += r128_drm.h -header-y += radeon_drm.h -header-y += savage_drm.h -header-y += sis_drm.h -header-y += via_drm.h -header-y += vmwgfx_drm.h diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 1816bb31273a..3fa18b7e9497 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -878,6 +878,7 @@ extern char *drm_get_tv_subconnector_name(int val); extern char *drm_get_tv_select_name(int val); extern void drm_fb_release(struct drm_file *file_priv); extern int drm_mode_group_init_legacy_group(struct drm_device *dev, struct drm_mode_group *group); +extern bool drm_probe_ddc(struct i2c_adapter *adapter); extern struct edid *drm_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter); extern int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1744b18c06b3..fe061489f91f 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -26,7 +26,19 @@ #include <linux/types.h> #include <linux/i2c.h> -/* From the VESA DisplayPort spec */ +/* + * Unless otherwise noted, all values are from the DP 1.1a spec. Note that + * DP and DPCD versions are independent. Differences from 1.0 are not noted, + * 1.0 devices basically don't exist in the wild. + * + * Abbreviations, in chronological order: + * + * eDP: Embedded DisplayPort version 1 + * DPI: DisplayPort Interoperability Guideline v1.1a + * 1.2: DisplayPort 1.2 + * + * 1.2 formally includes both eDP and DPI definitions. + */ #define AUX_NATIVE_WRITE 0x8 #define AUX_NATIVE_READ 0x9 @@ -53,7 +65,7 @@ #define DP_MAX_LANE_COUNT 0x002 # define DP_MAX_LANE_COUNT_MASK 0x1f -# define DP_TPS3_SUPPORTED (1 << 6) +# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ # define DP_ENHANCED_FRAME_CAP (1 << 7) #define DP_MAX_DOWNSPREAD 0x003 @@ -69,19 +81,33 @@ /* 10b = TMDS or HDMI */ /* 11b = Other */ # define DP_FORMAT_CONVERSION (1 << 3) +# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ #define DP_MAIN_LINK_CHANNEL_CODING 0x006 #define DP_DOWN_STREAM_PORT_COUNT 0x007 -#define DP_PORT_COUNT_MASK 0x0f -#define DP_OUI_SUPPORT (1 << 7) - -#define DP_EDP_CONFIGURATION_CAP 0x00d -#define DP_TRAINING_AUX_RD_INTERVAL 0x00e - -#define DP_PSR_SUPPORT 0x070 +# define DP_PORT_COUNT_MASK 0x0f +# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ +# define DP_OUI_SUPPORT (1 << 7) + +#define DP_I2C_SPEED_CAP 0x00c /* DPI */ +# define DP_I2C_SPEED_1K 0x01 +# define DP_I2C_SPEED_5K 0x02 +# define DP_I2C_SPEED_10K 0x04 +# define DP_I2C_SPEED_100K 0x08 +# define DP_I2C_SPEED_400K 0x10 +# define DP_I2C_SPEED_1M 0x20 + +#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ +#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ + +/* Multiple stream transport */ +#define DP_MSTM_CAP 0x021 /* 1.2 */ +# define DP_MST_CAP (1 << 0) + +#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED 1 -#define DP_PSR_CAPS 0x071 +#define DP_PSR_CAPS 0x071 /* XXX 1.2? */ # define DP_PSR_NO_TRAIN_ON_EXIT 1 # define DP_PSR_SETUP_TIME_330 (0 << 1) # define DP_PSR_SETUP_TIME_275 (1 << 1) @@ -93,11 +119,36 @@ # define DP_PSR_SETUP_TIME_MASK (7 << 1) # define DP_PSR_SETUP_TIME_SHIFT 1 +/* + * 0x80-0x8f describe downstream port capabilities, but there are two layouts + * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, + * each port's descriptor is one byte wide. If it was set, each port's is + * four bytes wide, starting with the one byte from the base info. As of + * DP interop v1.1a only VGA defines additional detail. + */ + +/* offset 0 */ +#define DP_DOWNSTREAM_PORT_0 0x80 +# define DP_DS_PORT_TYPE_MASK (7 << 0) +# define DP_DS_PORT_TYPE_DP 0 +# define DP_DS_PORT_TYPE_VGA 1 +# define DP_DS_PORT_TYPE_DVI 2 +# define DP_DS_PORT_TYPE_HDMI 3 +# define DP_DS_PORT_TYPE_NON_EDID 4 +# define DP_DS_PORT_HPD (1 << 3) +/* offset 1 for VGA is maximum megapixels per second / 8 */ +/* offset 2 */ +# define DP_DS_VGA_MAX_BPC_MASK (3 << 0) +# define DP_DS_VGA_8BPC 0 +# define DP_DS_VGA_10BPC 1 +# define DP_DS_VGA_12BPC 2 +# define DP_DS_VGA_16BPC 3 + /* link configuration */ #define DP_LINK_BW_SET 0x100 # define DP_LINK_BW_1_62 0x06 # define DP_LINK_BW_2_7 0x0a -# define DP_LINK_BW_5_4 0x14 +# define DP_LINK_BW_5_4 0x14 /* 1.2 */ #define DP_LANE_COUNT_SET 0x101 # define DP_LANE_COUNT_MASK 0x0f @@ -107,7 +158,7 @@ # define DP_TRAINING_PATTERN_DISABLE 0 # define DP_TRAINING_PATTERN_1 1 # define DP_TRAINING_PATTERN_2 2 -# define DP_TRAINING_PATTERN_3 3 +# define DP_TRAINING_PATTERN_3 3 /* 1.2 */ # define DP_TRAINING_PATTERN_MASK 0x3 # define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) @@ -148,24 +199,38 @@ #define DP_DOWNSPREAD_CTRL 0x107 # define DP_SPREAD_AMP_0_5 (1 << 4) +# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 # define DP_SET_ANSI_8B10B (1 << 0) -#define DP_PSR_EN_CFG 0x170 +#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ +/* bitmask as for DP_I2C_SPEED_CAP */ + +#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ + +#define DP_MSTM_CTRL 0x111 /* 1.2 */ +# define DP_MST_EN (1 << 0) +# define DP_UP_REQ_EN (1 << 1) +# define DP_UPSTREAM_IS_SRC (1 << 2) + +#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ # define DP_PSR_ENABLE (1 << 0) # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) # define DP_PSR_CRC_VERIFICATION (1 << 2) # define DP_PSR_FRAME_CAPTURE (1 << 3) +#define DP_SINK_COUNT 0x200 +/* prior to 1.2 bit 7 was reserved mbz */ +# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) +# define DP_SINK_CP_READY (1 << 6) + #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) # define DP_AUTOMATED_TEST_REQUEST (1 << 1) # define DP_CP_IRQ (1 << 2) # define DP_SINK_SPECIFIC_IRQ (1 << 6) -#define DP_EDP_CONFIGURATION_SET 0x10a - #define DP_LANE0_1_STATUS 0x202 #define DP_LANE2_3_STATUS 0x203 # define DP_LANE_CR_DONE (1 << 0) @@ -225,14 +290,14 @@ # define DP_SET_POWER_D0 0x1 # define DP_SET_POWER_D3 0x2 -#define DP_PSR_ERROR_STATUS 0x2006 +#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ # define DP_PSR_LINK_CRC_ERROR (1 << 0) # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) -#define DP_PSR_ESI 0x2007 +#define DP_PSR_ESI 0x2007 /* XXX 1.2? */ # define DP_PSR_CAPS_CHANGE (1 << 0) -#define DP_PSR_STATUS 0x2008 +#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ # define DP_PSR_SINK_INACTIVE 0 # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 # define DP_PSR_SINK_ACTIVE_RFB 2 diff --git a/include/drm/exynos_drm.h b/include/drm/exynos_drm.h index 1f2acdfbfd6d..3c13a3a4b158 100644 --- a/include/drm/exynos_drm.h +++ b/include/drm/exynos_drm.h @@ -25,182 +25,10 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ - #ifndef _EXYNOS_DRM_H_ #define _EXYNOS_DRM_H_ -#include <drm/drm.h> - -/** - * User-desired buffer creation information structure. - * - * @size: user-desired memory allocation size. - * - this size value would be page-aligned internally. - * @flags: user request for setting memory type or cache attributes. - * @handle: returned a handle to created gem object. - * - this handle will be set by gem module of kernel side. - */ -struct drm_exynos_gem_create { - uint64_t size; - unsigned int flags; - unsigned int handle; -}; - -/** - * A structure for getting buffer offset. - * - * @handle: a pointer to gem object created. - * @pad: just padding to be 64-bit aligned. - * @offset: relatived offset value of the memory region allocated. - * - this value should be set by user. - */ -struct drm_exynos_gem_map_off { - unsigned int handle; - unsigned int pad; - uint64_t offset; -}; - -/** - * A structure for mapping buffer. - * - * @handle: a handle to gem object created. - * @pad: just padding to be 64-bit aligned. - * @size: memory size to be mapped. - * @mapped: having user virtual address mmaped. - * - this variable would be filled by exynos gem module - * of kernel side with user virtual address which is allocated - * by do_mmap(). - */ -struct drm_exynos_gem_mmap { - unsigned int handle; - unsigned int pad; - uint64_t size; - uint64_t mapped; -}; - -/** - * A structure to gem information. - * - * @handle: a handle to gem object created. - * @flags: flag value including memory type and cache attribute and - * this value would be set by driver. - * @size: size to memory region allocated by gem and this size would - * be set by driver. - */ -struct drm_exynos_gem_info { - unsigned int handle; - unsigned int flags; - uint64_t size; -}; - -/** - * A structure for user connection request of virtual display. - * - * @connection: indicate whether doing connetion or not by user. - * @extensions: if this value is 1 then the vidi driver would need additional - * 128bytes edid data. - * @edid: the edid data pointer from user side. - */ -struct drm_exynos_vidi_connection { - unsigned int connection; - unsigned int extensions; - uint64_t edid; -}; - -/* memory type definitions. */ -enum e_drm_exynos_gem_mem_type { - /* Physically Continuous memory and used as default. */ - EXYNOS_BO_CONTIG = 0 << 0, - /* Physically Non-Continuous memory. */ - EXYNOS_BO_NONCONTIG = 1 << 0, - /* non-cachable mapping and used as default. */ - EXYNOS_BO_NONCACHABLE = 0 << 1, - /* cachable mapping. */ - EXYNOS_BO_CACHABLE = 1 << 1, - /* write-combine mapping. */ - EXYNOS_BO_WC = 1 << 2, - EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE | - EXYNOS_BO_WC -}; - -struct drm_exynos_g2d_get_ver { - __u32 major; - __u32 minor; -}; - -struct drm_exynos_g2d_cmd { - __u32 offset; - __u32 data; -}; - -enum drm_exynos_g2d_event_type { - G2D_EVENT_NOT, - G2D_EVENT_NONSTOP, - G2D_EVENT_STOP, /* not yet */ -}; - -struct drm_exynos_g2d_set_cmdlist { - __u64 cmd; - __u64 cmd_gem; - __u32 cmd_nr; - __u32 cmd_gem_nr; - - /* for g2d event */ - __u64 event_type; - __u64 user_data; -}; - -struct drm_exynos_g2d_exec { - __u64 async; -}; - -#define DRM_EXYNOS_GEM_CREATE 0x00 -#define DRM_EXYNOS_GEM_MAP_OFFSET 0x01 -#define DRM_EXYNOS_GEM_MMAP 0x02 -/* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */ -#define DRM_EXYNOS_GEM_GET 0x04 -#define DRM_EXYNOS_VIDI_CONNECTION 0x07 - -/* G2D */ -#define DRM_EXYNOS_G2D_GET_VER 0x20 -#define DRM_EXYNOS_G2D_SET_CMDLIST 0x21 -#define DRM_EXYNOS_G2D_EXEC 0x22 - -#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \ - DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create) - -#define DRM_IOCTL_EXYNOS_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \ - DRM_EXYNOS_GEM_MAP_OFFSET, struct drm_exynos_gem_map_off) - -#define DRM_IOCTL_EXYNOS_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + \ - DRM_EXYNOS_GEM_MMAP, struct drm_exynos_gem_mmap) - -#define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \ - DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info) - -#define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \ - DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection) - -#define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \ - DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver) -#define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \ - DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist) -#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \ - DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec) - -/* EXYNOS specific events */ -#define DRM_EXYNOS_G2D_EVENT 0x80000000 - -struct drm_exynos_g2d_event { - struct drm_event base; - __u64 user_data; - __u32 tv_sec; - __u32 tv_usec; - __u32 cmdlist_no; - __u32 reserved; -}; - -#ifdef __KERNEL__ +#include <uapi/drm/exynos_drm.h> /** * A structure for lcd panel information. @@ -257,5 +85,4 @@ struct exynos_drm_hdmi_pdata { int (*get_hpd)(void); }; -#endif /* __KERNEL__ */ #endif /* _EXYNOS_DRM_H_ */ diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h index a940d4e18917..63d609d8a3f6 100644 --- a/include/drm/i915_drm.h +++ b/include/drm/i915_drm.h @@ -23,933 +23,15 @@ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #ifndef _I915_DRM_H_ #define _I915_DRM_H_ -#include <drm/drm.h> - -/* Please note that modifications to all structs defined here are - * subject to backwards-compatibility constraints. - */ +#include <uapi/drm/i915_drm.h> -#ifdef __KERNEL__ /* For use by IPS driver */ extern unsigned long i915_read_mch_val(void); extern bool i915_gpu_raise(void); extern bool i915_gpu_lower(void); extern bool i915_gpu_busy(void); extern bool i915_gpu_turbo_disable(void); -#endif - -/* Each region is a minimum of 16k, and there are at most 255 of them. - */ -#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use - * of chars for next/prev indices */ -#define I915_LOG_MIN_TEX_REGION_SIZE 14 - -typedef struct _drm_i915_init { - enum { - I915_INIT_DMA = 0x01, - I915_CLEANUP_DMA = 0x02, - I915_RESUME_DMA = 0x03 - } func; - unsigned int mmio_offset; - int sarea_priv_offset; - unsigned int ring_start; - unsigned int ring_end; - unsigned int ring_size; - unsigned int front_offset; - unsigned int back_offset; - unsigned int depth_offset; - unsigned int w; - unsigned int h; - unsigned int pitch; - unsigned int pitch_bits; - unsigned int back_pitch; - unsigned int depth_pitch; - unsigned int cpp; - unsigned int chipset; -} drm_i915_init_t; - -typedef struct _drm_i915_sarea { - struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; - int last_upload; /* last time texture was uploaded */ - int last_enqueue; /* last time a buffer was enqueued */ - int last_dispatch; /* age of the most recently dispatched buffer */ - int ctxOwner; /* last context to upload state */ - int texAge; - int pf_enabled; /* is pageflipping allowed? */ - int pf_active; - int pf_current_page; /* which buffer is being displayed? */ - int perf_boxes; /* performance boxes to be displayed */ - int width, height; /* screen size in pixels */ - - drm_handle_t front_handle; - int front_offset; - int front_size; - - drm_handle_t back_handle; - int back_offset; - int back_size; - - drm_handle_t depth_handle; - int depth_offset; - int depth_size; - - drm_handle_t tex_handle; - int tex_offset; - int tex_size; - int log_tex_granularity; - int pitch; - int rotation; /* 0, 90, 180 or 270 */ - int rotated_offset; - int rotated_size; - int rotated_pitch; - int virtualX, virtualY; - - unsigned int front_tiled; - unsigned int back_tiled; - unsigned int depth_tiled; - unsigned int rotated_tiled; - unsigned int rotated2_tiled; - - int pipeA_x; - int pipeA_y; - int pipeA_w; - int pipeA_h; - int pipeB_x; - int pipeB_y; - int pipeB_w; - int pipeB_h; - - /* fill out some space for old userspace triple buffer */ - drm_handle_t unused_handle; - __u32 unused1, unused2, unused3; - - /* buffer object handles for static buffers. May change - * over the lifetime of the client. - */ - __u32 front_bo_handle; - __u32 back_bo_handle; - __u32 unused_bo_handle; - __u32 depth_bo_handle; - -} drm_i915_sarea_t; - -/* due to userspace building against these headers we need some compat here */ -#define planeA_x pipeA_x -#define planeA_y pipeA_y -#define planeA_w pipeA_w -#define planeA_h pipeA_h -#define planeB_x pipeB_x -#define planeB_y pipeB_y -#define planeB_w pipeB_w -#define planeB_h pipeB_h - -/* Flags for perf_boxes - */ -#define I915_BOX_RING_EMPTY 0x1 -#define I915_BOX_FLIP 0x2 -#define I915_BOX_WAIT 0x4 -#define I915_BOX_TEXTURE_LOAD 0x8 -#define I915_BOX_LOST_CONTEXT 0x10 - -/* I915 specific ioctls - * The device specific ioctl range is 0x40 to 0x79. - */ -#define DRM_I915_INIT 0x00 -#define DRM_I915_FLUSH 0x01 -#define DRM_I915_FLIP 0x02 -#define DRM_I915_BATCHBUFFER 0x03 -#define DRM_I915_IRQ_EMIT 0x04 -#define DRM_I915_IRQ_WAIT 0x05 -#define DRM_I915_GETPARAM 0x06 -#define DRM_I915_SETPARAM 0x07 -#define DRM_I915_ALLOC 0x08 -#define DRM_I915_FREE 0x09 -#define DRM_I915_INIT_HEAP 0x0a -#define DRM_I915_CMDBUFFER 0x0b -#define DRM_I915_DESTROY_HEAP 0x0c -#define DRM_I915_SET_VBLANK_PIPE 0x0d -#define DRM_I915_GET_VBLANK_PIPE 0x0e -#define DRM_I915_VBLANK_SWAP 0x0f -#define DRM_I915_HWS_ADDR 0x11 -#define DRM_I915_GEM_INIT 0x13 -#define DRM_I915_GEM_EXECBUFFER 0x14 -#define DRM_I915_GEM_PIN 0x15 -#define DRM_I915_GEM_UNPIN 0x16 -#define DRM_I915_GEM_BUSY 0x17 -#define DRM_I915_GEM_THROTTLE 0x18 -#define DRM_I915_GEM_ENTERVT 0x19 -#define DRM_I915_GEM_LEAVEVT 0x1a -#define DRM_I915_GEM_CREATE 0x1b -#define DRM_I915_GEM_PREAD 0x1c -#define DRM_I915_GEM_PWRITE 0x1d -#define DRM_I915_GEM_MMAP 0x1e -#define DRM_I915_GEM_SET_DOMAIN 0x1f -#define DRM_I915_GEM_SW_FINISH 0x20 -#define DRM_I915_GEM_SET_TILING 0x21 -#define DRM_I915_GEM_GET_TILING 0x22 -#define DRM_I915_GEM_GET_APERTURE 0x23 -#define DRM_I915_GEM_MMAP_GTT 0x24 -#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 -#define DRM_I915_GEM_MADVISE 0x26 -#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 -#define DRM_I915_OVERLAY_ATTRS 0x28 -#define DRM_I915_GEM_EXECBUFFER2 0x29 -#define DRM_I915_GET_SPRITE_COLORKEY 0x2a -#define DRM_I915_SET_SPRITE_COLORKEY 0x2b -#define DRM_I915_GEM_WAIT 0x2c -#define DRM_I915_GEM_CONTEXT_CREATE 0x2d -#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e -#define DRM_I915_GEM_SET_CACHING 0x2f -#define DRM_I915_GEM_GET_CACHING 0x30 -#define DRM_I915_REG_READ 0x31 - -#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) -#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) -#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) -#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) -#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) -#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) -#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) -#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) -#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) -#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) -#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) -#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) -#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) -#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) -#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) -#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) -#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) -#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) -#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) -#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) -#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) -#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) -#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) -#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) -#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) -#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) -#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) -#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) -#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) -#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) -#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) -#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) -#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) -#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) -#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) -#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) -#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) -#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) -#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) -#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) -#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) -#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) -#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) -#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) -#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) -#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) -#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) -#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) - -/* Allow drivers to submit batchbuffers directly to hardware, relying - * on the security mechanisms provided by hardware. - */ -typedef struct drm_i915_batchbuffer { - int start; /* agp offset */ - int used; /* nr bytes in use */ - int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ - int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ - int num_cliprects; /* mulitpass with multiple cliprects? */ - struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ -} drm_i915_batchbuffer_t; - -/* As above, but pass a pointer to userspace buffer which can be - * validated by the kernel prior to sending to hardware. - */ -typedef struct _drm_i915_cmdbuffer { - char __user *buf; /* pointer to userspace command buffer */ - int sz; /* nr bytes in buf */ - int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ - int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ - int num_cliprects; /* mulitpass with multiple cliprects? */ - struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ -} drm_i915_cmdbuffer_t; - -/* Userspace can request & wait on irq's: - */ -typedef struct drm_i915_irq_emit { - int __user *irq_seq; -} drm_i915_irq_emit_t; - -typedef struct drm_i915_irq_wait { - int irq_seq; -} drm_i915_irq_wait_t; - -/* Ioctl to query kernel params: - */ -#define I915_PARAM_IRQ_ACTIVE 1 -#define I915_PARAM_ALLOW_BATCHBUFFER 2 -#define I915_PARAM_LAST_DISPATCH 3 -#define I915_PARAM_CHIPSET_ID 4 -#define I915_PARAM_HAS_GEM 5 -#define I915_PARAM_NUM_FENCES_AVAIL 6 -#define I915_PARAM_HAS_OVERLAY 7 -#define I915_PARAM_HAS_PAGEFLIPPING 8 -#define I915_PARAM_HAS_EXECBUF2 9 -#define I915_PARAM_HAS_BSD 10 -#define I915_PARAM_HAS_BLT 11 -#define I915_PARAM_HAS_RELAXED_FENCING 12 -#define I915_PARAM_HAS_COHERENT_RINGS 13 -#define I915_PARAM_HAS_EXEC_CONSTANTS 14 -#define I915_PARAM_HAS_RELAXED_DELTA 15 -#define I915_PARAM_HAS_GEN7_SOL_RESET 16 -#define I915_PARAM_HAS_LLC 17 -#define I915_PARAM_HAS_ALIASING_PPGTT 18 -#define I915_PARAM_HAS_WAIT_TIMEOUT 19 -#define I915_PARAM_HAS_SEMAPHORES 20 -#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 -#define I915_PARAM_RSVD_FOR_FUTURE_USE 22 - -typedef struct drm_i915_getparam { - int param; - int __user *value; -} drm_i915_getparam_t; - -/* Ioctl to set kernel params: - */ -#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 -#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 -#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 -#define I915_SETPARAM_NUM_USED_FENCES 4 - -typedef struct drm_i915_setparam { - int param; - int value; -} drm_i915_setparam_t; - -/* A memory manager for regions of shared memory: - */ -#define I915_MEM_REGION_AGP 1 - -typedef struct drm_i915_mem_alloc { - int region; - int alignment; - int size; - int __user *region_offset; /* offset from start of fb or agp */ -} drm_i915_mem_alloc_t; - -typedef struct drm_i915_mem_free { - int region; - int region_offset; -} drm_i915_mem_free_t; - -typedef struct drm_i915_mem_init_heap { - int region; - int size; - int start; -} drm_i915_mem_init_heap_t; - -/* Allow memory manager to be torn down and re-initialized (eg on - * rotate): - */ -typedef struct drm_i915_mem_destroy_heap { - int region; -} drm_i915_mem_destroy_heap_t; - -/* Allow X server to configure which pipes to monitor for vblank signals - */ -#define DRM_I915_VBLANK_PIPE_A 1 -#define DRM_I915_VBLANK_PIPE_B 2 - -typedef struct drm_i915_vblank_pipe { - int pipe; -} drm_i915_vblank_pipe_t; - -/* Schedule buffer swap at given vertical blank: - */ -typedef struct drm_i915_vblank_swap { - drm_drawable_t drawable; - enum drm_vblank_seq_type seqtype; - unsigned int sequence; -} drm_i915_vblank_swap_t; - -typedef struct drm_i915_hws_addr { - __u64 addr; -} drm_i915_hws_addr_t; - -struct drm_i915_gem_init { - /** - * Beginning offset in the GTT to be managed by the DRM memory - * manager. - */ - __u64 gtt_start; - /** - * Ending offset in the GTT to be managed by the DRM memory - * manager. - */ - __u64 gtt_end; -}; - -struct drm_i915_gem_create { - /** - * Requested size for the object. - * - * The (page-aligned) allocated size for the object will be returned. - */ - __u64 size; - /** - * Returned handle for the object. - * - * Object handles are nonzero. - */ - __u32 handle; - __u32 pad; -}; - -struct drm_i915_gem_pread { - /** Handle for the object being read. */ - __u32 handle; - __u32 pad; - /** Offset into the object to read from */ - __u64 offset; - /** Length of data to read */ - __u64 size; - /** - * Pointer to write the data into. - * - * This is a fixed-size type for 32/64 compatibility. - */ - __u64 data_ptr; -}; - -struct drm_i915_gem_pwrite { - /** Handle for the object being written to. */ - __u32 handle; - __u32 pad; - /** Offset into the object to write to */ - __u64 offset; - /** Length of data to write */ - __u64 size; - /** - * Pointer to read the data from. - * - * This is a fixed-size type for 32/64 compatibility. - */ - __u64 data_ptr; -}; - -struct drm_i915_gem_mmap { - /** Handle for the object being mapped. */ - __u32 handle; - __u32 pad; - /** Offset in the object to map. */ - __u64 offset; - /** - * Length of data to map. - * - * The value will be page-aligned. - */ - __u64 size; - /** - * Returned pointer the data was mapped at. - * - * This is a fixed-size type for 32/64 compatibility. - */ - __u64 addr_ptr; -}; - -struct drm_i915_gem_mmap_gtt { - /** Handle for the object being mapped. */ - __u32 handle; - __u32 pad; - /** - * Fake offset to use for subsequent mmap call - * - * This is a fixed-size type for 32/64 compatibility. - */ - __u64 offset; -}; - -struct drm_i915_gem_set_domain { - /** Handle for the object */ - __u32 handle; - - /** New read domains */ - __u32 read_domains; - - /** New write domain */ - __u32 write_domain; -}; - -struct drm_i915_gem_sw_finish { - /** Handle for the object */ - __u32 handle; -}; - -struct drm_i915_gem_relocation_entry { - /** - * Handle of the buffer being pointed to by this relocation entry. - * - * It's appealing to make this be an index into the mm_validate_entry - * list to refer to the buffer, but this allows the driver to create - * a relocation list for state buffers and not re-write it per - * exec using the buffer. - */ - __u32 target_handle; - - /** - * Value to be added to the offset of the target buffer to make up - * the relocation entry. - */ - __u32 delta; - - /** Offset in the buffer the relocation entry will be written into */ - __u64 offset; - - /** - * Offset value of the target buffer that the relocation entry was last - * written as. - * - * If the buffer has the same offset as last time, we can skip syncing - * and writing the relocation. This value is written back out by - * the execbuffer ioctl when the relocation is written. - */ - __u64 presumed_offset; - - /** - * Target memory domains read by this operation. - */ - __u32 read_domains; - - /** - * Target memory domains written by this operation. - * - * Note that only one domain may be written by the whole - * execbuffer operation, so that where there are conflicts, - * the application will get -EINVAL back. - */ - __u32 write_domain; -}; - -/** @{ - * Intel memory domains - * - * Most of these just align with the various caches in - * the system and are used to flush and invalidate as - * objects end up cached in different domains. - */ -/** CPU cache */ -#define I915_GEM_DOMAIN_CPU 0x00000001 -/** Render cache, used by 2D and 3D drawing */ -#define I915_GEM_DOMAIN_RENDER 0x00000002 -/** Sampler cache, used by texture engine */ -#define I915_GEM_DOMAIN_SAMPLER 0x00000004 -/** Command queue, used to load batch buffers */ -#define I915_GEM_DOMAIN_COMMAND 0x00000008 -/** Instruction cache, used by shader programs */ -#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 -/** Vertex address cache */ -#define I915_GEM_DOMAIN_VERTEX 0x00000020 -/** GTT domain - aperture and scanout */ -#define I915_GEM_DOMAIN_GTT 0x00000040 -/** @} */ - -struct drm_i915_gem_exec_object { - /** - * User's handle for a buffer to be bound into the GTT for this - * operation. - */ - __u32 handle; - - /** Number of relocations to be performed on this buffer */ - __u32 relocation_count; - /** - * Pointer to array of struct drm_i915_gem_relocation_entry containing - * the relocations to be performed in this buffer. - */ - __u64 relocs_ptr; - - /** Required alignment in graphics aperture */ - __u64 alignment; - - /** - * Returned value of the updated offset of the object, for future - * presumed_offset writes. - */ - __u64 offset; -}; - -struct drm_i915_gem_execbuffer { - /** - * List of buffers to be validated with their relocations to be - * performend on them. - * - * This is a pointer to an array of struct drm_i915_gem_validate_entry. - * - * These buffers must be listed in an order such that all relocations - * a buffer is performing refer to buffers that have already appeared - * in the validate list. - */ - __u64 buffers_ptr; - __u32 buffer_count; - - /** Offset in the batchbuffer to start execution from. */ - __u32 batch_start_offset; - /** Bytes used in batchbuffer from batch_start_offset */ - __u32 batch_len; - __u32 DR1; - __u32 DR4; - __u32 num_cliprects; - /** This is a struct drm_clip_rect *cliprects */ - __u64 cliprects_ptr; -}; - -struct drm_i915_gem_exec_object2 { - /** - * User's handle for a buffer to be bound into the GTT for this - * operation. - */ - __u32 handle; - - /** Number of relocations to be performed on this buffer */ - __u32 relocation_count; - /** - * Pointer to array of struct drm_i915_gem_relocation_entry containing - * the relocations to be performed in this buffer. - */ - __u64 relocs_ptr; - - /** Required alignment in graphics aperture */ - __u64 alignment; - - /** - * Returned value of the updated offset of the object, for future - * presumed_offset writes. - */ - __u64 offset; - -#define EXEC_OBJECT_NEEDS_FENCE (1<<0) - __u64 flags; - __u64 rsvd1; - __u64 rsvd2; -}; - -struct drm_i915_gem_execbuffer2 { - /** - * List of gem_exec_object2 structs - */ - __u64 buffers_ptr; - __u32 buffer_count; - - /** Offset in the batchbuffer to start execution from. */ - __u32 batch_start_offset; - /** Bytes used in batchbuffer from batch_start_offset */ - __u32 batch_len; - __u32 DR1; - __u32 DR4; - __u32 num_cliprects; - /** This is a struct drm_clip_rect *cliprects */ - __u64 cliprects_ptr; -#define I915_EXEC_RING_MASK (7<<0) -#define I915_EXEC_DEFAULT (0<<0) -#define I915_EXEC_RENDER (1<<0) -#define I915_EXEC_BSD (2<<0) -#define I915_EXEC_BLT (3<<0) - -/* Used for switching the constants addressing mode on gen4+ RENDER ring. - * Gen6+ only supports relative addressing to dynamic state (default) and - * absolute addressing. - * - * These flags are ignored for the BSD and BLT rings. - */ -#define I915_EXEC_CONSTANTS_MASK (3<<6) -#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ -#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) -#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ - __u64 flags; - __u64 rsvd1; /* now used for context info */ - __u64 rsvd2; -}; - -/** Resets the SO write offset registers for transform feedback on gen7. */ -#define I915_EXEC_GEN7_SOL_RESET (1<<8) - -#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) -#define i915_execbuffer2_set_context_id(eb2, context) \ - (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK -#define i915_execbuffer2_get_context_id(eb2) \ - ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) - -struct drm_i915_gem_pin { - /** Handle of the buffer to be pinned. */ - __u32 handle; - __u32 pad; - - /** alignment required within the aperture */ - __u64 alignment; - - /** Returned GTT offset of the buffer. */ - __u64 offset; -}; - -struct drm_i915_gem_unpin { - /** Handle of the buffer to be unpinned. */ - __u32 handle; - __u32 pad; -}; - -struct drm_i915_gem_busy { - /** Handle of the buffer to check for busy */ - __u32 handle; - - /** Return busy status (1 if busy, 0 if idle). - * The high word is used to indicate on which rings the object - * currently resides: - * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) - */ - __u32 busy; -}; - -#define I915_CACHING_NONE 0 -#define I915_CACHING_CACHED 1 - -struct drm_i915_gem_caching { - /** - * Handle of the buffer to set/get the caching level of. */ - __u32 handle; - - /** - * Cacheing level to apply or return value - * - * bits0-15 are for generic caching control (i.e. the above defined - * values). bits16-31 are reserved for platform-specific variations - * (e.g. l3$ caching on gen7). */ - __u32 caching; -}; - -#define I915_TILING_NONE 0 -#define I915_TILING_X 1 -#define I915_TILING_Y 2 - -#define I915_BIT_6_SWIZZLE_NONE 0 -#define I915_BIT_6_SWIZZLE_9 1 -#define I915_BIT_6_SWIZZLE_9_10 2 -#define I915_BIT_6_SWIZZLE_9_11 3 -#define I915_BIT_6_SWIZZLE_9_10_11 4 -/* Not seen by userland */ -#define I915_BIT_6_SWIZZLE_UNKNOWN 5 -/* Seen by userland. */ -#define I915_BIT_6_SWIZZLE_9_17 6 -#define I915_BIT_6_SWIZZLE_9_10_17 7 - -struct drm_i915_gem_set_tiling { - /** Handle of the buffer to have its tiling state updated */ - __u32 handle; - - /** - * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, - * I915_TILING_Y). - * - * This value is to be set on request, and will be updated by the - * kernel on successful return with the actual chosen tiling layout. - * - * The tiling mode may be demoted to I915_TILING_NONE when the system - * has bit 6 swizzling that can't be managed correctly by GEM. - * - * Buffer contents become undefined when changing tiling_mode. - */ - __u32 tiling_mode; - - /** - * Stride in bytes for the object when in I915_TILING_X or - * I915_TILING_Y. - */ - __u32 stride; - - /** - * Returned address bit 6 swizzling required for CPU access through - * mmap mapping. - */ - __u32 swizzle_mode; -}; - -struct drm_i915_gem_get_tiling { - /** Handle of the buffer to get tiling state for. */ - __u32 handle; - - /** - * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, - * I915_TILING_Y). - */ - __u32 tiling_mode; - - /** - * Returned address bit 6 swizzling required for CPU access through - * mmap mapping. - */ - __u32 swizzle_mode; -}; - -struct drm_i915_gem_get_aperture { - /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ - __u64 aper_size; - - /** - * Available space in the aperture used by i915_gem_execbuffer, in - * bytes - */ - __u64 aper_available_size; -}; - -struct drm_i915_get_pipe_from_crtc_id { - /** ID of CRTC being requested **/ - __u32 crtc_id; - - /** pipe of requested CRTC **/ - __u32 pipe; -}; - -#define I915_MADV_WILLNEED 0 -#define I915_MADV_DONTNEED 1 -#define __I915_MADV_PURGED 2 /* internal state */ - -struct drm_i915_gem_madvise { - /** Handle of the buffer to change the backing store advice */ - __u32 handle; - - /* Advice: either the buffer will be needed again in the near future, - * or wont be and could be discarded under memory pressure. - */ - __u32 madv; - - /** Whether the backing store still exists. */ - __u32 retained; -}; - -/* flags */ -#define I915_OVERLAY_TYPE_MASK 0xff -#define I915_OVERLAY_YUV_PLANAR 0x01 -#define I915_OVERLAY_YUV_PACKED 0x02 -#define I915_OVERLAY_RGB 0x03 - -#define I915_OVERLAY_DEPTH_MASK 0xff00 -#define I915_OVERLAY_RGB24 0x1000 -#define I915_OVERLAY_RGB16 0x2000 -#define I915_OVERLAY_RGB15 0x3000 -#define I915_OVERLAY_YUV422 0x0100 -#define I915_OVERLAY_YUV411 0x0200 -#define I915_OVERLAY_YUV420 0x0300 -#define I915_OVERLAY_YUV410 0x0400 - -#define I915_OVERLAY_SWAP_MASK 0xff0000 -#define I915_OVERLAY_NO_SWAP 0x000000 -#define I915_OVERLAY_UV_SWAP 0x010000 -#define I915_OVERLAY_Y_SWAP 0x020000 -#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 - -#define I915_OVERLAY_FLAGS_MASK 0xff000000 -#define I915_OVERLAY_ENABLE 0x01000000 - -struct drm_intel_overlay_put_image { - /* various flags and src format description */ - __u32 flags; - /* source picture description */ - __u32 bo_handle; - /* stride values and offsets are in bytes, buffer relative */ - __u16 stride_Y; /* stride for packed formats */ - __u16 stride_UV; - __u32 offset_Y; /* offset for packet formats */ - __u32 offset_U; - __u32 offset_V; - /* in pixels */ - __u16 src_width; - __u16 src_height; - /* to compensate the scaling factors for partially covered surfaces */ - __u16 src_scan_width; - __u16 src_scan_height; - /* output crtc description */ - __u32 crtc_id; - __u16 dst_x; - __u16 dst_y; - __u16 dst_width; - __u16 dst_height; -}; - -/* flags */ -#define I915_OVERLAY_UPDATE_ATTRS (1<<0) -#define I915_OVERLAY_UPDATE_GAMMA (1<<1) -struct drm_intel_overlay_attrs { - __u32 flags; - __u32 color_key; - __s32 brightness; - __u32 contrast; - __u32 saturation; - __u32 gamma0; - __u32 gamma1; - __u32 gamma2; - __u32 gamma3; - __u32 gamma4; - __u32 gamma5; -}; - -/* - * Intel sprite handling - * - * Color keying works with a min/mask/max tuple. Both source and destination - * color keying is allowed. - * - * Source keying: - * Sprite pixels within the min & max values, masked against the color channels - * specified in the mask field, will be transparent. All other pixels will - * be displayed on top of the primary plane. For RGB surfaces, only the min - * and mask fields will be used; ranged compares are not allowed. - * - * Destination keying: - * Primary plane pixels that match the min value, masked against the color - * channels specified in the mask field, will be replaced by corresponding - * pixels from the sprite plane. - * - * Note that source & destination keying are exclusive; only one can be - * active on a given plane. - */ - -#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ -#define I915_SET_COLORKEY_DESTINATION (1<<1) -#define I915_SET_COLORKEY_SOURCE (1<<2) -struct drm_intel_sprite_colorkey { - __u32 plane_id; - __u32 min_value; - __u32 channel_mask; - __u32 max_value; - __u32 flags; -}; - -struct drm_i915_gem_wait { - /** Handle of BO we shall wait on */ - __u32 bo_handle; - __u32 flags; - /** Number of nanoseconds to wait, Returns time remaining. */ - __s64 timeout_ns; -}; - -struct drm_i915_gem_context_create { - /* output: id of new context*/ - __u32 ctx_id; - __u32 pad; -}; - -struct drm_i915_gem_context_destroy { - __u32 ctx_id; - __u32 pad; -}; - -struct drm_i915_reg_read { - __u64 offset; - __u64 val; /* Return value */ -}; #endif /* _I915_DRM_H_ */ diff --git a/include/linux/Kbuild b/include/linux/Kbuild index e149e8be9065..d114db9477f4 100644 --- a/include/linux/Kbuild +++ b/include/linux/Kbuild @@ -21,18 +21,15 @@ header-y += usb/ header-y += wimax/ ifneq ($(wildcard $(srctree)/arch/$(SRCARCH)/include/asm/a.out.h \ - $(srctree)/include/asm-$(SRCARCH)/a.out.h \ - $(INSTALL_HDR_PATH)/include/asm-*/a.out.h),) + $(srctree)/arch/$(SRCARCH)/include/uapi/asm/a.out.h),) header-y += a.out.h endif ifneq ($(wildcard $(srctree)/arch/$(SRCARCH)/include/asm/kvm.h \ - $(srctree)/include/asm-$(SRCARCH)/kvm.h \ - $(INSTALL_HDR_PATH)/include/asm-*/kvm.h),) + $(srctree)/arch/$(SRCARCH)/include/uapi/asm/kvm.h),) header-y += kvm.h endif ifneq ($(wildcard $(srctree)/arch/$(SRCARCH)/include/asm/kvm_para.h \ - $(srctree)/include/asm-$(SRCARCH)/kvm_para.h \ - $(INSTALL_HDR_PATH)/include/asm-*/kvm_para.h),) + $(srctree)/arch/$(SRCARCH)/include/uapi/asm/kvm_para.h),) header-y += kvm_para.h endif @@ -385,6 +382,7 @@ header-y += utsname.h header-y += uuid.h header-y += uvcvideo.h header-y += v4l2-common.h +header-y += v4l2-controls.h header-y += v4l2-dv-timings.h header-y += v4l2-mediabus.h header-y += v4l2-subdev.h diff --git a/include/linux/binfmts.h b/include/linux/binfmts.h index 366422bc1633..37935c2d2e8f 100644 --- a/include/linux/binfmts.h +++ b/include/linux/binfmts.h @@ -72,7 +72,7 @@ struct linux_binprm { /* Function parameter for binfmt->coredump */ struct coredump_params { - long signr; + siginfo_t *siginfo; struct pt_regs *regs; struct file *file; unsigned long limit; @@ -132,7 +132,6 @@ extern int copy_strings_kernel(int argc, const char *const *argv, struct linux_binprm *bprm); extern int prepare_bprm_creds(struct linux_binprm *bprm); extern void install_exec_creds(struct linux_binprm *bprm); -extern void do_coredump(long signr, int exit_code, struct pt_regs *regs); extern void set_binfmt(struct linux_binfmt *new); extern void free_bprm(struct linux_binprm *); diff --git a/include/linux/ceph/mon_client.h b/include/linux/ceph/mon_client.h index 1fb93e9080b0..a486f390dfbe 100644 --- a/include/linux/ceph/mon_client.h +++ b/include/linux/ceph/mon_client.h @@ -71,7 +71,6 @@ struct ceph_mon_client { int cur_mon; /* last monitor i contacted */ unsigned long sub_sent, sub_renew_after; struct ceph_connection con; - bool have_fsid; /* pending generic requests */ struct rb_root generic_request_tree; diff --git a/include/linux/ceph/osd_client.h b/include/linux/ceph/osd_client.h index cedfb1a8434a..d9b880e977e6 100644 --- a/include/linux/ceph/osd_client.h +++ b/include/linux/ceph/osd_client.h @@ -207,7 +207,7 @@ extern void ceph_osdc_handle_reply(struct ceph_osd_client *osdc, extern void ceph_osdc_handle_map(struct ceph_osd_client *osdc, struct ceph_msg *msg); -extern void ceph_calc_raw_layout(struct ceph_osd_client *osdc, +extern int ceph_calc_raw_layout(struct ceph_osd_client *osdc, struct ceph_file_layout *layout, u64 snapid, u64 off, u64 *plen, u64 *bno, diff --git a/include/linux/ceph/osdmap.h b/include/linux/ceph/osdmap.h index 25b930bffea6..e37acbe989a9 100644 --- a/include/linux/ceph/osdmap.h +++ b/include/linux/ceph/osdmap.h @@ -109,9 +109,9 @@ extern struct ceph_osdmap *osdmap_apply_incremental(void **p, void *end, extern void ceph_osdmap_destroy(struct ceph_osdmap *map); /* calculate mapping of a file extent to an object */ -extern void ceph_calc_file_object_mapping(struct ceph_file_layout *layout, - u64 off, u64 *plen, - u64 *bno, u64 *oxoff, u64 *oxlen); +extern int ceph_calc_file_object_mapping(struct ceph_file_layout *layout, + u64 off, u64 *plen, + u64 *bno, u64 *oxoff, u64 *oxlen); /* calculate mapping of object to a placement group */ extern int ceph_calc_object_layout(struct ceph_object_layout *ol, diff --git a/include/linux/compat.h b/include/linux/compat.h index fd4e29956d1c..3f53d002c7c5 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -160,11 +160,6 @@ struct compat_ustat { char f_fpack[6]; }; -typedef union compat_sigval { - compat_int_t sival_int; - compat_uptr_t sival_ptr; -} compat_sigval_t; - #define COMPAT_SIGEV_PAD_SIZE ((SIGEV_MAX_SIZE/sizeof(int)) - 3) typedef struct compat_sigevent { diff --git a/include/linux/coredump.h b/include/linux/coredump.h index ba4b85a6d9b8..1775eb8acc03 100644 --- a/include/linux/coredump.h +++ b/include/linux/coredump.h @@ -11,5 +11,10 @@ */ extern int dump_write(struct file *file, const void *addr, int nr); extern int dump_seek(struct file *file, loff_t off); +#ifdef CONFIG_COREDUMP +extern void do_coredump(siginfo_t *siginfo, struct pt_regs *regs); +#else +static inline void do_coredump(siginfo_t *siginfo, struct pt_regs *regs) {} +#endif #endif /* _LINUX_COREDUMP_H */ diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 9c02a4508b25..d3201e438d16 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -591,7 +591,7 @@ struct dma_device { struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)( struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, size_t period_len, enum dma_transfer_direction direction, - void *context); + unsigned long flags, void *context); struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)( struct dma_chan *chan, struct dma_interleaved_template *xt, unsigned long flags); @@ -653,10 +653,11 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg( static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic( struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, - size_t period_len, enum dma_transfer_direction dir) + size_t period_len, enum dma_transfer_direction dir, + unsigned long flags) { return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len, - period_len, dir, NULL); + period_len, dir, flags, NULL); } static inline int dmaengine_terminate_all(struct dma_chan *chan) diff --git a/include/linux/dvb/frontend.h b/include/linux/dvb/frontend.h index f50d4058c5fb..c12d452cb40d 100644 --- a/include/linux/dvb/frontend.h +++ b/include/linux/dvb/frontend.h @@ -62,6 +62,7 @@ typedef enum fe_caps { FE_CAN_8VSB = 0x200000, FE_CAN_16VSB = 0x400000, FE_HAS_EXTENDED_CAPS = 0x800000, /* We need more bitspace for newer APIs, indicate this. */ + FE_CAN_MULTISTREAM = 0x4000000, /* frontend supports multistream filtering */ FE_CAN_TURBO_FEC = 0x8000000, /* frontend supports "turbo fec modulation" */ FE_CAN_2G_MODULATION = 0x10000000, /* frontend supports "2nd generation modulation" (DVB-S2) */ FE_NEEDS_BENDING = 0x20000000, /* not supported anymore, don't use (frontend requires frequency bending) */ @@ -121,16 +122,27 @@ typedef enum fe_sec_mini_cmd { } fe_sec_mini_cmd_t; +/** + * enum fe_status - enumerates the possible frontend status + * @FE_HAS_SIGNAL: found something above the noise level + * @FE_HAS_CARRIER: found a DVB signal + * @FE_HAS_VITERBI: FEC is stable + * @FE_HAS_SYNC: found sync bytes + * @FE_HAS_LOCK: everything's working + * @FE_TIMEDOUT: no lock within the last ~2 seconds + * @FE_REINIT: frontend was reinitialized, application is recommended + * to reset DiSEqC, tone and parameters + */ + typedef enum fe_status { - FE_HAS_SIGNAL = 0x01, /* found something above the noise level */ - FE_HAS_CARRIER = 0x02, /* found a DVB signal */ - FE_HAS_VITERBI = 0x04, /* FEC is stable */ - FE_HAS_SYNC = 0x08, /* found sync bytes */ - FE_HAS_LOCK = 0x10, /* everything's working... */ - FE_TIMEDOUT = 0x20, /* no lock within the last ~2 seconds */ - FE_REINIT = 0x40 /* frontend was reinitialized, */ -} fe_status_t; /* application is recommended to reset */ - /* DiSEqC, tone and parameters */ + FE_HAS_SIGNAL = 0x01, + FE_HAS_CARRIER = 0x02, + FE_HAS_VITERBI = 0x04, + FE_HAS_SYNC = 0x08, + FE_HAS_LOCK = 0x10, + FE_TIMEDOUT = 0x20, + FE_REINIT = 0x40, +} fe_status_t; typedef enum fe_spectral_inversion { INVERSION_OFF, @@ -152,6 +164,7 @@ typedef enum fe_code_rate { FEC_AUTO, FEC_3_5, FEC_9_10, + FEC_2_5, } fe_code_rate_t; @@ -169,6 +182,7 @@ typedef enum fe_modulation { APSK_16, APSK_32, DQPSK, + QAM_4_NR, } fe_modulation_t; typedef enum fe_transmit_mode { @@ -179,6 +193,8 @@ typedef enum fe_transmit_mode { TRANSMISSION_MODE_1K, TRANSMISSION_MODE_16K, TRANSMISSION_MODE_32K, + TRANSMISSION_MODE_C1, + TRANSMISSION_MODE_C3780, } fe_transmit_mode_t; #if defined(__DVB_CORE__) || !defined (__KERNEL__) @@ -202,6 +218,9 @@ typedef enum fe_guard_interval { GUARD_INTERVAL_1_128, GUARD_INTERVAL_19_128, GUARD_INTERVAL_19_256, + GUARD_INTERVAL_PN420, + GUARD_INTERVAL_PN595, + GUARD_INTERVAL_PN945, } fe_guard_interval_t; @@ -213,6 +232,12 @@ typedef enum fe_hierarchy { HIERARCHY_AUTO } fe_hierarchy_t; +enum fe_interleaving { + INTERLEAVING_NONE, + INTERLEAVING_AUTO, + INTERLEAVING_240, + INTERLEAVING_720, +}; #if defined(__DVB_CORE__) || !defined (__KERNEL__) struct dvb_qpsk_parameters { @@ -314,9 +339,9 @@ struct dvb_frontend_event { #define DTV_ISDBT_LAYER_ENABLED 41 -#define DTV_ISDBS_TS_ID 42 - -#define DTV_DVBT2_PLP_ID 43 +#define DTV_STREAM_ID 42 +#define DTV_ISDBS_TS_ID_LEGACY DTV_STREAM_ID +#define DTV_DVBT2_PLP_ID_LEGACY 43 #define DTV_ENUM_DELSYS 44 @@ -337,7 +362,10 @@ struct dvb_frontend_event { #define DTV_ATSCMH_SCCC_CODE_MODE_C 58 #define DTV_ATSCMH_SCCC_CODE_MODE_D 59 -#define DTV_MAX_COMMAND DTV_ATSCMH_SCCC_CODE_MODE_D +#define DTV_INTERLEAVING 60 +#define DTV_LNA 61 + +#define DTV_MAX_COMMAND DTV_LNA typedef enum fe_pilot { PILOT_ON, @@ -366,7 +394,7 @@ typedef enum fe_delivery_system { SYS_ISDBC, SYS_ATSC, SYS_ATSCMH, - SYS_DMBTH, + SYS_DTMB, SYS_CMMB, SYS_DAB, SYS_DVBT2, @@ -374,8 +402,9 @@ typedef enum fe_delivery_system { SYS_DVBC_ANNEX_C, } fe_delivery_system_t; - +/* backward compatibility */ #define SYS_DVBC_ANNEX_AC SYS_DVBC_ANNEX_A +#define SYS_DMBTH SYS_DTMB /* DMB-TH is legacy name, use DTMB instead */ /* ATSC-MH */ @@ -409,6 +438,8 @@ enum atscmh_rs_code_mode { ATSCMH_RSCODE_RES = 3, }; +#define NO_STREAM_ID_FILTER (~0U) +#define LNA_AUTO (~0U) struct dtv_cmds_h { char *name; /* A display name for debugging purposes */ diff --git a/include/linux/dvb/version.h b/include/linux/dvb/version.h index 43d9e8d462d4..20e5eac2ffd3 100644 --- a/include/linux/dvb/version.h +++ b/include/linux/dvb/version.h @@ -24,6 +24,6 @@ #define _DVBVERSION_H_ #define DVB_API_VERSION 5 -#define DVB_API_VERSION_MINOR 6 +#define DVB_API_VERSION_MINOR 8 #endif /*_DVBVERSION_H_*/ diff --git a/include/linux/elf.h b/include/linux/elf.h index 0a05051a8924..59ef40650e1e 100644 --- a/include/linux/elf.h +++ b/include/linux/elf.h @@ -372,6 +372,12 @@ typedef struct elf64_shdr { #define NT_PRPSINFO 3 #define NT_TASKSTRUCT 4 #define NT_AUXV 6 +/* + * Note to userspace developers: size of NT_SIGINFO note may increase + * in the future to accomodate more fields, don't assume it is fixed! + */ +#define NT_SIGINFO 0x53494749 +#define NT_FILE 0x46494c45 #define NT_PRXFPREG 0x46e62b7f /* copied from gdb5.1/include/elf/common.h */ #define NT_PPC_VMX 0x100 /* PowerPC Altivec/VMX registers */ #define NT_PPC_SPE 0x101 /* PowerPC SPE/EVR registers */ diff --git a/include/linux/eventpoll.h b/include/linux/eventpoll.h index f4bb378ccf6a..41085d0f3955 100644 --- a/include/linux/eventpoll.h +++ b/include/linux/eventpoll.h @@ -25,6 +25,7 @@ #define EPOLL_CTL_ADD 1 #define EPOLL_CTL_DEL 2 #define EPOLL_CTL_MOD 3 +#define EPOLL_CTL_DISABLE 4 /* * Request the handling of system wakeup events so as to prevent system suspends diff --git a/include/linux/falloc.h b/include/linux/falloc.h index 73e0b628e058..d39b824a780c 100644 --- a/include/linux/falloc.h +++ b/include/linux/falloc.h @@ -3,6 +3,7 @@ #define FALLOC_FL_KEEP_SIZE 0x01 /* default is extend size */ #define FALLOC_FL_PUNCH_HOLE 0x02 /* de-allocates range */ +#define FALLOC_FL_NO_HIDE_STALE 0x04 /* reserved codepoint */ #ifdef __KERNEL__ diff --git a/include/linux/genalloc.h b/include/linux/genalloc.h index 5e98eeb2af3b..dd7c569aacad 100644 --- a/include/linux/genalloc.h +++ b/include/linux/genalloc.h @@ -29,6 +29,20 @@ #ifndef __GENALLOC_H__ #define __GENALLOC_H__ +/** + * Allocation callback function type definition + * @map: Pointer to bitmap + * @size: The bitmap size in bits + * @start: The bitnumber to start searching at + * @nr: The number of zeroed bits we're looking for + * @data: optional additional data used by @genpool_algo_t + */ +typedef unsigned long (*genpool_algo_t)(unsigned long *map, + unsigned long size, + unsigned long start, + unsigned int nr, + void *data); + /* * General purpose special memory pool descriptor. */ @@ -36,6 +50,9 @@ struct gen_pool { spinlock_t lock; struct list_head chunks; /* list of chunks in this pool */ int min_alloc_order; /* minimum allocation order */ + + genpool_algo_t algo; /* allocation function */ + void *data; }; /* @@ -78,4 +95,14 @@ extern void gen_pool_for_each_chunk(struct gen_pool *, void (*)(struct gen_pool *, struct gen_pool_chunk *, void *), void *); extern size_t gen_pool_avail(struct gen_pool *); extern size_t gen_pool_size(struct gen_pool *); + +extern void gen_pool_set_algo(struct gen_pool *pool, genpool_algo_t algo, + void *data); + +extern unsigned long gen_pool_first_fit(unsigned long *map, unsigned long size, + unsigned long start, unsigned int nr, void *data); + +extern unsigned long gen_pool_best_fit(unsigned long *map, unsigned long size, + unsigned long start, unsigned int nr, void *data); + #endif /* __GENALLOC_H__ */ diff --git a/include/linux/i2c-mux-gpio.h b/include/linux/i2c-mux-gpio.h index a36343a37ebc..4406108201fe 100644 --- a/include/linux/i2c-mux-gpio.h +++ b/include/linux/i2c-mux-gpio.h @@ -21,6 +21,9 @@ * @values: Array of bitmasks of GPIO settings (low/high) for each * position * @n_values: Number of multiplexer positions (busses to instantiate) + * @classes: Optional I2C auto-detection classes + * @gpio_chip: Optional GPIO chip name; if set, GPIO pin numbers are given + * relative to the base GPIO number of that chip * @gpios: Array of GPIO numbers used to control MUX * @n_gpios: Number of GPIOs used to control MUX * @idle: Bitmask to write to MUX when idle or GPIO_I2CMUX_NO_IDLE if not used @@ -30,6 +33,8 @@ struct i2c_mux_gpio_platform_data { int base_nr; const unsigned *values; int n_values; + const unsigned *classes; + char *gpio_chip; const unsigned *gpios; int n_gpios; unsigned idle; diff --git a/include/linux/i2c-mux.h b/include/linux/i2c-mux.h index c79083830014..40cb05a97b46 100644 --- a/include/linux/i2c-mux.h +++ b/include/linux/i2c-mux.h @@ -36,6 +36,7 @@ struct i2c_adapter *i2c_add_mux_adapter(struct i2c_adapter *parent, struct device *mux_dev, void *mux_priv, u32 force_nr, u32 chan_id, + unsigned int class, int (*select) (struct i2c_adapter *, void *mux_dev, u32 chan_id), int (*deselect) (struct i2c_adapter *, diff --git a/include/linux/i2c.h b/include/linux/i2c.h index 5970266930a2..94aed0c85bb0 100644 --- a/include/linux/i2c.h +++ b/include/linux/i2c.h @@ -144,7 +144,7 @@ extern s32 i2c_smbus_write_i2c_block_data(const struct i2c_client *client, * The driver.owner field should be set to the module owner of this driver. * The driver.name field should be set to the name of this driver. * - * For automatic device detection, both @detect and @address_data must + * For automatic device detection, both @detect and @address_list must * be defined. @class should also be set, otherwise only devices forced * with module parameters will be created. The detect function must * fill at least the name field of the i2c_board_info structure it is diff --git a/include/linux/i2c/pca954x.h b/include/linux/i2c/pca954x.h index 28f1f8d5ab1f..1712677d5904 100644 --- a/include/linux/i2c/pca954x.h +++ b/include/linux/i2c/pca954x.h @@ -36,6 +36,7 @@ struct pca954x_platform_mode { int adap_id; unsigned int deselect_on_exit:1; + unsigned int class; }; /* Per mux/switch data, used with i2c_register_board_info */ diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h index a12a38107c1a..9a5e28462324 100644 --- a/include/linux/i2c/twl.h +++ b/include/linux/i2c/twl.h @@ -188,6 +188,7 @@ int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); int twl_get_type(void); int twl_get_version(void); +int twl_get_hfclk_rate(void); int twl6030_interrupt_unmask(u8 bit_mask, u8 offset); int twl6030_interrupt_mask(u8 bit_mask, u8 offset); @@ -663,7 +664,7 @@ struct twl4030_codec_data { unsigned int check_defaults:1; unsigned int reset_registers:1; unsigned int hs_extmute:1; - void (*set_hs_extmute)(int mute); + int hs_extmute_gpio; }; struct twl4030_vibra_data { diff --git a/include/linux/ioport.h b/include/linux/ioport.h index 589e0e75efae..85ac9b9b72a2 100644 --- a/include/linux/ioport.h +++ b/include/linux/ioport.h @@ -29,8 +29,9 @@ struct resource { #define IORESOURCE_BITS 0x000000ff /* Bus-specific bits */ #define IORESOURCE_TYPE_BITS 0x00001f00 /* Resource type */ -#define IORESOURCE_IO 0x00000100 +#define IORESOURCE_IO 0x00000100 /* PCI/ISA I/O ports */ #define IORESOURCE_MEM 0x00000200 +#define IORESOURCE_REG 0x00000300 /* Register offsets */ #define IORESOURCE_IRQ 0x00000400 #define IORESOURCE_DMA 0x00000800 #define IORESOURCE_BUS 0x00001000 diff --git a/include/linux/libfdt.h b/include/linux/libfdt.h index a0c3bf6c9edb..4c0306c69b4e 100644 --- a/include/linux/libfdt.h +++ b/include/linux/libfdt.h @@ -2,7 +2,7 @@ #define _INCLUDE_LIBFDT_H_ #include <linux/libfdt_env.h> -#include <> -#include <> +#include "../../scripts/dtc/libfdt/fdt.h" +#include "../../scripts/dtc/libfdt/libfdt.h" #endif /* _INCLUDE_LIBFDT_H_ */ diff --git a/include/linux/mfd/88pm860x.h b/include/linux/mfd/88pm860x.h index 7b24943779fa..cd97530205c2 100644 --- a/include/linux/mfd/88pm860x.h +++ b/include/linux/mfd/88pm860x.h @@ -34,27 +34,26 @@ enum { PM8606_ID_MAX, }; -enum { - PM8606_BACKLIGHT1 = 0, - PM8606_BACKLIGHT2, - PM8606_BACKLIGHT3, -}; - -enum { - PM8606_LED1_RED = 0, - PM8606_LED1_GREEN, - PM8606_LED1_BLUE, - PM8606_LED2_RED, - PM8606_LED2_GREEN, - PM8606_LED2_BLUE, - PM8607_LED_VIBRATOR, -}; - /* 8606 Registers */ #define PM8606_DCM_BOOST (0x00) #define PM8606_PWM (0x01) +#define PM8607_MISC2 (0x42) + +/* Power Up Log Register */ +#define PM8607_POWER_UP_LOG (0x3F) + +/* Charger Control Registers */ +#define PM8607_CCNT (0x47) +#define PM8607_CHG_CTRL1 (0x48) +#define PM8607_CHG_CTRL2 (0x49) +#define PM8607_CHG_CTRL3 (0x4A) +#define PM8607_CHG_CTRL4 (0x4B) +#define PM8607_CHG_CTRL5 (0x4C) +#define PM8607_CHG_CTRL6 (0x4D) +#define PM8607_CHG_CTRL7 (0x4E) + /* Backlight Registers */ #define PM8606_WLED1A (0x02) #define PM8606_WLED1B (0x03) @@ -205,6 +204,71 @@ enum { #define PM8607_PD_PREBIAS (0x56) /* prebias time */ #define PM8607_GPADC_MISC1 (0x57) +/* bit definitions of MEAS_EN1*/ +#define PM8607_MEAS_EN1_VBAT (1 << 0) +#define PM8607_MEAS_EN1_VCHG (1 << 1) +#define PM8607_MEAS_EN1_VSYS (1 << 2) +#define PM8607_MEAS_EN1_TINT (1 << 3) +#define PM8607_MEAS_EN1_RFTMP (1 << 4) +#define PM8607_MEAS_EN1_TBAT (1 << 5) +#define PM8607_MEAS_EN1_GPADC2 (1 << 6) +#define PM8607_MEAS_EN1_GPADC3 (1 << 7) + +/* Battery Monitor Registers */ +#define PM8607_GP_BIAS2 (0x5A) +#define PM8607_VBAT_LOWTH (0x5B) +#define PM8607_VCHG_LOWTH (0x5C) +#define PM8607_VSYS_LOWTH (0x5D) +#define PM8607_TINT_LOWTH (0x5E) +#define PM8607_GPADC0_LOWTH (0x5F) +#define PM8607_GPADC1_LOWTH (0x60) +#define PM8607_GPADC2_LOWTH (0x61) +#define PM8607_GPADC3_LOWTH (0x62) +#define PM8607_VBAT_HIGHTH (0x63) +#define PM8607_VCHG_HIGHTH (0x64) +#define PM8607_VSYS_HIGHTH (0x65) +#define PM8607_TINT_HIGHTH (0x66) +#define PM8607_GPADC0_HIGHTH (0x67) +#define PM8607_GPADC1_HIGHTH (0x68) +#define PM8607_GPADC2_HIGHTH (0x69) +#define PM8607_GPADC3_HIGHTH (0x6A) +#define PM8607_IBAT_MEAS1 (0x6B) +#define PM8607_IBAT_MEAS2 (0x6C) +#define PM8607_VBAT_MEAS1 (0x6D) +#define PM8607_VBAT_MEAS2 (0x6E) +#define PM8607_VCHG_MEAS1 (0x6F) +#define PM8607_VCHG_MEAS2 (0x70) +#define PM8607_VSYS_MEAS1 (0x71) +#define PM8607_VSYS_MEAS2 (0x72) +#define PM8607_TINT_MEAS1 (0x73) +#define PM8607_TINT_MEAS2 (0x74) +#define PM8607_GPADC0_MEAS1 (0x75) +#define PM8607_GPADC0_MEAS2 (0x76) +#define PM8607_GPADC1_MEAS1 (0x77) +#define PM8607_GPADC1_MEAS2 (0x78) +#define PM8607_GPADC2_MEAS1 (0x79) +#define PM8607_GPADC2_MEAS2 (0x7A) +#define PM8607_GPADC3_MEAS1 (0x7B) +#define PM8607_GPADC3_MEAS2 (0x7C) +#define PM8607_CCNT_MEAS1 (0x95) +#define PM8607_CCNT_MEAS2 (0x96) +#define PM8607_VBAT_AVG (0x97) +#define PM8607_VCHG_AVG (0x98) +#define PM8607_VSYS_AVG (0x99) +#define PM8607_VBAT_MIN (0x9A) +#define PM8607_VCHG_MIN (0x9B) +#define PM8607_VSYS_MIN (0x9C) +#define PM8607_VBAT_MAX (0x9D) +#define PM8607_VCHG_MAX (0x9E) +#define PM8607_VSYS_MAX (0x9F) + +#define PM8607_GPADC_MISC2 (0x59) +#define PM8607_GPADC0_GP_BIAS_A0 (1 << 0) +#define PM8607_GPADC1_GP_BIAS_A1 (1 << 1) +#define PM8607_GPADC2_GP_BIAS_A2 (1 << 2) +#define PM8607_GPADC3_GP_BIAS_A3 (1 << 3) +#define PM8607_GPADC2_GP_BIAS_OUT2 (1 << 6) + /* RTC Control Registers */ #define PM8607_RTC1 (0xA0) #define PM8607_RTC_COUNTER1 (0xA1) @@ -322,7 +386,7 @@ struct pm860x_chip { struct regmap *regmap_companion; int buck3_double; /* DVC ramp slope double */ - unsigned short companion_addr; + int companion_addr; unsigned short osc_vote; int id; int irq_mode; @@ -340,16 +404,12 @@ enum { }; struct pm860x_backlight_pdata { - int id; int pwm; int iset; - unsigned long flags; }; struct pm860x_led_pdata { - int id; int iset; - unsigned long flags; }; struct pm860x_rtc_pdata { @@ -370,7 +430,8 @@ struct pm860x_touch_pdata { }; struct pm860x_power_pdata { - unsigned fast_charge; /* charge current */ + int max_capacity; + int resistor; }; struct pm860x_platform_data { @@ -379,15 +440,30 @@ struct pm860x_platform_data { struct pm860x_rtc_pdata *rtc; struct pm860x_touch_pdata *touch; struct pm860x_power_pdata *power; - struct regulator_init_data *regulator; - - unsigned short companion_addr; /* I2C address of companion chip */ + struct regulator_init_data *buck1; + struct regulator_init_data *buck2; + struct regulator_init_data *buck3; + struct regulator_init_data *ldo1; + struct regulator_init_data *ldo2; + struct regulator_init_data *ldo3; + struct regulator_init_data *ldo4; + struct regulator_init_data *ldo5; + struct regulator_init_data *ldo6; + struct regulator_init_data *ldo7; + struct regulator_init_data *ldo8; + struct regulator_init_data *ldo9; + struct regulator_init_data *ldo10; + struct regulator_init_data *ldo12; + struct regulator_init_data *ldo_vibrator; + struct regulator_init_data *ldo14; + struct charger_desc *chg_desc; + + int companion_addr; /* I2C address of companion chip */ int i2c_port; /* Controlled by GI2C or PI2C */ int irq_mode; /* Clear interrupt by read/write(0/1) */ int irq_base; /* IRQ base number of 88pm860x */ int num_leds; int num_backlights; - int num_regulators; }; extern int pm8606_osc_enable(struct pm860x_chip *, unsigned short); @@ -408,8 +484,4 @@ extern int pm860x_page_bulk_write(struct i2c_client *, int, int, extern int pm860x_page_set_bits(struct i2c_client *, int, unsigned char, unsigned char); -extern int pm860x_device_init(struct pm860x_chip *chip, - struct pm860x_platform_data *pdata) __devinit ; -extern void pm860x_device_exit(struct pm860x_chip *chip) __devexit ; - #endif /* __LINUX_MFD_88PM860X_H */ diff --git a/include/linux/mfd/ab3100.h b/include/linux/mfd/ab3100.h new file mode 100644 index 000000000000..afd3080bde24 --- /dev/null +++ b/include/linux/mfd/ab3100.h @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2007-2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * AB3100 core access functions + * Author: Linus Walleij <linus.walleij@stericsson.com> + * + */ + +#include <linux/regulator/machine.h> + +struct device; + +#ifndef MFD_AB3100_H +#define MFD_AB3100_H + + +#define AB3100_P1A 0xc0 +#define AB3100_P1B 0xc1 +#define AB3100_P1C 0xc2 +#define AB3100_P1D 0xc3 +#define AB3100_P1E 0xc4 +#define AB3100_P1F 0xc5 +#define AB3100_P1G 0xc6 +#define AB3100_R2A 0xc7 +#define AB3100_R2B 0xc8 + +/* + * AB3100, EVENTA1, A2 and A3 event register flags + * these are catenated into a single 32-bit flag in the code + * for event notification broadcasts. + */ +#define AB3100_EVENTA1_ONSWA (0x01<<16) +#define AB3100_EVENTA1_ONSWB (0x02<<16) +#define AB3100_EVENTA1_ONSWC (0x04<<16) +#define AB3100_EVENTA1_DCIO (0x08<<16) +#define AB3100_EVENTA1_OVER_TEMP (0x10<<16) +#define AB3100_EVENTA1_SIM_OFF (0x20<<16) +#define AB3100_EVENTA1_VBUS (0x40<<16) +#define AB3100_EVENTA1_VSET_USB (0x80<<16) + +#define AB3100_EVENTA2_READY_TX (0x01<<8) +#define AB3100_EVENTA2_READY_RX (0x02<<8) +#define AB3100_EVENTA2_OVERRUN_ERROR (0x04<<8) +#define AB3100_EVENTA2_FRAMING_ERROR (0x08<<8) +#define AB3100_EVENTA2_CHARG_OVERCURRENT (0x10<<8) +#define AB3100_EVENTA2_MIDR (0x20<<8) +#define AB3100_EVENTA2_BATTERY_REM (0x40<<8) +#define AB3100_EVENTA2_ALARM (0x80<<8) + +#define AB3100_EVENTA3_ADC_TRIG5 (0x01) +#define AB3100_EVENTA3_ADC_TRIG4 (0x02) +#define AB3100_EVENTA3_ADC_TRIG3 (0x04) +#define AB3100_EVENTA3_ADC_TRIG2 (0x08) +#define AB3100_EVENTA3_ADC_TRIGVBAT (0x10) +#define AB3100_EVENTA3_ADC_TRIGVTX (0x20) +#define AB3100_EVENTA3_ADC_TRIG1 (0x40) +#define AB3100_EVENTA3_ADC_TRIG0 (0x80) + +/* AB3100, STR register flags */ +#define AB3100_STR_ONSWA (0x01) +#define AB3100_STR_ONSWB (0x02) +#define AB3100_STR_ONSWC (0x04) +#define AB3100_STR_DCIO (0x08) +#define AB3100_STR_BOOT_MODE (0x10) +#define AB3100_STR_SIM_OFF (0x20) +#define AB3100_STR_BATT_REMOVAL (0x40) +#define AB3100_STR_VBUS (0x80) + +/* + * AB3100 contains 8 regulators, one external regulator controller + * and a buck converter, further the LDO E and buck converter can + * have separate settings if they are in sleep mode, this is + * modeled as a separate regulator. + */ +#define AB3100_NUM_REGULATORS 10 + +/** + * struct ab3100 + * @access_mutex: lock out concurrent accesses to the AB3100 registers + * @dev: pointer to the containing device + * @i2c_client: I2C client for this chip + * @testreg_client: secondary client for test registers + * @chip_name: name of this chip variant + * @chip_id: 8 bit chip ID for this chip variant + * @event_subscribers: event subscribers are listed here + * @startup_events: a copy of the first reading of the event registers + * @startup_events_read: whether the first events have been read + * + * This struct is PRIVATE and devices using it should NOT + * access ANY fields. It is used as a token for calling the + * AB3100 functions. + */ +struct ab3100 { + struct mutex access_mutex; + struct device *dev; + struct i2c_client *i2c_client; + struct i2c_client *testreg_client; + char chip_name[32]; + u8 chip_id; + struct blocking_notifier_head event_subscribers; + u8 startup_events[3]; + bool startup_events_read; +}; + +/** + * struct ab3100_platform_data + * Data supplied to initialize board connections to the AB3100 + * @reg_constraints: regulator constraints for target board + * the order of these constraints are: LDO A, C, D, E, + * F, G, H, K, EXT and BUCK. + * @reg_initvals: initial values for the regulator registers + * plus two sleep settings for LDO E and the BUCK converter. + * exactly AB3100_NUM_REGULATORS+2 values must be sent in. + * Order: LDO A, C, E, E sleep, F, G, H, K, EXT, BUCK, + * BUCK sleep, LDO D. (LDO D need to be initialized last.) + * @external_voltage: voltage level of the external regulator. + */ +struct ab3100_platform_data { + struct regulator_init_data reg_constraints[AB3100_NUM_REGULATORS]; + u8 reg_initvals[AB3100_NUM_REGULATORS+2]; + int external_voltage; +}; + +int ab3100_event_register(struct ab3100 *ab3100, + struct notifier_block *nb); +int ab3100_event_unregister(struct ab3100 *ab3100, + struct notifier_block *nb); + +#endif /* MFD_AB3100_H */ diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h index 1318ca622633..5d5298d56026 100644 --- a/include/linux/mfd/abx500.h +++ b/include/linux/mfd/abx500.h @@ -1,12 +1,9 @@ /* * Copyright (C) 2007-2009 ST-Ericsson AB * License terms: GNU General Public License (GPL) version 2 - * AB3100 core access functions - * Author: Linus Walleij <linus.walleij@stericsson.com> * * ABX500 core access functions. - * The abx500 interface is used for the Analog Baseband chip - * ab3100 and ab8500. + * The abx500 interface is used for the Analog Baseband chips. * * Author: Mattias Wallin <mattias.wallin@stericsson.com> * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> @@ -21,118 +18,6 @@ struct device; #ifndef MFD_ABX500_H #define MFD_ABX500_H -#define AB3100_P1A 0xc0 -#define AB3100_P1B 0xc1 -#define AB3100_P1C 0xc2 -#define AB3100_P1D 0xc3 -#define AB3100_P1E 0xc4 -#define AB3100_P1F 0xc5 -#define AB3100_P1G 0xc6 -#define AB3100_R2A 0xc7 -#define AB3100_R2B 0xc8 - -/* - * AB3100, EVENTA1, A2 and A3 event register flags - * these are catenated into a single 32-bit flag in the code - * for event notification broadcasts. - */ -#define AB3100_EVENTA1_ONSWA (0x01<<16) -#define AB3100_EVENTA1_ONSWB (0x02<<16) -#define AB3100_EVENTA1_ONSWC (0x04<<16) -#define AB3100_EVENTA1_DCIO (0x08<<16) -#define AB3100_EVENTA1_OVER_TEMP (0x10<<16) -#define AB3100_EVENTA1_SIM_OFF (0x20<<16) -#define AB3100_EVENTA1_VBUS (0x40<<16) -#define AB3100_EVENTA1_VSET_USB (0x80<<16) - -#define AB3100_EVENTA2_READY_TX (0x01<<8) -#define AB3100_EVENTA2_READY_RX (0x02<<8) -#define AB3100_EVENTA2_OVERRUN_ERROR (0x04<<8) -#define AB3100_EVENTA2_FRAMING_ERROR (0x08<<8) -#define AB3100_EVENTA2_CHARG_OVERCURRENT (0x10<<8) -#define AB3100_EVENTA2_MIDR (0x20<<8) -#define AB3100_EVENTA2_BATTERY_REM (0x40<<8) -#define AB3100_EVENTA2_ALARM (0x80<<8) - -#define AB3100_EVENTA3_ADC_TRIG5 (0x01) -#define AB3100_EVENTA3_ADC_TRIG4 (0x02) -#define AB3100_EVENTA3_ADC_TRIG3 (0x04) -#define AB3100_EVENTA3_ADC_TRIG2 (0x08) -#define AB3100_EVENTA3_ADC_TRIGVBAT (0x10) -#define AB3100_EVENTA3_ADC_TRIGVTX (0x20) -#define AB3100_EVENTA3_ADC_TRIG1 (0x40) -#define AB3100_EVENTA3_ADC_TRIG0 (0x80) - -/* AB3100, STR register flags */ -#define AB3100_STR_ONSWA (0x01) -#define AB3100_STR_ONSWB (0x02) -#define AB3100_STR_ONSWC (0x04) -#define AB3100_STR_DCIO (0x08) -#define AB3100_STR_BOOT_MODE (0x10) -#define AB3100_STR_SIM_OFF (0x20) -#define AB3100_STR_BATT_REMOVAL (0x40) -#define AB3100_STR_VBUS (0x80) - -/* - * AB3100 contains 8 regulators, one external regulator controller - * and a buck converter, further the LDO E and buck converter can - * have separate settings if they are in sleep mode, this is - * modeled as a separate regulator. - */ -#define AB3100_NUM_REGULATORS 10 - -/** - * struct ab3100 - * @access_mutex: lock out concurrent accesses to the AB3100 registers - * @dev: pointer to the containing device - * @i2c_client: I2C client for this chip - * @testreg_client: secondary client for test registers - * @chip_name: name of this chip variant - * @chip_id: 8 bit chip ID for this chip variant - * @event_subscribers: event subscribers are listed here - * @startup_events: a copy of the first reading of the event registers - * @startup_events_read: whether the first events have been read - * - * This struct is PRIVATE and devices using it should NOT - * access ANY fields. It is used as a token for calling the - * AB3100 functions. - */ -struct ab3100 { - struct mutex access_mutex; - struct device *dev; - struct i2c_client *i2c_client; - struct i2c_client *testreg_client; - char chip_name[32]; - u8 chip_id; - struct blocking_notifier_head event_subscribers; - u8 startup_events[3]; - bool startup_events_read; -}; - -/** - * struct ab3100_platform_data - * Data supplied to initialize board connections to the AB3100 - * @reg_constraints: regulator constraints for target board - * the order of these constraints are: LDO A, C, D, E, - * F, G, H, K, EXT and BUCK. - * @reg_initvals: initial values for the regulator registers - * plus two sleep settings for LDO E and the BUCK converter. - * exactly AB3100_NUM_REGULATORS+2 values must be sent in. - * Order: LDO A, C, E, E sleep, F, G, H, K, EXT, BUCK, - * BUCK sleep, LDO D. (LDO D need to be initialized last.) - * @external_voltage: voltage level of the external regulator. - */ -struct ab3100_platform_data { - struct regulator_init_data reg_constraints[AB3100_NUM_REGULATORS]; - u8 reg_initvals[AB3100_NUM_REGULATORS+2]; - int external_voltage; -}; - -int ab3100_event_register(struct ab3100 *ab3100, - struct notifier_block *nb); -int ab3100_event_unregister(struct ab3100 *ab3100, - struct notifier_block *nb); - /** * struct abx500_init_setting * Initial value of the registers for driver to use during setup. diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h index 3764cb6759e3..1491044efa10 100644 --- a/include/linux/mfd/abx500/ab8500.h +++ b/include/linux/mfd/abx500/ab8500.h @@ -341,6 +341,4 @@ static inline int is_ab8500_2p0(struct ab8500 *ab) return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0)); } -int ab8500_irq_get_virq(struct ab8500 *ab8500, int irq); - #endif /* MFD_AB8500_H */ diff --git a/include/linux/mfd/anatop.h b/include/linux/mfd/anatop.h deleted file mode 100644 index 7f92acf03d9e..000000000000 --- a/include/linux/mfd/anatop.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * anatop.h - Anatop MFD driver - * - * Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> - * Copyright (C) 2012 Linaro - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __LINUX_MFD_ANATOP_H -#define __LINUX_MFD_ANATOP_H - -#include <linux/spinlock.h> - -/** - * anatop - MFD data - * @ioreg: ioremap register - * @reglock: spinlock for register read/write - */ -struct anatop { - void *ioreg; - spinlock_t reglock; -}; - -extern u32 anatop_read_reg(struct anatop *, u32); -extern void anatop_write_reg(struct anatop *, u32, u32, u32); - -#endif /* __LINUX_MFD_ANATOP_H */ diff --git a/include/linux/mfd/da9055/core.h b/include/linux/mfd/da9055/core.h new file mode 100644 index 000000000000..c96ad682c59e --- /dev/null +++ b/include/linux/mfd/da9055/core.h @@ -0,0 +1,94 @@ +/* + * da9055 declarations for DA9055 PMICs. + * + * Copyright(c) 2012 Dialog Semiconductor Ltd. + * + * Author: David Dajun Chen <dchen@diasemi.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __DA9055_CORE_H +#define __DA9055_CORE_H + +#include <linux/interrupt.h> +#include <linux/regmap.h> + +/* + * PMIC IRQ + */ +#define DA9055_IRQ_ALARM 0x01 +#define DA9055_IRQ_TICK 0x02 +#define DA9055_IRQ_NONKEY 0x00 +#define DA9055_IRQ_REGULATOR 0x0B +#define DA9055_IRQ_HWMON 0x03 + +struct da9055_pdata; + +struct da9055 { + struct regmap *regmap; + struct regmap_irq_chip_data *irq_data; + struct device *dev; + struct i2c_client *i2c_client; + + int irq_base; + int chip_irq; +}; + +/* Device I/O */ +static inline int da9055_reg_read(struct da9055 *da9055, unsigned char reg) +{ + int val, ret; + + ret = regmap_read(da9055->regmap, reg, &val); + if (ret < 0) + return ret; + + return val; +} + +static inline int da9055_reg_write(struct da9055 *da9055, unsigned char reg, + unsigned char val) +{ + return regmap_write(da9055->regmap, reg, val); +} + +static inline int da9055_group_read(struct da9055 *da9055, unsigned char reg, + unsigned reg_cnt, unsigned char *val) +{ + return regmap_bulk_read(da9055->regmap, reg, val, reg_cnt); +} + +static inline int da9055_group_write(struct da9055 *da9055, unsigned char reg, + unsigned reg_cnt, unsigned char *val) +{ + return regmap_raw_write(da9055->regmap, reg, val, reg_cnt); +} + +static inline int da9055_reg_update(struct da9055 *da9055, unsigned char reg, + unsigned char bit_mask, + unsigned char reg_val) +{ + return regmap_update_bits(da9055->regmap, reg, bit_mask, reg_val); +} + +/* Generic Device API */ +int da9055_device_init(struct da9055 *da9055); +void da9055_device_exit(struct da9055 *da9055); + +extern struct regmap_config da9055_regmap_config; + +#endif /* __DA9055_CORE_H */ diff --git a/include/linux/mfd/da9055/pdata.h b/include/linux/mfd/da9055/pdata.h new file mode 100644 index 000000000000..147293b4471d --- /dev/null +++ b/include/linux/mfd/da9055/pdata.h @@ -0,0 +1,32 @@ +/* Copyright (C) 2012 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#ifndef __DA9055_PDATA_H +#define __DA9055_PDATA_H + +#define DA9055_MAX_REGULATORS 8 + +struct da9055; + +enum gpio_select { + NO_GPIO = 0, + GPIO_1, + GPIO_2 +}; + +struct da9055_pdata { + int (*init) (struct da9055 *da9055); + int irq_base; + int gpio_base; + + struct regulator_init_data *regulators[DA9055_MAX_REGULATORS]; + bool reset_enable; /* Enable RTC in RESET Mode */ + enum gpio_select *gpio_rsel; /* Select regulator set thru GPIO 1/2 */ + enum gpio_select *gpio_ren; /* Enable regulator thru GPIO 1/2 */ +}; +#endif /* __DA9055_PDATA_H */ diff --git a/include/linux/mfd/da9055/reg.h b/include/linux/mfd/da9055/reg.h new file mode 100644 index 000000000000..df237ee54803 --- /dev/null +++ b/include/linux/mfd/da9055/reg.h @@ -0,0 +1,699 @@ +/* + * DA9055 declarations for DA9055 PMICs. + * + * Copyright(c) 2012 Dialog Semiconductor Ltd. + * + * Author: David Dajun Chen <dchen@diasemi.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __DA9055_REG_H +#define __DA9055_REG_H + +/* + * PMIC registers + */ + /* PAGE0 */ +#define DA9055_REG_PAGE_CON 0x00 + +/* System Control and Event Registers */ +#define DA9055_REG_STATUS_A 0x01 +#define DA9055_REG_STATUS_B 0x02 +#define DA9055_REG_FAULT_LOG 0x03 +#define DA9055_REG_EVENT_A 0x04 +#define DA9055_REG_EVENT_B 0x05 +#define DA9055_REG_EVENT_C 0x06 +#define DA9055_REG_IRQ_MASK_A 0x07 +#define DA9055_REG_IRQ_MASK_B 0x08 +#define DA9055_REG_IRQ_MASK_C 0x09 +#define DA9055_REG_CONTROL_A 0x0A +#define DA9055_REG_CONTROL_B 0x0B +#define DA9055_REG_CONTROL_C 0x0C +#define DA9055_REG_CONTROL_D 0x0D +#define DA9055_REG_CONTROL_E 0x0E +#define DA9055_REG_PD_DIS 0x0F + +/* GPIO Control Registers */ +#define DA9055_REG_GPIO0_1 0x10 +#define DA9055_REG_GPIO2 0x11 +#define DA9055_REG_GPIO_MODE0_2 0x12 + +/* Regulator Control Registers */ +#define DA9055_REG_BCORE_CONT 0x13 +#define DA9055_REG_BMEM_CONT 0x14 +#define DA9055_REG_LDO1_CONT 0x15 +#define DA9055_REG_LDO2_CONT 0x16 +#define DA9055_REG_LDO3_CONT 0x17 +#define DA9055_REG_LDO4_CONT 0x18 +#define DA9055_REG_LDO5_CONT 0x19 +#define DA9055_REG_LDO6_CONT 0x1A + +/* GP-ADC Control Registers */ +#define DA9055_REG_ADC_MAN 0x1B +#define DA9055_REG_ADC_CONT 0x1C +#define DA9055_REG_VSYS_MON 0x1D +#define DA9055_REG_ADC_RES_L 0x1E +#define DA9055_REG_ADC_RES_H 0x1F +#define DA9055_REG_VSYS_RES 0x20 +#define DA9055_REG_ADCIN1_RES 0x21 +#define DA9055_REG_ADCIN2_RES 0x22 +#define DA9055_REG_ADCIN3_RES 0x23 + +/* Sequencer Control Registers */ +#define DA9055_REG_EN_32K 0x35 + +/* Regulator Setting Registers */ +#define DA9055_REG_BUCK_LIM 0x37 +#define DA9055_REG_BCORE_MODE 0x38 +#define DA9055_REG_VBCORE_A 0x39 +#define DA9055_REG_VBMEM_A 0x3A +#define DA9055_REG_VLDO1_A 0x3B +#define DA9055_REG_VLDO2_A 0x3C +#define DA9055_REG_VLDO3_A 0x3D +#define DA9055_REG_VLDO4_A 0x3E +#define DA9055_REG_VLDO5_A 0x3F +#define DA9055_REG_VLDO6_A 0x40 +#define DA9055_REG_VBCORE_B 0x41 +#define DA9055_REG_VBMEM_B 0x42 +#define DA9055_REG_VLDO1_B 0x43 +#define DA9055_REG_VLDO2_B 0x44 +#define DA9055_REG_VLDO3_B 0x45 +#define DA9055_REG_VLDO4_B 0x46 +#define DA9055_REG_VLDO5_B 0x47 +#define DA9055_REG_VLDO6_B 0x48 + +/* GP-ADC Threshold Registers */ +#define DA9055_REG_AUTO1_HIGH 0x49 +#define DA9055_REG_AUTO1_LOW 0x4A +#define DA9055_REG_AUTO2_HIGH 0x4B +#define DA9055_REG_AUTO2_LOW 0x4C +#define DA9055_REG_AUTO3_HIGH 0x4D +#define DA9055_REG_AUTO3_LOW 0x4E + +/* OTP */ +#define DA9055_REG_OPT_COUNT 0x50 +#define DA9055_REG_OPT_ADDR 0x51 +#define DA9055_REG_OPT_DATA 0x52 + +/* RTC Calendar and Alarm Registers */ +#define DA9055_REG_COUNT_S 0x53 +#define DA9055_REG_COUNT_MI 0x54 +#define DA9055_REG_COUNT_H 0x55 +#define DA9055_REG_COUNT_D 0x56 +#define DA9055_REG_COUNT_MO 0x57 +#define DA9055_REG_COUNT_Y 0x58 +#define DA9055_REG_ALARM_MI 0x59 +#define DA9055_REG_ALARM_H 0x5A +#define DA9055_REG_ALARM_D 0x5B +#define DA9055_REG_ALARM_MO 0x5C +#define DA9055_REG_ALARM_Y 0x5D +#define DA9055_REG_SECOND_A 0x5E +#define DA9055_REG_SECOND_B 0x5F +#define DA9055_REG_SECOND_C 0x60 +#define DA9055_REG_SECOND_D 0x61 + +/* Customer Trim and Configuration */ +#define DA9055_REG_T_OFFSET 0x63 +#define DA9055_REG_INTERFACE 0x64 +#define DA9055_REG_CONFIG_A 0x65 +#define DA9055_REG_CONFIG_B 0x66 +#define DA9055_REG_CONFIG_C 0x67 +#define DA9055_REG_CONFIG_D 0x68 +#define DA9055_REG_CONFIG_E 0x69 +#define DA9055_REG_TRIM_CLDR 0x6F + +/* General Purpose Registers */ +#define DA9055_REG_GP_ID_0 0x70 +#define DA9055_REG_GP_ID_1 0x71 +#define DA9055_REG_GP_ID_2 0x72 +#define DA9055_REG_GP_ID_3 0x73 +#define DA9055_REG_GP_ID_4 0x74 +#define DA9055_REG_GP_ID_5 0x75 +#define DA9055_REG_GP_ID_6 0x76 +#define DA9055_REG_GP_ID_7 0x77 +#define DA9055_REG_GP_ID_8 0x78 +#define DA9055_REG_GP_ID_9 0x79 +#define DA9055_REG_GP_ID_10 0x7A +#define DA9055_REG_GP_ID_11 0x7B +#define DA9055_REG_GP_ID_12 0x7C +#define DA9055_REG_GP_ID_13 0x7D +#define DA9055_REG_GP_ID_14 0x7E +#define DA9055_REG_GP_ID_15 0x7F +#define DA9055_REG_GP_ID_16 0x80 +#define DA9055_REG_GP_ID_17 0x81 +#define DA9055_REG_GP_ID_18 0x82 +#define DA9055_REG_GP_ID_19 0x83 + +#define DA9055_MAX_REGISTER_CNT DA9055_REG_GP_ID_19 + +/* + * PMIC registers bits + */ + +/* DA9055_REG_PAGE_CON (addr=0x00) */ +#define DA9055_PAGE_WRITE_MODE (0<<6) +#define DA9055_REPEAT_WRITE_MODE (1<<6) + +/* DA9055_REG_STATUS_A (addr=0x01) */ +#define DA9055_NOKEY_STS 0x01 +#define DA9055_WAKE_STS 0x02 +#define DA9055_DVC_BUSY_STS 0x04 +#define DA9055_COMP1V2_STS 0x08 +#define DA9055_NJIG_STS 0x10 +#define DA9055_LDO5_LIM_STS 0x20 +#define DA9055_LDO6_LIM_STS 0x40 + +/* DA9055_REG_STATUS_B (addr=0x02) */ +#define DA9055_GPI0_STS 0x01 +#define DA9055_GPI1_STS 0x02 +#define DA9055_GPI2_STS 0x04 + +/* DA9055_REG_FAULT_LOG (addr=0x03) */ +#define DA9055_TWD_ERROR_FLG 0x01 +#define DA9055_POR_FLG 0x02 +#define DA9055_VDD_FAULT_FLG 0x04 +#define DA9055_VDD_START_FLG 0x08 +#define DA9055_TEMP_CRIT_FLG 0x10 +#define DA9055_KEY_RESET_FLG 0x20 +#define DA9055_WAIT_SHUT_FLG 0x80 + +/* DA9055_REG_EVENT_A (addr=0x04) */ +#define DA9055_NOKEY_EINT 0x01 +#define DA9055_ALARM_EINT 0x02 +#define DA9055_TICK_EINT 0x04 +#define DA9055_ADC_RDY_EINT 0x08 +#define DA9055_SEQ_RDY_EINT 0x10 +#define DA9055_EVENTS_B_EINT 0x20 +#define DA9055_EVENTS_C_EINT 0x40 + +/* DA9055_REG_EVENT_B (addr=0x05) */ +#define DA9055_E_WAKE_EINT 0x01 +#define DA9055_E_TEMP_EINT 0x02 +#define DA9055_E_COMP1V2_EINT 0x04 +#define DA9055_E_LDO_LIM_EINT 0x08 +#define DA9055_E_NJIG_EINT 0x20 +#define DA9055_E_VDD_MON_EINT 0x40 +#define DA9055_E_VDD_WARN_EINT 0x80 + +/* DA9055_REG_EVENT_C (addr=0x06) */ +#define DA9055_E_GPI0_EINT 0x01 +#define DA9055_E_GPI1_EINT 0x02 +#define DA9055_E_GPI2_EINT 0x04 + +/* DA9055_REG_IRQ_MASK_A (addr=0x07) */ +#define DA9055_M_NONKEY_EINT 0x01 +#define DA9055_M_ALARM_EINT 0x02 +#define DA9055_M_TICK_EINT 0x04 +#define DA9055_M_ADC_RDY_EINT 0x08 +#define DA9055_M_SEQ_RDY_EINT 0x10 + +/* DA9055_REG_IRQ_MASK_B (addr=0x08) */ +#define DA9055_M_WAKE_EINT 0x01 +#define DA9055_M_TEMP_EINT 0x02 +#define DA9055_M_COMP_1V2_EINT 0x04 +#define DA9055_M_LDO_LIM_EINT 0x08 +#define DA9055_M_NJIG_EINT 0x20 +#define DA9055_M_VDD_MON_EINT 0x40 +#define DA9055_M_VDD_WARN_EINT 0x80 + +/* DA9055_REG_IRQ_MASK_C (addr=0x09) */ +#define DA9055_M_GPI0_EINT 0x01 +#define DA9055_M_GPI1_EINT 0x02 +#define DA9055_M_GPI2_EINT 0x04 + +/* DA9055_REG_CONTROL_A (addr=0xA) */ +#define DA9055_DEBOUNCING_SHIFT 0x00 +#define DA9055_DEBOUNCING_MASK 0x07 +#define DA9055_NRES_MODE_SHIFT 0x03 +#define DA9055_NRES_MODE_MASK 0x08 +#define DA9055_SLEW_RATE_SHIFT 0x04 +#define DA9055_SLEW_RATE_MASK 0x30 +#define DA9055_NOKEY_LOCK_SHIFT 0x06 +#define DA9055_NOKEY_LOCK_MASK 0x40 + +/* DA9055_REG_CONTROL_B (addr=0xB) */ +#define DA9055_RTC_MODE_PD 0x01 +#define DA9055_RTC_MODE_SD_SHIFT 0x01 +#define DA9055_RTC_MODE_SD 0x02 +#define DA9055_RTC_EN 0x04 +#define DA9055_ECO_MODE_SHIFT 0x03 +#define DA9055_ECO_MODE_MASK 0x08 +#define DA9055_TWDSCALE_SHIFT 4 +#define DA9055_TWDSCALE_MASK 0x70 +#define DA9055_V_LOCK_SHIFT 0x07 +#define DA9055_V_LOCK_MASK 0x80 + +/* DA9055_REG_CONTROL_C (addr=0xC) */ +#define DA9055_SYSTEM_EN_SHIFT 0x00 +#define DA9055_SYSTEM_EN_MASK 0x01 +#define DA9055_POWERN_EN_SHIFT 0x01 +#define DA9055_POWERN_EN_MASK 0x02 +#define DA9055_POWER1_EN_SHIFT 0x02 +#define DA9055_POWER1_EN_MASK 0x04 + +/* DA9055_REG_CONTROL_D (addr=0xD) */ +#define DA9055_STANDBY_SHIFT 0x02 +#define DA9055_STANDBY_MASK 0x08 +#define DA9055_AUTO_BOOT_SHIFT 0x03 +#define DA9055_AUTO_BOOT_MASK 0x04 + +/* DA9055_REG_CONTROL_E (addr=0xE) */ +#define DA9055_WATCHDOG_SHIFT 0x00 +#define DA9055_WATCHDOG_MASK 0x01 +#define DA9055_SHUTDOWN_SHIFT 0x01 +#define DA9055_SHUTDOWN_MASK 0x02 +#define DA9055_WAKE_UP_SHIFT 0x02 +#define DA9055_WAKE_UP_MASK 0x04 + +/* DA9055_REG_GPIO (addr=0x10/0x11) */ +#define DA9055_GPIO0_PIN_SHIFT 0x00 +#define DA9055_GPIO0_PIN_MASK 0x03 +#define DA9055_GPIO0_TYPE_SHIFT 0x02 +#define DA9055_GPIO0_TYPE_MASK 0x04 +#define DA9055_GPIO0_WEN_SHIFT 0x03 +#define DA9055_GPIO0_WEN_MASK 0x08 +#define DA9055_GPIO1_PIN_SHIFT 0x04 +#define DA9055_GPIO1_PIN_MASK 0x30 +#define DA9055_GPIO1_TYPE_SHIFT 0x06 +#define DA9055_GPIO1_TYPE_MASK 0x40 +#define DA9055_GPIO1_WEN_SHIFT 0x07 +#define DA9055_GPIO1_WEN_MASK 0x80 +#define DA9055_GPIO2_PIN_SHIFT 0x00 +#define DA9055_GPIO2_PIN_MASK 0x30 +#define DA9055_GPIO2_TYPE_SHIFT 0x02 +#define DA9055_GPIO2_TYPE_MASK 0x04 +#define DA9055_GPIO2_WEN_SHIFT 0x03 +#define DA9055_GPIO2_WEN_MASK 0x08 + +/* DA9055_REG_GPIO_MODE (addr=0x12) */ +#define DA9055_GPIO0_MODE_SHIFT 0x00 +#define DA9055_GPIO0_MODE_MASK 0x01 +#define DA9055_GPIO1_MODE_SHIFT 0x01 +#define DA9055_GPIO1_MODE_MASK 0x02 +#define DA9055_GPIO2_MODE_SHIFT 0x02 +#define DA9055_GPIO2_MODE_MASK 0x04 + +/* DA9055_REG_BCORE_CONT (addr=0x13) */ +#define DA9055_BCORE_EN_SHIFT 0x00 +#define DA9055_BCORE_EN_MASK 0x01 +#define DA9055_BCORE_GPI_SHIFT 0x01 +#define DA9055_BCORE_GPI_MASK 0x02 +#define DA9055_BCORE_PD_DIS_SHIFT 0x03 +#define DA9055_BCORE_PD_DIS_MASK 0x04 +#define DA9055_VBCORE_SEL_SHIFT 0x04 +#define DA9055_SEL_REG_A 0x0 +#define DA9055_SEL_REG_B 0x10 +#define DA9055_VBCORE_SEL_MASK 0x10 +#define DA9055_V_GPI_MASK 0x60 +#define DA9055_V_GPI_SHIFT 0x05 +#define DA9055_E_GPI_MASK 0x06 +#define DA9055_E_GPI_SHIFT 0x01 +#define DA9055_VBCORE_GPI_SHIFT 0x05 +#define DA9055_VBCORE_GPI_MASK 0x60 +#define DA9055_BCORE_CONF_SHIFT 0x07 +#define DA9055_BCORE_CONF_MASK 0x80 + +/* DA9055_REG_BMEM_CONT (addr=0x14) */ +#define DA9055_BMEM_EN_SHIFT 0x00 +#define DA9055_BMEM_EN_MASK 0x01 +#define DA9055_BMEM_GPI_SHIFT 0x01 +#define DA9055_BMEM_GPI_MASK 0x06 +#define DA9055_BMEM_PD_DIS_SHIFT 0x03 +#define DA9055_BMEM_PD_DIS_MASK 0x08 +#define DA9055_VBMEM_SEL_SHIT 0x04 +#define DA9055_VBMEM_SEL_VBMEM_A (0<<4) +#define DA9055_VBMEM_SEL_VBMEM_B (1<<4) +#define DA9055_VBMEM_SEL_MASK 0x10 +#define DA9055_VBMEM_GPI_SHIFT 0x05 +#define DA9055_VBMEM_GPI_MASK 0x60 +#define DA9055_BMEM_CONF_SHIFT 0x07 +#define DA9055_BMEM_CONF_MASK 0x80 + +/* DA9055_REG_LDO_CONT (addr=0x15-0x1A) */ +#define DA9055_LDO_EN_SHIFT 0x00 +#define DA9055_LDO_EN_MASK 0x01 +#define DA9055_LDO_GPI_SHIFT 0x01 +#define DA9055_LDO_GPI_MASK 0x06 +#define DA9055_LDO_PD_DIS_SHIFT 0x03 +#define DA9055_LDO_PD_DIS_MASK 0x08 +#define DA9055_VLDO_SEL_SHIFT 0x04 +#define DA9055_VLDO_SEL_MASK 0x10 +#define DA9055_VLDO_SEL_VLDO_A 0x00 +#define DA9055_VLDO_SEL_VLDO_B 0x01 +#define DA9055_VLDO_GPI_SHIFT 0x05 +#define DA9055_VLDO_GPI_MASK 0x60 +#define DA9055_LDO_CONF_SHIFT 0x07 +#define DA9055_LDO_CONF_MASK 0x80 +#define DA9055_REGUALTOR_SET_A 0x00 +#define DA9055_REGUALTOR_SET_B 0x10 + +/* DA9055_REG_ADC_MAN (addr=0x1B) */ +#define DA9055_ADC_MUX_SHIFT 0 +#define DA9055_ADC_MUX_MASK 0xF +#define DA9055_ADC_MUX_VSYS 0x0 +#define DA9055_ADC_MUX_ADCIN1 0x01 +#define DA9055_ADC_MUX_ADCIN2 0x02 +#define DA9055_ADC_MUX_ADCIN3 0x03 +#define DA9055_ADC_MUX_T_SENSE 0x04 +#define DA9055_ADC_MAN_SHIFT 0x04 +#define DA9055_ADC_MAN_CONV 0x10 +#define DA9055_ADC_LSB_MASK 0X03 +#define DA9055_ADC_MODE_MASK 0x20 +#define DA9055_ADC_MODE_SHIFT 5 +#define DA9055_ADC_MODE_1MS (1<<5) +#define DA9055_COMP1V2_EN_SHIFT 7 + +/* DA9055_REG_ADC_CONT (addr=0x1C) */ +#define DA9055_ADC_AUTO_VSYS_EN_SHIFT 0 +#define DA9055_ADC_AUTO_AD1_EN_SHIFT 1 +#define DA9055_ADC_AUTO_AD2_EN_SHIFT 2 +#define DA9055_ADC_AUTO_AD3_EN_SHIFT 3 +#define DA9055_ADC_ISRC_EN_SHIFT 4 +#define DA9055_ADC_ADCIN1_DEB_SHIFT 5 +#define DA9055_ADC_ADCIN2_DEB_SHIFT 6 +#define DA9055_ADC_ADCIN3_DEB_SHIFT 7 +#define DA9055_AD1_ISRC_MASK 0x10 +#define DA9055_AD1_ISRC_SHIFT 4 + +/* DA9055_REG_VSYS_MON (addr=0x1D) */ +#define DA9055_VSYS_VAL_SHIFT 0 +#define DA9055_VSYS_VAL_MASK 0xFF +#define DA9055_VSYS_VAL_BASE 0x00 +#define DA9055_VSYS_VAL_MAX DA9055_VSYS_VAL_MASK +#define DA9055_VSYS_VOLT_BASE 2500 +#define DA9055_VSYS_VOLT_INC 10 +#define DA9055_VSYS_STEPS 255 +#define DA9055_VSYS_VOLT_MIN 2500 + +/* DA9044_REG_XXX_RES (addr=0x20-0x23) */ +#define DA9055_ADC_VAL_SHIFT 0 +#define DA9055_ADC_VAL_MASK 0xFF +#define DA9055_ADC_VAL_BASE 0x00 +#define DA9055_ADC_VAL_MAX DA9055_ADC_VAL_MASK +#define DA9055_ADC_VOLT_BASE 0 +#define DA9055_ADC_VSYS_VOLT_BASE 2500 +#define DA9055_ADC_VOLT_INC 10 +#define DA9055_ADC_VSYS_VOLT_INC 12 +#define DA9055_ADC_STEPS 255 + +/* DA9055_REG_EN_32K (addr=0x35)*/ +#define DA9055_STARTUP_TIME_MASK 0x07 +#define DA9055_STARTUP_TIME_0S 0x0 +#define DA9055_STARTUP_TIME_0_52S 0x1 +#define DA9055_STARTUP_TIME_1S 0x2 +#define DA9055_CRYSTAL_EN 0x08 +#define DA9055_DELAY_MODE_EN 0x10 +#define DA9055_OUT_CLCK_GATED 0x20 +#define DA9055_RTC_CLOCK_GATED 0x40 +#define DA9055_EN_32KOUT_BUF 0x80 + +/* DA9055_REG_RESET (addr=0x36) */ +/* Timer up to 31.744 ms */ +#define DA9055_RESET_TIMER_VAL_SHIFT 0 +#define DA9055_RESET_LOW_VAL_MASK 0x3F +#define DA9055_RESET_LOW_VAL_BASE 0 +#define DA9055_RESET_LOW_VAL_MAX DA9055_RESET_LOW_VAL_MASK +#define DA9055_RESET_US_LOW_BASE 1024 /* min val in units of us */ +#define DA9055_RESET_US_LOW_INC 1024 /* inc val in units of us */ +#define DA9055_RESET_US_LOW_STEP 30 + +/* Timer up to 1048.576ms */ +#define DA9055_RESET_HIGH_VAL_MASK 0x3F +#define DA9055_RESET_HIGH_VAL_BASE 0 +#define DA9055_RESET_HIGH_VAL_MAX DA9055_RESET_HIGH_VAL_MASK +#define DA9055_RESET_US_HIGH_BASE 32768 /* min val in units of us */ +#define DA9055_RESET_US_HIGH_INC 32768 /* inv val in units of us */ +#define DA9055_RESET_US_HIGH_STEP 31 + +/* DA9055_REG_BUCK_ILIM (addr=0x37)*/ +#define DA9055_BMEM_ILIM_SHIFT 0 +#define DA9055_ILIM_MASK 0x3 +#define DA9055_ILIM_500MA 0x0 +#define DA9055_ILIM_600MA 0x1 +#define DA9055_ILIM_700MA 0x2 +#define DA9055_ILIM_800MA 0x3 +#define DA9055_BCORE_ILIM_SHIFT 2 + +/* DA9055_REG_BCORE_MODE (addr=0x38) */ +#define DA9055_BMEM_MODE_SHIFT 0 +#define DA9055_MODE_MASK 0x3 +#define DA9055_MODE_AB 0x0 +#define DA9055_MODE_SLEEP 0x1 +#define DA9055_MODE_SYNCHRO 0x2 +#define DA9055_MODE_AUTO 0x3 +#define DA9055_BCORE_MODE_SHIFT 2 + +/* DA9055_REG_VBCORE_A/B (addr=0x39/0x41)*/ +#define DA9055_VBCORE_VAL_SHIFT 0 +#define DA9055_VBCORE_VAL_MASK 0x3F +#define DA9055_VBCORE_VAL_BASE 0x09 +#define DA9055_VBCORE_VAL_MAX DA9055_VBCORE_VAL_MASK +#define DA9055_VBCORE_VOLT_BASE 750 +#define DA9055_VBCORE_VOLT_INC 25 +#define DA9055_VBCORE_STEPS 53 +#define DA9055_VBCORE_VOLT_MIN DA9055_VBCORE_VOLT_BASE +#define DA9055_BCORE_SL_SYNCHRO (0<<7) +#define DA9055_BCORE_SL_SLEEP (1<<7) + +/* DA9055_REG_VBMEM_A/B (addr=0x3A/0x42)*/ +#define DA9055_VBMEM_VAL_SHIFT 0 +#define DA9055_VBMEM_VAL_MASK 0x3F +#define DA9055_VBMEM_VAL_BASE 0x00 +#define DA9055_VBMEM_VAL_MAX DA9055_VBMEM_VAL_MASK +#define DA9055_VBMEM_VOLT_BASE 925 +#define DA9055_VBMEM_VOLT_INC 25 +#define DA9055_VBMEM_STEPS 63 +#define DA9055_VBMEM_VOLT_MIN DA9055_VBMEM_VOLT_BASE +#define DA9055_BCMEM_SL_SYNCHRO (0<<7) +#define DA9055_BCMEM_SL_SLEEP (1<<7) + + +/* DA9055_REG_VLDO (addr=0x3B-0x40/0x43-0x48)*/ +#define DA9055_VLDO_VAL_SHIFT 0 +#define DA9055_VLDO_VAL_MASK 0x3F +#define DA9055_VLDO6_VAL_MASK 0x7F +#define DA9055_VLDO_VAL_BASE 0x02 +#define DA9055_VLDO2_VAL_BASE 0x03 +#define DA9055_VLDO6_VAL_BASE 0x00 +#define DA9055_VLDO_VAL_MAX DA9055_VLDO_VAL_MASK +#define DA9055_VLDO6_VAL_MAX DA9055_VLDO6_VAL_MASK +#define DA9055_VLDO_VOLT_BASE 900 +#define DA9055_VLDO_VOLT_INC 50 +#define DA9055_VLDO6_VOLT_INC 20 +#define DA9055_VLDO_STEPS 48 +#define DA9055_VLDO5_STEPS 37 +#define DA9055_VLDO6_STEPS 120 +#define DA9055_VLDO_VOLT_MIN DA9055_VLDO_VOLT_BASE +#define DA9055_LDO_MODE_SHIFT 7 +#define DA9055_LDO_SL_NORMAL 0 +#define DA9055_LDO_SL_SLEEP 1 + +/* DA9055_REG_OTP_CONT (addr=0x50) */ +#define DA9055_OTP_TIM_NORMAL (0<<0) +#define DA9055_OTP_TIM_MARGINAL (1<<0) +#define DA9055_OTP_GP_RD_SHIFT 1 +#define DA9055_OTP_APPS_RD_SHIFT 2 +#define DA9055_PC_DONE_SHIFT 3 +#define DA9055_OTP_GP_LOCK_SHIFT 4 +#define DA9055_OTP_APPS_LOCK_SHIFT 5 +#define DA9055_OTP_CONF_LOCK_SHIFT 6 +#define DA9055_OTP_WRITE_DIS_SHIFT 7 + +/* DA9055_REG_COUNT_S (addr=0x53) */ +#define DA9055_RTC_SEC 0x3F +#define DA9055_RTC_MONITOR_EN 0x40 +#define DA9055_RTC_READ 0x80 + +/* DA9055_REG_COUNT_MI (addr=0x54) */ +#define DA9055_RTC_MIN 0x3F + +/* DA9055_REG_COUNT_H (addr=0x55) */ +#define DA9055_RTC_HOUR 0x1F + +/* DA9055_REG_COUNT_D (addr=0x56) */ +#define DA9055_RTC_DAY 0x1F + +/* DA9055_REG_COUNT_MO (addr=0x57) */ +#define DA9055_RTC_MONTH 0x0F + +/* DA9055_REG_COUNT_Y (addr=0x58) */ +#define DA9055_RTC_YEAR 0x3F +#define DA9055_RTC_YEAR_BASE 2000 + +/* DA9055_REG_ALARM_MI (addr=0x59) */ +#define DA9055_RTC_ALM_MIN 0x3F +#define DA9055_ALARM_STATUS_SHIFT 6 +#define DA9055_ALARM_STATUS_MASK 0x3 +#define DA9055_ALARM_STATUS_NO_ALARM 0x0 +#define DA9055_ALARM_STATUS_TICK 0x1 +#define DA9055_ALARM_STATUS_TIMER_ALARM 0x2 +#define DA9055_ALARM_STATUS_BOTH 0x3 + +/* DA9055_REG_ALARM_H (addr=0x5A) */ +#define DA9055_RTC_ALM_HOUR 0x1F + +/* DA9055_REG_ALARM_D (addr=0x5B) */ +#define DA9055_RTC_ALM_DAY 0x1F + +/* DA9055_REG_ALARM_MO (addr=0x5C) */ +#define DA9055_RTC_ALM_MONTH 0x0F +#define DA9055_RTC_TICK_WAKE_MASK 0x20 +#define DA9055_RTC_TICK_WAKE_SHIFT 5 +#define DA9055_RTC_TICK_TYPE 0x10 +#define DA9055_RTC_TICK_TYPE_SHIFT 0x4 +#define DA9055_RTC_TICK_SEC 0x0 +#define DA9055_RTC_TICK_MIN 0x1 +#define DA9055_ALARAM_TICK_WAKE 0x20 + +/* DA9055_REG_ALARM_Y (addr=0x5D) */ +#define DA9055_RTC_TICK_EN 0x80 +#define DA9055_RTC_ALM_EN 0x40 +#define DA9055_RTC_TICK_ALM_MASK 0xC0 +#define DA9055_RTC_ALM_YEAR 0x3F + +/* DA9055_REG_TRIM_CLDR (addr=0x62) */ +#define DA9055_TRIM_32K_SHIFT 0 +#define DA9055_TRIM_32K_MASK 0x7F +#define DA9055_TRIM_DECREMENT (1<<7) +#define DA9055_TRIM_INCREMENT (0<<7) +#define DA9055_TRIM_VAL_BASE 0x0 +#define DA9055_TRIM_PPM_BASE 0x0 /* min val in units of 0.1PPM */ +#define DA9055_TRIM_PPM_INC 19 /* min inc in units of 0.1PPM */ +#define DA9055_TRIM_STEPS 127 + +/* DA9055_REG_CONFIG_A (addr=0x65) */ +#define DA9055_PM_I_V_VDDCORE (0<<0) +#define DA9055_PM_I_V_VDD_IO (1<<0) +#define DA9055_VDD_FAULT_TYPE_ACT_LOW (0<<1) +#define DA9055_VDD_FAULT_TYPE_ACT_HIGH (1<<1) +#define DA9055_PM_O_TYPE_PUSH_PULL (0<<2) +#define DA9055_PM_O_TYPE_OPEN_DRAIN (1<<2) +#define DA9055_IRQ_TYPE_ACT_LOW (0<<3) +#define DA9055_IRQ_TYPE_ACT_HIGH (1<<3) +#define DA9055_NIRQ_MODE_IMM (0<<4) +#define DA9055_NIRQ_MODE_ACTIVE (1<<4) +#define DA9055_GPI_V_VDDCORE (0<<5) +#define DA9055_GPI_V_VDD_IO (1<<5) +#define DA9055_PM_IF_V_VDDCORE (0<<6) +#define DA9055_PM_IF_V_VDD_IO (1<<6) + +/* DA9055_REG_CONFIG_B (addr=0x66) */ +#define DA9055_VDD_FAULT_VAL_SHIFT 0 +#define DA9055_VDD_FAULT_VAL_MASK 0xF +#define DA9055_VDD_FAULT_VAL_BASE 0x0 +#define DA9055_VDD_FAULT_VAL_MAX DA9055_VDD_FAULT_VAL_MASK +#define DA9055_VDD_FAULT_VOLT_BASE 2500 +#define DA9055_VDD_FAULT_VOLT_INC 50 +#define DA9055_VDD_FAULT_STEPS 15 + +#define DA9055_VDD_HYST_VAL_SHIFT 4 +#define DA9055_VDD_HYST_VAL_MASK 0x7 +#define DA9055_VDD_HYST_VAL_BASE 0x0 +#define DA9055_VDD_HYST_VAL_MAX DA9055_VDD_HYST_VAL_MASK +#define DA9055_VDD_HYST_VOLT_BASE 100 +#define DA9055_VDD_HYST_VOLT_INC 50 +#define DA9055_VDD_HYST_STEPS 7 +#define DA9055_VDD_HYST_VOLT_MIN DA9055_VDD_HYST_VOLT_BASE + +#define DA9055_VDD_FAULT_EN_SHIFT 7 + +/* DA9055_REG_CONFIG_C (addr=0x67) */ +#define DA9055_BCORE_CLK_INV_SHIFT 0 +#define DA9055_BMEM_CLK_INV_SHIFT 1 +#define DA9055_NFAULT_CONF_SHIFT 2 +#define DA9055_LDO_SD_SHIFT 4 +#define DA9055_LDO5_BYP_SHIFT 6 +#define DA9055_LDO6_BYP_SHIFT 7 + +/* DA9055_REG_CONFIG_D (addr=0x68) */ +#define DA9055_NONKEY_PIN_SHIFT 0 +#define DA9055_NONKEY_PIN_MASK 0x3 +#define DA9055_NONKEY_PIN_PORT_MODE 0x0 +#define DA9055_NONKEY_PIN_KEY_MODE 0x1 +#define DA9055_NONKEY_PIN_MULTI_FUNC 0x2 +#define DA9055_NONKEY_PIN_DEDICT 0x3 +#define DA9055_NONKEY_SD_SHIFT 2 +#define DA9055_KEY_DELAY_SHIFT 3 +#define DA9055_KEY_DELAY_MASK 0x3 +#define DA9055_KEY_DELAY_4S 0x0 +#define DA9055_KEY_DELAY_6S 0x1 +#define DA9055_KEY_DELAY_8S 0x2 +#define DA9055_KEY_DELAY_10S 0x3 + +/* DA9055_REG_CONFIG_E (addr=0x69) */ +#define DA9055_GPIO_PUPD_PULL_UP 0x0 +#define DA9055_GPIO_PUPD_OPEN_DRAIN 0x1 +#define DA9055_GPIO0_PUPD_SHIFT 0 +#define DA9055_GPIO1_PUPD_SHIFT 1 +#define DA9055_GPIO2_PUPD_SHIFT 2 +#define DA9055_UVOV_DELAY_SHIFT 4 +#define DA9055_UVOV_DELAY_MASK 0x3 +#define DA9055_RESET_DURATION_SHIFT 6 +#define DA9055_RESET_DURATION_MASK 0x3 +#define DA9055_RESET_DURATION_0MS 0x0 +#define DA9055_RESET_DURATION_100MS 0x1 +#define DA9055_RESET_DURATION_500MS 0x2 +#define DA9055_RESET_DURATION_1000MS 0x3 + +/* DA9055_REG_MON_REG_1 (addr=0x6A) */ +#define DA9055_MON_THRES_SHIFT 0 +#define DA9055_MON_THRES_MASK 0x3 +#define DA9055_MON_RES_SHIFT 2 +#define DA9055_MON_DEB_SHIFT 3 +#define DA9055_MON_MODE_SHIFT 4 +#define DA9055_MON_MODE_MASK 0x3 +#define DA9055_START_MAX_SHIFT 6 +#define DA9055_START_MAX_MASK 0x3 + +/* DA9055_REG_MON_REG_2 (addr=0x6B) */ +#define DA9055_LDO1_MON_EN_SHIFT 0 +#define DA9055_LDO2_MON_EN_SHIFT 1 +#define DA9055_LDO3_MON_EN_SHIFT 2 +#define DA9055_LDO4_MON_EN_SHIFT 3 +#define DA9055_LDO5_MON_EN_SHIFT 4 +#define DA9055_LDO6_MON_EN_SHIFT 5 +#define DA9055_BCORE_MON_EN_SHIFT 6 +#define DA9055_BMEM_MON_EN_SHIFT 7 + +/* DA9055_REG_CONFIG_F (addr=0x6C) */ +#define DA9055_LDO1_DEF_SHIFT 0 +#define DA9055_LDO2_DEF_SHIFT 1 +#define DA9055_LDO3_DEF_SHIFT 2 +#define DA9055_LDO4_DEF_SHIFT 3 +#define DA9055_LDO5_DEF_SHIFT 4 +#define DA9055_LDO6_DEF_SHIFT 5 +#define DA9055_BCORE_DEF_SHIFT 6 +#define DA9055_BMEM_DEF_SHIFT 7 + +/* DA9055_REG_MON_REG_4 (addr=0x6D) */ +#define DA9055_MON_A8_IDX_SHIFT 0 +#define DA9055_MON_A89_IDX_MASK 0x3 +#define DA9055_MON_A89_IDX_NONE 0x0 +#define DA9055_MON_A89_IDX_BUCKCORE 0x1 +#define DA9055_MON_A89_IDX_LDO3 0x2 +#define DA9055_MON_A9_IDX_SHIFT 5 + +/* DA9055_REG_MON_REG_5 (addr=0x6E) */ +#define DA9055_MON_A10_IDX_SHIFT 0 +#define DA9055_MON_A10_IDX_MASK 0x3 +#define DA9055_MON_A10_IDX_NONE 0x0 +#define DA9055_MON_A10_IDX_LDO1 0x1 +#define DA9055_MON_A10_IDX_LDO2 0x2 +#define DA9055_MON_A10_IDX_LDO5 0x3 +#define DA9055_MON_A10_IDX_LDO6 0x4 + +#endif /* __DA9055_REG_H */ diff --git a/include/linux/mfd/lp8788-isink.h b/include/linux/mfd/lp8788-isink.h new file mode 100644 index 000000000000..f38262d21ff1 --- /dev/null +++ b/include/linux/mfd/lp8788-isink.h @@ -0,0 +1,52 @@ +/* + * TI LP8788 MFD - common definitions for current sinks + * + * Copyright 2012 Texas Instruments + * + * Author: Milo(Woogyom) Kim <milo.kim@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __ISINK_LP8788_H__ +#define __ISINK_LP8788_H__ + +/* register address */ +#define LP8788_ISINK_CTRL 0x99 +#define LP8788_ISINK12_IOUT 0x9A +#define LP8788_ISINK3_IOUT 0x9B +#define LP8788_ISINK1_PWM 0x9C +#define LP8788_ISINK2_PWM 0x9D +#define LP8788_ISINK3_PWM 0x9E + +/* mask bits */ +#define LP8788_ISINK1_IOUT_M 0x0F /* Addr 9Ah */ +#define LP8788_ISINK2_IOUT_M 0xF0 +#define LP8788_ISINK3_IOUT_M 0x0F /* Addr 9Bh */ + +/* 6 bits used for PWM code : Addr 9C ~ 9Eh */ +#define LP8788_ISINK_MAX_PWM 63 +#define LP8788_ISINK_SCALE_OFFSET 3 + +static const u8 lp8788_iout_addr[] = { + LP8788_ISINK12_IOUT, + LP8788_ISINK12_IOUT, + LP8788_ISINK3_IOUT, +}; + +static const u8 lp8788_iout_mask[] = { + LP8788_ISINK1_IOUT_M, + LP8788_ISINK2_IOUT_M, + LP8788_ISINK3_IOUT_M, +}; + +static const u8 lp8788_pwm_addr[] = { + LP8788_ISINK1_PWM, + LP8788_ISINK2_PWM, + LP8788_ISINK3_PWM, +}; + +#endif diff --git a/include/linux/mfd/lp8788.h b/include/linux/mfd/lp8788.h new file mode 100644 index 000000000000..cec364bdccfa --- /dev/null +++ b/include/linux/mfd/lp8788.h @@ -0,0 +1,364 @@ +/* + * TI LP8788 MFD Device + * + * Copyright 2012 Texas Instruments + * + * Author: Milo(Woogyom) Kim <milo.kim@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __MFD_LP8788_H__ +#define __MFD_LP8788_H__ + +#include <linux/gpio.h> +#include <linux/irqdomain.h> +#include <linux/regmap.h> + +#define LP8788_DEV_BUCK "lp8788-buck" +#define LP8788_DEV_DLDO "lp8788-dldo" +#define LP8788_DEV_ALDO "lp8788-aldo" +#define LP8788_DEV_CHARGER "lp8788-charger" +#define LP8788_DEV_RTC "lp8788-rtc" +#define LP8788_DEV_BACKLIGHT "lp8788-backlight" +#define LP8788_DEV_VIBRATOR "lp8788-vibrator" +#define LP8788_DEV_KEYLED "lp8788-keyled" +#define LP8788_DEV_ADC "lp8788-adc" + +#define LP8788_NUM_BUCKS 4 +#define LP8788_NUM_DLDOS 12 +#define LP8788_NUM_ALDOS 10 +#define LP8788_NUM_BUCK2_DVS 2 + +#define LP8788_CHG_IRQ "CHG_IRQ" +#define LP8788_PRSW_IRQ "PRSW_IRQ" +#define LP8788_BATT_IRQ "BATT_IRQ" +#define LP8788_ALM_IRQ "ALARM_IRQ" + +enum lp8788_int_id { + /* interrup register 1 : Addr 00h */ + LP8788_INT_TSDL, + LP8788_INT_TSDH, + LP8788_INT_UVLO, + LP8788_INT_FLAGMON, + LP8788_INT_PWRON_TIME, + LP8788_INT_PWRON, + LP8788_INT_COMP1, + LP8788_INT_COMP2, + + /* interrupt register 2 : Addr 01h */ + LP8788_INT_CHG_INPUT_STATE, + LP8788_INT_CHG_STATE, + LP8788_INT_EOC, + LP8788_INT_CHG_RESTART, + LP8788_INT_RESTART_TIMEOUT, + LP8788_INT_FULLCHG_TIMEOUT, + LP8788_INT_PRECHG_TIMEOUT, + + /* interrupt register 3 : Addr 02h */ + LP8788_INT_RTC_ALARM1 = 17, + LP8788_INT_RTC_ALARM2, + LP8788_INT_ENTER_SYS_SUPPORT, + LP8788_INT_EXIT_SYS_SUPPORT, + LP8788_INT_BATT_LOW, + LP8788_INT_NO_BATT, + + LP8788_INT_MAX = 24, +}; + +enum lp8788_dvs_sel { + DVS_SEL_V0, + DVS_SEL_V1, + DVS_SEL_V2, + DVS_SEL_V3, +}; + +enum lp8788_ext_ldo_en_id { + EN_ALDO1, + EN_ALDO234, + EN_ALDO5, + EN_ALDO7, + EN_DLDO7, + EN_DLDO911, + EN_LDOS_MAX, +}; + +enum lp8788_charger_event { + NO_CHARGER, + CHARGER_DETECTED, +}; + +enum lp8788_bl_ctrl_mode { + LP8788_BL_REGISTER_ONLY, + LP8788_BL_COMB_PWM_BASED, /* PWM + I2C, changed by PWM input */ + LP8788_BL_COMB_REGISTER_BASED, /* PWM + I2C, changed by I2C */ +}; + +enum lp8788_bl_dim_mode { + LP8788_DIM_EXPONENTIAL, + LP8788_DIM_LINEAR, +}; + +enum lp8788_bl_full_scale_current { + LP8788_FULLSCALE_5000uA, + LP8788_FULLSCALE_8500uA, + LP8788_FULLSCALE_1200uA, + LP8788_FULLSCALE_1550uA, + LP8788_FULLSCALE_1900uA, + LP8788_FULLSCALE_2250uA, + LP8788_FULLSCALE_2600uA, + LP8788_FULLSCALE_2950uA, +}; + +enum lp8788_bl_ramp_step { + LP8788_RAMP_8us, + LP8788_RAMP_1024us, + LP8788_RAMP_2048us, + LP8788_RAMP_4096us, + LP8788_RAMP_8192us, + LP8788_RAMP_16384us, + LP8788_RAMP_32768us, + LP8788_RAMP_65538us, +}; + +enum lp8788_bl_pwm_polarity { + LP8788_PWM_ACTIVE_HIGH, + LP8788_PWM_ACTIVE_LOW, +}; + +enum lp8788_isink_scale { + LP8788_ISINK_SCALE_100mA, + LP8788_ISINK_SCALE_120mA, +}; + +enum lp8788_isink_number { + LP8788_ISINK_1, + LP8788_ISINK_2, + LP8788_ISINK_3, +}; + +enum lp8788_alarm_sel { + LP8788_ALARM_1, + LP8788_ALARM_2, + LP8788_ALARM_MAX, +}; + +enum lp8788_adc_id { + LPADC_VBATT_5P5, + LPADC_VIN_CHG, + LPADC_IBATT, + LPADC_IC_TEMP, + LPADC_VBATT_6P0, + LPADC_VBATT_5P0, + LPADC_ADC1, + LPADC_ADC2, + LPADC_VDD, + LPADC_VCOIN, + LPADC_VDD_LDO, + LPADC_ADC3, + LPADC_ADC4, + LPADC_MAX, +}; + +struct lp8788; + +/* + * lp8788_buck1_dvs + * @gpio : gpio pin number for dvs control + * @vsel : dvs selector for buck v1 register + */ +struct lp8788_buck1_dvs { + int gpio; + enum lp8788_dvs_sel vsel; +}; + +/* + * lp8788_buck2_dvs + * @gpio : two gpio pin numbers are used for dvs + * @vsel : dvs selector for buck v2 register + */ +struct lp8788_buck2_dvs { + int gpio[LP8788_NUM_BUCK2_DVS]; + enum lp8788_dvs_sel vsel; +}; + +/* + * struct lp8788_ldo_enable_pin + * + * Basically, all LDOs are enabled through the I2C commands. + * But ALDO 1 ~ 5, 7, DLDO 7, 9, 11 can be enabled by external gpio pins. + * + * @gpio : gpio number which is used for enabling ldos + * @init_state : initial gpio state (ex. GPIOF_OUT_INIT_LOW) + */ +struct lp8788_ldo_enable_pin { + int gpio; + int init_state; +}; + +/* + * struct lp8788_chg_param + * @addr : charging control register address (range : 0x11 ~ 0x1C) + * @val : charging parameter value + */ +struct lp8788_chg_param { + u8 addr; + u8 val; +}; + +/* + * struct lp8788_charger_platform_data + * @vbatt_adc : adc selection id for battery voltage + * @batt_temp_adc : adc selection id for battery temperature + * @max_vbatt_mv : used for calculating battery capacity + * @chg_params : initial charging parameters + * @num_chg_params : numbers of charging parameters + * @charger_event : the charger event can be reported to the platform side + */ +struct lp8788_charger_platform_data { + enum lp8788_adc_id vbatt_adc; + enum lp8788_adc_id batt_temp_adc; + unsigned int max_vbatt_mv; + struct lp8788_chg_param *chg_params; + int num_chg_params; + void (*charger_event) (struct lp8788 *lp, + enum lp8788_charger_event event); +}; + +/* + * struct lp8788_bl_pwm_data + * @pwm_set_intensity : set duty of pwm + * @pwm_get_intensity : get current duty of pwm + */ +struct lp8788_bl_pwm_data { + void (*pwm_set_intensity) (int brightness, int max_brightness); + int (*pwm_get_intensity) (int max_brightness); +}; + +/* + * struct lp8788_backlight_platform_data + * @name : backlight driver name. (default: "lcd-backlight") + * @initial_brightness : initial value of backlight brightness + * @bl_mode : brightness control by pwm or lp8788 register + * @dim_mode : dimming mode selection + * @full_scale : full scale current setting + * @rise_time : brightness ramp up step time + * @fall_time : brightness ramp down step time + * @pwm_pol : pwm polarity setting when bl_mode is pwm based + * @pwm_data : platform specific pwm generation functions + * only valid when bl_mode is pwm based + */ +struct lp8788_backlight_platform_data { + char *name; + int initial_brightness; + enum lp8788_bl_ctrl_mode bl_mode; + enum lp8788_bl_dim_mode dim_mode; + enum lp8788_bl_full_scale_current full_scale; + enum lp8788_bl_ramp_step rise_time; + enum lp8788_bl_ramp_step fall_time; + enum lp8788_bl_pwm_polarity pwm_pol; + struct lp8788_bl_pwm_data pwm_data; +}; + +/* + * struct lp8788_led_platform_data + * @name : led driver name. (default: "keyboard-backlight") + * @scale : current scale + * @num : current sink number + * @iout_code : current output value (Addr 9Ah ~ 9Bh) + */ +struct lp8788_led_platform_data { + char *name; + enum lp8788_isink_scale scale; + enum lp8788_isink_number num; + int iout_code; +}; + +/* + * struct lp8788_vib_platform_data + * @name : vibrator driver name + * @scale : current scale + * @num : current sink number + * @iout_code : current output value (Addr 9Ah ~ 9Bh) + * @pwm_code : PWM code value (Addr 9Ch ~ 9Eh) + */ +struct lp8788_vib_platform_data { + char *name; + enum lp8788_isink_scale scale; + enum lp8788_isink_number num; + int iout_code; + int pwm_code; +}; + +/* + * struct lp8788_platform_data + * @init_func : used for initializing registers + * before mfd driver is registered + * @buck_data : regulator initial data for buck + * @dldo_data : regulator initial data for digital ldo + * @aldo_data : regulator initial data for analog ldo + * @buck1_dvs : gpio configurations for buck1 dvs + * @buck2_dvs : gpio configurations for buck2 dvs + * @ldo_pin : gpio configurations for enabling LDOs + * @chg_pdata : platform data for charger driver + * @alarm_sel : rtc alarm selection (1 or 2) + * @bl_pdata : configurable data for backlight driver + * @led_pdata : configurable data for led driver + * @vib_pdata : configurable data for vibrator driver + * @adc_pdata : iio map data for adc driver + */ +struct lp8788_platform_data { + /* general system information */ + int (*init_func) (struct lp8788 *lp); + + /* regulators */ + struct regulator_init_data *buck_data[LP8788_NUM_BUCKS]; + struct regulator_init_data *dldo_data[LP8788_NUM_DLDOS]; + struct regulator_init_data *aldo_data[LP8788_NUM_ALDOS]; + struct lp8788_buck1_dvs *buck1_dvs; + struct lp8788_buck2_dvs *buck2_dvs; + struct lp8788_ldo_enable_pin *ldo_pin[EN_LDOS_MAX]; + + /* charger */ + struct lp8788_charger_platform_data *chg_pdata; + + /* rtc alarm */ + enum lp8788_alarm_sel alarm_sel; + + /* backlight */ + struct lp8788_backlight_platform_data *bl_pdata; + + /* current sinks */ + struct lp8788_led_platform_data *led_pdata; + struct lp8788_vib_platform_data *vib_pdata; + + /* adc iio map data */ + struct iio_map *adc_pdata; +}; + +/* + * struct lp8788 + * @dev : parent device pointer + * @regmap : used for i2c communcation on accessing registers + * @irqdm : interrupt domain for handling nested interrupt + * @irq : pin number of IRQ_N + * @pdata : lp8788 platform specific data + */ +struct lp8788 { + struct device *dev; + struct regmap *regmap; + struct irq_domain *irqdm; + int irq; + struct lp8788_platform_data *pdata; +}; + +int lp8788_irq_init(struct lp8788 *lp, int chip_irq); +void lp8788_irq_exit(struct lp8788 *lp); +int lp8788_read_byte(struct lp8788 *lp, u8 reg, u8 *data); +int lp8788_read_multi_bytes(struct lp8788 *lp, u8 reg, u8 *data, size_t count); +int lp8788_write_byte(struct lp8788 *lp, u8 reg, u8 data); +int lp8788_update_bits(struct lp8788 *lp, u8 reg, u8 mask, u8 data); +#endif diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h index fec5256c3f5d..3e1df644c407 100644 --- a/include/linux/mfd/lpc_ich.h +++ b/include/linux/mfd/lpc_ich.h @@ -43,6 +43,7 @@ struct lpc_ich_info { char name[32]; unsigned int iTCO_version; unsigned int gpio_version; + u8 use_gpio; }; #endif diff --git a/include/linux/mfd/max8907.h b/include/linux/mfd/max8907.h new file mode 100644 index 000000000000..b06f7a6a1e80 --- /dev/null +++ b/include/linux/mfd/max8907.h @@ -0,0 +1,252 @@ +/* + * Functions to access MAX8907 power management chip. + * + * Copyright (C) 2010 Gyungoh Yoo <jack.yoo@maxim-ic.com> + * Copyright (C) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_MFD_MAX8907_H +#define __LINUX_MFD_MAX8907_H + +#include <linux/mutex.h> +#include <linux/pm.h> + +#define MAX8907_GEN_I2C_ADDR (0x78 >> 1) +#define MAX8907_ADC_I2C_ADDR (0x8e >> 1) +#define MAX8907_RTC_I2C_ADDR (0xd0 >> 1) + +/* MAX8907 register map */ +#define MAX8907_REG_SYSENSEL 0x00 +#define MAX8907_REG_ON_OFF_IRQ1 0x01 +#define MAX8907_REG_ON_OFF_IRQ1_MASK 0x02 +#define MAX8907_REG_ON_OFF_STAT 0x03 +#define MAX8907_REG_SDCTL1 0x04 +#define MAX8907_REG_SDSEQCNT1 0x05 +#define MAX8907_REG_SDV1 0x06 +#define MAX8907_REG_SDCTL2 0x07 +#define MAX8907_REG_SDSEQCNT2 0x08 +#define MAX8907_REG_SDV2 0x09 +#define MAX8907_REG_SDCTL3 0x0A +#define MAX8907_REG_SDSEQCNT3 0x0B +#define MAX8907_REG_SDV3 0x0C +#define MAX8907_REG_ON_OFF_IRQ2 0x0D +#define MAX8907_REG_ON_OFF_IRQ2_MASK 0x0E +#define MAX8907_REG_RESET_CNFG 0x0F +#define MAX8907_REG_LDOCTL16 0x10 +#define MAX8907_REG_LDOSEQCNT16 0x11 +#define MAX8907_REG_LDO16VOUT 0x12 +#define MAX8907_REG_SDBYSEQCNT 0x13 +#define MAX8907_REG_LDOCTL17 0x14 +#define MAX8907_REG_LDOSEQCNT17 0x15 +#define MAX8907_REG_LDO17VOUT 0x16 +#define MAX8907_REG_LDOCTL1 0x18 +#define MAX8907_REG_LDOSEQCNT1 0x19 +#define MAX8907_REG_LDO1VOUT 0x1A +#define MAX8907_REG_LDOCTL2 0x1C +#define MAX8907_REG_LDOSEQCNT2 0x1D +#define MAX8907_REG_LDO2VOUT 0x1E +#define MAX8907_REG_LDOCTL3 0x20 +#define MAX8907_REG_LDOSEQCNT3 0x21 +#define MAX8907_REG_LDO3VOUT 0x22 +#define MAX8907_REG_LDOCTL4 0x24 +#define MAX8907_REG_LDOSEQCNT4 0x25 +#define MAX8907_REG_LDO4VOUT 0x26 +#define MAX8907_REG_LDOCTL5 0x28 +#define MAX8907_REG_LDOSEQCNT5 0x29 +#define MAX8907_REG_LDO5VOUT 0x2A +#define MAX8907_REG_LDOCTL6 0x2C +#define MAX8907_REG_LDOSEQCNT6 0x2D +#define MAX8907_REG_LDO6VOUT 0x2E +#define MAX8907_REG_LDOCTL7 0x30 +#define MAX8907_REG_LDOSEQCNT7 0x31 +#define MAX8907_REG_LDO7VOUT 0x32 +#define MAX8907_REG_LDOCTL8 0x34 +#define MAX8907_REG_LDOSEQCNT8 0x35 +#define MAX8907_REG_LDO8VOUT 0x36 +#define MAX8907_REG_LDOCTL9 0x38 +#define MAX8907_REG_LDOSEQCNT9 0x39 +#define MAX8907_REG_LDO9VOUT 0x3A +#define MAX8907_REG_LDOCTL10 0x3C +#define MAX8907_REG_LDOSEQCNT10 0x3D +#define MAX8907_REG_LDO10VOUT 0x3E +#define MAX8907_REG_LDOCTL11 0x40 +#define MAX8907_REG_LDOSEQCNT11 0x41 +#define MAX8907_REG_LDO11VOUT 0x42 +#define MAX8907_REG_LDOCTL12 0x44 +#define MAX8907_REG_LDOSEQCNT12 0x45 +#define MAX8907_REG_LDO12VOUT 0x46 +#define MAX8907_REG_LDOCTL13 0x48 +#define MAX8907_REG_LDOSEQCNT13 0x49 +#define MAX8907_REG_LDO13VOUT 0x4A +#define MAX8907_REG_LDOCTL14 0x4C +#define MAX8907_REG_LDOSEQCNT14 0x4D +#define MAX8907_REG_LDO14VOUT 0x4E +#define MAX8907_REG_LDOCTL15 0x50 +#define MAX8907_REG_LDOSEQCNT15 0x51 +#define MAX8907_REG_LDO15VOUT 0x52 +#define MAX8907_REG_OUT5VEN 0x54 +#define MAX8907_REG_OUT5VSEQ 0x55 +#define MAX8907_REG_OUT33VEN 0x58 +#define MAX8907_REG_OUT33VSEQ 0x59 +#define MAX8907_REG_LDOCTL19 0x5C +#define MAX8907_REG_LDOSEQCNT19 0x5D +#define MAX8907_REG_LDO19VOUT 0x5E +#define MAX8907_REG_LBCNFG 0x60 +#define MAX8907_REG_SEQ1CNFG 0x64 +#define MAX8907_REG_SEQ2CNFG 0x65 +#define MAX8907_REG_SEQ3CNFG 0x66 +#define MAX8907_REG_SEQ4CNFG 0x67 +#define MAX8907_REG_SEQ5CNFG 0x68 +#define MAX8907_REG_SEQ6CNFG 0x69 +#define MAX8907_REG_SEQ7CNFG 0x6A +#define MAX8907_REG_LDOCTL18 0x72 +#define MAX8907_REG_LDOSEQCNT18 0x73 +#define MAX8907_REG_LDO18VOUT 0x74 +#define MAX8907_REG_BBAT_CNFG 0x78 +#define MAX8907_REG_CHG_CNTL1 0x7C +#define MAX8907_REG_CHG_CNTL2 0x7D +#define MAX8907_REG_CHG_IRQ1 0x7E +#define MAX8907_REG_CHG_IRQ2 0x7F +#define MAX8907_REG_CHG_IRQ1_MASK 0x80 +#define MAX8907_REG_CHG_IRQ2_MASK 0x81 +#define MAX8907_REG_CHG_STAT 0x82 +#define MAX8907_REG_WLED_MODE_CNTL 0x84 +#define MAX8907_REG_ILED_CNTL 0x84 +#define MAX8907_REG_II1RR 0x8E +#define MAX8907_REG_II2RR 0x8F +#define MAX8907_REG_LDOCTL20 0x9C +#define MAX8907_REG_LDOSEQCNT20 0x9D +#define MAX8907_REG_LDO20VOUT 0x9E + +/* RTC register map */ +#define MAX8907_REG_RTC_SEC 0x00 +#define MAX8907_REG_RTC_MIN 0x01 +#define MAX8907_REG_RTC_HOURS 0x02 +#define MAX8907_REG_RTC_WEEKDAY 0x03 +#define MAX8907_REG_RTC_DATE 0x04 +#define MAX8907_REG_RTC_MONTH 0x05 +#define MAX8907_REG_RTC_YEAR1 0x06 +#define MAX8907_REG_RTC_YEAR2 0x07 +#define MAX8907_REG_ALARM0_SEC 0x08 +#define MAX8907_REG_ALARM0_MIN 0x09 +#define MAX8907_REG_ALARM0_HOURS 0x0A +#define MAX8907_REG_ALARM0_WEEKDAY 0x0B +#define MAX8907_REG_ALARM0_DATE 0x0C +#define MAX8907_REG_ALARM0_MONTH 0x0D +#define MAX8907_REG_ALARM0_YEAR1 0x0E +#define MAX8907_REG_ALARM0_YEAR2 0x0F +#define MAX8907_REG_ALARM1_SEC 0x10 +#define MAX8907_REG_ALARM1_MIN 0x11 +#define MAX8907_REG_ALARM1_HOURS 0x12 +#define MAX8907_REG_ALARM1_WEEKDAY 0x13 +#define MAX8907_REG_ALARM1_DATE 0x14 +#define MAX8907_REG_ALARM1_MONTH 0x15 +#define MAX8907_REG_ALARM1_YEAR1 0x16 +#define MAX8907_REG_ALARM1_YEAR2 0x17 +#define MAX8907_REG_ALARM0_CNTL 0x18 +#define MAX8907_REG_ALARM1_CNTL 0x19 +#define MAX8907_REG_RTC_STATUS 0x1A +#define MAX8907_REG_RTC_CNTL 0x1B +#define MAX8907_REG_RTC_IRQ 0x1C +#define MAX8907_REG_RTC_IRQ_MASK 0x1D +#define MAX8907_REG_MPL_CNTL 0x1E + +/* ADC and Touch Screen Controller register map */ +#define MAX8907_CTL 0 +#define MAX8907_SEQCNT 1 +#define MAX8907_VOUT 2 + +/* mask bit fields */ +#define MAX8907_MASK_LDO_SEQ 0x1C +#define MAX8907_MASK_LDO_EN 0x01 +#define MAX8907_MASK_VBBATTCV 0x03 +#define MAX8907_MASK_OUT5V_VINEN 0x10 +#define MAX8907_MASK_OUT5V_ENSRC 0x0E +#define MAX8907_MASK_OUT5V_EN 0x01 +#define MAX8907_MASK_POWER_OFF 0x40 + +/* Regulator IDs */ +#define MAX8907_MBATT 0 +#define MAX8907_SD1 1 +#define MAX8907_SD2 2 +#define MAX8907_SD3 3 +#define MAX8907_LDO1 4 +#define MAX8907_LDO2 5 +#define MAX8907_LDO3 6 +#define MAX8907_LDO4 7 +#define MAX8907_LDO5 8 +#define MAX8907_LDO6 9 +#define MAX8907_LDO7 10 +#define MAX8907_LDO8 11 +#define MAX8907_LDO9 12 +#define MAX8907_LDO10 13 +#define MAX8907_LDO11 14 +#define MAX8907_LDO12 15 +#define MAX8907_LDO13 16 +#define MAX8907_LDO14 17 +#define MAX8907_LDO15 18 +#define MAX8907_LDO16 19 +#define MAX8907_LDO17 20 +#define MAX8907_LDO18 21 +#define MAX8907_LDO19 22 +#define MAX8907_LDO20 23 +#define MAX8907_OUT5V 24 +#define MAX8907_OUT33V 25 +#define MAX8907_BBAT 26 +#define MAX8907_SDBY 27 +#define MAX8907_VRTC 28 +#define MAX8907_NUM_REGULATORS (MAX8907_VRTC + 1) + +/* IRQ definitions */ +enum { + MAX8907_IRQ_VCHG_DC_OVP = 0, + MAX8907_IRQ_VCHG_DC_F, + MAX8907_IRQ_VCHG_DC_R, + MAX8907_IRQ_VCHG_THM_OK_R, + MAX8907_IRQ_VCHG_THM_OK_F, + MAX8907_IRQ_VCHG_MBATTLOW_F, + MAX8907_IRQ_VCHG_MBATTLOW_R, + MAX8907_IRQ_VCHG_RST, + MAX8907_IRQ_VCHG_DONE, + MAX8907_IRQ_VCHG_TOPOFF, + MAX8907_IRQ_VCHG_TMR_FAULT, + + MAX8907_IRQ_GPM_RSTIN = 0, + MAX8907_IRQ_GPM_MPL, + MAX8907_IRQ_GPM_SW_3SEC, + MAX8907_IRQ_GPM_EXTON_F, + MAX8907_IRQ_GPM_EXTON_R, + MAX8907_IRQ_GPM_SW_1SEC, + MAX8907_IRQ_GPM_SW_F, + MAX8907_IRQ_GPM_SW_R, + MAX8907_IRQ_GPM_SYSCKEN_F, + MAX8907_IRQ_GPM_SYSCKEN_R, + + MAX8907_IRQ_RTC_ALARM1 = 0, + MAX8907_IRQ_RTC_ALARM0, +}; + +struct max8907_platform_data { + struct regulator_init_data *init_data[MAX8907_NUM_REGULATORS]; + bool pm_off; +}; + +struct regmap_irq_chips_data; + +struct max8907 { + struct device *dev; + struct mutex irq_lock; + struct i2c_client *i2c_gen; + struct i2c_client *i2c_rtc; + struct regmap *regmap_gen; + struct regmap *regmap_rtc; + struct regmap_irq_chip_data *irqc_chg; + struct regmap_irq_chip_data *irqc_on_off; + struct regmap_irq_chip_data *irqc_rtc; +}; + +#endif diff --git a/include/linux/mfd/max8925.h b/include/linux/mfd/max8925.h index 15b2392a56fb..74d8e2969630 100644 --- a/include/linux/mfd/max8925.h +++ b/include/linux/mfd/max8925.h @@ -158,8 +158,6 @@ enum { #define TSC_IRQ_MASK (0x03) #define RTC_IRQ_MASK (0x0c) -#define MAX8925_MAX_REGULATOR (23) - #define MAX8925_NAME_SIZE (32) /* IRQ definitions */ @@ -236,7 +234,29 @@ struct max8925_platform_data { struct max8925_backlight_pdata *backlight; struct max8925_touch_pdata *touch; struct max8925_power_pdata *power; - struct regulator_init_data *regulator[MAX8925_MAX_REGULATOR]; + struct regulator_init_data *sd1; + struct regulator_init_data *sd2; + struct regulator_init_data *sd3; + struct regulator_init_data *ldo1; + struct regulator_init_data *ldo2; + struct regulator_init_data *ldo3; + struct regulator_init_data *ldo4; + struct regulator_init_data *ldo5; + struct regulator_init_data *ldo6; + struct regulator_init_data *ldo7; + struct regulator_init_data *ldo8; + struct regulator_init_data *ldo9; + struct regulator_init_data *ldo10; + struct regulator_init_data *ldo11; + struct regulator_init_data *ldo12; + struct regulator_init_data *ldo13; + struct regulator_init_data *ldo14; + struct regulator_init_data *ldo15; + struct regulator_init_data *ldo16; + struct regulator_init_data *ldo17; + struct regulator_init_data *ldo18; + struct regulator_init_data *ldo19; + struct regulator_init_data *ldo20; int irq_base; int tsc_irq; diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h index 9cbc642d40ad..29f6616e12f0 100644 --- a/include/linux/mfd/palmas.h +++ b/include/linux/mfd/palmas.h @@ -23,6 +23,9 @@ #define PALMAS_NUM_CLIENTS 3 struct palmas_pmic; +struct palmas_gpadc; +struct palmas_resource; +struct palmas_usb; struct palmas { struct device *dev; @@ -41,6 +44,9 @@ struct palmas { /* Child Devices */ struct palmas_pmic *pmic; + struct palmas_gpadc *gpadc; + struct palmas_resource *resource; + struct palmas_usb *usb; /* GPIO MUXing */ u8 gpio_muxed; @@ -48,6 +54,23 @@ struct palmas { u8 pwm_muxed; }; +struct palmas_gpadc_platform_data { + /* Channel 3 current source is only enabled during conversion */ + int ch3_current; + + /* Channel 0 current source can be used for battery detection. + * If used for battery detection this will cause a permanent current + * consumption depending on current level set here. + */ + int ch0_current; + + /* default BAT_REMOVAL_DAT setting on device probe */ + int bat_removal; + + /* Sets the START_POLARITY bit in the RT_CTRL register */ + int start_polarity; +}; + struct palmas_reg_init { /* warm_rest controls the voltage levels after a warm reset * @@ -107,21 +130,94 @@ struct palmas_reg_init { }; +enum palmas_regulators { + /* SMPS regulators */ + PALMAS_REG_SMPS12, + PALMAS_REG_SMPS123, + PALMAS_REG_SMPS3, + PALMAS_REG_SMPS45, + PALMAS_REG_SMPS457, + PALMAS_REG_SMPS6, + PALMAS_REG_SMPS7, + PALMAS_REG_SMPS8, + PALMAS_REG_SMPS9, + PALMAS_REG_SMPS10, + /* LDO regulators */ + PALMAS_REG_LDO1, + PALMAS_REG_LDO2, + PALMAS_REG_LDO3, + PALMAS_REG_LDO4, + PALMAS_REG_LDO5, + PALMAS_REG_LDO6, + PALMAS_REG_LDO7, + PALMAS_REG_LDO8, + PALMAS_REG_LDO9, + PALMAS_REG_LDOLN, + PALMAS_REG_LDOUSB, + /* Total number of regulators */ + PALMAS_NUM_REGS, +}; + struct palmas_pmic_platform_data { /* An array of pointers to regulator init data indexed by regulator * ID */ - struct regulator_init_data **reg_data; + struct regulator_init_data *reg_data[PALMAS_NUM_REGS]; /* An array of pointers to structures containing sleep mode and DVS * configuration for regulators indexed by ID */ - struct palmas_reg_init **reg_init; + struct palmas_reg_init *reg_init[PALMAS_NUM_REGS]; /* use LDO6 for vibrator control */ int ldo6_vibrator; +}; +struct palmas_usb_platform_data { + /* Set this if platform wishes its own vbus control */ + int no_control_vbus; + /* Do we enable the wakeup comparator on probe */ + int wakeup; +}; + +struct palmas_resource_platform_data { + int regen1_mode_sleep; + int regen2_mode_sleep; + int sysen1_mode_sleep; + int sysen2_mode_sleep; + + /* bitfield to be loaded to NSLEEP_RES_ASSIGN */ + u8 nsleep_res; + /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */ + u8 nsleep_smps; + /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */ + u8 nsleep_ldo1; + /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */ + u8 nsleep_ldo2; + + /* bitfield to be loaded to ENABLE1_RES_ASSIGN */ + u8 enable1_res; + /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */ + u8 enable1_smps; + /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */ + u8 enable1_ldo1; + /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */ + u8 enable1_ldo2; + + /* bitfield to be loaded to ENABLE2_RES_ASSIGN */ + u8 enable2_res; + /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */ + u8 enable2_smps; + /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */ + u8 enable2_ldo1; + /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */ + u8 enable2_ldo2; +}; + +struct palmas_clk_platform_data { + int clk32kg_mode_sleep; + int clk32kgaudio_mode_sleep; }; struct palmas_platform_data { @@ -138,8 +234,49 @@ struct palmas_platform_data { u8 pad1, pad2; struct palmas_pmic_platform_data *pmic_pdata; + struct palmas_gpadc_platform_data *gpadc_pdata; + struct palmas_usb_platform_data *usb_pdata; + struct palmas_resource_platform_data *resource_pdata; + struct palmas_clk_platform_data *clk_pdata; +}; + +struct palmas_gpadc_calibration { + s32 gain; + s32 gain_error; + s32 offset_error; }; +struct palmas_gpadc { + struct device *dev; + struct palmas *palmas; + + int ch3_current; + int ch0_current; + + int gpadc_force; + + int bat_removal; + + struct mutex reading_lock; + struct completion irq_complete; + + int eoc_sw_irq; + + struct palmas_gpadc_calibration *palmas_cal_tbl; + + int conv0_channel; + int conv1_channel; + int rt_channel; +}; + +struct palmas_gpadc_result { + s32 raw_code; + s32 corrected_code; + s32 result; +}; + +#define PALMAS_MAX_CHANNELS 16 + /* Define the palmas IRQ numbers */ enum palmas_irqs { /* INT1 registers */ @@ -182,34 +319,6 @@ enum palmas_irqs { PALMAS_NUM_IRQ, }; -enum palmas_regulators { - /* SMPS regulators */ - PALMAS_REG_SMPS12, - PALMAS_REG_SMPS123, - PALMAS_REG_SMPS3, - PALMAS_REG_SMPS45, - PALMAS_REG_SMPS457, - PALMAS_REG_SMPS6, - PALMAS_REG_SMPS7, - PALMAS_REG_SMPS8, - PALMAS_REG_SMPS9, - PALMAS_REG_SMPS10, - /* LDO regulators */ - PALMAS_REG_LDO1, - PALMAS_REG_LDO2, - PALMAS_REG_LDO3, - PALMAS_REG_LDO4, - PALMAS_REG_LDO5, - PALMAS_REG_LDO6, - PALMAS_REG_LDO7, - PALMAS_REG_LDO8, - PALMAS_REG_LDO9, - PALMAS_REG_LDOLN, - PALMAS_REG_LDOUSB, - /* Total number of regulators */ - PALMAS_NUM_REGS, -}; - struct palmas_pmic { struct palmas *palmas; struct device *dev; @@ -223,6 +332,69 @@ struct palmas_pmic { int range[PALMAS_REG_SMPS10]; }; +struct palmas_resource { + struct palmas *palmas; + struct device *dev; +}; + +struct palmas_usb { + struct palmas *palmas; + struct device *dev; + + /* for vbus reporting with irqs disabled */ + spinlock_t lock; + + struct regulator *vbus_reg; + + /* used to set vbus, in atomic path */ + struct work_struct set_vbus_work; + + int irq1; + int irq2; + int irq3; + int irq4; + + int vbus_enable; + + u8 linkstat; +}; + +#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator) + +enum usb_irq_events { + /* Wakeup events from INT3 */ + PALMAS_USB_ID_WAKEPUP, + PALMAS_USB_VBUS_WAKEUP, + + /* ID_OTG_EVENTS */ + PALMAS_USB_ID_GND, + N_PALMAS_USB_ID_GND, + PALMAS_USB_ID_C, + N_PALMAS_USB_ID_C, + PALMAS_USB_ID_B, + N_PALMAS_USB_ID_B, + PALMAS_USB_ID_A, + N_PALMAS_USB_ID_A, + PALMAS_USB_ID_FLOAT, + N_PALMAS_USB_ID_FLOAT, + + /* VBUS_OTG_EVENTS */ + PALMAS_USB_VB_SESS_END, + N_PALMAS_USB_VB_SESS_END, + PALMAS_USB_VB_SESS_VLD, + N_PALMAS_USB_VB_SESS_VLD, + PALMAS_USB_VA_SESS_VLD, + N_PALMAS_USB_VA_SESS_VLD, + PALMAS_USB_VA_VBUS_VLD, + N_PALMAS_USB_VA_VBUS_VLD, + PALMAS_USB_VADP_SNS, + N_PALMAS_USB_VADP_SNS, + PALMAS_USB_VADP_PRB, + N_PALMAS_USB_VADP_PRB, + PALMAS_USB_VOTG_SESS_VLD, + N_PALMAS_USB_VOTG_SESS_VLD, +}; + /* defines so we can store the mux settings */ #define PALMAS_GPIO_0_MUXED (1 << 0) #define PALMAS_GPIO_1_MUXED (1 << 1) diff --git a/include/linux/mfd/rc5t583.h b/include/linux/mfd/rc5t583.h index 3661c59aa1e9..36c242e52ef1 100644 --- a/include/linux/mfd/rc5t583.h +++ b/include/linux/mfd/rc5t583.h @@ -146,6 +146,28 @@ #define RC5T583_GPIO_MON_IOIN 0xAB #define RC5T583_GPIO_GPOFUNC 0xAC +/* RTC registers */ +#define RC5T583_RTC_SEC 0xE0 +#define RC5T583_RTC_MIN 0xE1 +#define RC5T583_RTC_HOUR 0xE2 +#define RC5T583_RTC_WDAY 0xE3 +#define RC5T583_RTC_DAY 0xE4 +#define RC5T583_RTC_MONTH 0xE5 +#define RC5T583_RTC_YEAR 0xE6 +#define RC5T583_RTC_ADJ 0xE7 +#define RC5T583_RTC_AW_MIN 0xE8 +#define RC5T583_RTC_AW_HOUR 0xE9 +#define RC5T583_RTC_AW_WEEK 0xEA +#define RC5T583_RTC_AD_MIN 0xEB +#define RC5T583_RTC_AD_HOUR 0xEC +#define RC5T583_RTC_CTL1 0xED +#define RC5T583_RTC_CTL2 0xEE +#define RC5T583_RTC_AY_MIN 0xF0 +#define RC5T583_RTC_AY_HOUR 0xF1 +#define RC5T583_RTC_AY_DAY 0xF2 +#define RC5T583_RTC_AY_MONTH 0xF3 +#define RC5T583_RTC_AY_YEAR 0xF4 + /* RICOH_RC5T583 IRQ definitions */ enum { RC5T583_IRQ_ONKEY, diff --git a/include/linux/mfd/smsc.h b/include/linux/mfd/smsc.h new file mode 100644 index 000000000000..9747b29f356f --- /dev/null +++ b/include/linux/mfd/smsc.h @@ -0,0 +1,109 @@ +/* + * SMSC ECE1099 + * + * Copyright 2012 Texas Instruments Inc. + * + * Author: Sourav Poddar <sourav.poddar@ti.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __LINUX_MFD_SMSC_H +#define __LINUX_MFD_SMSC_H + +#include <linux/regmap.h> + +#define SMSC_ID_ECE1099 1 +#define SMSC_NUM_CLIENTS 2 + +#define SMSC_BASE_ADDR 0x38 +#define OMAP_GPIO_SMSC_IRQ 151 + +#define SMSC_MAXGPIO 32 +#define SMSC_BANK(offs) ((offs) >> 3) +#define SMSC_BIT(offs) (1u << ((offs) & 0x7)) + +struct smsc { + struct device *dev; + struct i2c_client *i2c_clients[SMSC_NUM_CLIENTS]; + struct regmap *regmap; + int clk; + /* Stored chip id */ + int id; +}; + +struct smsc_gpio; +struct smsc_keypad; + +static inline int smsc_read(struct device *child, unsigned int reg, + unsigned int *dest) +{ + struct smsc *smsc = dev_get_drvdata(child->parent); + + return regmap_read(smsc->regmap, reg, dest); +} + +static inline int smsc_write(struct device *child, unsigned int reg, + unsigned int value) +{ + struct smsc *smsc = dev_get_drvdata(child->parent); + + return regmap_write(smsc->regmap, reg, value); +} + +/* Registers for SMSC */ +#define SMSC_RESET 0xF5 +#define SMSC_GRP_INT 0xF9 +#define SMSC_CLK_CTRL 0xFA +#define SMSC_WKUP_CTRL 0xFB +#define SMSC_DEV_ID 0xFC +#define SMSC_DEV_REV 0xFD +#define SMSC_VEN_ID_L 0xFE +#define SMSC_VEN_ID_H 0xFF + +/* CLK VALUE */ +#define SMSC_CLK_VALUE 0x13 + +/* Registers for function GPIO INPUT */ +#define SMSC_GPIO_DATA_IN_START 0x00 + +/* Registers for function GPIO OUPUT */ +#define SMSC_GPIO_DATA_OUT_START 0x05 + +/* Definitions for SMSC GPIO CONFIGURATION REGISTER*/ +#define SMSC_GPIO_INPUT_LOW 0x01 +#define SMSC_GPIO_INPUT_RISING 0x09 +#define SMSC_GPIO_INPUT_FALLING 0x11 +#define SMSC_GPIO_INPUT_BOTH_EDGE 0x19 +#define SMSC_GPIO_OUTPUT_PP 0x21 +#define SMSC_GPIO_OUTPUT_OP 0x31 + +#define GRP_INT_STAT 0xf9 +#define SMSC_GPI_INT 0x0f +#define SMSC_CFG_START 0x0A + +/* Registers for SMSC GPIO INTERRUPT STATUS REGISTER*/ +#define SMSC_GPIO_INT_STAT_START 0x32 + +/* Registers for SMSC GPIO INTERRUPT MASK REGISTER*/ +#define SMSC_GPIO_INT_MASK_START 0x37 + +/* Registers for SMSC function KEYPAD*/ +#define SMSC_KP_OUT 0x40 +#define SMSC_KP_IN 0x41 +#define SMSC_KP_INT_STAT 0x42 +#define SMSC_KP_INT_MASK 0x43 + +/* Definitions for keypad */ +#define SMSC_KP_KSO 0x70 +#define SMSC_KP_KSI 0x51 +#define SMSC_KSO_ALL_LOW 0x20 +#define SMSC_KP_SET_LOW_PWR 0x0B +#define SMSC_KP_SET_HIGH 0xFF +#define SMSC_KSO_EVAL 0x00 + +#endif /* __LINUX_MFD_SMSC_H */ diff --git a/include/linux/mfd/syscon.h b/include/linux/mfd/syscon.h new file mode 100644 index 000000000000..6aeb6b8da64d --- /dev/null +++ b/include/linux/mfd/syscon.h @@ -0,0 +1,23 @@ +/* + * System Control Driver + * + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012 Linaro Ltd. + * + * Author: Dong Aisheng <dong.aisheng@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __LINUX_MFD_SYSCON_H__ +#define __LINUX_MFD_SYSCON_H__ + +extern struct regmap *syscon_node_to_regmap(struct device_node *np); +extern struct regmap *syscon_regmap_lookup_by_compatible(const char *s); +extern struct regmap *syscon_regmap_lookup_by_phandle( + struct device_node *np, + const char *property); +#endif /* __LINUX_MFD_SYSCON_H__ */ diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h new file mode 100644 index 000000000000..dab34a1deb2c --- /dev/null +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -0,0 +1,319 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_IMX6Q_IOMUXC_GPR_H +#define __LINUX_IMX6Q_IOMUXC_GPR_H + +#include <linux/bitops.h> + +#define IOMUXC_GPR0 0x00 +#define IOMUXC_GPR1 0x04 +#define IOMUXC_GPR2 0x08 +#define IOMUXC_GPR3 0x0c +#define IOMUXC_GPR4 0x10 +#define IOMUXC_GPR5 0x14 +#define IOMUXC_GPR6 0x18 +#define IOMUXC_GPR7 0x1c +#define IOMUXC_GPR8 0x20 +#define IOMUXC_GPR9 0x24 +#define IOMUXC_GPR10 0x28 +#define IOMUXC_GPR11 0x2c +#define IOMUXC_GPR12 0x30 +#define IOMUXC_GPR13 0x34 + +#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_MASK (0x3 << 30) +#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0x0 << 30) +#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7 (0x1 << 30) +#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_SSI_SRCK (0x2 << 30) +#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 30) +#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_MASK (0x3 << 28) +#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR_MUXED (0x0 << 28) +#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR (0x1 << 28) +#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_DO_SCKR (0x2 << 28) +#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_MASK (0x3 << 26) +#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7_MUXED (0x0 << 26) +#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7 (0x1 << 26) +#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_SSI_STCK (0x2 << 26) +#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_TX_BIT_CLK (0x3 << 26) +#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_MASK (0x3 << 24) +#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0x3 << 24) +#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7 (0x3 << 24) +#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK (0x3 << 24) +#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 24) +#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_MASK (0x3 << 22) +#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2_MUXED (0x0 << 22) +#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2 (0x1 << 22) +#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_SSI_STCK (0x2 << 22) +#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_TX_BIT_CLK (0x3 << 22) +#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_MASK (0x3 << 20) +#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2_MUXED (0x0 << 20) +#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2 (0x1 << 20) +#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_SSI_SRCK (0x2 << 20) +#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_RX_BIT_CLK (0x3 << 20) +#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_MASK (0x3 << 18) +#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1_MUXED (0x0 << 18) +#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1 (0x1 << 18) +#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_STCK (0x2 << 18) +#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_TX_BIT_CLK (0x3 << 18) +#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_MASK (0x3 << 16) +#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1_MUXED (0x0 << 16) +#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1 (0x1 << 16) +#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_SRCK (0x2 << 16) +#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_RX_BIT_CLK (0x3 << 16) +#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_MASK (0x3 << 14) +#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK1 (0x0 << 14) +#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK2 (0x1 << 14) +#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK3 (0x2 << 14) +#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK BIT(7) +#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_SPDIF 0x0 +#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX BIT(7) +#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK BIT(6) +#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_ESAI 0x0 +#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3 BIT(6) +#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_MASK BIT(5) +#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_ECSPI4 0x0 +#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_EPIT2 BIT(5) +#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK BIT(4) +#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_ECSPI4 0x0 +#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1 BIT(4) +#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_MASK BIT(3) +#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_ECSPI2 0x0 +#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_I2C1 BIT(3) +#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_MASK BIT(2) +#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_ECSPI1 0x0 +#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_I2C2 BIT(2) +#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_MASK BIT(1) +#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_ECSPI1 0x0 +#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_I2C3 BIT(1) +#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_MASK BIT(0) +#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IPU1 0x0 +#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IOMUX BIT(0) + +#define IMX6Q_GPR1_PCIE_REQ_MASK (0x3 << 30) +#define IMX6Q_GPR1_PCIE_EXIT_L1 BIT(28) +#define IMX6Q_GPR1_PCIE_RDY_L23 BIT(27) +#define IMX6Q_GPR1_PCIE_ENTER_L1 BIT(26) +#define IMX6Q_GPR1_MIPI_COLOR_SW BIT(25) +#define IMX6Q_GPR1_DPI_OFF BIT(24) +#define IMX6Q_GPR1_EXC_MON_MASK BIT(22) +#define IMX6Q_GPR1_EXC_MON_OKAY 0x0 +#define IMX6Q_GPR1_EXC_MON_SLVE BIT(22) +#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK BIT(21) +#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET 0x0 +#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX BIT(21) +#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(20) +#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0 +#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(20) +#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(19) +#define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET 0x0 +#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(19) +#define IMX6Q_GPR1_PCIE_TEST_PD BIT(18) +#define IMX6Q_GPR1_IPU_VPU_MUX_MASK BIT(17) +#define IMX6Q_GPR1_IPU_VPU_MUX_IPU1 0x0 +#define IMX6Q_GPR1_IPU_VPU_MUX_IPU2 BIT(17) +#define IMX6Q_GPR1_PCIE_REF_CLK_EN BIT(16) +#define IMX6Q_GPR1_USB_EXP_MODE BIT(15) +#define IMX6Q_GPR1_PCIE_INT BIT(14) +#define IMX6Q_GPR1_USB_OTG_ID_SEL_MASK BIT(13) +#define IMX6Q_GPR1_USB_OTG_ID_SEL_ENET_RX_ER 0x0 +#define IMX6Q_GPR1_USB_OTG_ID_SEL_GPIO_1 BIT(13) +#define IMX6Q_GPR1_GINT BIT(12) +#define IMX6Q_GPR1_ADDRS3_MASK (0x3 << 10) +#define IMX6Q_GPR1_ADDRS3_32MB (0x0 << 10) +#define IMX6Q_GPR1_ADDRS3_64MB (0x1 << 10) +#define IMX6Q_GPR1_ADDRS3_128MB (0x2 << 10) +#define IMX6Q_GPR1_ACT_CS3 BIT(9) +#define IMX6Q_GPR1_ADDRS2_MASK (0x3 << 7) +#define IMX6Q_GPR1_ACT_CS2 BIT(6) +#define IMX6Q_GPR1_ADDRS1_MASK (0x3 << 4) +#define IMX6Q_GPR1_ACT_CS1 BIT(3) +#define IMX6Q_GPR1_ADDRS0_MASK (0x3 << 1) +#define IMX6Q_GPR1_ACT_CS0 BIT(0) + +#define IMX6Q_GPR2_COUNTER_RESET_VAL_MASK (0x3 << 20) +#define IMX6Q_GPR2_COUNTER_RESET_VAL_5 (0x0 << 20) +#define IMX6Q_GPR2_COUNTER_RESET_VAL_3 (0x1 << 20) +#define IMX6Q_GPR2_COUNTER_RESET_VAL_4 (0x2 << 20) +#define IMX6Q_GPR2_COUNTER_RESET_VAL_6 (0x3 << 20) +#define IMX6Q_GPR2_LVDS_CLK_SHIFT_MASK (0x7 << 16) +#define IMX6Q_GPR2_LVDS_CLK_SHIFT_0 (0x0 << 16) +#define IMX6Q_GPR2_LVDS_CLK_SHIFT_1 (0x1 << 16) +#define IMX6Q_GPR2_LVDS_CLK_SHIFT_2 (0x2 << 16) +#define IMX6Q_GPR2_LVDS_CLK_SHIFT_3 (0x3 << 16) +#define IMX6Q_GPR2_LVDS_CLK_SHIFT_4 (0x4 << 16) +#define IMX6Q_GPR2_LVDS_CLK_SHIFT_5 (0x5 << 16) +#define IMX6Q_GPR2_LVDS_CLK_SHIFT_6 (0x6 << 16) +#define IMX6Q_GPR2_LVDS_CLK_SHIFT_7 (0x7 << 16) +#define IMX6Q_GPR2_BGREF_RRMODE_MASK BIT(15) +#define IMX6Q_GPR2_BGREF_RRMODE_EXT_RESISTOR 0x0 +#define IMX6Q_GPR2_BGREF_RRMODE_INT_RESISTOR BIT(15) +#define IMX6Q_GPR2_DI1_VS_POLARITY_MASK BIT(10) +#define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_H 0x0 +#define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_L BIT(10) +#define IMX6Q_GPR2_DI0_VS_POLARITY_MASK BIT(9) +#define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_H 0x0 +#define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_L BIT(9) +#define IMX6Q_GPR2_BIT_MAPPING_CH1_MASK BIT(8) +#define IMX6Q_GPR2_BIT_MAPPING_CH1_SPWG 0x0 +#define IMX6Q_GPR2_BIT_MAPPING_CH1_JEIDA BIT(8) +#define IMX6Q_GPR2_DATA_WIDTH_CH1_MASK BIT(7) +#define IMX6Q_GPR2_DATA_WIDTH_CH1_18BIT 0x0 +#define IMX6Q_GPR2_DATA_WIDTH_CH1_24BIT BIT(7) +#define IMX6Q_GPR2_BIT_MAPPING_CH0_MASK BIT(6) +#define IMX6Q_GPR2_BIT_MAPPING_CH0_SPWG 0x0 +#define IMX6Q_GPR2_BIT_MAPPING_CH0_JEIDA BIT(6) +#define IMX6Q_GPR2_DATA_WIDTH_CH0_MASK BIT(5) +#define IMX6Q_GPR2_DATA_WIDTH_CH0_18BIT 0x0 +#define IMX6Q_GPR2_DATA_WIDTH_CH0_24BIT BIT(5) +#define IMX6Q_GPR2_SPLIT_MODE_EN BIT(4) +#define IMX6Q_GPR2_CH1_MODE_MASK (0x3 << 2) +#define IMX6Q_GPR2_CH1_MODE_DISABLE (0x0 << 2) +#define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI0 (0x1 << 2) +#define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI1 (0x3 << 2) +#define IMX6Q_GPR2_CH0_MODE_MASK (0x3 << 0) +#define IMX6Q_GPR2_CH0_MODE_DISABLE (0x0 << 0) +#define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI0 (0x1 << 0) +#define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI1 (0x3 << 0) + +#define IMX6Q_GPR3_GPU_DBG_MASK (0x3 << 29) +#define IMX6Q_GPR3_GPU_DBG_GPU3D (0x0 << 29) +#define IMX6Q_GPR3_GPU_DBG_GPU2D (0x1 << 29) +#define IMX6Q_GPR3_GPU_DBG_OPENVG (0x2 << 29) +#define IMX6Q_GPR3_BCH_WR_CACHE_CTL BIT(28) +#define IMX6Q_GPR3_BCH_RD_CACHE_CTL BIT(27) +#define IMX6Q_GPR3_USDHCX_WR_CACHE_CTL BIT(26) +#define IMX6Q_GPR3_USDHCX_RD_CACHE_CTL BIT(25) +#define IMX6Q_GPR3_OCRAM_CTL_MASK (0xf << 21) +#define IMX6Q_GPR3_OCRAM_STATUS_MASK (0xf << 17) +#define IMX6Q_GPR3_CORE3_DBG_ACK_EN BIT(16) +#define IMX6Q_GPR3_CORE2_DBG_ACK_EN BIT(15) +#define IMX6Q_GPR3_CORE1_DBG_ACK_EN BIT(14) +#define IMX6Q_GPR3_CORE0_DBG_ACK_EN BIT(13) +#define IMX6Q_GPR3_TZASC2_BOOT_LOCK BIT(12) +#define IMX6Q_GPR3_TZASC1_BOOT_LOCK BIT(11) +#define IMX6Q_GPR3_IPU_DIAG_MASK BIT(10) +#define IMX6Q_GPR3_LVDS1_MUX_CTL_MASK (0x3 << 8) +#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI0 (0x0 << 8) +#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI1 (0x1 << 8) +#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI0 (0x2 << 8) +#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI1 (0x3 << 8) +#define IMX6Q_GPR3_LVDS0_MUX_CTL_MASK (0x3 << 6) +#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI0 (0x0 << 6) +#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6) +#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0 (0x2 << 6) +#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1 (0x3 << 6) +#define IMX6Q_GPR3_MIPI_MUX_CTL_MASK (0x3 << 4) +#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0 (0x0 << 4) +#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1 (0x1 << 4) +#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI0 (0x2 << 4) +#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI1 (0x3 << 4) +#define IMX6Q_GPR3_HDMI_MUX_CTL_MASK (0x3 << 2) +#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI0 (0x0 << 2) +#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI1 (0x1 << 2) +#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI0 (0x2 << 2) +#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI1 (0x3 << 2) + +#define IMX6Q_GPR4_VDOA_WR_CACHE_SEL BIT(31) +#define IMX6Q_GPR4_VDOA_RD_CACHE_SEL BIT(30) +#define IMX6Q_GPR4_VDOA_WR_CACHE_VAL BIT(29) +#define IMX6Q_GPR4_VDOA_RD_CACHE_VAL BIT(28) +#define IMX6Q_GPR4_PCIE_WR_CACHE_SEL BIT(27) +#define IMX6Q_GPR4_PCIE_RD_CACHE_SEL BIT(26) +#define IMX6Q_GPR4_PCIE_WR_CACHE_VAL BIT(25) +#define IMX6Q_GPR4_PCIE_RD_CACHE_VAL BIT(24) +#define IMX6Q_GPR4_SDMA_STOP_ACK BIT(19) +#define IMX6Q_GPR4_CAN2_STOP_ACK BIT(18) +#define IMX6Q_GPR4_CAN1_STOP_ACK BIT(17) +#define IMX6Q_GPR4_ENET_STOP_ACK BIT(16) +#define IMX6Q_GPR4_SOC_VERSION_MASK (0xff << 8) +#define IMX6Q_GPR4_SOC_VERSION_OFF 0x8 +#define IMX6Q_GPR4_VPU_WR_CACHE_SEL BIT(7) +#define IMX6Q_GPR4_VPU_RD_CACHE_SEL BIT(6) +#define IMX6Q_GPR4_VPU_P_WR_CACHE_VAL BIT(3) +#define IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK BIT(2) +#define IMX6Q_GPR4_IPU_WR_CACHE_CTL BIT(1) +#define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) + +#define IMX6Q_GPR5_L2_CLK_STOP BIT(8) + +#define IMX6Q_GPR9_TZASC2_BYP BIT(1) +#define IMX6Q_GPR9_TZASC1_BYP BIT(0) + +#define IMX6Q_GPR10_LOCK_DBG_EN BIT(29) +#define IMX6Q_GPR10_LOCK_DBG_CLK_EN BIT(28) +#define IMX6Q_GPR10_LOCK_SEC_ERR_RESP BIT(27) +#define IMX6Q_GPR10_LOCK_OCRAM_TZ_ADDR (0x3f << 21) +#define IMX6Q_GPR10_LOCK_OCRAM_TZ_EN BIT(20) +#define IMX6Q_GPR10_LOCK_DCIC2_MUX_MASK (0x3 << 18) +#define IMX6Q_GPR10_LOCK_DCIC1_MUX_MASK (0x3 << 16) +#define IMX6Q_GPR10_DBG_EN BIT(13) +#define IMX6Q_GPR10_DBG_CLK_EN BIT(12) +#define IMX6Q_GPR10_SEC_ERR_RESP_MASK BIT(11) +#define IMX6Q_GPR10_SEC_ERR_RESP_OKEY 0x0 +#define IMX6Q_GPR10_SEC_ERR_RESP_SLVE BIT(11) +#define IMX6Q_GPR10_OCRAM_TZ_ADDR_MASK (0x3f << 5) +#define IMX6Q_GPR10_OCRAM_TZ_EN_MASK BIT(4) +#define IMX6Q_GPR10_DCIC2_MUX_CTL_MASK (0x3 << 2) +#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI0 (0x0 << 2) +#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1 (0x1 << 2) +#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0 (0x2 << 2) +#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI1 (0x3 << 2) +#define IMX6Q_GPR10_DCIC1_MUX_CTL_MASK (0x3 << 0) +#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0 (0x0 << 0) +#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI1 (0x1 << 0) +#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0 (0x2 << 0) +#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI1 (0x3 << 0) + +#define IMX6Q_GPR12_ARMP_IPG_CLK_EN BIT(27) +#define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26) +#define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25) +#define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24) +#define IMX6Q_GPR12_PCIE_CTL_2 BIT(10) + +#define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30) +#define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29) +#define IMX6Q_GPR13_CAN1_STOP_REQ BIT(28) +#define IMX6Q_GPR13_ENET_STOP_REQ BIT(27) +#define IMX6Q_GPR13_SATA_PHY_8_MASK (0x7 << 24) +#define IMX6Q_GPR13_SATA_PHY_8_0_5_DB (0x0 << 24) +#define IMX6Q_GPR13_SATA_PHY_8_1_0_DB (0x1 << 24) +#define IMX6Q_GPR13_SATA_PHY_8_1_5_DB (0x2 << 24) +#define IMX6Q_GPR13_SATA_PHY_8_2_0_DB (0x3 << 24) +#define IMX6Q_GPR13_SATA_PHY_8_2_5_DB (0x4 << 24) +#define IMX6Q_GPR13_SATA_PHY_8_3_0_DB (0x5 << 24) +#define IMX6Q_GPR13_SATA_PHY_8_3_5_DB (0x6 << 24) +#define IMX6Q_GPR13_SATA_PHY_8_4_0_DB (0x7 << 24) +#define IMX6Q_GPR13_SATA_PHY_7_MASK (0x1f << 19) +#define IMX6Q_GPR13_SATA_PHY_7_SATA1I (0x10 << 19) +#define IMX6Q_GPR13_SATA_PHY_7_SATA1M (0x10 << 19) +#define IMX6Q_GPR13_SATA_PHY_7_SATA1X (0x1a << 19) +#define IMX6Q_GPR13_SATA_PHY_7_SATA2I (0x12 << 19) +#define IMX6Q_GPR13_SATA_PHY_7_SATA2M (0x12 << 19) +#define IMX6Q_GPR13_SATA_PHY_7_SATA2X (0x1a << 19) +#define IMX6Q_GPR13_SATA_PHY_6_MASK (0x7 << 16) +#define IMX6Q_GPR13_SATA_SPEED_MASK BIT(15) +#define IMX6Q_GPR13_SATA_SPEED_1P5G 0x0 +#define IMX6Q_GPR13_SATA_SPEED_3P0G BIT(15) +#define IMX6Q_GPR13_SATA_PHY_5 BIT(14) +#define IMX6Q_GPR13_SATA_PHY_4_MASK (0x7 << 11) +#define IMX6Q_GPR13_SATA_PHY_4_16_16 (0x0 << 11) +#define IMX6Q_GPR13_SATA_PHY_4_14_16 (0x1 << 11) +#define IMX6Q_GPR13_SATA_PHY_4_12_16 (0x2 << 11) +#define IMX6Q_GPR13_SATA_PHY_4_10_16 (0x3 << 11) +#define IMX6Q_GPR13_SATA_PHY_4_9_16 (0x4 << 11) +#define IMX6Q_GPR13_SATA_PHY_4_8_16 (0x5 << 11) +#define IMX6Q_GPR13_SATA_PHY_3_MASK (0xf << 7) +#define IMX6Q_GPR13_SATA_PHY_3_OFF 0x7 +#define IMX6Q_GPR13_SATA_PHY_2_MASK (0x1f << 2) +#define IMX6Q_GPR13_SATA_PHY_2_OFF 0x2 +#define IMX6Q_GPR13_SATA_PHY_1_MASK (0x3 << 0) +#define IMX6Q_GPR13_SATA_PHY_1_FAST (0x0 << 0) +#define IMX6Q_GPR13_SATA_PHY_1_MED (0x1 << 0) +#define IMX6Q_GPR13_SATA_PHY_1_SLOW (0x2 << 0) + +#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */ diff --git a/include/linux/mfd/tc3589x.h b/include/linux/mfd/tc3589x.h index 3acb3a8e3af5..6b8e1ff4672b 100644 --- a/include/linux/mfd/tc3589x.h +++ b/include/linux/mfd/tc3589x.h @@ -117,6 +117,7 @@ struct tc3589x { struct mutex lock; struct device *dev; struct i2c_client *i2c; + struct irq_domain *domain; int irq_base; int num_gpio; diff --git a/include/linux/mfd/tps65217.h b/include/linux/mfd/tps65217.h index 7cd83d826ed8..290762f93930 100644 --- a/include/linux/mfd/tps65217.h +++ b/include/linux/mfd/tps65217.h @@ -213,6 +213,23 @@ enum tps65217_regulator_id { /* Number of total regulators available */ #define TPS65217_NUM_REGULATOR (TPS65217_NUM_DCDC + TPS65217_NUM_LDO) +enum tps65217_bl_isel { + TPS65217_BL_ISET1 = 1, + TPS65217_BL_ISET2, +}; + +enum tps65217_bl_fdim { + TPS65217_BL_FDIM_100HZ, + TPS65217_BL_FDIM_200HZ, + TPS65217_BL_FDIM_500HZ, + TPS65217_BL_FDIM_1000HZ, +}; + +struct tps65217_bl_pdata { + enum tps65217_bl_isel isel; + enum tps65217_bl_fdim fdim; +}; + /** * struct tps65217_board - packages regulator init data * @tps65217_regulator_data: regulator initialization values @@ -222,6 +239,7 @@ enum tps65217_regulator_id { struct tps65217_board { struct regulator_init_data *tps65217_init_data[TPS65217_NUM_REGULATOR]; struct device_node *of_node[TPS65217_NUM_REGULATOR]; + struct tps65217_bl_pdata *bl_pdata; }; /** diff --git a/include/linux/mfd/tps6586x.h b/include/linux/mfd/tps6586x.h index 94514710a03f..2dd123194958 100644 --- a/include/linux/mfd/tps6586x.h +++ b/include/linux/mfd/tps6586x.h @@ -78,6 +78,7 @@ struct tps6586x_platform_data { int gpio_base; int irq_base; + bool pm_off; }; /* diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h index 9bf8767818b4..02e894f3ff45 100644 --- a/include/linux/mfd/tps65910.h +++ b/include/linux/mfd/tps65910.h @@ -132,6 +132,16 @@ * */ +/* RTC_CTRL_REG bitfields */ +#define TPS65910_RTC_CTRL_STOP_RTC 0x01 /*0=stop, 1=run */ +#define TPS65910_RTC_CTRL_GET_TIME 0x40 + +/* RTC_STATUS_REG bitfields */ +#define TPS65910_RTC_STATUS_ALARM 0x40 + +/* RTC_INTERRUPTS_REG bitfields */ +#define TPS65910_RTC_INTERRUPTS_EVERY 0x03 +#define TPS65910_RTC_INTERRUPTS_IT_ALARM 0x08 /*Register BCK1 (0x80) register.RegisterDescription */ #define BCK1_BCKUP_MASK 0xFF @@ -366,6 +376,8 @@ /*Register DEVCTRL (0x80) register.RegisterDescription */ +#define DEVCTRL_PWR_OFF_MASK 0x80 +#define DEVCTRL_PWR_OFF_SHIFT 7 #define DEVCTRL_RTC_PWDN_MASK 0x40 #define DEVCTRL_RTC_PWDN_SHIFT 6 #define DEVCTRL_CK32K_CTRL_MASK 0x20 @@ -809,6 +821,7 @@ struct tps65910_board { int vmbch2_threshold; bool en_ck32k_xtal; bool en_dev_slp; + bool pm_off; struct tps65910_sleep_keepon_data *slp_keepon; bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO]; unsigned long regulator_ext_sleep_control[TPS65910_NUM_REGS]; diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h index ba43d4806b83..a8eff4ad9be5 100644 --- a/include/linux/mfd/twl6040.h +++ b/include/linux/mfd/twl6040.h @@ -143,7 +143,7 @@ #define TWL6040_GPO1 0x01 #define TWL6040_GPO2 0x02 -#define TWL6040_GPO3 0x03 +#define TWL6040_GPO3 0x04 /* ACCCTL (0x2D) fields */ @@ -158,7 +158,7 @@ #define TWL6040_VIBROCDET 0x20 #define TWL6040_TSHUTDET 0x40 -#define TWL6040_CELLS 2 +#define TWL6040_CELLS 3 #define TWL6040_REV_ES1_0 0x00 #define TWL6040_REV_ES1_1 0x01 /* Rev ES1.1 and ES1.2 */ @@ -176,6 +176,8 @@ #define TWL6040_SYSCLK_SEL_LPPLL 0 #define TWL6040_SYSCLK_SEL_HPPLL 1 +#define TWL6040_GPO_MAX 3 + struct twl6040_codec_data { u16 hs_left_step; u16 hs_right_step; @@ -192,11 +194,16 @@ struct twl6040_vibra_data { int vddvibr_uV; /* VDDVIBR volt, set 0 for fixed reg */ }; +struct twl6040_gpo_data { + int gpio_base; +}; + struct twl6040_platform_data { int audpwron_gpio; /* audio power-on gpio */ struct twl6040_codec_data *codec; struct twl6040_vibra_data *vibra; + struct twl6040_gpo_data *gpo; }; struct regmap; diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h index f0361c031927..fc87be4fdc25 100644 --- a/include/linux/mfd/wm8994/pdata.h +++ b/include/linux/mfd/wm8994/pdata.h @@ -164,6 +164,10 @@ struct wm8994_pdata { int num_micd_rates; struct wm8958_micd_rate *micd_rates; + /* Power up delays to add after microphone bias power up (ms) */ + int micb1_delay; + int micb2_delay; + /* LINEOUT can be differential or single ended */ unsigned int lineout1_diff:1; unsigned int lineout2_diff:1; diff --git a/include/linux/nbd.h b/include/linux/nbd.h index d146ca10c0f5..5c86e2b33e2d 100644 --- a/include/linux/nbd.h +++ b/include/linux/nbd.h @@ -27,13 +27,22 @@ #define NBD_SET_SIZE_BLOCKS _IO( 0xab, 7 ) #define NBD_DISCONNECT _IO( 0xab, 8 ) #define NBD_SET_TIMEOUT _IO( 0xab, 9 ) +#define NBD_SET_FLAGS _IO( 0xab, 10) enum { NBD_CMD_READ = 0, NBD_CMD_WRITE = 1, - NBD_CMD_DISC = 2 + NBD_CMD_DISC = 2, + /* there is a gap here to match userspace */ + NBD_CMD_TRIM = 4 }; +/* values for flags field */ +#define NBD_FLAG_HAS_FLAGS (1 << 0) /* nbd-server supports flags */ +#define NBD_FLAG_READ_ONLY (1 << 1) /* device is read-only */ +/* there is a gap here to match userspace */ +#define NBD_FLAG_SEND_TRIM (1 << 5) /* send trim/discard */ + #define nbd_cmd(req) ((req)->cmd[0]) /* userspace doesn't need the nbd_device structure */ @@ -42,10 +51,6 @@ enum { #include <linux/wait.h> #include <linux/mutex.h> -/* values for flags field */ -#define NBD_READ_ONLY 0x0001 -#define NBD_WRITE_NOCHK 0x0002 - struct request; struct nbd_device { diff --git a/include/linux/of.h b/include/linux/of.h index f594c528842f..72843b72a2b2 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -317,6 +317,12 @@ static inline const char* of_node_full_name(struct device_node *np) return "<no-node>"; } +static inline struct device_node *of_find_node_by_name(struct device_node *from, + const char *name) +{ + return NULL; +} + static inline bool of_have_populated_dt(void) { return false; diff --git a/include/linux/omap3isp.h b/include/linux/omap3isp.h index c73a34c3434d..c090cf9249bb 100644 --- a/include/linux/omap3isp.h +++ b/include/linux/omap3isp.h @@ -28,6 +28,7 @@ #define OMAP3_ISP_USER_H #include <linux/types.h> +#include <linux/videodev2.h> /* * Private IOCTLs @@ -427,7 +428,7 @@ struct omap3isp_ccdc_update_config { #define OMAP3ISP_PREV_COLOR_CONV (1 << 8) #define OMAP3ISP_PREV_YC_LIMIT (1 << 9) #define OMAP3ISP_PREV_DEFECT_COR (1 << 10) -#define OMAP3ISP_PREV_GAMMABYPASS (1 << 11) +/* Bit 11 was OMAP3ISP_PREV_GAMMABYPASS, now merged with OMAP3ISP_PREV_GAMMA */ #define OMAP3ISP_PREV_DRK_FRM_CAPTURE (1 << 12) #define OMAP3ISP_PREV_DRK_FRM_SUBTRACT (1 << 13) #define OMAP3ISP_PREV_LENS_SHADING (1 << 14) @@ -436,6 +437,7 @@ struct omap3isp_ccdc_update_config { #define OMAP3ISP_PREV_NF_TBL_SIZE 64 #define OMAP3ISP_PREV_CFA_TBL_SIZE 576 +#define OMAP3ISP_PREV_CFA_BLK_SIZE (OMAP3ISP_PREV_CFA_TBL_SIZE / 4) #define OMAP3ISP_PREV_GAMMA_TBL_SIZE 1024 #define OMAP3ISP_PREV_YENH_TBL_SIZE 128 @@ -477,7 +479,7 @@ struct omap3isp_prev_cfa { enum omap3isp_cfa_fmt format; __u8 gradthrs_vert; __u8 gradthrs_horz; - __u32 table[OMAP3ISP_PREV_CFA_TBL_SIZE]; + __u32 table[4][OMAP3ISP_PREV_CFA_BLK_SIZE]; }; /** diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 33880f6f4e51..9d36b829533a 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -1427,6 +1427,7 @@ #define PCI_DEVICE_ID_VIA_CX700_IDE 0x0581 #define PCI_DEVICE_ID_VIA_VX800 0x8353 #define PCI_DEVICE_ID_VIA_VX855 0x8409 +#define PCI_DEVICE_ID_VIA_VX900 0x8410 #define PCI_DEVICE_ID_VIA_8371_1 0x8391 #define PCI_DEVICE_ID_VIA_82C598_1 0x8598 #define PCI_DEVICE_ID_VIA_838X_1 0xB188 diff --git a/include/linux/platform_data/asoc-mx27vis.h b/include/linux/platform_data/asoc-mx27vis.h new file mode 100644 index 000000000000..409adcd04d04 --- /dev/null +++ b/include/linux/platform_data/asoc-mx27vis.h @@ -0,0 +1,11 @@ +#ifndef __PLATFORM_DATA_ASOC_MX27VIS_H +#define __PLATFORM_DATA_ASOC_MX27VIS_H + +struct snd_mx27vis_platform_data { + int amp_gain0_gpio; + int amp_gain1_gpio; + int amp_mutel_gpio; + int amp_muter_gpio; +}; + +#endif /* __PLATFORM_DATA_ASOC_MX27VIS_H */ diff --git a/include/linux/platform_data/asoc-ti-mcbsp.h b/include/linux/platform_data/asoc-ti-mcbsp.h index 18814127809a..c78d90b28b19 100644 --- a/include/linux/platform_data/asoc-ti-mcbsp.h +++ b/include/linux/platform_data/asoc-ti-mcbsp.h @@ -47,8 +47,6 @@ struct omap_mcbsp_platform_data { bool has_wakeup; /* Wakeup capability */ bool has_ccr; /* Transceiver has configuration control registers */ int (*enable_st_clock)(unsigned int, bool); - int (*set_clk_src)(struct device *dev, struct clk *clk, const char *src); - int (*mux_signal)(struct device *dev, const char *signal, const char *src); }; /** diff --git a/include/linux/platform_data/davinci_asp.h b/include/linux/platform_data/davinci_asp.h new file mode 100644 index 000000000000..d0c5825876f8 --- /dev/null +++ b/include/linux/platform_data/davinci_asp.h @@ -0,0 +1,105 @@ +/* + * TI DaVinci Audio Serial Port support + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DAVINCI_ASP_H +#define __DAVINCI_ASP_H + +struct snd_platform_data { + u32 tx_dma_offset; + u32 rx_dma_offset; + int asp_chan_q; /* event queue number for ASP channel */ + int ram_chan_q; /* event queue number for RAM channel */ + unsigned int codec_fmt; + /* + * Allowing this is more efficient and eliminates left and right swaps + * caused by underruns, but will swap the left and right channels + * when compared to previous behavior. + */ + unsigned enable_channel_combine:1; + unsigned sram_size_playback; + unsigned sram_size_capture; + + /* + * If McBSP peripheral gets the clock from an external pin, + * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR + * and MCBSP_CLKS. + * Depending on different hardware connections it is possible + * to use this setting to change the behaviour of McBSP + * driver. + */ + int clk_input_pin; + + /* + * This flag works when both clock and FS are outputs for the cpu + * and makes clock more accurate (FS is not symmetrical and the + * clock is very fast. + * The clock becoming faster is named + * i2s continuous serial clock (I2S_SCK) and it is an externally + * visible bit clock. + * + * first line : WordSelect + * second line : ContinuousSerialClock + * third line: SerialData + * + * SYMMETRICAL APPROACH: + * _______________________ LEFT + * _| RIGHT |______________________| + * _ _ _ _ _ _ _ _ + * _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_ + * _ _ _ _ _ _ _ _ + * _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_ + * \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ + * + * ACCURATE CLOCK APPROACH: + * ______________ LEFT + * _| RIGHT |_______________________________| + * _ _ _ _ _ _ _ _ _ + * _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| | + * _ _ _ _ dummy cycles + * _/ \_ ... _/ \_/ \_ ... _/ \__________________ + * \_/ \_/ \_/ \_/ + * + */ + bool i2s_accurate_sck; + + /* McASP specific fields */ + int tdm_slots; + u8 op_mode; + u8 num_serializer; + u8 *serial_dir; + u8 version; + u8 txnumevt; + u8 rxnumevt; +}; + +enum { + MCASP_VERSION_1 = 0, /* DM646x */ + MCASP_VERSION_2, /* DA8xx/OMAPL1x */ + MCASP_VERSION_3, /* TI81xx/AM33xx */ +}; + +enum mcbsp_clk_input_pin { + MCBSP_CLKR = 0, /* as in DM365 */ + MCBSP_CLKS, +}; + +#define INACTIVE_MODE 0 +#define TX_MODE 1 +#define RX_MODE 2 + +#define DAVINCI_MCASP_IIS_MODE 0 +#define DAVINCI_MCASP_DIT_MODE 1 + +#endif diff --git a/include/linux/platform_data/lp8727.h b/include/linux/platform_data/lp8727.h index ea98c6133d32..47128a50e04e 100644 --- a/include/linux/platform_data/lp8727.h +++ b/include/linux/platform_data/lp8727.h @@ -13,32 +13,32 @@ #define _LP8727_H enum lp8727_eoc_level { - EOC_5P, - EOC_10P, - EOC_16P, - EOC_20P, - EOC_25P, - EOC_33P, - EOC_50P, + LP8727_EOC_5P, + LP8727_EOC_10P, + LP8727_EOC_16P, + LP8727_EOC_20P, + LP8727_EOC_25P, + LP8727_EOC_33P, + LP8727_EOC_50P, }; enum lp8727_ichg { - ICHG_90mA, - ICHG_100mA, - ICHG_400mA, - ICHG_450mA, - ICHG_500mA, - ICHG_600mA, - ICHG_700mA, - ICHG_800mA, - ICHG_900mA, - ICHG_1000mA, + LP8727_ICHG_90mA, + LP8727_ICHG_100mA, + LP8727_ICHG_400mA, + LP8727_ICHG_450mA, + LP8727_ICHG_500mA, + LP8727_ICHG_600mA, + LP8727_ICHG_700mA, + LP8727_ICHG_800mA, + LP8727_ICHG_900mA, + LP8727_ICHG_1000mA, }; /** * struct lp8727_chg_param * @eoc_level : end of charge level setting - * @ichg : charging current + * @ichg : charging current */ struct lp8727_chg_param { enum lp8727_eoc_level eoc_level; @@ -47,19 +47,22 @@ struct lp8727_chg_param { /** * struct lp8727_platform_data - * @get_batt_present : check battery status - exists or not - * @get_batt_level : get battery voltage (mV) + * @get_batt_present : check battery status - exists or not + * @get_batt_level : get battery voltage (mV) * @get_batt_capacity : get battery capacity (%) - * @get_batt_temp : get battery temperature - * @ac, @usb : charging parameters each charger type + * @get_batt_temp : get battery temperature + * @ac : charging parameters for AC type charger + * @usb : charging parameters for USB type charger + * @debounce_msec : interrupt debounce time */ struct lp8727_platform_data { u8 (*get_batt_present)(void); u16 (*get_batt_level)(void); u8 (*get_batt_capacity)(void); u8 (*get_batt_temp)(void); - struct lp8727_chg_param ac; - struct lp8727_chg_param usb; + struct lp8727_chg_param *ac; + struct lp8727_chg_param *usb; + unsigned int debounce_msec; }; #endif diff --git a/include/linux/platform_data/omap-twl4030.h b/include/linux/platform_data/omap-twl4030.h new file mode 100644 index 000000000000..c7bef788daab --- /dev/null +++ b/include/linux/platform_data/omap-twl4030.h @@ -0,0 +1,32 @@ +/** + * omap-twl4030.h - ASoC machine driver for TI SoC based boards with twl4030 + * codec, header. + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ + +#ifndef _OMAP_TWL4030_H_ +#define _OMAP_TWL4030_H_ + +struct omap_tw4030_pdata { + const char *card_name; +}; + +#endif /* _OMAP_TWL4030_H_ */ diff --git a/include/linux/power/charger-manager.h b/include/linux/power/charger-manager.h index cd22029e32aa..0e86840eb603 100644 --- a/include/linux/power/charger-manager.h +++ b/include/linux/power/charger-manager.h @@ -109,24 +109,43 @@ struct charger_cable { * struct charger_regulator * @regulator_name: the name of regulator for using charger. * @consumer: the regulator consumer for the charger. + * @externally_control: + * Set if the charger-manager cannot control charger, + * the charger will be maintained with disabled state. * @cables: * the array of charger cables to enable/disable charger * and set current limit according to constratint data of * struct charger_cable if only charger cable included * in the array of charger cables is attached/detached. * @num_cables: the number of charger cables. + * @attr_g: Attribute group for the charger(regulator) + * @attr_name: "name" sysfs entry + * @attr_state: "state" sysfs entry + * @attr_externally_control: "externally_control" sysfs entry + * @attrs: Arrays pointing to attr_name/state/externally_control for attr_g */ struct charger_regulator { /* The name of regulator for charging */ const char *regulator_name; struct regulator *consumer; + /* charger never on when system is on */ + int externally_control; + /* * Store constraint information related to current limit, * each cable have different condition for charging. */ struct charger_cable *cables; int num_cables; + + struct attribute_group attr_g; + struct device_attribute attr_name; + struct device_attribute attr_state; + struct device_attribute attr_externally_control; + struct attribute *attrs[4]; + + struct charger_manager *cm; }; /** @@ -140,7 +159,11 @@ struct charger_regulator { * If it has dropped more than fullbatt_vchkdrop_uV after * fullbatt_vchkdrop_ms, CM will restart charging. * @fullbatt_uV: voltage in microvolt - * If it is not being charged and VBATT >= fullbatt_uV, + * If VBATT >= fullbatt_uV, it is assumed to be full. + * @fullbatt_soc: state of Charge in % + * If state of Charge >= fullbatt_soc, it is assumed to be full. + * @fullbatt_full_capacity: full capacity measure + * If full capacity of battery >= fullbatt_full_capacity, * it is assumed to be full. * @polling_interval_ms: interval in millisecond at which * charger manager will monitor battery health @@ -148,7 +171,7 @@ struct charger_regulator { * Specify where information for existance of battery can be obtained * @psy_charger_stat: the names of power-supply for chargers * @num_charger_regulator: the number of entries in charger_regulators - * @charger_regulators: array of regulator_bulk_data for chargers + * @charger_regulators: array of charger regulators * @psy_fuel_gauge: the name of power-supply for fuel gauge * @temperature_out_of_range: * Determine whether the status is overheat or cold or normal. @@ -158,6 +181,13 @@ struct charger_regulator { * @measure_battery_temp: * true: measure battery temperature * false: measure ambient temperature + * @charging_max_duration_ms: Maximum possible duration for charging + * If whole charging duration exceed 'charging_max_duration_ms', + * cm stop charging. + * @discharging_max_duration_ms: + * Maximum possible duration for discharging with charger cable + * after full-batt. If discharging duration exceed 'discharging + * max_duration_ms', cm start charging. */ struct charger_desc { char *psy_name; @@ -168,6 +198,8 @@ struct charger_desc { unsigned int fullbatt_vchkdrop_ms; unsigned int fullbatt_vchkdrop_uV; unsigned int fullbatt_uV; + unsigned int fullbatt_soc; + unsigned int fullbatt_full_capacity; enum data_source battery_present; @@ -180,6 +212,9 @@ struct charger_desc { int (*temperature_out_of_range)(int *mC); bool measure_battery_temp; + + u64 charging_max_duration_ms; + u64 discharging_max_duration_ms; }; #define PSY_NAME_MAX 30 @@ -194,8 +229,6 @@ struct charger_desc { * @charger_enabled: the state of charger * @fullbatt_vchk_jiffies_at: * jiffies at the time full battery check will occur. - * @fullbatt_vchk_uV: voltage in microvolt - * criteria for full battery * @fullbatt_vchk_work: work queue for full battery check * @emergency_stop: * When setting true, stop charging @@ -206,6 +239,8 @@ struct charger_desc { * saved status of external power before entering suspend-to-RAM * @status_save_batt: * saved status of battery before entering suspend-to-RAM + * @charging_start_time: saved start time of enabling charging + * @charging_end_time: saved end time of disabling charging */ struct charger_manager { struct list_head entry; @@ -218,7 +253,6 @@ struct charger_manager { bool charger_enabled; unsigned long fullbatt_vchk_jiffies_at; - unsigned int fullbatt_vchk_uV; struct delayed_work fullbatt_vchk_work; int emergency_stop; @@ -229,6 +263,9 @@ struct charger_manager { bool status_save_ext_pwr_inserted; bool status_save_batt; + + u64 charging_start_time; + u64 charging_end_time; }; #ifdef CONFIG_CHARGER_MANAGER diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h index 0bafbb15f29c..e5ef45834c3c 100644 --- a/include/linux/power_supply.h +++ b/include/linux/power_supply.h @@ -88,6 +88,7 @@ enum power_supply_property { POWER_SUPPLY_PROP_HEALTH, POWER_SUPPLY_PROP_PRESENT, POWER_SUPPLY_PROP_ONLINE, + POWER_SUPPLY_PROP_AUTHENTIC, POWER_SUPPLY_PROP_TECHNOLOGY, POWER_SUPPLY_PROP_CYCLE_COUNT, POWER_SUPPLY_PROP_VOLTAGE_MAX, @@ -110,7 +111,9 @@ enum power_supply_property { POWER_SUPPLY_PROP_CHARGE_AVG, POWER_SUPPLY_PROP_CHARGE_COUNTER, POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT, + POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX, POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE, + POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX, POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN, POWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN, POWER_SUPPLY_PROP_ENERGY_FULL, @@ -248,6 +251,7 @@ static inline bool power_supply_is_amp_property(enum power_supply_property psp) case POWER_SUPPLY_PROP_CHARGE_AVG: case POWER_SUPPLY_PROP_CHARGE_COUNTER: case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT: + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX: case POWER_SUPPLY_PROP_CURRENT_MAX: case POWER_SUPPLY_PROP_CURRENT_NOW: case POWER_SUPPLY_PROP_CURRENT_AVG: @@ -276,6 +280,7 @@ static inline bool power_supply_is_watt_property(enum power_supply_property psp) case POWER_SUPPLY_PROP_VOLTAGE_AVG: case POWER_SUPPLY_PROP_VOLTAGE_OCV: case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE: + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX: case POWER_SUPPLY_PROP_POWER_NOW: return 1; default: diff --git a/include/linux/pstore.h b/include/linux/pstore.h index c892587d9b81..ee3034a40884 100644 --- a/include/linux/pstore.h +++ b/include/linux/pstore.h @@ -64,14 +64,6 @@ struct pstore_info { void *data; }; - -#ifdef CONFIG_PSTORE_FTRACE -extern void pstore_ftrace_call(unsigned long ip, unsigned long parent_ip); -#else -static inline void pstore_ftrace_call(unsigned long ip, unsigned long parent_ip) -{ } -#endif - #ifdef CONFIG_PSTORE extern int pstore_register(struct pstore_info *); #else diff --git a/include/linux/rio.h b/include/linux/rio.h index a90ebadd9da0..d2dff22cf681 100644 --- a/include/linux/rio.h +++ b/include/linux/rio.h @@ -30,6 +30,7 @@ #define RIO_MAX_MPORTS 8 #define RIO_MAX_MPORT_RESOURCES 16 #define RIO_MAX_DEV_RESOURCES 16 +#define RIO_MAX_MPORT_NAME 40 #define RIO_GLOBAL_TABLE 0xff /* Indicates access of a switch's global routing table if it @@ -235,6 +236,7 @@ enum rio_phy_type { * @phys_efptr: RIO port extended features pointer * @name: Port name string * @priv: Master port private data + * @dma: DMA device associated with mport */ struct rio_mport { struct list_head dbells; /* list of doorbell events */ @@ -255,13 +257,21 @@ struct rio_mport { */ enum rio_phy_type phy_type; /* RapidIO phy type */ u32 phys_efptr; - unsigned char name[40]; + unsigned char name[RIO_MAX_MPORT_NAME]; void *priv; /* Master port private data */ #ifdef CONFIG_RAPIDIO_DMA_ENGINE struct dma_device dma; #endif }; +struct rio_id_table { + u16 start; /* logical minimal id */ + u16 next; /* hint for find */ + u32 max; /* max number of IDs in table */ + spinlock_t lock; + unsigned long *table; +}; + /** * struct rio_net - RIO network info * @node: Node in global list of RIO networks @@ -273,9 +283,11 @@ struct rio_mport { struct rio_net { struct list_head node; /* node in list of networks */ struct list_head devices; /* list of devices in this net */ + struct list_head switches; /* list of switches in this net */ struct list_head mports; /* list of ports accessing net */ struct rio_mport *hport; /* primary port for accessing net */ unsigned char id; /* RIO network ID */ + struct rio_id_table destid_table; /* destID allocation table */ }; /* Definitions used by switch sysfs initialization callback */ @@ -299,6 +311,8 @@ struct rio_net { * @add_outb_message: Callback to add a message to an outbound mailbox queue. * @add_inb_buffer: Callback to add a buffer to an inbound mailbox queue. * @get_inb_message: Callback to get a message from an inbound mailbox queue. + * @map_inb: Callback to map RapidIO address region into local memory space. + * @unmap_inb: Callback to unmap RapidIO address region mapped with map_inb(). */ struct rio_ops { int (*lcread) (struct rio_mport *mport, int index, u32 offset, int len, @@ -321,6 +335,9 @@ struct rio_ops { int mbox, void *buffer, size_t len); int (*add_inb_buffer)(struct rio_mport *mport, int mbox, void *buf); void *(*get_inb_message)(struct rio_mport *mport, int mbox); + int (*map_inb)(struct rio_mport *mport, dma_addr_t lstart, + u64 rstart, u32 size, u32 flags); + void (*unmap_inb)(struct rio_mport *mport, dma_addr_t lstart); }; #define RIO_RESOURCE_MEM 0x00000100 @@ -403,7 +420,7 @@ union rio_pw_msg { #ifdef CONFIG_RAPIDIO_DMA_ENGINE -/** +/* * enum rio_write_type - RIO write transaction types used in DMA transfers * * Note: RapidIO specification defines write (NWRITE) and diff --git a/include/linux/rio_drv.h b/include/linux/rio_drv.h index 31ad146be316..b75c05920ab5 100644 --- a/include/linux/rio_drv.h +++ b/include/linux/rio_drv.h @@ -365,6 +365,11 @@ void rio_release_regions(struct rio_dev *); int rio_request_region(struct rio_dev *, int, char *); void rio_release_region(struct rio_dev *, int); +/* Memory mapping functions */ +extern int rio_map_inb_region(struct rio_mport *mport, dma_addr_t local, + u64 rbase, u32 size, u32 rflags); +extern void rio_unmap_inb_region(struct rio_mport *mport, dma_addr_t lstart); + /* Port-Write management */ extern int rio_request_inb_pwrite(struct rio_dev *, int (*)(struct rio_dev *, union rio_pw_msg*, int)); diff --git a/include/linux/rtc-ds2404.h b/include/linux/rtc-ds2404.h new file mode 100644 index 000000000000..22c53825528f --- /dev/null +++ b/include/linux/rtc-ds2404.h @@ -0,0 +1,20 @@ +/* + * ds2404.h - platform data structure for the DS2404 RTC. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 Sven Schnelle <svens@stackframe.org> + */ + +#ifndef __LINUX_DS2404_H +#define __LINUX_DS2404_H + +struct ds2404_platform_data { + + unsigned int gpio_rst; + unsigned int gpio_clk; + unsigned int gpio_dq; +}; +#endif diff --git a/include/linux/rtc.h b/include/linux/rtc.h index f071b3922c67..20ec4d3bed73 100644 --- a/include/linux/rtc.h +++ b/include/linux/rtc.h @@ -276,7 +276,7 @@ static inline bool is_leap_year(unsigned int year) return (!(year % 4) && (year % 100)) || !(year % 400); } -#ifdef CONFIG_RTC_HCTOSYS +#ifdef CONFIG_RTC_HCTOSYS_DEVICE extern int rtc_hctosys_ret; #else #define rtc_hctosys_ret -ENODEV diff --git a/include/linux/sched.h b/include/linux/sched.h index 9d51e260bde0..9c5612f0374b 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -405,7 +405,6 @@ static inline void arch_pick_mmap_layout(struct mm_struct *mm) {} extern void set_dumpable(struct mm_struct *mm, int value); extern int get_dumpable(struct mm_struct *mm); -extern int __get_dumpable(unsigned long mm_flags); /* get/set_dumpable() values */ #define SUID_DUMPABLE_DISABLED 0 diff --git a/include/linux/slab.h b/include/linux/slab.h index 0dd2dfa7beca..83d1a1454b7e 100644 --- a/include/linux/slab.h +++ b/include/linux/slab.h @@ -321,7 +321,8 @@ static inline void *kmem_cache_alloc_node(struct kmem_cache *cachep, * request comes from. */ #if defined(CONFIG_DEBUG_SLAB) || defined(CONFIG_SLUB) || \ - (defined(CONFIG_SLAB) && defined(CONFIG_TRACING)) + (defined(CONFIG_SLAB) && defined(CONFIG_TRACING)) || \ + (defined(CONFIG_SLOB) && defined(CONFIG_TRACING)) extern void *__kmalloc_track_caller(size_t, gfp_t, unsigned long); #define kmalloc_track_caller(size, flags) \ __kmalloc_track_caller(size, flags, _RET_IP_) @@ -340,7 +341,8 @@ extern void *__kmalloc_track_caller(size_t, gfp_t, unsigned long); * allocation request comes from. */ #if defined(CONFIG_DEBUG_SLAB) || defined(CONFIG_SLUB) || \ - (defined(CONFIG_SLAB) && defined(CONFIG_TRACING)) + (defined(CONFIG_SLAB) && defined(CONFIG_TRACING)) || \ + (defined(CONFIG_SLOB) && defined(CONFIG_TRACING)) extern void *__kmalloc_node_track_caller(size_t, gfp_t, int, unsigned long); #define kmalloc_node_track_caller(size, flags, node) \ __kmalloc_node_track_caller(size, flags, node, \ diff --git a/include/linux/slab_def.h b/include/linux/slab_def.h index 0c634fa376c9..cc290f0bdb34 100644 --- a/include/linux/slab_def.h +++ b/include/linux/slab_def.h @@ -45,7 +45,6 @@ struct kmem_cache { unsigned int colour_off; /* colour offset */ struct kmem_cache *slabp_cache; unsigned int slab_size; - unsigned int dflags; /* dynamic flags */ /* constructor func */ void (*ctor)(void *obj); @@ -112,19 +111,13 @@ void *kmem_cache_alloc(struct kmem_cache *, gfp_t); void *__kmalloc(size_t size, gfp_t flags); #ifdef CONFIG_TRACING -extern void *kmem_cache_alloc_trace(size_t size, - struct kmem_cache *cachep, gfp_t flags); -extern size_t slab_buffer_size(struct kmem_cache *cachep); +extern void *kmem_cache_alloc_trace(struct kmem_cache *, gfp_t, size_t); #else static __always_inline void * -kmem_cache_alloc_trace(size_t size, struct kmem_cache *cachep, gfp_t flags) +kmem_cache_alloc_trace(struct kmem_cache *cachep, gfp_t flags, size_t size) { return kmem_cache_alloc(cachep, flags); } -static inline size_t slab_buffer_size(struct kmem_cache *cachep) -{ - return 0; -} #endif static __always_inline void *kmalloc(size_t size, gfp_t flags) @@ -154,7 +147,7 @@ found: #endif cachep = malloc_sizes[i].cs_cachep; - ret = kmem_cache_alloc_trace(size, cachep, flags); + ret = kmem_cache_alloc_trace(cachep, flags, size); return ret; } @@ -166,16 +159,16 @@ extern void *__kmalloc_node(size_t size, gfp_t flags, int node); extern void *kmem_cache_alloc_node(struct kmem_cache *, gfp_t flags, int node); #ifdef CONFIG_TRACING -extern void *kmem_cache_alloc_node_trace(size_t size, - struct kmem_cache *cachep, +extern void *kmem_cache_alloc_node_trace(struct kmem_cache *cachep, gfp_t flags, - int nodeid); + int nodeid, + size_t size); #else static __always_inline void * -kmem_cache_alloc_node_trace(size_t size, - struct kmem_cache *cachep, +kmem_cache_alloc_node_trace(struct kmem_cache *cachep, gfp_t flags, - int nodeid) + int nodeid, + size_t size) { return kmem_cache_alloc_node(cachep, flags, nodeid); } @@ -207,7 +200,7 @@ found: #endif cachep = malloc_sizes[i].cs_cachep; - return kmem_cache_alloc_node_trace(size, cachep, flags, node); + return kmem_cache_alloc_node_trace(cachep, flags, node, size); } return __kmalloc_node(size, flags, node); } diff --git a/include/linux/slob_def.h b/include/linux/slob_def.h index 0ec00b39d006..f28e14a12e3f 100644 --- a/include/linux/slob_def.h +++ b/include/linux/slob_def.h @@ -1,12 +1,14 @@ #ifndef __LINUX_SLOB_DEF_H #define __LINUX_SLOB_DEF_H +#include <linux/numa.h> + void *kmem_cache_alloc_node(struct kmem_cache *, gfp_t flags, int node); static __always_inline void *kmem_cache_alloc(struct kmem_cache *cachep, gfp_t flags) { - return kmem_cache_alloc_node(cachep, flags, -1); + return kmem_cache_alloc_node(cachep, flags, NUMA_NO_NODE); } void *__kmalloc_node(size_t size, gfp_t flags, int node); @@ -26,7 +28,7 @@ static __always_inline void *kmalloc_node(size_t size, gfp_t flags, int node) */ static __always_inline void *kmalloc(size_t size, gfp_t flags) { - return __kmalloc_node(size, flags, -1); + return __kmalloc_node(size, flags, NUMA_NO_NODE); } static __always_inline void *__kmalloc(size_t size, gfp_t flags) diff --git a/include/linux/v4l2-common.h b/include/linux/v4l2-common.h index 0fa8b64c3cdb..4f0667e010dd 100644 --- a/include/linux/v4l2-common.h +++ b/include/linux/v4l2-common.h @@ -53,10 +53,10 @@ /* Backward compatibility target definitions --- to be removed. */ #define V4L2_SEL_TGT_CROP_ACTIVE V4L2_SEL_TGT_CROP #define V4L2_SEL_TGT_COMPOSE_ACTIVE V4L2_SEL_TGT_COMPOSE -#define V4L2_SUBDEV_SEL_TGT_CROP_ACTUAL \ - V4L2_SEL_TGT_CROP -#define V4L2_SUBDEV_SEL_TGT_COMPOSE_ACTUAL \ - V4L2_SEL_TGT_COMPOSE +#define V4L2_SUBDEV_SEL_TGT_CROP_ACTUAL V4L2_SEL_TGT_CROP +#define V4L2_SUBDEV_SEL_TGT_COMPOSE_ACTUAL V4L2_SEL_TGT_COMPOSE +#define V4L2_SUBDEV_SEL_TGT_CROP_BOUNDS V4L2_SEL_TGT_CROP_BOUNDS +#define V4L2_SUBDEV_SEL_TGT_COMPOSE_BOUNDS V4L2_SEL_TGT_COMPOSE_BOUNDS /* Selection flags */ #define V4L2_SEL_FLAG_GE (1 << 0) diff --git a/include/linux/v4l2-controls.h b/include/linux/v4l2-controls.h new file mode 100644 index 000000000000..421d24c7f686 --- /dev/null +++ b/include/linux/v4l2-controls.h @@ -0,0 +1,761 @@ +/* + * Video for Linux Two controls header file + * + * Copyright (C) 1999-2012 the contributors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Alternatively you can redistribute this file under the terms of the + * BSD license as stated below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. The names of its contributors may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The contents of this header was split off from videodev2.h. All control + * definitions should be added to this header, which is included by + * videodev2.h. + */ + +#ifndef __LINUX_V4L2_CONTROLS_H +#define __LINUX_V4L2_CONTROLS_H + +/* Control classes */ +#define V4L2_CTRL_CLASS_USER 0x00980000 /* Old-style 'user' controls */ +#define V4L2_CTRL_CLASS_MPEG 0x00990000 /* MPEG-compression controls */ +#define V4L2_CTRL_CLASS_CAMERA 0x009a0000 /* Camera class controls */ +#define V4L2_CTRL_CLASS_FM_TX 0x009b0000 /* FM Modulator control class */ +#define V4L2_CTRL_CLASS_FLASH 0x009c0000 /* Camera flash controls */ +#define V4L2_CTRL_CLASS_JPEG 0x009d0000 /* JPEG-compression controls */ +#define V4L2_CTRL_CLASS_IMAGE_SOURCE 0x009e0000 /* Image source controls */ +#define V4L2_CTRL_CLASS_IMAGE_PROC 0x009f0000 /* Image processing controls */ +#define V4L2_CTRL_CLASS_DV 0x00a00000 /* Digital Video controls */ + +/* User-class control IDs */ + +#define V4L2_CID_BASE (V4L2_CTRL_CLASS_USER | 0x900) +#define V4L2_CID_USER_BASE V4L2_CID_BASE +#define V4L2_CID_USER_CLASS (V4L2_CTRL_CLASS_USER | 1) +#define V4L2_CID_BRIGHTNESS (V4L2_CID_BASE+0) +#define V4L2_CID_CONTRAST (V4L2_CID_BASE+1) +#define V4L2_CID_SATURATION (V4L2_CID_BASE+2) +#define V4L2_CID_HUE (V4L2_CID_BASE+3) +#define V4L2_CID_AUDIO_VOLUME (V4L2_CID_BASE+5) +#define V4L2_CID_AUDIO_BALANCE (V4L2_CID_BASE+6) +#define V4L2_CID_AUDIO_BASS (V4L2_CID_BASE+7) +#define V4L2_CID_AUDIO_TREBLE (V4L2_CID_BASE+8) +#define V4L2_CID_AUDIO_MUTE (V4L2_CID_BASE+9) +#define V4L2_CID_AUDIO_LOUDNESS (V4L2_CID_BASE+10) +#define V4L2_CID_BLACK_LEVEL (V4L2_CID_BASE+11) /* Deprecated */ +#define V4L2_CID_AUTO_WHITE_BALANCE (V4L2_CID_BASE+12) +#define V4L2_CID_DO_WHITE_BALANCE (V4L2_CID_BASE+13) +#define V4L2_CID_RED_BALANCE (V4L2_CID_BASE+14) +#define V4L2_CID_BLUE_BALANCE (V4L2_CID_BASE+15) +#define V4L2_CID_GAMMA (V4L2_CID_BASE+16) +#define V4L2_CID_WHITENESS (V4L2_CID_GAMMA) /* Deprecated */ +#define V4L2_CID_EXPOSURE (V4L2_CID_BASE+17) +#define V4L2_CID_AUTOGAIN (V4L2_CID_BASE+18) +#define V4L2_CID_GAIN (V4L2_CID_BASE+19) +#define V4L2_CID_HFLIP (V4L2_CID_BASE+20) +#define V4L2_CID_VFLIP (V4L2_CID_BASE+21) + +/* Deprecated; use V4L2_CID_PAN_RESET and V4L2_CID_TILT_RESET */ +#define V4L2_CID_HCENTER (V4L2_CID_BASE+22) +#define V4L2_CID_VCENTER (V4L2_CID_BASE+23) + +#define V4L2_CID_POWER_LINE_FREQUENCY (V4L2_CID_BASE+24) +enum v4l2_power_line_frequency { + V4L2_CID_POWER_LINE_FREQUENCY_DISABLED = 0, + V4L2_CID_POWER_LINE_FREQUENCY_50HZ = 1, + V4L2_CID_POWER_LINE_FREQUENCY_60HZ = 2, + V4L2_CID_POWER_LINE_FREQUENCY_AUTO = 3, +}; +#define V4L2_CID_HUE_AUTO (V4L2_CID_BASE+25) +#define V4L2_CID_WHITE_BALANCE_TEMPERATURE (V4L2_CID_BASE+26) +#define V4L2_CID_SHARPNESS (V4L2_CID_BASE+27) +#define V4L2_CID_BACKLIGHT_COMPENSATION (V4L2_CID_BASE+28) +#define V4L2_CID_CHROMA_AGC (V4L2_CID_BASE+29) +#define V4L2_CID_COLOR_KILLER (V4L2_CID_BASE+30) +#define V4L2_CID_COLORFX (V4L2_CID_BASE+31) +enum v4l2_colorfx { + V4L2_COLORFX_NONE = 0, + V4L2_COLORFX_BW = 1, + V4L2_COLORFX_SEPIA = 2, + V4L2_COLORFX_NEGATIVE = 3, + V4L2_COLORFX_EMBOSS = 4, + V4L2_COLORFX_SKETCH = 5, + V4L2_COLORFX_SKY_BLUE = 6, + V4L2_COLORFX_GRASS_GREEN = 7, + V4L2_COLORFX_SKIN_WHITEN = 8, + V4L2_COLORFX_VIVID = 9, + V4L2_COLORFX_AQUA = 10, + V4L2_COLORFX_ART_FREEZE = 11, + V4L2_COLORFX_SILHOUETTE = 12, + V4L2_COLORFX_SOLARIZATION = 13, + V4L2_COLORFX_ANTIQUE = 14, + V4L2_COLORFX_SET_CBCR = 15, +}; +#define V4L2_CID_AUTOBRIGHTNESS (V4L2_CID_BASE+32) +#define V4L2_CID_BAND_STOP_FILTER (V4L2_CID_BASE+33) + +#define V4L2_CID_ROTATE (V4L2_CID_BASE+34) +#define V4L2_CID_BG_COLOR (V4L2_CID_BASE+35) + +#define V4L2_CID_CHROMA_GAIN (V4L2_CID_BASE+36) + +#define V4L2_CID_ILLUMINATORS_1 (V4L2_CID_BASE+37) +#define V4L2_CID_ILLUMINATORS_2 (V4L2_CID_BASE+38) + +#define V4L2_CID_MIN_BUFFERS_FOR_CAPTURE (V4L2_CID_BASE+39) +#define V4L2_CID_MIN_BUFFERS_FOR_OUTPUT (V4L2_CID_BASE+40) + +#define V4L2_CID_ALPHA_COMPONENT (V4L2_CID_BASE+41) +#define V4L2_CID_COLORFX_CBCR (V4L2_CID_BASE+42) + +/* last CID + 1 */ +#define V4L2_CID_LASTP1 (V4L2_CID_BASE+43) + + +/* MPEG-class control IDs */ + +#define V4L2_CID_MPEG_BASE (V4L2_CTRL_CLASS_MPEG | 0x900) +#define V4L2_CID_MPEG_CLASS (V4L2_CTRL_CLASS_MPEG | 1) + +/* MPEG streams, specific to multiplexed streams */ +#define V4L2_CID_MPEG_STREAM_TYPE (V4L2_CID_MPEG_BASE+0) +enum v4l2_mpeg_stream_type { + V4L2_MPEG_STREAM_TYPE_MPEG2_PS = 0, /* MPEG-2 program stream */ + V4L2_MPEG_STREAM_TYPE_MPEG2_TS = 1, /* MPEG-2 transport stream */ + V4L2_MPEG_STREAM_TYPE_MPEG1_SS = 2, /* MPEG-1 system stream */ + V4L2_MPEG_STREAM_TYPE_MPEG2_DVD = 3, /* MPEG-2 DVD-compatible stream */ + V4L2_MPEG_STREAM_TYPE_MPEG1_VCD = 4, /* MPEG-1 VCD-compatible stream */ + V4L2_MPEG_STREAM_TYPE_MPEG2_SVCD = 5, /* MPEG-2 SVCD-compatible stream */ +}; +#define V4L2_CID_MPEG_STREAM_PID_PMT (V4L2_CID_MPEG_BASE+1) +#define V4L2_CID_MPEG_STREAM_PID_AUDIO (V4L2_CID_MPEG_BASE+2) +#define V4L2_CID_MPEG_STREAM_PID_VIDEO (V4L2_CID_MPEG_BASE+3) +#define V4L2_CID_MPEG_STREAM_PID_PCR (V4L2_CID_MPEG_BASE+4) +#define V4L2_CID_MPEG_STREAM_PES_ID_AUDIO (V4L2_CID_MPEG_BASE+5) +#define V4L2_CID_MPEG_STREAM_PES_ID_VIDEO (V4L2_CID_MPEG_BASE+6) +#define V4L2_CID_MPEG_STREAM_VBI_FMT (V4L2_CID_MPEG_BASE+7) +enum v4l2_mpeg_stream_vbi_fmt { + V4L2_MPEG_STREAM_VBI_FMT_NONE = 0, /* No VBI in the MPEG stream */ + V4L2_MPEG_STREAM_VBI_FMT_IVTV = 1, /* VBI in private packets, IVTV format */ +}; + +/* MPEG audio controls specific to multiplexed streams */ +#define V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ (V4L2_CID_MPEG_BASE+100) +enum v4l2_mpeg_audio_sampling_freq { + V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100 = 0, + V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000 = 1, + V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000 = 2, +}; +#define V4L2_CID_MPEG_AUDIO_ENCODING (V4L2_CID_MPEG_BASE+101) +enum v4l2_mpeg_audio_encoding { + V4L2_MPEG_AUDIO_ENCODING_LAYER_1 = 0, + V4L2_MPEG_AUDIO_ENCODING_LAYER_2 = 1, + V4L2_MPEG_AUDIO_ENCODING_LAYER_3 = 2, + V4L2_MPEG_AUDIO_ENCODING_AAC = 3, + V4L2_MPEG_AUDIO_ENCODING_AC3 = 4, +}; +#define V4L2_CID_MPEG_AUDIO_L1_BITRATE (V4L2_CID_MPEG_BASE+102) +enum v4l2_mpeg_audio_l1_bitrate { + V4L2_MPEG_AUDIO_L1_BITRATE_32K = 0, + V4L2_MPEG_AUDIO_L1_BITRATE_64K = 1, + V4L2_MPEG_AUDIO_L1_BITRATE_96K = 2, + V4L2_MPEG_AUDIO_L1_BITRATE_128K = 3, + V4L2_MPEG_AUDIO_L1_BITRATE_160K = 4, + V4L2_MPEG_AUDIO_L1_BITRATE_192K = 5, + V4L2_MPEG_AUDIO_L1_BITRATE_224K = 6, + V4L2_MPEG_AUDIO_L1_BITRATE_256K = 7, + V4L2_MPEG_AUDIO_L1_BITRATE_288K = 8, + V4L2_MPEG_AUDIO_L1_BITRATE_320K = 9, + V4L2_MPEG_AUDIO_L1_BITRATE_352K = 10, + V4L2_MPEG_AUDIO_L1_BITRATE_384K = 11, + V4L2_MPEG_AUDIO_L1_BITRATE_416K = 12, + V4L2_MPEG_AUDIO_L1_BITRATE_448K = 13, +}; +#define V4L2_CID_MPEG_AUDIO_L2_BITRATE (V4L2_CID_MPEG_BASE+103) +enum v4l2_mpeg_audio_l2_bitrate { + V4L2_MPEG_AUDIO_L2_BITRATE_32K = 0, + V4L2_MPEG_AUDIO_L2_BITRATE_48K = 1, + V4L2_MPEG_AUDIO_L2_BITRATE_56K = 2, + V4L2_MPEG_AUDIO_L2_BITRATE_64K = 3, + V4L2_MPEG_AUDIO_L2_BITRATE_80K = 4, + V4L2_MPEG_AUDIO_L2_BITRATE_96K = 5, + V4L2_MPEG_AUDIO_L2_BITRATE_112K = 6, + V4L2_MPEG_AUDIO_L2_BITRATE_128K = 7, + V4L2_MPEG_AUDIO_L2_BITRATE_160K = 8, + V4L2_MPEG_AUDIO_L2_BITRATE_192K = 9, + V4L2_MPEG_AUDIO_L2_BITRATE_224K = 10, + V4L2_MPEG_AUDIO_L2_BITRATE_256K = 11, + V4L2_MPEG_AUDIO_L2_BITRATE_320K = 12, + V4L2_MPEG_AUDIO_L2_BITRATE_384K = 13, +}; +#define V4L2_CID_MPEG_AUDIO_L3_BITRATE (V4L2_CID_MPEG_BASE+104) +enum v4l2_mpeg_audio_l3_bitrate { + V4L2_MPEG_AUDIO_L3_BITRATE_32K = 0, + V4L2_MPEG_AUDIO_L3_BITRATE_40K = 1, + V4L2_MPEG_AUDIO_L3_BITRATE_48K = 2, + V4L2_MPEG_AUDIO_L3_BITRATE_56K = 3, + V4L2_MPEG_AUDIO_L3_BITRATE_64K = 4, + V4L2_MPEG_AUDIO_L3_BITRATE_80K = 5, + V4L2_MPEG_AUDIO_L3_BITRATE_96K = 6, + V4L2_MPEG_AUDIO_L3_BITRATE_112K = 7, + V4L2_MPEG_AUDIO_L3_BITRATE_128K = 8, + V4L2_MPEG_AUDIO_L3_BITRATE_160K = 9, + V4L2_MPEG_AUDIO_L3_BITRATE_192K = 10, + V4L2_MPEG_AUDIO_L3_BITRATE_224K = 11, + V4L2_MPEG_AUDIO_L3_BITRATE_256K = 12, + V4L2_MPEG_AUDIO_L3_BITRATE_320K = 13, +}; +#define V4L2_CID_MPEG_AUDIO_MODE (V4L2_CID_MPEG_BASE+105) +enum v4l2_mpeg_audio_mode { + V4L2_MPEG_AUDIO_MODE_STEREO = 0, + V4L2_MPEG_AUDIO_MODE_JOINT_STEREO = 1, + V4L2_MPEG_AUDIO_MODE_DUAL = 2, + V4L2_MPEG_AUDIO_MODE_MONO = 3, +}; +#define V4L2_CID_MPEG_AUDIO_MODE_EXTENSION (V4L2_CID_MPEG_BASE+106) +enum v4l2_mpeg_audio_mode_extension { + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_4 = 0, + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_8 = 1, + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_12 = 2, + V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_16 = 3, +}; +#define V4L2_CID_MPEG_AUDIO_EMPHASIS (V4L2_CID_MPEG_BASE+107) +enum v4l2_mpeg_audio_emphasis { + V4L2_MPEG_AUDIO_EMPHASIS_NONE = 0, + V4L2_MPEG_AUDIO_EMPHASIS_50_DIV_15_uS = 1, + V4L2_MPEG_AUDIO_EMPHASIS_CCITT_J17 = 2, +}; +#define V4L2_CID_MPEG_AUDIO_CRC (V4L2_CID_MPEG_BASE+108) +enum v4l2_mpeg_audio_crc { + V4L2_MPEG_AUDIO_CRC_NONE = 0, + V4L2_MPEG_AUDIO_CRC_CRC16 = 1, +}; +#define V4L2_CID_MPEG_AUDIO_MUTE (V4L2_CID_MPEG_BASE+109) +#define V4L2_CID_MPEG_AUDIO_AAC_BITRATE (V4L2_CID_MPEG_BASE+110) +#define V4L2_CID_MPEG_AUDIO_AC3_BITRATE (V4L2_CID_MPEG_BASE+111) +enum v4l2_mpeg_audio_ac3_bitrate { + V4L2_MPEG_AUDIO_AC3_BITRATE_32K = 0, + V4L2_MPEG_AUDIO_AC3_BITRATE_40K = 1, + V4L2_MPEG_AUDIO_AC3_BITRATE_48K = 2, + V4L2_MPEG_AUDIO_AC3_BITRATE_56K = 3, + V4L2_MPEG_AUDIO_AC3_BITRATE_64K = 4, + V4L2_MPEG_AUDIO_AC3_BITRATE_80K = 5, + V4L2_MPEG_AUDIO_AC3_BITRATE_96K = 6, + V4L2_MPEG_AUDIO_AC3_BITRATE_112K = 7, + V4L2_MPEG_AUDIO_AC3_BITRATE_128K = 8, + V4L2_MPEG_AUDIO_AC3_BITRATE_160K = 9, + V4L2_MPEG_AUDIO_AC3_BITRATE_192K = 10, + V4L2_MPEG_AUDIO_AC3_BITRATE_224K = 11, + V4L2_MPEG_AUDIO_AC3_BITRATE_256K = 12, + V4L2_MPEG_AUDIO_AC3_BITRATE_320K = 13, + V4L2_MPEG_AUDIO_AC3_BITRATE_384K = 14, + V4L2_MPEG_AUDIO_AC3_BITRATE_448K = 15, + V4L2_MPEG_AUDIO_AC3_BITRATE_512K = 16, + V4L2_MPEG_AUDIO_AC3_BITRATE_576K = 17, + V4L2_MPEG_AUDIO_AC3_BITRATE_640K = 18, +}; +#define V4L2_CID_MPEG_AUDIO_DEC_PLAYBACK (V4L2_CID_MPEG_BASE+112) +enum v4l2_mpeg_audio_dec_playback { + V4L2_MPEG_AUDIO_DEC_PLAYBACK_AUTO = 0, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_STEREO = 1, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_LEFT = 2, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_RIGHT = 3, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_MONO = 4, + V4L2_MPEG_AUDIO_DEC_PLAYBACK_SWAPPED_STEREO = 5, +}; +#define V4L2_CID_MPEG_AUDIO_DEC_MULTILINGUAL_PLAYBACK (V4L2_CID_MPEG_BASE+113) + +/* MPEG video controls specific to multiplexed streams */ +#define V4L2_CID_MPEG_VIDEO_ENCODING (V4L2_CID_MPEG_BASE+200) +enum v4l2_mpeg_video_encoding { + V4L2_MPEG_VIDEO_ENCODING_MPEG_1 = 0, + V4L2_MPEG_VIDEO_ENCODING_MPEG_2 = 1, + V4L2_MPEG_VIDEO_ENCODING_MPEG_4_AVC = 2, +}; +#define V4L2_CID_MPEG_VIDEO_ASPECT (V4L2_CID_MPEG_BASE+201) +enum v4l2_mpeg_video_aspect { + V4L2_MPEG_VIDEO_ASPECT_1x1 = 0, + V4L2_MPEG_VIDEO_ASPECT_4x3 = 1, + V4L2_MPEG_VIDEO_ASPECT_16x9 = 2, + V4L2_MPEG_VIDEO_ASPECT_221x100 = 3, +}; +#define V4L2_CID_MPEG_VIDEO_B_FRAMES (V4L2_CID_MPEG_BASE+202) +#define V4L2_CID_MPEG_VIDEO_GOP_SIZE (V4L2_CID_MPEG_BASE+203) +#define V4L2_CID_MPEG_VIDEO_GOP_CLOSURE (V4L2_CID_MPEG_BASE+204) +#define V4L2_CID_MPEG_VIDEO_PULLDOWN (V4L2_CID_MPEG_BASE+205) +#define V4L2_CID_MPEG_VIDEO_BITRATE_MODE (V4L2_CID_MPEG_BASE+206) +enum v4l2_mpeg_video_bitrate_mode { + V4L2_MPEG_VIDEO_BITRATE_MODE_VBR = 0, + V4L2_MPEG_VIDEO_BITRATE_MODE_CBR = 1, +}; +#define V4L2_CID_MPEG_VIDEO_BITRATE (V4L2_CID_MPEG_BASE+207) +#define V4L2_CID_MPEG_VIDEO_BITRATE_PEAK (V4L2_CID_MPEG_BASE+208) +#define V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION (V4L2_CID_MPEG_BASE+209) +#define V4L2_CID_MPEG_VIDEO_MUTE (V4L2_CID_MPEG_BASE+210) +#define V4L2_CID_MPEG_VIDEO_MUTE_YUV (V4L2_CID_MPEG_BASE+211) +#define V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE (V4L2_CID_MPEG_BASE+212) +#define V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER (V4L2_CID_MPEG_BASE+213) +#define V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB (V4L2_CID_MPEG_BASE+214) +#define V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE (V4L2_CID_MPEG_BASE+215) +#define V4L2_CID_MPEG_VIDEO_HEADER_MODE (V4L2_CID_MPEG_BASE+216) +enum v4l2_mpeg_video_header_mode { + V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE = 0, + V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME = 1, + +}; +#define V4L2_CID_MPEG_VIDEO_MAX_REF_PIC (V4L2_CID_MPEG_BASE+217) +#define V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE (V4L2_CID_MPEG_BASE+218) +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES (V4L2_CID_MPEG_BASE+219) +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB (V4L2_CID_MPEG_BASE+220) +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE (V4L2_CID_MPEG_BASE+221) +enum v4l2_mpeg_video_multi_slice_mode { + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE = 0, + V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB = 1, + V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES = 2, +}; +#define V4L2_CID_MPEG_VIDEO_VBV_SIZE (V4L2_CID_MPEG_BASE+222) +#define V4L2_CID_MPEG_VIDEO_DEC_PTS (V4L2_CID_MPEG_BASE+223) +#define V4L2_CID_MPEG_VIDEO_DEC_FRAME (V4L2_CID_MPEG_BASE+224) + +#define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP (V4L2_CID_MPEG_BASE+300) +#define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP (V4L2_CID_MPEG_BASE+301) +#define V4L2_CID_MPEG_VIDEO_H263_B_FRAME_QP (V4L2_CID_MPEG_BASE+302) +#define V4L2_CID_MPEG_VIDEO_H263_MIN_QP (V4L2_CID_MPEG_BASE+303) +#define V4L2_CID_MPEG_VIDEO_H263_MAX_QP (V4L2_CID_MPEG_BASE+304) +#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP (V4L2_CID_MPEG_BASE+350) +#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP (V4L2_CID_MPEG_BASE+351) +#define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP (V4L2_CID_MPEG_BASE+352) +#define V4L2_CID_MPEG_VIDEO_H264_MIN_QP (V4L2_CID_MPEG_BASE+353) +#define V4L2_CID_MPEG_VIDEO_H264_MAX_QP (V4L2_CID_MPEG_BASE+354) +#define V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM (V4L2_CID_MPEG_BASE+355) +#define V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE (V4L2_CID_MPEG_BASE+356) +#define V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE (V4L2_CID_MPEG_BASE+357) +enum v4l2_mpeg_video_h264_entropy_mode { + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC = 0, + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC = 1, +}; +#define V4L2_CID_MPEG_VIDEO_H264_I_PERIOD (V4L2_CID_MPEG_BASE+358) +#define V4L2_CID_MPEG_VIDEO_H264_LEVEL (V4L2_CID_MPEG_BASE+359) +enum v4l2_mpeg_video_h264_level { + V4L2_MPEG_VIDEO_H264_LEVEL_1_0 = 0, + V4L2_MPEG_VIDEO_H264_LEVEL_1B = 1, + V4L2_MPEG_VIDEO_H264_LEVEL_1_1 = 2, + V4L2_MPEG_VIDEO_H264_LEVEL_1_2 = 3, + V4L2_MPEG_VIDEO_H264_LEVEL_1_3 = 4, + V4L2_MPEG_VIDEO_H264_LEVEL_2_0 = 5, + V4L2_MPEG_VIDEO_H264_LEVEL_2_1 = 6, + V4L2_MPEG_VIDEO_H264_LEVEL_2_2 = 7, + V4L2_MPEG_VIDEO_H264_LEVEL_3_0 = 8, + V4L2_MPEG_VIDEO_H264_LEVEL_3_1 = 9, + V4L2_MPEG_VIDEO_H264_LEVEL_3_2 = 10, + V4L2_MPEG_VIDEO_H264_LEVEL_4_0 = 11, + V4L2_MPEG_VIDEO_H264_LEVEL_4_1 = 12, + V4L2_MPEG_VIDEO_H264_LEVEL_4_2 = 13, + V4L2_MPEG_VIDEO_H264_LEVEL_5_0 = 14, + V4L2_MPEG_VIDEO_H264_LEVEL_5_1 = 15, +}; +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA (V4L2_CID_MPEG_BASE+360) +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA (V4L2_CID_MPEG_BASE+361) +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE (V4L2_CID_MPEG_BASE+362) +enum v4l2_mpeg_video_h264_loop_filter_mode { + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED = 0, + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED = 1, + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY = 2, +}; +#define V4L2_CID_MPEG_VIDEO_H264_PROFILE (V4L2_CID_MPEG_BASE+363) +enum v4l2_mpeg_video_h264_profile { + V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE = 0, + V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE = 1, + V4L2_MPEG_VIDEO_H264_PROFILE_MAIN = 2, + V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED = 3, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH = 4, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10 = 5, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422 = 6, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE = 7, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10_INTRA = 8, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422_INTRA = 9, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_INTRA = 10, + V4L2_MPEG_VIDEO_H264_PROFILE_CAVLC_444_INTRA = 11, + V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_BASELINE = 12, + V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH = 13, + V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH_INTRA = 14, + V4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH = 15, + V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH = 16, +}; +#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT (V4L2_CID_MPEG_BASE+364) +#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH (V4L2_CID_MPEG_BASE+365) +#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE (V4L2_CID_MPEG_BASE+366) +#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC (V4L2_CID_MPEG_BASE+367) +enum v4l2_mpeg_video_h264_vui_sar_idc { + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED = 0, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1 = 1, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_12x11 = 2, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_10x11 = 3, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_16x11 = 4, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_40x33 = 5, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_24x11 = 6, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_20x11 = 7, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_32x11 = 8, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_80x33 = 9, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_18x11 = 10, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_15x11 = 11, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_64x33 = 12, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_160x99 = 13, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_4x3 = 14, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_3x2 = 15, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_2x1 = 16, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED = 17, +}; +#define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (V4L2_CID_MPEG_BASE+400) +#define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP (V4L2_CID_MPEG_BASE+401) +#define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP (V4L2_CID_MPEG_BASE+402) +#define V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP (V4L2_CID_MPEG_BASE+403) +#define V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP (V4L2_CID_MPEG_BASE+404) +#define V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL (V4L2_CID_MPEG_BASE+405) +enum v4l2_mpeg_video_mpeg4_level { + V4L2_MPEG_VIDEO_MPEG4_LEVEL_0 = 0, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_0B = 1, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_1 = 2, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_2 = 3, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_3 = 4, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_3B = 5, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_4 = 6, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_5 = 7, +}; +#define V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE (V4L2_CID_MPEG_BASE+406) +enum v4l2_mpeg_video_mpeg4_profile { + V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE = 0, + V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE = 1, + V4L2_MPEG_VIDEO_MPEG4_PROFILE_CORE = 2, + V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE_SCALABLE = 3, + V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_CODING_EFFICIENCY = 4, +}; +#define V4L2_CID_MPEG_VIDEO_MPEG4_QPEL (V4L2_CID_MPEG_BASE+407) + +/* MPEG-class control IDs specific to the CX2341x driver as defined by V4L2 */ +#define V4L2_CID_MPEG_CX2341X_BASE (V4L2_CTRL_CLASS_MPEG | 0x1000) +#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+0) +enum v4l2_mpeg_cx2341x_video_spatial_filter_mode { + V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_MANUAL = 0, + V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_AUTO = 1, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE+1) +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+2) +enum v4l2_mpeg_cx2341x_video_luma_spatial_filter_type { + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_OFF = 0, + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_HOR = 1, + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_VERT = 2, + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_HV_SEPARABLE = 3, + V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_SYM_NON_SEPARABLE = 4, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+3) +enum v4l2_mpeg_cx2341x_video_chroma_spatial_filter_type { + V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_OFF = 0, + V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_1D_HOR = 1, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+4) +enum v4l2_mpeg_cx2341x_video_temporal_filter_mode { + V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_MANUAL = 0, + V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_AUTO = 1, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE+5) +#define V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+6) +enum v4l2_mpeg_cx2341x_video_median_filter_type { + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_OFF = 0, + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR = 1, + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_VERT = 2, + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR_VERT = 3, + V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_DIAG = 4, +}; +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE+7) +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+8) +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE+9) +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+10) +#define V4L2_CID_MPEG_CX2341X_STREAM_INSERT_NAV_PACKETS (V4L2_CID_MPEG_CX2341X_BASE+11) + +/* MPEG-class control IDs specific to the Samsung MFC 5.1 driver as defined by V4L2 */ +#define V4L2_CID_MPEG_MFC51_BASE (V4L2_CTRL_CLASS_MPEG | 0x1100) + +#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY (V4L2_CID_MPEG_MFC51_BASE+0) +#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY_ENABLE (V4L2_CID_MPEG_MFC51_BASE+1) +#define V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE (V4L2_CID_MPEG_MFC51_BASE+2) +enum v4l2_mpeg_mfc51_video_frame_skip_mode { + V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_DISABLED = 0, + V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT = 1, + V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT = 2, +}; +#define V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE (V4L2_CID_MPEG_MFC51_BASE+3) +enum v4l2_mpeg_mfc51_video_force_frame_type { + V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_DISABLED = 0, + V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_I_FRAME = 1, + V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_NOT_CODED = 2, +}; +#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING (V4L2_CID_MPEG_MFC51_BASE+4) +#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV (V4L2_CID_MPEG_MFC51_BASE+5) +#define V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT (V4L2_CID_MPEG_MFC51_BASE+6) +#define V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF (V4L2_CID_MPEG_MFC51_BASE+7) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY (V4L2_CID_MPEG_MFC51_BASE+50) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK (V4L2_CID_MPEG_MFC51_BASE+51) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH (V4L2_CID_MPEG_MFC51_BASE+52) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC (V4L2_CID_MPEG_MFC51_BASE+53) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P (V4L2_CID_MPEG_MFC51_BASE+54) + + +/* Camera class control IDs */ + +#define V4L2_CID_CAMERA_CLASS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x900) +#define V4L2_CID_CAMERA_CLASS (V4L2_CTRL_CLASS_CAMERA | 1) + +#define V4L2_CID_EXPOSURE_AUTO (V4L2_CID_CAMERA_CLASS_BASE+1) +enum v4l2_exposure_auto_type { + V4L2_EXPOSURE_AUTO = 0, + V4L2_EXPOSURE_MANUAL = 1, + V4L2_EXPOSURE_SHUTTER_PRIORITY = 2, + V4L2_EXPOSURE_APERTURE_PRIORITY = 3 +}; +#define V4L2_CID_EXPOSURE_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+2) +#define V4L2_CID_EXPOSURE_AUTO_PRIORITY (V4L2_CID_CAMERA_CLASS_BASE+3) + +#define V4L2_CID_PAN_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+4) +#define V4L2_CID_TILT_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+5) +#define V4L2_CID_PAN_RESET (V4L2_CID_CAMERA_CLASS_BASE+6) +#define V4L2_CID_TILT_RESET (V4L2_CID_CAMERA_CLASS_BASE+7) + +#define V4L2_CID_PAN_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+8) +#define V4L2_CID_TILT_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+9) + +#define V4L2_CID_FOCUS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+10) +#define V4L2_CID_FOCUS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+11) +#define V4L2_CID_FOCUS_AUTO (V4L2_CID_CAMERA_CLASS_BASE+12) + +#define V4L2_CID_ZOOM_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+13) +#define V4L2_CID_ZOOM_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+14) +#define V4L2_CID_ZOOM_CONTINUOUS (V4L2_CID_CAMERA_CLASS_BASE+15) + +#define V4L2_CID_PRIVACY (V4L2_CID_CAMERA_CLASS_BASE+16) + +#define V4L2_CID_IRIS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+17) +#define V4L2_CID_IRIS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+18) + +#define V4L2_CID_AUTO_EXPOSURE_BIAS (V4L2_CID_CAMERA_CLASS_BASE+19) + +#define V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE (V4L2_CID_CAMERA_CLASS_BASE+20) +enum v4l2_auto_n_preset_white_balance { + V4L2_WHITE_BALANCE_MANUAL = 0, + V4L2_WHITE_BALANCE_AUTO = 1, + V4L2_WHITE_BALANCE_INCANDESCENT = 2, + V4L2_WHITE_BALANCE_FLUORESCENT = 3, + V4L2_WHITE_BALANCE_FLUORESCENT_H = 4, + V4L2_WHITE_BALANCE_HORIZON = 5, + V4L2_WHITE_BALANCE_DAYLIGHT = 6, + V4L2_WHITE_BALANCE_FLASH = 7, + V4L2_WHITE_BALANCE_CLOUDY = 8, + V4L2_WHITE_BALANCE_SHADE = 9, +}; + +#define V4L2_CID_WIDE_DYNAMIC_RANGE (V4L2_CID_CAMERA_CLASS_BASE+21) +#define V4L2_CID_IMAGE_STABILIZATION (V4L2_CID_CAMERA_CLASS_BASE+22) + +#define V4L2_CID_ISO_SENSITIVITY (V4L2_CID_CAMERA_CLASS_BASE+23) +#define V4L2_CID_ISO_SENSITIVITY_AUTO (V4L2_CID_CAMERA_CLASS_BASE+24) +enum v4l2_iso_sensitivity_auto_type { + V4L2_ISO_SENSITIVITY_MANUAL = 0, + V4L2_ISO_SENSITIVITY_AUTO = 1, +}; + +#define V4L2_CID_EXPOSURE_METERING (V4L2_CID_CAMERA_CLASS_BASE+25) +enum v4l2_exposure_metering { + V4L2_EXPOSURE_METERING_AVERAGE = 0, + V4L2_EXPOSURE_METERING_CENTER_WEIGHTED = 1, + V4L2_EXPOSURE_METERING_SPOT = 2, +}; + +#define V4L2_CID_SCENE_MODE (V4L2_CID_CAMERA_CLASS_BASE+26) +enum v4l2_scene_mode { + V4L2_SCENE_MODE_NONE = 0, + V4L2_SCENE_MODE_BACKLIGHT = 1, + V4L2_SCENE_MODE_BEACH_SNOW = 2, + V4L2_SCENE_MODE_CANDLE_LIGHT = 3, + V4L2_SCENE_MODE_DAWN_DUSK = 4, + V4L2_SCENE_MODE_FALL_COLORS = 5, + V4L2_SCENE_MODE_FIREWORKS = 6, + V4L2_SCENE_MODE_LANDSCAPE = 7, + V4L2_SCENE_MODE_NIGHT = 8, + V4L2_SCENE_MODE_PARTY_INDOOR = 9, + V4L2_SCENE_MODE_PORTRAIT = 10, + V4L2_SCENE_MODE_SPORTS = 11, + V4L2_SCENE_MODE_SUNSET = 12, + V4L2_SCENE_MODE_TEXT = 13, +}; + +#define V4L2_CID_3A_LOCK (V4L2_CID_CAMERA_CLASS_BASE+27) +#define V4L2_LOCK_EXPOSURE (1 << 0) +#define V4L2_LOCK_WHITE_BALANCE (1 << 1) +#define V4L2_LOCK_FOCUS (1 << 2) + +#define V4L2_CID_AUTO_FOCUS_START (V4L2_CID_CAMERA_CLASS_BASE+28) +#define V4L2_CID_AUTO_FOCUS_STOP (V4L2_CID_CAMERA_CLASS_BASE+29) +#define V4L2_CID_AUTO_FOCUS_STATUS (V4L2_CID_CAMERA_CLASS_BASE+30) +#define V4L2_AUTO_FOCUS_STATUS_IDLE (0 << 0) +#define V4L2_AUTO_FOCUS_STATUS_BUSY (1 << 0) +#define V4L2_AUTO_FOCUS_STATUS_REACHED (1 << 1) +#define V4L2_AUTO_FOCUS_STATUS_FAILED (1 << 2) + +#define V4L2_CID_AUTO_FOCUS_RANGE (V4L2_CID_CAMERA_CLASS_BASE+31) +enum v4l2_auto_focus_range { + V4L2_AUTO_FOCUS_RANGE_AUTO = 0, + V4L2_AUTO_FOCUS_RANGE_NORMAL = 1, + V4L2_AUTO_FOCUS_RANGE_MACRO = 2, + V4L2_AUTO_FOCUS_RANGE_INFINITY = 3, +}; + + +/* FM Modulator class control IDs */ + +#define V4L2_CID_FM_TX_CLASS_BASE (V4L2_CTRL_CLASS_FM_TX | 0x900) +#define V4L2_CID_FM_TX_CLASS (V4L2_CTRL_CLASS_FM_TX | 1) + +#define V4L2_CID_RDS_TX_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 1) +#define V4L2_CID_RDS_TX_PI (V4L2_CID_FM_TX_CLASS_BASE + 2) +#define V4L2_CID_RDS_TX_PTY (V4L2_CID_FM_TX_CLASS_BASE + 3) +#define V4L2_CID_RDS_TX_PS_NAME (V4L2_CID_FM_TX_CLASS_BASE + 5) +#define V4L2_CID_RDS_TX_RADIO_TEXT (V4L2_CID_FM_TX_CLASS_BASE + 6) + +#define V4L2_CID_AUDIO_LIMITER_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 64) +#define V4L2_CID_AUDIO_LIMITER_RELEASE_TIME (V4L2_CID_FM_TX_CLASS_BASE + 65) +#define V4L2_CID_AUDIO_LIMITER_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 66) + +#define V4L2_CID_AUDIO_COMPRESSION_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 80) +#define V4L2_CID_AUDIO_COMPRESSION_GAIN (V4L2_CID_FM_TX_CLASS_BASE + 81) +#define V4L2_CID_AUDIO_COMPRESSION_THRESHOLD (V4L2_CID_FM_TX_CLASS_BASE + 82) +#define V4L2_CID_AUDIO_COMPRESSION_ATTACK_TIME (V4L2_CID_FM_TX_CLASS_BASE + 83) +#define V4L2_CID_AUDIO_COMPRESSION_RELEASE_TIME (V4L2_CID_FM_TX_CLASS_BASE + 84) + +#define V4L2_CID_PILOT_TONE_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 96) +#define V4L2_CID_PILOT_TONE_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 97) +#define V4L2_CID_PILOT_TONE_FREQUENCY (V4L2_CID_FM_TX_CLASS_BASE + 98) + +#define V4L2_CID_TUNE_PREEMPHASIS (V4L2_CID_FM_TX_CLASS_BASE + 112) +enum v4l2_preemphasis { + V4L2_PREEMPHASIS_DISABLED = 0, + V4L2_PREEMPHASIS_50_uS = 1, + V4L2_PREEMPHASIS_75_uS = 2, +}; +#define V4L2_CID_TUNE_POWER_LEVEL (V4L2_CID_FM_TX_CLASS_BASE + 113) +#define V4L2_CID_TUNE_ANTENNA_CAPACITOR (V4L2_CID_FM_TX_CLASS_BASE + 114) + + +/* Flash and privacy (indicator) light controls */ + +#define V4L2_CID_FLASH_CLASS_BASE (V4L2_CTRL_CLASS_FLASH | 0x900) +#define V4L2_CID_FLASH_CLASS (V4L2_CTRL_CLASS_FLASH | 1) + +#define V4L2_CID_FLASH_LED_MODE (V4L2_CID_FLASH_CLASS_BASE + 1) +enum v4l2_flash_led_mode { + V4L2_FLASH_LED_MODE_NONE, + V4L2_FLASH_LED_MODE_FLASH, + V4L2_FLASH_LED_MODE_TORCH, +}; + +#define V4L2_CID_FLASH_STROBE_SOURCE (V4L2_CID_FLASH_CLASS_BASE + 2) +enum v4l2_flash_strobe_source { + V4L2_FLASH_STROBE_SOURCE_SOFTWARE, + V4L2_FLASH_STROBE_SOURCE_EXTERNAL, +}; + +#define V4L2_CID_FLASH_STROBE (V4L2_CID_FLASH_CLASS_BASE + 3) +#define V4L2_CID_FLASH_STROBE_STOP (V4L2_CID_FLASH_CLASS_BASE + 4) +#define V4L2_CID_FLASH_STROBE_STATUS (V4L2_CID_FLASH_CLASS_BASE + 5) + +#define V4L2_CID_FLASH_TIMEOUT (V4L2_CID_FLASH_CLASS_BASE + 6) +#define V4L2_CID_FLASH_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 7) +#define V4L2_CID_FLASH_TORCH_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 8) +#define V4L2_CID_FLASH_INDICATOR_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 9) + +#define V4L2_CID_FLASH_FAULT (V4L2_CID_FLASH_CLASS_BASE + 10) +#define V4L2_FLASH_FAULT_OVER_VOLTAGE (1 << 0) +#define V4L2_FLASH_FAULT_TIMEOUT (1 << 1) +#define V4L2_FLASH_FAULT_OVER_TEMPERATURE (1 << 2) +#define V4L2_FLASH_FAULT_SHORT_CIRCUIT (1 << 3) +#define V4L2_FLASH_FAULT_OVER_CURRENT (1 << 4) +#define V4L2_FLASH_FAULT_INDICATOR (1 << 5) + +#define V4L2_CID_FLASH_CHARGE (V4L2_CID_FLASH_CLASS_BASE + 11) +#define V4L2_CID_FLASH_READY (V4L2_CID_FLASH_CLASS_BASE + 12) + + +/* JPEG-class control IDs */ + +#define V4L2_CID_JPEG_CLASS_BASE (V4L2_CTRL_CLASS_JPEG | 0x900) +#define V4L2_CID_JPEG_CLASS (V4L2_CTRL_CLASS_JPEG | 1) + +#define V4L2_CID_JPEG_CHROMA_SUBSAMPLING (V4L2_CID_JPEG_CLASS_BASE + 1) +enum v4l2_jpeg_chroma_subsampling { + V4L2_JPEG_CHROMA_SUBSAMPLING_444 = 0, + V4L2_JPEG_CHROMA_SUBSAMPLING_422 = 1, + V4L2_JPEG_CHROMA_SUBSAMPLING_420 = 2, + V4L2_JPEG_CHROMA_SUBSAMPLING_411 = 3, + V4L2_JPEG_CHROMA_SUBSAMPLING_410 = 4, + V4L2_JPEG_CHROMA_SUBSAMPLING_GRAY = 5, +}; +#define V4L2_CID_JPEG_RESTART_INTERVAL (V4L2_CID_JPEG_CLASS_BASE + 2) +#define V4L2_CID_JPEG_COMPRESSION_QUALITY (V4L2_CID_JPEG_CLASS_BASE + 3) + +#define V4L2_CID_JPEG_ACTIVE_MARKER (V4L2_CID_JPEG_CLASS_BASE + 4) +#define V4L2_JPEG_ACTIVE_MARKER_APP0 (1 << 0) +#define V4L2_JPEG_ACTIVE_MARKER_APP1 (1 << 1) +#define V4L2_JPEG_ACTIVE_MARKER_COM (1 << 16) +#define V4L2_JPEG_ACTIVE_MARKER_DQT (1 << 17) +#define V4L2_JPEG_ACTIVE_MARKER_DHT (1 << 18) + +/* Image source controls */ +#define V4L2_CID_IMAGE_SOURCE_CLASS_BASE (V4L2_CTRL_CLASS_IMAGE_SOURCE | 0x900) +#define V4L2_CID_IMAGE_SOURCE_CLASS (V4L2_CTRL_CLASS_IMAGE_SOURCE | 1) + +#define V4L2_CID_VBLANK (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 1) +#define V4L2_CID_HBLANK (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 2) +#define V4L2_CID_ANALOGUE_GAIN (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 3) + + +/* Image processing controls */ + +#define V4L2_CID_IMAGE_PROC_CLASS_BASE (V4L2_CTRL_CLASS_IMAGE_PROC | 0x900) +#define V4L2_CID_IMAGE_PROC_CLASS (V4L2_CTRL_CLASS_IMAGE_PROC | 1) + +#define V4L2_CID_LINK_FREQ (V4L2_CID_IMAGE_PROC_CLASS_BASE + 1) +#define V4L2_CID_PIXEL_RATE (V4L2_CID_IMAGE_PROC_CLASS_BASE + 2) + +#endif diff --git a/include/linux/v4l2-subdev.h b/include/linux/v4l2-subdev.h index 8c57ee9872bb..a33c4daadce3 100644 --- a/include/linux/v4l2-subdev.h +++ b/include/linux/v4l2-subdev.h @@ -148,6 +148,14 @@ struct v4l2_subdev_selection { __u32 reserved[8]; }; +struct v4l2_subdev_edid { + __u32 pad; + __u32 start_block; + __u32 blocks; + __u32 reserved[5]; + __u8 __user *edid; +}; + #define VIDIOC_SUBDEV_G_FMT _IOWR('V', 4, struct v4l2_subdev_format) #define VIDIOC_SUBDEV_S_FMT _IOWR('V', 5, struct v4l2_subdev_format) #define VIDIOC_SUBDEV_G_FRAME_INTERVAL \ @@ -166,5 +174,7 @@ struct v4l2_subdev_selection { _IOWR('V', 61, struct v4l2_subdev_selection) #define VIDIOC_SUBDEV_S_SELECTION \ _IOWR('V', 62, struct v4l2_subdev_selection) +#define VIDIOC_SUBDEV_G_EDID _IOWR('V', 40, struct v4l2_subdev_edid) +#define VIDIOC_SUBDEV_S_EDID _IOWR('V', 41, struct v4l2_subdev_edid) #endif diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h index 7a147c8299ab..61395ef85a00 100644 --- a/include/linux/videodev2.h +++ b/include/linux/videodev2.h @@ -1,7 +1,7 @@ /* * Video for Linux Two header file * - * Copyright (C) 1999-2007 the contributors + * Copyright (C) 1999-2012 the contributors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -65,6 +65,7 @@ #include <linux/ioctl.h> #include <linux/types.h> #include <linux/v4l2-common.h> +#include <linux/v4l2-controls.h> /* * Common stuff for both V4L1 and V4L2 @@ -161,6 +162,7 @@ enum v4l2_buf_type { #endif V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE = 9, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE = 10, + /* Deprecated, do not use */ V4L2_BUF_TYPE_PRIVATE = 0x80, }; @@ -368,6 +370,7 @@ struct v4l2_pix_format { /* three non contiguous planes - Y, Cb, Cr */ #define V4L2_PIX_FMT_YUV420M v4l2_fourcc('Y', 'M', '1', '2') /* 12 YUV420 planar */ +#define V4L2_PIX_FMT_YVU420M v4l2_fourcc('Y', 'M', '2', '1') /* 12 YVU420 planar */ /* Bayer formats - see http://www.siliconimaging.com/RGB%20Bayer.htm */ #define V4L2_PIX_FMT_SBGGR8 v4l2_fourcc('B', 'A', '8', '1') /* 8 BGBG.. GRGR.. */ @@ -1188,7 +1191,8 @@ struct v4l2_input { /* capabilities flags */ #define V4L2_IN_CAP_PRESETS 0x00000001 /* Supports S_DV_PRESET */ -#define V4L2_IN_CAP_CUSTOM_TIMINGS 0x00000002 /* Supports S_DV_TIMINGS */ +#define V4L2_IN_CAP_DV_TIMINGS 0x00000002 /* Supports S_DV_TIMINGS */ +#define V4L2_IN_CAP_CUSTOM_TIMINGS V4L2_IN_CAP_DV_TIMINGS /* For compatibility */ #define V4L2_IN_CAP_STD 0x00000004 /* Supports S_STD */ /* @@ -1211,7 +1215,8 @@ struct v4l2_output { /* capabilities flags */ #define V4L2_OUT_CAP_PRESETS 0x00000001 /* Supports S_DV_PRESET */ -#define V4L2_OUT_CAP_CUSTOM_TIMINGS 0x00000002 /* Supports S_DV_TIMINGS */ +#define V4L2_OUT_CAP_DV_TIMINGS 0x00000002 /* Supports S_DV_TIMINGS */ +#define V4L2_OUT_CAP_CUSTOM_TIMINGS V4L2_OUT_CAP_DV_TIMINGS /* For compatibility */ #define V4L2_OUT_CAP_STD 0x00000004 /* Supports S_STD */ /* @@ -1241,16 +1246,6 @@ struct v4l2_ext_controls { struct v4l2_ext_control *controls; }; -/* Values for ctrl_class field */ -#define V4L2_CTRL_CLASS_USER 0x00980000 /* Old-style 'user' controls */ -#define V4L2_CTRL_CLASS_MPEG 0x00990000 /* MPEG-compression controls */ -#define V4L2_CTRL_CLASS_CAMERA 0x009a0000 /* Camera class controls */ -#define V4L2_CTRL_CLASS_FM_TX 0x009b0000 /* FM Modulator control class */ -#define V4L2_CTRL_CLASS_FLASH 0x009c0000 /* Camera flash controls */ -#define V4L2_CTRL_CLASS_JPEG 0x009d0000 /* JPEG-compression controls */ -#define V4L2_CTRL_CLASS_IMAGE_SOURCE 0x009e0000 /* Image source controls */ -#define V4L2_CTRL_CLASS_IMAGE_PROC 0x009f0000 /* Image processing controls */ - #define V4L2_CTRL_ID_MASK (0x0fffffff) #define V4L2_CTRL_ID2CLASS(id) ((id) & 0x0fff0000UL) #define V4L2_CTRL_DRIVER_PRIV(id) (((id) & 0xffff) >= 0x1000) @@ -1306,692 +1301,31 @@ struct v4l2_querymenu { /* User-class control IDs defined by V4L2 */ #define V4L2_CID_MAX_CTRLS 1024 -#define V4L2_CID_BASE (V4L2_CTRL_CLASS_USER | 0x900) -#define V4L2_CID_USER_BASE V4L2_CID_BASE /* IDs reserved for driver specific controls */ #define V4L2_CID_PRIVATE_BASE 0x08000000 -#define V4L2_CID_USER_CLASS (V4L2_CTRL_CLASS_USER | 1) -#define V4L2_CID_BRIGHTNESS (V4L2_CID_BASE+0) -#define V4L2_CID_CONTRAST (V4L2_CID_BASE+1) -#define V4L2_CID_SATURATION (V4L2_CID_BASE+2) -#define V4L2_CID_HUE (V4L2_CID_BASE+3) -#define V4L2_CID_AUDIO_VOLUME (V4L2_CID_BASE+5) -#define V4L2_CID_AUDIO_BALANCE (V4L2_CID_BASE+6) -#define V4L2_CID_AUDIO_BASS (V4L2_CID_BASE+7) -#define V4L2_CID_AUDIO_TREBLE (V4L2_CID_BASE+8) -#define V4L2_CID_AUDIO_MUTE (V4L2_CID_BASE+9) -#define V4L2_CID_AUDIO_LOUDNESS (V4L2_CID_BASE+10) -#define V4L2_CID_BLACK_LEVEL (V4L2_CID_BASE+11) /* Deprecated */ -#define V4L2_CID_AUTO_WHITE_BALANCE (V4L2_CID_BASE+12) -#define V4L2_CID_DO_WHITE_BALANCE (V4L2_CID_BASE+13) -#define V4L2_CID_RED_BALANCE (V4L2_CID_BASE+14) -#define V4L2_CID_BLUE_BALANCE (V4L2_CID_BASE+15) -#define V4L2_CID_GAMMA (V4L2_CID_BASE+16) -#define V4L2_CID_WHITENESS (V4L2_CID_GAMMA) /* Deprecated */ -#define V4L2_CID_EXPOSURE (V4L2_CID_BASE+17) -#define V4L2_CID_AUTOGAIN (V4L2_CID_BASE+18) -#define V4L2_CID_GAIN (V4L2_CID_BASE+19) -#define V4L2_CID_HFLIP (V4L2_CID_BASE+20) -#define V4L2_CID_VFLIP (V4L2_CID_BASE+21) - -/* Deprecated; use V4L2_CID_PAN_RESET and V4L2_CID_TILT_RESET */ -#define V4L2_CID_HCENTER (V4L2_CID_BASE+22) -#define V4L2_CID_VCENTER (V4L2_CID_BASE+23) - -#define V4L2_CID_POWER_LINE_FREQUENCY (V4L2_CID_BASE+24) -enum v4l2_power_line_frequency { - V4L2_CID_POWER_LINE_FREQUENCY_DISABLED = 0, - V4L2_CID_POWER_LINE_FREQUENCY_50HZ = 1, - V4L2_CID_POWER_LINE_FREQUENCY_60HZ = 2, - V4L2_CID_POWER_LINE_FREQUENCY_AUTO = 3, -}; -#define V4L2_CID_HUE_AUTO (V4L2_CID_BASE+25) -#define V4L2_CID_WHITE_BALANCE_TEMPERATURE (V4L2_CID_BASE+26) -#define V4L2_CID_SHARPNESS (V4L2_CID_BASE+27) -#define V4L2_CID_BACKLIGHT_COMPENSATION (V4L2_CID_BASE+28) -#define V4L2_CID_CHROMA_AGC (V4L2_CID_BASE+29) -#define V4L2_CID_COLOR_KILLER (V4L2_CID_BASE+30) -#define V4L2_CID_COLORFX (V4L2_CID_BASE+31) -enum v4l2_colorfx { - V4L2_COLORFX_NONE = 0, - V4L2_COLORFX_BW = 1, - V4L2_COLORFX_SEPIA = 2, - V4L2_COLORFX_NEGATIVE = 3, - V4L2_COLORFX_EMBOSS = 4, - V4L2_COLORFX_SKETCH = 5, - V4L2_COLORFX_SKY_BLUE = 6, - V4L2_COLORFX_GRASS_GREEN = 7, - V4L2_COLORFX_SKIN_WHITEN = 8, - V4L2_COLORFX_VIVID = 9, - V4L2_COLORFX_AQUA = 10, - V4L2_COLORFX_ART_FREEZE = 11, - V4L2_COLORFX_SILHOUETTE = 12, - V4L2_COLORFX_SOLARIZATION = 13, - V4L2_COLORFX_ANTIQUE = 14, - V4L2_COLORFX_SET_CBCR = 15, -}; -#define V4L2_CID_AUTOBRIGHTNESS (V4L2_CID_BASE+32) -#define V4L2_CID_BAND_STOP_FILTER (V4L2_CID_BASE+33) - -#define V4L2_CID_ROTATE (V4L2_CID_BASE+34) -#define V4L2_CID_BG_COLOR (V4L2_CID_BASE+35) - -#define V4L2_CID_CHROMA_GAIN (V4L2_CID_BASE+36) - -#define V4L2_CID_ILLUMINATORS_1 (V4L2_CID_BASE+37) -#define V4L2_CID_ILLUMINATORS_2 (V4L2_CID_BASE+38) - -#define V4L2_CID_MIN_BUFFERS_FOR_CAPTURE (V4L2_CID_BASE+39) -#define V4L2_CID_MIN_BUFFERS_FOR_OUTPUT (V4L2_CID_BASE+40) - -#define V4L2_CID_ALPHA_COMPONENT (V4L2_CID_BASE+41) -#define V4L2_CID_COLORFX_CBCR (V4L2_CID_BASE+42) - -/* last CID + 1 */ -#define V4L2_CID_LASTP1 (V4L2_CID_BASE+43) - -/* MPEG-class control IDs defined by V4L2 */ -#define V4L2_CID_MPEG_BASE (V4L2_CTRL_CLASS_MPEG | 0x900) -#define V4L2_CID_MPEG_CLASS (V4L2_CTRL_CLASS_MPEG | 1) - -/* MPEG streams, specific to multiplexed streams */ -#define V4L2_CID_MPEG_STREAM_TYPE (V4L2_CID_MPEG_BASE+0) -enum v4l2_mpeg_stream_type { - V4L2_MPEG_STREAM_TYPE_MPEG2_PS = 0, /* MPEG-2 program stream */ - V4L2_MPEG_STREAM_TYPE_MPEG2_TS = 1, /* MPEG-2 transport stream */ - V4L2_MPEG_STREAM_TYPE_MPEG1_SS = 2, /* MPEG-1 system stream */ - V4L2_MPEG_STREAM_TYPE_MPEG2_DVD = 3, /* MPEG-2 DVD-compatible stream */ - V4L2_MPEG_STREAM_TYPE_MPEG1_VCD = 4, /* MPEG-1 VCD-compatible stream */ - V4L2_MPEG_STREAM_TYPE_MPEG2_SVCD = 5, /* MPEG-2 SVCD-compatible stream */ -}; -#define V4L2_CID_MPEG_STREAM_PID_PMT (V4L2_CID_MPEG_BASE+1) -#define V4L2_CID_MPEG_STREAM_PID_AUDIO (V4L2_CID_MPEG_BASE+2) -#define V4L2_CID_MPEG_STREAM_PID_VIDEO (V4L2_CID_MPEG_BASE+3) -#define V4L2_CID_MPEG_STREAM_PID_PCR (V4L2_CID_MPEG_BASE+4) -#define V4L2_CID_MPEG_STREAM_PES_ID_AUDIO (V4L2_CID_MPEG_BASE+5) -#define V4L2_CID_MPEG_STREAM_PES_ID_VIDEO (V4L2_CID_MPEG_BASE+6) -#define V4L2_CID_MPEG_STREAM_VBI_FMT (V4L2_CID_MPEG_BASE+7) -enum v4l2_mpeg_stream_vbi_fmt { - V4L2_MPEG_STREAM_VBI_FMT_NONE = 0, /* No VBI in the MPEG stream */ - V4L2_MPEG_STREAM_VBI_FMT_IVTV = 1, /* VBI in private packets, IVTV format */ -}; - -/* MPEG audio controls specific to multiplexed streams */ -#define V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ (V4L2_CID_MPEG_BASE+100) -enum v4l2_mpeg_audio_sampling_freq { - V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100 = 0, - V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000 = 1, - V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000 = 2, -}; -#define V4L2_CID_MPEG_AUDIO_ENCODING (V4L2_CID_MPEG_BASE+101) -enum v4l2_mpeg_audio_encoding { - V4L2_MPEG_AUDIO_ENCODING_LAYER_1 = 0, - V4L2_MPEG_AUDIO_ENCODING_LAYER_2 = 1, - V4L2_MPEG_AUDIO_ENCODING_LAYER_3 = 2, - V4L2_MPEG_AUDIO_ENCODING_AAC = 3, - V4L2_MPEG_AUDIO_ENCODING_AC3 = 4, -}; -#define V4L2_CID_MPEG_AUDIO_L1_BITRATE (V4L2_CID_MPEG_BASE+102) -enum v4l2_mpeg_audio_l1_bitrate { - V4L2_MPEG_AUDIO_L1_BITRATE_32K = 0, - V4L2_MPEG_AUDIO_L1_BITRATE_64K = 1, - V4L2_MPEG_AUDIO_L1_BITRATE_96K = 2, - V4L2_MPEG_AUDIO_L1_BITRATE_128K = 3, - V4L2_MPEG_AUDIO_L1_BITRATE_160K = 4, - V4L2_MPEG_AUDIO_L1_BITRATE_192K = 5, - V4L2_MPEG_AUDIO_L1_BITRATE_224K = 6, - V4L2_MPEG_AUDIO_L1_BITRATE_256K = 7, - V4L2_MPEG_AUDIO_L1_BITRATE_288K = 8, - V4L2_MPEG_AUDIO_L1_BITRATE_320K = 9, - V4L2_MPEG_AUDIO_L1_BITRATE_352K = 10, - V4L2_MPEG_AUDIO_L1_BITRATE_384K = 11, - V4L2_MPEG_AUDIO_L1_BITRATE_416K = 12, - V4L2_MPEG_AUDIO_L1_BITRATE_448K = 13, -}; -#define V4L2_CID_MPEG_AUDIO_L2_BITRATE (V4L2_CID_MPEG_BASE+103) -enum v4l2_mpeg_audio_l2_bitrate { - V4L2_MPEG_AUDIO_L2_BITRATE_32K = 0, - V4L2_MPEG_AUDIO_L2_BITRATE_48K = 1, - V4L2_MPEG_AUDIO_L2_BITRATE_56K = 2, - V4L2_MPEG_AUDIO_L2_BITRATE_64K = 3, - V4L2_MPEG_AUDIO_L2_BITRATE_80K = 4, - V4L2_MPEG_AUDIO_L2_BITRATE_96K = 5, - V4L2_MPEG_AUDIO_L2_BITRATE_112K = 6, - V4L2_MPEG_AUDIO_L2_BITRATE_128K = 7, - V4L2_MPEG_AUDIO_L2_BITRATE_160K = 8, - V4L2_MPEG_AUDIO_L2_BITRATE_192K = 9, - V4L2_MPEG_AUDIO_L2_BITRATE_224K = 10, - V4L2_MPEG_AUDIO_L2_BITRATE_256K = 11, - V4L2_MPEG_AUDIO_L2_BITRATE_320K = 12, - V4L2_MPEG_AUDIO_L2_BITRATE_384K = 13, -}; -#define V4L2_CID_MPEG_AUDIO_L3_BITRATE (V4L2_CID_MPEG_BASE+104) -enum v4l2_mpeg_audio_l3_bitrate { - V4L2_MPEG_AUDIO_L3_BITRATE_32K = 0, - V4L2_MPEG_AUDIO_L3_BITRATE_40K = 1, - V4L2_MPEG_AUDIO_L3_BITRATE_48K = 2, - V4L2_MPEG_AUDIO_L3_BITRATE_56K = 3, - V4L2_MPEG_AUDIO_L3_BITRATE_64K = 4, - V4L2_MPEG_AUDIO_L3_BITRATE_80K = 5, - V4L2_MPEG_AUDIO_L3_BITRATE_96K = 6, - V4L2_MPEG_AUDIO_L3_BITRATE_112K = 7, - V4L2_MPEG_AUDIO_L3_BITRATE_128K = 8, - V4L2_MPEG_AUDIO_L3_BITRATE_160K = 9, - V4L2_MPEG_AUDIO_L3_BITRATE_192K = 10, - V4L2_MPEG_AUDIO_L3_BITRATE_224K = 11, - V4L2_MPEG_AUDIO_L3_BITRATE_256K = 12, - V4L2_MPEG_AUDIO_L3_BITRATE_320K = 13, -}; -#define V4L2_CID_MPEG_AUDIO_MODE (V4L2_CID_MPEG_BASE+105) -enum v4l2_mpeg_audio_mode { - V4L2_MPEG_AUDIO_MODE_STEREO = 0, - V4L2_MPEG_AUDIO_MODE_JOINT_STEREO = 1, - V4L2_MPEG_AUDIO_MODE_DUAL = 2, - V4L2_MPEG_AUDIO_MODE_MONO = 3, -}; -#define V4L2_CID_MPEG_AUDIO_MODE_EXTENSION (V4L2_CID_MPEG_BASE+106) -enum v4l2_mpeg_audio_mode_extension { - V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_4 = 0, - V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_8 = 1, - V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_12 = 2, - V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_16 = 3, -}; -#define V4L2_CID_MPEG_AUDIO_EMPHASIS (V4L2_CID_MPEG_BASE+107) -enum v4l2_mpeg_audio_emphasis { - V4L2_MPEG_AUDIO_EMPHASIS_NONE = 0, - V4L2_MPEG_AUDIO_EMPHASIS_50_DIV_15_uS = 1, - V4L2_MPEG_AUDIO_EMPHASIS_CCITT_J17 = 2, -}; -#define V4L2_CID_MPEG_AUDIO_CRC (V4L2_CID_MPEG_BASE+108) -enum v4l2_mpeg_audio_crc { - V4L2_MPEG_AUDIO_CRC_NONE = 0, - V4L2_MPEG_AUDIO_CRC_CRC16 = 1, -}; -#define V4L2_CID_MPEG_AUDIO_MUTE (V4L2_CID_MPEG_BASE+109) -#define V4L2_CID_MPEG_AUDIO_AAC_BITRATE (V4L2_CID_MPEG_BASE+110) -#define V4L2_CID_MPEG_AUDIO_AC3_BITRATE (V4L2_CID_MPEG_BASE+111) -enum v4l2_mpeg_audio_ac3_bitrate { - V4L2_MPEG_AUDIO_AC3_BITRATE_32K = 0, - V4L2_MPEG_AUDIO_AC3_BITRATE_40K = 1, - V4L2_MPEG_AUDIO_AC3_BITRATE_48K = 2, - V4L2_MPEG_AUDIO_AC3_BITRATE_56K = 3, - V4L2_MPEG_AUDIO_AC3_BITRATE_64K = 4, - V4L2_MPEG_AUDIO_AC3_BITRATE_80K = 5, - V4L2_MPEG_AUDIO_AC3_BITRATE_96K = 6, - V4L2_MPEG_AUDIO_AC3_BITRATE_112K = 7, - V4L2_MPEG_AUDIO_AC3_BITRATE_128K = 8, - V4L2_MPEG_AUDIO_AC3_BITRATE_160K = 9, - V4L2_MPEG_AUDIO_AC3_BITRATE_192K = 10, - V4L2_MPEG_AUDIO_AC3_BITRATE_224K = 11, - V4L2_MPEG_AUDIO_AC3_BITRATE_256K = 12, - V4L2_MPEG_AUDIO_AC3_BITRATE_320K = 13, - V4L2_MPEG_AUDIO_AC3_BITRATE_384K = 14, - V4L2_MPEG_AUDIO_AC3_BITRATE_448K = 15, - V4L2_MPEG_AUDIO_AC3_BITRATE_512K = 16, - V4L2_MPEG_AUDIO_AC3_BITRATE_576K = 17, - V4L2_MPEG_AUDIO_AC3_BITRATE_640K = 18, -}; -#define V4L2_CID_MPEG_AUDIO_DEC_PLAYBACK (V4L2_CID_MPEG_BASE+112) -enum v4l2_mpeg_audio_dec_playback { - V4L2_MPEG_AUDIO_DEC_PLAYBACK_AUTO = 0, - V4L2_MPEG_AUDIO_DEC_PLAYBACK_STEREO = 1, - V4L2_MPEG_AUDIO_DEC_PLAYBACK_LEFT = 2, - V4L2_MPEG_AUDIO_DEC_PLAYBACK_RIGHT = 3, - V4L2_MPEG_AUDIO_DEC_PLAYBACK_MONO = 4, - V4L2_MPEG_AUDIO_DEC_PLAYBACK_SWAPPED_STEREO = 5, -}; -#define V4L2_CID_MPEG_AUDIO_DEC_MULTILINGUAL_PLAYBACK (V4L2_CID_MPEG_BASE+113) - -/* MPEG video controls specific to multiplexed streams */ -#define V4L2_CID_MPEG_VIDEO_ENCODING (V4L2_CID_MPEG_BASE+200) -enum v4l2_mpeg_video_encoding { - V4L2_MPEG_VIDEO_ENCODING_MPEG_1 = 0, - V4L2_MPEG_VIDEO_ENCODING_MPEG_2 = 1, - V4L2_MPEG_VIDEO_ENCODING_MPEG_4_AVC = 2, -}; -#define V4L2_CID_MPEG_VIDEO_ASPECT (V4L2_CID_MPEG_BASE+201) -enum v4l2_mpeg_video_aspect { - V4L2_MPEG_VIDEO_ASPECT_1x1 = 0, - V4L2_MPEG_VIDEO_ASPECT_4x3 = 1, - V4L2_MPEG_VIDEO_ASPECT_16x9 = 2, - V4L2_MPEG_VIDEO_ASPECT_221x100 = 3, -}; -#define V4L2_CID_MPEG_VIDEO_B_FRAMES (V4L2_CID_MPEG_BASE+202) -#define V4L2_CID_MPEG_VIDEO_GOP_SIZE (V4L2_CID_MPEG_BASE+203) -#define V4L2_CID_MPEG_VIDEO_GOP_CLOSURE (V4L2_CID_MPEG_BASE+204) -#define V4L2_CID_MPEG_VIDEO_PULLDOWN (V4L2_CID_MPEG_BASE+205) -#define V4L2_CID_MPEG_VIDEO_BITRATE_MODE (V4L2_CID_MPEG_BASE+206) -enum v4l2_mpeg_video_bitrate_mode { - V4L2_MPEG_VIDEO_BITRATE_MODE_VBR = 0, - V4L2_MPEG_VIDEO_BITRATE_MODE_CBR = 1, -}; -#define V4L2_CID_MPEG_VIDEO_BITRATE (V4L2_CID_MPEG_BASE+207) -#define V4L2_CID_MPEG_VIDEO_BITRATE_PEAK (V4L2_CID_MPEG_BASE+208) -#define V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION (V4L2_CID_MPEG_BASE+209) -#define V4L2_CID_MPEG_VIDEO_MUTE (V4L2_CID_MPEG_BASE+210) -#define V4L2_CID_MPEG_VIDEO_MUTE_YUV (V4L2_CID_MPEG_BASE+211) -#define V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE (V4L2_CID_MPEG_BASE+212) -#define V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER (V4L2_CID_MPEG_BASE+213) -#define V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB (V4L2_CID_MPEG_BASE+214) -#define V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE (V4L2_CID_MPEG_BASE+215) -#define V4L2_CID_MPEG_VIDEO_HEADER_MODE (V4L2_CID_MPEG_BASE+216) -enum v4l2_mpeg_video_header_mode { - V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE = 0, - V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME = 1, - -}; -#define V4L2_CID_MPEG_VIDEO_MAX_REF_PIC (V4L2_CID_MPEG_BASE+217) -#define V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE (V4L2_CID_MPEG_BASE+218) -#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES (V4L2_CID_MPEG_BASE+219) -#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB (V4L2_CID_MPEG_BASE+220) -#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE (V4L2_CID_MPEG_BASE+221) -enum v4l2_mpeg_video_multi_slice_mode { - V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE = 0, - V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB = 1, - V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES = 2, -}; -#define V4L2_CID_MPEG_VIDEO_VBV_SIZE (V4L2_CID_MPEG_BASE+222) -#define V4L2_CID_MPEG_VIDEO_DEC_PTS (V4L2_CID_MPEG_BASE+223) -#define V4L2_CID_MPEG_VIDEO_DEC_FRAME (V4L2_CID_MPEG_BASE+224) - -#define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP (V4L2_CID_MPEG_BASE+300) -#define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP (V4L2_CID_MPEG_BASE+301) -#define V4L2_CID_MPEG_VIDEO_H263_B_FRAME_QP (V4L2_CID_MPEG_BASE+302) -#define V4L2_CID_MPEG_VIDEO_H263_MIN_QP (V4L2_CID_MPEG_BASE+303) -#define V4L2_CID_MPEG_VIDEO_H263_MAX_QP (V4L2_CID_MPEG_BASE+304) -#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP (V4L2_CID_MPEG_BASE+350) -#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP (V4L2_CID_MPEG_BASE+351) -#define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP (V4L2_CID_MPEG_BASE+352) -#define V4L2_CID_MPEG_VIDEO_H264_MIN_QP (V4L2_CID_MPEG_BASE+353) -#define V4L2_CID_MPEG_VIDEO_H264_MAX_QP (V4L2_CID_MPEG_BASE+354) -#define V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM (V4L2_CID_MPEG_BASE+355) -#define V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE (V4L2_CID_MPEG_BASE+356) -#define V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE (V4L2_CID_MPEG_BASE+357) -enum v4l2_mpeg_video_h264_entropy_mode { - V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC = 0, - V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC = 1, -}; -#define V4L2_CID_MPEG_VIDEO_H264_I_PERIOD (V4L2_CID_MPEG_BASE+358) -#define V4L2_CID_MPEG_VIDEO_H264_LEVEL (V4L2_CID_MPEG_BASE+359) -enum v4l2_mpeg_video_h264_level { - V4L2_MPEG_VIDEO_H264_LEVEL_1_0 = 0, - V4L2_MPEG_VIDEO_H264_LEVEL_1B = 1, - V4L2_MPEG_VIDEO_H264_LEVEL_1_1 = 2, - V4L2_MPEG_VIDEO_H264_LEVEL_1_2 = 3, - V4L2_MPEG_VIDEO_H264_LEVEL_1_3 = 4, - V4L2_MPEG_VIDEO_H264_LEVEL_2_0 = 5, - V4L2_MPEG_VIDEO_H264_LEVEL_2_1 = 6, - V4L2_MPEG_VIDEO_H264_LEVEL_2_2 = 7, - V4L2_MPEG_VIDEO_H264_LEVEL_3_0 = 8, - V4L2_MPEG_VIDEO_H264_LEVEL_3_1 = 9, - V4L2_MPEG_VIDEO_H264_LEVEL_3_2 = 10, - V4L2_MPEG_VIDEO_H264_LEVEL_4_0 = 11, - V4L2_MPEG_VIDEO_H264_LEVEL_4_1 = 12, - V4L2_MPEG_VIDEO_H264_LEVEL_4_2 = 13, - V4L2_MPEG_VIDEO_H264_LEVEL_5_0 = 14, - V4L2_MPEG_VIDEO_H264_LEVEL_5_1 = 15, -}; -#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA (V4L2_CID_MPEG_BASE+360) -#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA (V4L2_CID_MPEG_BASE+361) -#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE (V4L2_CID_MPEG_BASE+362) -enum v4l2_mpeg_video_h264_loop_filter_mode { - V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED = 0, - V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED = 1, - V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY = 2, -}; -#define V4L2_CID_MPEG_VIDEO_H264_PROFILE (V4L2_CID_MPEG_BASE+363) -enum v4l2_mpeg_video_h264_profile { - V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE = 0, - V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE = 1, - V4L2_MPEG_VIDEO_H264_PROFILE_MAIN = 2, - V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED = 3, - V4L2_MPEG_VIDEO_H264_PROFILE_HIGH = 4, - V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10 = 5, - V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422 = 6, - V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE = 7, - V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10_INTRA = 8, - V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422_INTRA = 9, - V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_INTRA = 10, - V4L2_MPEG_VIDEO_H264_PROFILE_CAVLC_444_INTRA = 11, - V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_BASELINE = 12, - V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH = 13, - V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH_INTRA = 14, - V4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH = 15, - V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH = 16, -}; -#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT (V4L2_CID_MPEG_BASE+364) -#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH (V4L2_CID_MPEG_BASE+365) -#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE (V4L2_CID_MPEG_BASE+366) -#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC (V4L2_CID_MPEG_BASE+367) -enum v4l2_mpeg_video_h264_vui_sar_idc { - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED = 0, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1 = 1, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_12x11 = 2, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_10x11 = 3, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_16x11 = 4, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_40x33 = 5, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_24x11 = 6, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_20x11 = 7, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_32x11 = 8, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_80x33 = 9, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_18x11 = 10, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_15x11 = 11, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_64x33 = 12, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_160x99 = 13, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_4x3 = 14, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_3x2 = 15, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_2x1 = 16, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED = 17, -}; -#define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (V4L2_CID_MPEG_BASE+400) -#define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP (V4L2_CID_MPEG_BASE+401) -#define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP (V4L2_CID_MPEG_BASE+402) -#define V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP (V4L2_CID_MPEG_BASE+403) -#define V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP (V4L2_CID_MPEG_BASE+404) -#define V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL (V4L2_CID_MPEG_BASE+405) -enum v4l2_mpeg_video_mpeg4_level { - V4L2_MPEG_VIDEO_MPEG4_LEVEL_0 = 0, - V4L2_MPEG_VIDEO_MPEG4_LEVEL_0B = 1, - V4L2_MPEG_VIDEO_MPEG4_LEVEL_1 = 2, - V4L2_MPEG_VIDEO_MPEG4_LEVEL_2 = 3, - V4L2_MPEG_VIDEO_MPEG4_LEVEL_3 = 4, - V4L2_MPEG_VIDEO_MPEG4_LEVEL_3B = 5, - V4L2_MPEG_VIDEO_MPEG4_LEVEL_4 = 6, - V4L2_MPEG_VIDEO_MPEG4_LEVEL_5 = 7, -}; -#define V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE (V4L2_CID_MPEG_BASE+406) -enum v4l2_mpeg_video_mpeg4_profile { - V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE = 0, - V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE = 1, - V4L2_MPEG_VIDEO_MPEG4_PROFILE_CORE = 2, - V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE_SCALABLE = 3, - V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_CODING_EFFICIENCY = 4, -}; -#define V4L2_CID_MPEG_VIDEO_MPEG4_QPEL (V4L2_CID_MPEG_BASE+407) - -/* MPEG-class control IDs specific to the CX2341x driver as defined by V4L2 */ -#define V4L2_CID_MPEG_CX2341X_BASE (V4L2_CTRL_CLASS_MPEG | 0x1000) -#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+0) -enum v4l2_mpeg_cx2341x_video_spatial_filter_mode { - V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_MANUAL = 0, - V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_AUTO = 1, -}; -#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE+1) -#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+2) -enum v4l2_mpeg_cx2341x_video_luma_spatial_filter_type { - V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_OFF = 0, - V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_HOR = 1, - V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_VERT = 2, - V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_HV_SEPARABLE = 3, - V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_SYM_NON_SEPARABLE = 4, -}; -#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+3) -enum v4l2_mpeg_cx2341x_video_chroma_spatial_filter_type { - V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_OFF = 0, - V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_1D_HOR = 1, -}; -#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+4) -enum v4l2_mpeg_cx2341x_video_temporal_filter_mode { - V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_MANUAL = 0, - V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_AUTO = 1, -}; -#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE+5) -#define V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+6) -enum v4l2_mpeg_cx2341x_video_median_filter_type { - V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_OFF = 0, - V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR = 1, - V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_VERT = 2, - V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR_VERT = 3, - V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_DIAG = 4, -}; -#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE+7) -#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+8) -#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE+9) -#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+10) -#define V4L2_CID_MPEG_CX2341X_STREAM_INSERT_NAV_PACKETS (V4L2_CID_MPEG_CX2341X_BASE+11) - -/* MPEG-class control IDs specific to the Samsung MFC 5.1 driver as defined by V4L2 */ -#define V4L2_CID_MPEG_MFC51_BASE (V4L2_CTRL_CLASS_MPEG | 0x1100) - -#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY (V4L2_CID_MPEG_MFC51_BASE+0) -#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY_ENABLE (V4L2_CID_MPEG_MFC51_BASE+1) -#define V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE (V4L2_CID_MPEG_MFC51_BASE+2) -enum v4l2_mpeg_mfc51_video_frame_skip_mode { - V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_DISABLED = 0, - V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT = 1, - V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT = 2, -}; -#define V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE (V4L2_CID_MPEG_MFC51_BASE+3) -enum v4l2_mpeg_mfc51_video_force_frame_type { - V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_DISABLED = 0, - V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_I_FRAME = 1, - V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_NOT_CODED = 2, -}; -#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING (V4L2_CID_MPEG_MFC51_BASE+4) -#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV (V4L2_CID_MPEG_MFC51_BASE+5) -#define V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT (V4L2_CID_MPEG_MFC51_BASE+6) -#define V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF (V4L2_CID_MPEG_MFC51_BASE+7) -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY (V4L2_CID_MPEG_MFC51_BASE+50) -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK (V4L2_CID_MPEG_MFC51_BASE+51) -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH (V4L2_CID_MPEG_MFC51_BASE+52) -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC (V4L2_CID_MPEG_MFC51_BASE+53) -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P (V4L2_CID_MPEG_MFC51_BASE+54) - -/* Camera class control IDs */ -#define V4L2_CID_CAMERA_CLASS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x900) -#define V4L2_CID_CAMERA_CLASS (V4L2_CTRL_CLASS_CAMERA | 1) - -#define V4L2_CID_EXPOSURE_AUTO (V4L2_CID_CAMERA_CLASS_BASE+1) -enum v4l2_exposure_auto_type { - V4L2_EXPOSURE_AUTO = 0, - V4L2_EXPOSURE_MANUAL = 1, - V4L2_EXPOSURE_SHUTTER_PRIORITY = 2, - V4L2_EXPOSURE_APERTURE_PRIORITY = 3 -}; -#define V4L2_CID_EXPOSURE_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+2) -#define V4L2_CID_EXPOSURE_AUTO_PRIORITY (V4L2_CID_CAMERA_CLASS_BASE+3) - -#define V4L2_CID_PAN_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+4) -#define V4L2_CID_TILT_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+5) -#define V4L2_CID_PAN_RESET (V4L2_CID_CAMERA_CLASS_BASE+6) -#define V4L2_CID_TILT_RESET (V4L2_CID_CAMERA_CLASS_BASE+7) - -#define V4L2_CID_PAN_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+8) -#define V4L2_CID_TILT_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+9) - -#define V4L2_CID_FOCUS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+10) -#define V4L2_CID_FOCUS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+11) -#define V4L2_CID_FOCUS_AUTO (V4L2_CID_CAMERA_CLASS_BASE+12) - -#define V4L2_CID_ZOOM_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+13) -#define V4L2_CID_ZOOM_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+14) -#define V4L2_CID_ZOOM_CONTINUOUS (V4L2_CID_CAMERA_CLASS_BASE+15) - -#define V4L2_CID_PRIVACY (V4L2_CID_CAMERA_CLASS_BASE+16) - -#define V4L2_CID_IRIS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+17) -#define V4L2_CID_IRIS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+18) - -#define V4L2_CID_AUTO_EXPOSURE_BIAS (V4L2_CID_CAMERA_CLASS_BASE+19) - -#define V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE (V4L2_CID_CAMERA_CLASS_BASE+20) -enum v4l2_auto_n_preset_white_balance { - V4L2_WHITE_BALANCE_MANUAL = 0, - V4L2_WHITE_BALANCE_AUTO = 1, - V4L2_WHITE_BALANCE_INCANDESCENT = 2, - V4L2_WHITE_BALANCE_FLUORESCENT = 3, - V4L2_WHITE_BALANCE_FLUORESCENT_H = 4, - V4L2_WHITE_BALANCE_HORIZON = 5, - V4L2_WHITE_BALANCE_DAYLIGHT = 6, - V4L2_WHITE_BALANCE_FLASH = 7, - V4L2_WHITE_BALANCE_CLOUDY = 8, - V4L2_WHITE_BALANCE_SHADE = 9, -}; - -#define V4L2_CID_WIDE_DYNAMIC_RANGE (V4L2_CID_CAMERA_CLASS_BASE+21) -#define V4L2_CID_IMAGE_STABILIZATION (V4L2_CID_CAMERA_CLASS_BASE+22) - -#define V4L2_CID_ISO_SENSITIVITY (V4L2_CID_CAMERA_CLASS_BASE+23) -#define V4L2_CID_ISO_SENSITIVITY_AUTO (V4L2_CID_CAMERA_CLASS_BASE+24) -enum v4l2_iso_sensitivity_auto_type { - V4L2_ISO_SENSITIVITY_MANUAL = 0, - V4L2_ISO_SENSITIVITY_AUTO = 1, -}; - -#define V4L2_CID_EXPOSURE_METERING (V4L2_CID_CAMERA_CLASS_BASE+25) -enum v4l2_exposure_metering { - V4L2_EXPOSURE_METERING_AVERAGE = 0, - V4L2_EXPOSURE_METERING_CENTER_WEIGHTED = 1, - V4L2_EXPOSURE_METERING_SPOT = 2, -}; - -#define V4L2_CID_SCENE_MODE (V4L2_CID_CAMERA_CLASS_BASE+26) -enum v4l2_scene_mode { - V4L2_SCENE_MODE_NONE = 0, - V4L2_SCENE_MODE_BACKLIGHT = 1, - V4L2_SCENE_MODE_BEACH_SNOW = 2, - V4L2_SCENE_MODE_CANDLE_LIGHT = 3, - V4L2_SCENE_MODE_DAWN_DUSK = 4, - V4L2_SCENE_MODE_FALL_COLORS = 5, - V4L2_SCENE_MODE_FIREWORKS = 6, - V4L2_SCENE_MODE_LANDSCAPE = 7, - V4L2_SCENE_MODE_NIGHT = 8, - V4L2_SCENE_MODE_PARTY_INDOOR = 9, - V4L2_SCENE_MODE_PORTRAIT = 10, - V4L2_SCENE_MODE_SPORTS = 11, - V4L2_SCENE_MODE_SUNSET = 12, - V4L2_SCENE_MODE_TEXT = 13, -}; - -#define V4L2_CID_3A_LOCK (V4L2_CID_CAMERA_CLASS_BASE+27) -#define V4L2_LOCK_EXPOSURE (1 << 0) -#define V4L2_LOCK_WHITE_BALANCE (1 << 1) -#define V4L2_LOCK_FOCUS (1 << 2) - -#define V4L2_CID_AUTO_FOCUS_START (V4L2_CID_CAMERA_CLASS_BASE+28) -#define V4L2_CID_AUTO_FOCUS_STOP (V4L2_CID_CAMERA_CLASS_BASE+29) -#define V4L2_CID_AUTO_FOCUS_STATUS (V4L2_CID_CAMERA_CLASS_BASE+30) -#define V4L2_AUTO_FOCUS_STATUS_IDLE (0 << 0) -#define V4L2_AUTO_FOCUS_STATUS_BUSY (1 << 0) -#define V4L2_AUTO_FOCUS_STATUS_REACHED (1 << 1) -#define V4L2_AUTO_FOCUS_STATUS_FAILED (1 << 2) - -#define V4L2_CID_AUTO_FOCUS_RANGE (V4L2_CID_CAMERA_CLASS_BASE+31) -enum v4l2_auto_focus_range { - V4L2_AUTO_FOCUS_RANGE_AUTO = 0, - V4L2_AUTO_FOCUS_RANGE_NORMAL = 1, - V4L2_AUTO_FOCUS_RANGE_MACRO = 2, - V4L2_AUTO_FOCUS_RANGE_INFINITY = 3, -}; - -/* FM Modulator class control IDs */ -#define V4L2_CID_FM_TX_CLASS_BASE (V4L2_CTRL_CLASS_FM_TX | 0x900) -#define V4L2_CID_FM_TX_CLASS (V4L2_CTRL_CLASS_FM_TX | 1) - -#define V4L2_CID_RDS_TX_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 1) -#define V4L2_CID_RDS_TX_PI (V4L2_CID_FM_TX_CLASS_BASE + 2) -#define V4L2_CID_RDS_TX_PTY (V4L2_CID_FM_TX_CLASS_BASE + 3) -#define V4L2_CID_RDS_TX_PS_NAME (V4L2_CID_FM_TX_CLASS_BASE + 5) -#define V4L2_CID_RDS_TX_RADIO_TEXT (V4L2_CID_FM_TX_CLASS_BASE + 6) - -#define V4L2_CID_AUDIO_LIMITER_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 64) -#define V4L2_CID_AUDIO_LIMITER_RELEASE_TIME (V4L2_CID_FM_TX_CLASS_BASE + 65) -#define V4L2_CID_AUDIO_LIMITER_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 66) - -#define V4L2_CID_AUDIO_COMPRESSION_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 80) -#define V4L2_CID_AUDIO_COMPRESSION_GAIN (V4L2_CID_FM_TX_CLASS_BASE + 81) -#define V4L2_CID_AUDIO_COMPRESSION_THRESHOLD (V4L2_CID_FM_TX_CLASS_BASE + 82) -#define V4L2_CID_AUDIO_COMPRESSION_ATTACK_TIME (V4L2_CID_FM_TX_CLASS_BASE + 83) -#define V4L2_CID_AUDIO_COMPRESSION_RELEASE_TIME (V4L2_CID_FM_TX_CLASS_BASE + 84) - -#define V4L2_CID_PILOT_TONE_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 96) -#define V4L2_CID_PILOT_TONE_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 97) -#define V4L2_CID_PILOT_TONE_FREQUENCY (V4L2_CID_FM_TX_CLASS_BASE + 98) - -#define V4L2_CID_TUNE_PREEMPHASIS (V4L2_CID_FM_TX_CLASS_BASE + 112) -enum v4l2_preemphasis { - V4L2_PREEMPHASIS_DISABLED = 0, - V4L2_PREEMPHASIS_50_uS = 1, - V4L2_PREEMPHASIS_75_uS = 2, -}; -#define V4L2_CID_TUNE_POWER_LEVEL (V4L2_CID_FM_TX_CLASS_BASE + 113) -#define V4L2_CID_TUNE_ANTENNA_CAPACITOR (V4L2_CID_FM_TX_CLASS_BASE + 114) - -/* Flash and privacy (indicator) light controls */ -#define V4L2_CID_FLASH_CLASS_BASE (V4L2_CTRL_CLASS_FLASH | 0x900) -#define V4L2_CID_FLASH_CLASS (V4L2_CTRL_CLASS_FLASH | 1) - -#define V4L2_CID_FLASH_LED_MODE (V4L2_CID_FLASH_CLASS_BASE + 1) -enum v4l2_flash_led_mode { - V4L2_FLASH_LED_MODE_NONE, - V4L2_FLASH_LED_MODE_FLASH, - V4L2_FLASH_LED_MODE_TORCH, -}; - -#define V4L2_CID_FLASH_STROBE_SOURCE (V4L2_CID_FLASH_CLASS_BASE + 2) -enum v4l2_flash_strobe_source { - V4L2_FLASH_STROBE_SOURCE_SOFTWARE, - V4L2_FLASH_STROBE_SOURCE_EXTERNAL, -}; - -#define V4L2_CID_FLASH_STROBE (V4L2_CID_FLASH_CLASS_BASE + 3) -#define V4L2_CID_FLASH_STROBE_STOP (V4L2_CID_FLASH_CLASS_BASE + 4) -#define V4L2_CID_FLASH_STROBE_STATUS (V4L2_CID_FLASH_CLASS_BASE + 5) - -#define V4L2_CID_FLASH_TIMEOUT (V4L2_CID_FLASH_CLASS_BASE + 6) -#define V4L2_CID_FLASH_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 7) -#define V4L2_CID_FLASH_TORCH_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 8) -#define V4L2_CID_FLASH_INDICATOR_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 9) - -#define V4L2_CID_FLASH_FAULT (V4L2_CID_FLASH_CLASS_BASE + 10) -#define V4L2_FLASH_FAULT_OVER_VOLTAGE (1 << 0) -#define V4L2_FLASH_FAULT_TIMEOUT (1 << 1) -#define V4L2_FLASH_FAULT_OVER_TEMPERATURE (1 << 2) -#define V4L2_FLASH_FAULT_SHORT_CIRCUIT (1 << 3) -#define V4L2_FLASH_FAULT_OVER_CURRENT (1 << 4) -#define V4L2_FLASH_FAULT_INDICATOR (1 << 5) - -#define V4L2_CID_FLASH_CHARGE (V4L2_CID_FLASH_CLASS_BASE + 11) -#define V4L2_CID_FLASH_READY (V4L2_CID_FLASH_CLASS_BASE + 12) - -/* JPEG-class control IDs defined by V4L2 */ -#define V4L2_CID_JPEG_CLASS_BASE (V4L2_CTRL_CLASS_JPEG | 0x900) -#define V4L2_CID_JPEG_CLASS (V4L2_CTRL_CLASS_JPEG | 1) - -#define V4L2_CID_JPEG_CHROMA_SUBSAMPLING (V4L2_CID_JPEG_CLASS_BASE + 1) -enum v4l2_jpeg_chroma_subsampling { - V4L2_JPEG_CHROMA_SUBSAMPLING_444 = 0, - V4L2_JPEG_CHROMA_SUBSAMPLING_422 = 1, - V4L2_JPEG_CHROMA_SUBSAMPLING_420 = 2, - V4L2_JPEG_CHROMA_SUBSAMPLING_411 = 3, - V4L2_JPEG_CHROMA_SUBSAMPLING_410 = 4, - V4L2_JPEG_CHROMA_SUBSAMPLING_GRAY = 5, -}; -#define V4L2_CID_JPEG_RESTART_INTERVAL (V4L2_CID_JPEG_CLASS_BASE + 2) -#define V4L2_CID_JPEG_COMPRESSION_QUALITY (V4L2_CID_JPEG_CLASS_BASE + 3) - -#define V4L2_CID_JPEG_ACTIVE_MARKER (V4L2_CID_JPEG_CLASS_BASE + 4) -#define V4L2_JPEG_ACTIVE_MARKER_APP0 (1 << 0) -#define V4L2_JPEG_ACTIVE_MARKER_APP1 (1 << 1) -#define V4L2_JPEG_ACTIVE_MARKER_COM (1 << 16) -#define V4L2_JPEG_ACTIVE_MARKER_DQT (1 << 17) -#define V4L2_JPEG_ACTIVE_MARKER_DHT (1 << 18) - -/* Image source controls */ -#define V4L2_CID_IMAGE_SOURCE_CLASS_BASE (V4L2_CTRL_CLASS_IMAGE_SOURCE | 0x900) -#define V4L2_CID_IMAGE_SOURCE_CLASS (V4L2_CTRL_CLASS_IMAGE_SOURCE | 1) - -#define V4L2_CID_VBLANK (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 1) -#define V4L2_CID_HBLANK (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 2) -#define V4L2_CID_ANALOGUE_GAIN (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 3) - -/* Image processing controls */ -#define V4L2_CID_IMAGE_PROC_CLASS_BASE (V4L2_CTRL_CLASS_IMAGE_PROC | 0x900) -#define V4L2_CID_IMAGE_PROC_CLASS (V4L2_CTRL_CLASS_IMAGE_PROC | 1) - -#define V4L2_CID_LINK_FREQ (V4L2_CID_IMAGE_PROC_CLASS_BASE + 1) -#define V4L2_CID_PIXEL_RATE (V4L2_CID_IMAGE_PROC_CLASS_BASE + 2) + +/* DV-class control IDs defined by V4L2 */ +#define V4L2_CID_DV_CLASS_BASE (V4L2_CTRL_CLASS_DV | 0x900) +#define V4L2_CID_DV_CLASS (V4L2_CTRL_CLASS_DV | 1) + +#define V4L2_CID_DV_TX_HOTPLUG (V4L2_CID_DV_CLASS_BASE + 1) +#define V4L2_CID_DV_TX_RXSENSE (V4L2_CID_DV_CLASS_BASE + 2) +#define V4L2_CID_DV_TX_EDID_PRESENT (V4L2_CID_DV_CLASS_BASE + 3) +#define V4L2_CID_DV_TX_MODE (V4L2_CID_DV_CLASS_BASE + 4) +enum v4l2_dv_tx_mode { + V4L2_DV_TX_MODE_DVI_D = 0, + V4L2_DV_TX_MODE_HDMI = 1, +}; +#define V4L2_CID_DV_TX_RGB_RANGE (V4L2_CID_DV_CLASS_BASE + 5) +enum v4l2_dv_rgb_range { + V4L2_DV_RGB_RANGE_AUTO = 0, + V4L2_DV_RGB_RANGE_LIMITED = 1, + V4L2_DV_RGB_RANGE_FULL = 2, +}; + +#define V4L2_CID_DV_RX_POWER_PRESENT (V4L2_CID_DV_CLASS_BASE + 100) +#define V4L2_CID_DV_RX_RGB_RANGE (V4L2_CID_DV_CLASS_BASE + 101) /* * T U N I N G diff --git a/include/linux/virtio.h b/include/linux/virtio.h index a1ba8bbd9fbe..533b1157f22e 100644 --- a/include/linux/virtio.h +++ b/include/linux/virtio.h @@ -50,6 +50,8 @@ void *virtqueue_detach_unused_buf(struct virtqueue *vq); unsigned int virtqueue_get_vring_size(struct virtqueue *vq); +int virtqueue_get_queue_index(struct virtqueue *vq); + /** * virtio_device - representation of a device using virtio * @index: unique position on the virtio bus diff --git a/include/linux/virtio_config.h b/include/linux/virtio_config.h index fc457f452f64..e2850a7ea276 100644 --- a/include/linux/virtio_config.h +++ b/include/linux/virtio_config.h @@ -84,7 +84,9 @@ * nvqs: the number of virtqueues to find * vqs: on success, includes new virtqueues * callbacks: array of callbacks, for each virtqueue + * include a NULL entry for vqs that do not need a callback * names: array of virtqueue names (mainly for debugging) + * include a NULL entry for vqs unused by driver * Returns 0 on success or error status * @del_vqs: free virtqueues found by find_vqs(). * @get_features: get the array of feature bits for this device. @@ -98,6 +100,7 @@ * vdev: the virtio_device * This returns a pointer to the bus name a la pci_name from which * the caller can then copy. + * @set_vq_affinity: set the affinity for a virtqueue. */ typedef void vq_callback_t(struct virtqueue *); struct virtio_config_ops { @@ -116,6 +119,7 @@ struct virtio_config_ops { u32 (*get_features)(struct virtio_device *vdev); void (*finalize_features)(struct virtio_device *vdev); const char *(*bus_name)(struct virtio_device *vdev); + int (*set_vq_affinity)(struct virtqueue *vq, int cpu); }; /* If driver didn't advertise the feature, it will never appear. */ @@ -190,5 +194,24 @@ const char *virtio_bus_name(struct virtio_device *vdev) return vdev->config->bus_name(vdev); } +/** + * virtqueue_set_affinity - setting affinity for a virtqueue + * @vq: the virtqueue + * @cpu: the cpu no. + * + * Pay attention the function are best-effort: the affinity hint may not be set + * due to config support, irq type and sharing. + * + */ +static inline +int virtqueue_set_affinity(struct virtqueue *vq, int cpu) +{ + struct virtio_device *vdev = vq->vdev; + if (vdev->config->set_vq_affinity) + return vdev->config->set_vq_affinity(vq, cpu); + return 0; +} + + #endif /* __KERNEL__ */ #endif /* _LINUX_VIRTIO_CONFIG_H */ diff --git a/include/linux/virtio_ring.h b/include/linux/virtio_ring.h index e338730c2660..c2d793a06ad7 100644 --- a/include/linux/virtio_ring.h +++ b/include/linux/virtio_ring.h @@ -165,7 +165,8 @@ static inline int vring_need_event(__u16 event_idx, __u16 new_idx, __u16 old) struct virtio_device; struct virtqueue; -struct virtqueue *vring_new_virtqueue(unsigned int num, +struct virtqueue *vring_new_virtqueue(unsigned int index, + unsigned int num, unsigned int vring_align, struct virtio_device *vdev, bool weak_barriers, diff --git a/include/media/ad9389b.h b/include/media/ad9389b.h new file mode 100644 index 000000000000..5ba9af869b8b --- /dev/null +++ b/include/media/ad9389b.h @@ -0,0 +1,49 @@ +/* + * Analog Devices AD9389B/AD9889B video encoder driver header + * + * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. + * + * This program is free software; you may redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef AD9389B_H +#define AD9389B_H + +enum ad9389b_tmds_pll_gear { + AD9389B_TMDS_PLL_GEAR_AUTOMATIC, + AD9389B_TMDS_PLL_GEAR_SEMI_AUTOMATIC, +}; + +/* Platform dependent definitions */ +struct ad9389b_platform_data { + enum ad9389b_tmds_pll_gear tmds_pll_gear ; + /* Differential Data/Clock Output Drive Strength (reg. 0xa2/0xa3) */ + u8 diff_data_drive_strength; + u8 diff_clk_drive_strength; +}; + +/* notify events */ +#define AD9389B_MONITOR_DETECT 0 +#define AD9389B_EDID_DETECT 1 + +struct ad9389b_monitor_detect { + int present; +}; + +struct ad9389b_edid_detect { + int present; + int segment; +}; + +#endif diff --git a/include/media/adv7604.h b/include/media/adv7604.h new file mode 100644 index 000000000000..171b957db743 --- /dev/null +++ b/include/media/adv7604.h @@ -0,0 +1,153 @@ +/* + * adv7604 - Analog Devices ADV7604 video decoder driver + * + * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. + * + * This program is free software; you may redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + */ + +#ifndef _ADV7604_ +#define _ADV7604_ + +/* Analog input muxing modes (AFE register 0x02, [2:0]) */ +enum adv7604_ain_sel { + ADV7604_AIN1_2_3_NC_SYNC_1_2 = 0, + ADV7604_AIN4_5_6_NC_SYNC_2_1 = 1, + ADV7604_AIN7_8_9_NC_SYNC_3_1 = 2, + ADV7604_AIN10_11_12_NC_SYNC_4_1 = 3, + ADV7604_AIN9_4_5_6_SYNC_2_1 = 4, +}; + +/* Bus rotation and reordering (IO register 0x04, [7:5]) */ +enum adv7604_op_ch_sel { + ADV7604_OP_CH_SEL_GBR = 0, + ADV7604_OP_CH_SEL_GRB = 1, + ADV7604_OP_CH_SEL_BGR = 2, + ADV7604_OP_CH_SEL_RGB = 3, + ADV7604_OP_CH_SEL_BRG = 4, + ADV7604_OP_CH_SEL_RBG = 5, +}; + +/* Primary mode (IO register 0x01, [3:0]) */ +enum adv7604_prim_mode { + ADV7604_PRIM_MODE_COMP = 1, + ADV7604_PRIM_MODE_RGB = 2, + ADV7604_PRIM_MODE_HDMI_COMP = 5, + ADV7604_PRIM_MODE_HDMI_GR = 6, +}; + +/* Input Color Space (IO register 0x02, [7:4]) */ +enum adv7604_inp_color_space { + ADV7604_INP_COLOR_SPACE_LIM_RGB = 0, + ADV7604_INP_COLOR_SPACE_FULL_RGB = 1, + ADV7604_INP_COLOR_SPACE_LIM_YCbCr_601 = 2, + ADV7604_INP_COLOR_SPACE_LIM_YCbCr_709 = 3, + ADV7604_INP_COLOR_SPACE_XVYCC_601 = 4, + ADV7604_INP_COLOR_SPACE_XVYCC_709 = 5, + ADV7604_INP_COLOR_SPACE_FULL_YCbCr_601 = 6, + ADV7604_INP_COLOR_SPACE_FULL_YCbCr_709 = 7, + ADV7604_INP_COLOR_SPACE_AUTO = 0xf, +}; + +/* Select output format (IO register 0x03, [7:0]) */ +enum adv7604_op_format_sel { + ADV7604_OP_FORMAT_SEL_SDR_ITU656_8 = 0x00, + ADV7604_OP_FORMAT_SEL_SDR_ITU656_10 = 0x01, + ADV7604_OP_FORMAT_SEL_SDR_ITU656_12_MODE0 = 0x02, + ADV7604_OP_FORMAT_SEL_SDR_ITU656_12_MODE1 = 0x06, + ADV7604_OP_FORMAT_SEL_SDR_ITU656_12_MODE2 = 0x0a, + ADV7604_OP_FORMAT_SEL_DDR_422_8 = 0x20, + ADV7604_OP_FORMAT_SEL_DDR_422_10 = 0x21, + ADV7604_OP_FORMAT_SEL_DDR_422_12_MODE0 = 0x22, + ADV7604_OP_FORMAT_SEL_DDR_422_12_MODE1 = 0x23, + ADV7604_OP_FORMAT_SEL_DDR_422_12_MODE2 = 0x24, + ADV7604_OP_FORMAT_SEL_SDR_444_24 = 0x40, + ADV7604_OP_FORMAT_SEL_SDR_444_30 = 0x41, + ADV7604_OP_FORMAT_SEL_SDR_444_36_MODE0 = 0x42, + ADV7604_OP_FORMAT_SEL_DDR_444_24 = 0x60, + ADV7604_OP_FORMAT_SEL_DDR_444_30 = 0x61, + ADV7604_OP_FORMAT_SEL_DDR_444_36 = 0x62, + ADV7604_OP_FORMAT_SEL_SDR_ITU656_16 = 0x80, + ADV7604_OP_FORMAT_SEL_SDR_ITU656_20 = 0x81, + ADV7604_OP_FORMAT_SEL_SDR_ITU656_24_MODE0 = 0x82, + ADV7604_OP_FORMAT_SEL_SDR_ITU656_24_MODE1 = 0x86, + ADV7604_OP_FORMAT_SEL_SDR_ITU656_24_MODE2 = 0x8a, +}; + +/* Platform dependent definition */ +struct adv7604_platform_data { + /* connector - HDMI or DVI? */ + unsigned connector_hdmi:1; + + /* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */ + unsigned disable_pwrdnb:1; + + /* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */ + unsigned disable_cable_det_rst:1; + + /* Analog input muxing mode */ + enum adv7604_ain_sel ain_sel; + + /* Bus rotation and reordering */ + enum adv7604_op_ch_sel op_ch_sel; + + /* Primary mode */ + enum adv7604_prim_mode prim_mode; + + /* Select output format */ + enum adv7604_op_format_sel op_format_sel; + + /* IO register 0x02 */ + unsigned alt_gamma:1; + unsigned op_656_range:1; + unsigned rgb_out:1; + unsigned alt_data_sat:1; + + /* IO register 0x05 */ + unsigned blank_data:1; + unsigned insert_av_codes:1; + unsigned replicate_av_codes:1; + unsigned invert_cbcr:1; + + /* IO register 0x30 */ + unsigned output_bus_lsb_to_msb:1; + + /* Free run */ + unsigned hdmi_free_run_mode; + + /* i2c addresses: 0 == use default */ + u8 i2c_avlink; + u8 i2c_cec; + u8 i2c_infoframe; + u8 i2c_esdp; + u8 i2c_dpp; + u8 i2c_afe; + u8 i2c_repeater; + u8 i2c_edid; + u8 i2c_hdmi; + u8 i2c_test; + u8 i2c_cp; + u8 i2c_vdp; +}; + +#define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE (V4L2_CID_DV_CLASS_BASE + 0x1000) +#define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL (V4L2_CID_DV_CLASS_BASE + 0x1001) +#define V4L2_CID_ADV_RX_FREE_RUN_COLOR (V4L2_CID_DV_CLASS_BASE + 0x1002) + +/* notify events */ +#define ADV7604_HOTPLUG 1 +#define ADV7604_FMT_CHANGE 2 + +#endif diff --git a/include/media/ir-rx51.h b/include/media/ir-rx51.h new file mode 100644 index 000000000000..104aa892f31b --- /dev/null +++ b/include/media/ir-rx51.h @@ -0,0 +1,10 @@ +#ifndef _LIRC_RX51_H +#define _LIRC_RX51_H + +struct lirc_rx51_platform_data { + int pwm_timer; + + int(*set_max_mpu_wakeup_lat)(struct device *dev, long t); +}; + +#endif diff --git a/include/media/mt9v032.h b/include/media/mt9v032.h index 5e27f9be6b95..78fd39eac219 100644 --- a/include/media/mt9v032.h +++ b/include/media/mt9v032.h @@ -7,6 +7,9 @@ struct mt9v032_platform_data { unsigned int clk_pol:1; void (*set_clock)(struct v4l2_subdev *subdev, unsigned int rate); + + const s64 *link_freqs; + s64 link_def_freq; }; #endif diff --git a/include/media/omap3isp.h b/include/media/omap3isp.h index 4d94be5226af..95842696857f 100644 --- a/include/media/omap3isp.h +++ b/include/media/omap3isp.h @@ -42,12 +42,6 @@ enum isp_interface_type { }; enum { - ISP_BRIDGE_DISABLE = 0, - ISP_BRIDGE_LITTLE_ENDIAN = 2, - ISP_BRIDGE_BIG_ENDIAN = 3, -}; - -enum { ISP_LANE_SHIFT_0 = 0, ISP_LANE_SHIFT_2 = 1, ISP_LANE_SHIFT_4 = 2, @@ -67,17 +61,15 @@ enum { * 0 - Active high, 1 - Active low * @vs_pol: Vertical synchronization polarity * 0 - Active high, 1 - Active low - * @bridge: CCDC Bridge input control - * ISP_BRIDGE_DISABLE - Disable - * ISP_BRIDGE_LITTLE_ENDIAN - Little endian - * ISP_BRIDGE_BIG_ENDIAN - Big endian + * @data_pol: Data polarity + * 0 - Normal, 1 - One's complement */ struct isp_parallel_platform_data { unsigned int data_lane_shift:2; unsigned int clk_pol:1; unsigned int hs_pol:1; unsigned int vs_pol:1; - unsigned int bridge:2; + unsigned int data_pol:1; }; enum { diff --git a/include/media/s5k4ecgx.h b/include/media/s5k4ecgx.h new file mode 100644 index 000000000000..90c1be792ffe --- /dev/null +++ b/include/media/s5k4ecgx.h @@ -0,0 +1,37 @@ +/* + * S5K4ECGX image sensor header file + * + * Copyright (C) 2012, Linaro + * Copyright (C) 2012, Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef S5K4ECGX_H +#define S5K4ECGX_H + +/** + * struct s5k4ecgx_gpio - data structure describing a GPIO + * @gpio : GPIO number + * @level: indicates active state of the @gpio + */ +struct s5k4ecgx_gpio { + int gpio; + int level; +}; + +/** + * struct ss5k4ecgx_platform_data- s5k4ecgx driver platform data + * @gpio_reset: GPIO driving RESET pin + * @gpio_stby : GPIO driving STBY pin + */ + +struct s5k4ecgx_platform_data { + struct s5k4ecgx_gpio gpio_reset; + struct s5k4ecgx_gpio gpio_stby; +}; + +#endif /* S5K4ECGX_H */ diff --git a/include/media/s5p_fimc.h b/include/media/s5p_fimc.h index 8587aaf73646..09421a611d73 100644 --- a/include/media/s5p_fimc.h +++ b/include/media/s5p_fimc.h @@ -12,6 +12,8 @@ #ifndef S5P_FIMC_H_ #define S5P_FIMC_H_ +#include <media/media-entity.h> + enum cam_bus_type { FIMC_ITU_601 = 1, FIMC_ITU_656, @@ -80,4 +82,20 @@ struct fimc_pipeline { struct media_pipeline *m_pipeline; }; +/* + * Media pipeline operations to be called from within the fimc(-lite) + * video node when it is the last entity of the pipeline. Implemented + * by corresponding media device driver. + */ +struct fimc_pipeline_ops { + int (*open)(struct fimc_pipeline *p, struct media_entity *me, + bool resume); + int (*close)(struct fimc_pipeline *p); + int (*set_stream)(struct fimc_pipeline *p, bool state); +}; + +#define fimc_pipeline_call(f, op, p, args...) \ + (!(f) ? -ENODEV : (((f)->pipeline_ops && (f)->pipeline_ops->op) ? \ + (f)->pipeline_ops->op((p), ##args) : -ENOIOCTLCMD)) + #endif /* S5P_FIMC_H_ */ diff --git a/include/media/s5p_hdmi.h b/include/media/s5p_hdmi.h index 361a751f73af..181642b8d0a5 100644 --- a/include/media/s5p_hdmi.h +++ b/include/media/s5p_hdmi.h @@ -20,6 +20,7 @@ struct i2c_board_info; * @hdmiphy_info: template for HDMIPHY I2C device * @mhl_bus: controller id for MHL control bus * @mhl_info: template for MHL I2C device + * @hpd_gpio: GPIO for Hot-Plug-Detect pin * * NULL pointer for *_info fields indicates that * the corresponding chip is not present @@ -29,6 +30,7 @@ struct s5p_hdmi_platform_data { struct i2c_board_info *hdmiphy_info; int mhl_bus; struct i2c_board_info *mhl_info; + int hpd_gpio; }; #endif /* S5P_HDMI_H */ diff --git a/include/media/saa7146.h b/include/media/saa7146.h index 773e527deabe..96058a5a4acc 100644 --- a/include/media/saa7146.h +++ b/include/media/saa7146.h @@ -117,8 +117,6 @@ struct saa7146_dev { struct module *module; - struct list_head item; - struct v4l2_device v4l2_dev; struct v4l2_ctrl_handler ctrl_handler; @@ -166,8 +164,6 @@ static inline struct saa7146_dev *to_saa7146_dev(struct v4l2_device *v4l2_dev) int saa7146_i2c_adapter_prepare(struct saa7146_dev *dev, struct i2c_adapter *i2c_adapter, u32 bitrate); /* from saa7146_core.c */ -extern struct list_head saa7146_devices; -extern struct mutex saa7146_devices_lock; int saa7146_register_extension(struct saa7146_extension*); int saa7146_unregister_extension(struct saa7146_extension*); struct saa7146_format* saa7146_format_by_fourcc(struct saa7146_dev *dev, int fourcc); diff --git a/include/media/soc_camera.h b/include/media/soc_camera.h index d865dcf9879f..6442edc2a151 100644 --- a/include/media/soc_camera.h +++ b/include/media/soc_camera.h @@ -85,12 +85,14 @@ struct soc_camera_host_ops { void (*put_formats)(struct soc_camera_device *); int (*cropcap)(struct soc_camera_device *, struct v4l2_cropcap *); int (*get_crop)(struct soc_camera_device *, struct v4l2_crop *); - int (*set_crop)(struct soc_camera_device *, struct v4l2_crop *); + int (*set_crop)(struct soc_camera_device *, const struct v4l2_crop *); + int (*get_selection)(struct soc_camera_device *, struct v4l2_selection *); + int (*set_selection)(struct soc_camera_device *, struct v4l2_selection *); /* * The difference to .set_crop() is, that .set_livecrop is not allowed * to change the output sizes */ - int (*set_livecrop)(struct soc_camera_device *, struct v4l2_crop *); + int (*set_livecrop)(struct soc_camera_device *, const struct v4l2_crop *); int (*set_fmt)(struct soc_camera_device *, struct v4l2_format *); int (*try_fmt)(struct soc_camera_device *, struct v4l2_format *); void (*init_videobuf)(struct videobuf_queue *, @@ -254,6 +256,16 @@ unsigned long soc_camera_apply_sensor_flags(struct soc_camera_link *icl, unsigned long soc_camera_apply_board_flags(struct soc_camera_link *icl, const struct v4l2_mbus_config *cfg); +int soc_camera_power_on(struct device *dev, struct soc_camera_link *icl); +int soc_camera_power_off(struct device *dev, struct soc_camera_link *icl); + +static inline int soc_camera_set_power(struct device *dev, + struct soc_camera_link *icl, bool on) +{ + return on ? soc_camera_power_on(dev, icl) + : soc_camera_power_off(dev, icl); +} + /* This is only temporary here - until v4l2-subdev begins to link to video_device */ #include <linux/i2c.h> static inline struct video_device *soc_camera_i2c_to_vdev(const struct i2c_client *client) diff --git a/include/media/v4l2-chip-ident.h b/include/media/v4l2-chip-ident.h index 58f914a40b20..4ee125bae719 100644 --- a/include/media/v4l2-chip-ident.h +++ b/include/media/v4l2-chip-ident.h @@ -183,6 +183,9 @@ enum { /* module adv7393: just ident 7393 */ V4L2_IDENT_ADV7393 = 7393, + /* module adv7604: just ident 7604 */ + V4L2_IDENT_ADV7604 = 7604, + /* module saa7706h: just ident 7706 */ V4L2_IDENT_SAA7706H = 7706, @@ -212,6 +215,9 @@ enum { V4L2_IDENT_CX23888_AV = 8881, /* Integrated A/V decoder */ V4L2_IDENT_CX23888_IR = 8882, /* Integrated infrared controller */ + /* module ad9389b: just ident 9389 */ + V4L2_IDENT_AD9389B = 9389, + /* module tda9840: just ident 9840 */ V4L2_IDENT_TDA9840 = 9840, diff --git a/include/media/v4l2-common.h b/include/media/v4l2-common.h index a298ec49ddc4..1a0b2db4c5d3 100644 --- a/include/media/v4l2-common.h +++ b/include/media/v4l2-common.h @@ -133,7 +133,7 @@ struct v4l2_subdev *v4l2_i2c_new_subdev_board(struct v4l2_device *v4l2_dev, struct i2c_adapter *adapter, struct i2c_board_info *info, const unsigned short *probe_addrs); -/* Initialize an v4l2_subdev with data from an i2c_client struct */ +/* Initialize a v4l2_subdev with data from an i2c_client struct */ void v4l2_i2c_subdev_init(struct v4l2_subdev *sd, struct i2c_client *client, const struct v4l2_subdev_ops *ops); /* Return i2c client address of v4l2_subdev. */ @@ -166,7 +166,7 @@ struct spi_device; struct v4l2_subdev *v4l2_spi_new_subdev(struct v4l2_device *v4l2_dev, struct spi_master *master, struct spi_board_info *info); -/* Initialize an v4l2_subdev with data from an spi_device struct */ +/* Initialize a v4l2_subdev with data from an spi_device struct */ void v4l2_spi_subdev_init(struct v4l2_subdev *sd, struct spi_device *spi, const struct v4l2_subdev_ops *ops); #endif @@ -212,4 +212,17 @@ const struct v4l2_frmsize_discrete *v4l2_find_nearest_format( const struct v4l2_discrete_probe *probe, s32 width, s32 height); +bool v4l_match_dv_timings(const struct v4l2_dv_timings *t1, + const struct v4l2_dv_timings *t2, + unsigned pclock_delta); + +bool v4l2_detect_cvt(unsigned frame_height, unsigned hfreq, unsigned vsync, + u32 polarities, struct v4l2_dv_timings *fmt); + +bool v4l2_detect_gtf(unsigned frame_height, unsigned hfreq, unsigned vsync, + u32 polarities, struct v4l2_fract aspect, + struct v4l2_dv_timings *fmt); + +struct v4l2_fract v4l2_calc_aspect_ratio(u8 hor_landscape, u8 vert_portrait); + #endif /* V4L2_COMMON_H_ */ diff --git a/include/media/v4l2-ctrls.h b/include/media/v4l2-ctrls.h index 776605f1cbe2..801adb466bd2 100644 --- a/include/media/v4l2-ctrls.h +++ b/include/media/v4l2-ctrls.h @@ -384,14 +384,28 @@ struct v4l2_ctrl *v4l2_ctrl_add_ctrl(struct v4l2_ctrl_handler *hdl, * @hdl: The control handler. * @add: The control handler whose controls you want to add to * the @hdl control handler. + * @filter: This function will filter which controls should be added. * - * Does nothing if either of the two is a NULL pointer. + * Does nothing if either of the two handlers is a NULL pointer. + * If @filter is NULL, then all controls are added. Otherwise only those + * controls for which @filter returns true will be added. * In case of an error @hdl->error will be set to the error code (if it * wasn't set already). */ int v4l2_ctrl_add_handler(struct v4l2_ctrl_handler *hdl, - struct v4l2_ctrl_handler *add); + struct v4l2_ctrl_handler *add, + bool (*filter)(const struct v4l2_ctrl *ctrl)); +/** v4l2_ctrl_radio_filter() - Standard filter for radio controls. + * @ctrl: The control that is filtered. + * + * This will return true for any controls that are valid for radio device + * nodes. Those are all of the V4L2_CID_AUDIO_* user controls and all FM + * transmitter class controls. + * + * This function is to be used with v4l2_ctrl_add_handler(). + */ +bool v4l2_ctrl_radio_filter(const struct v4l2_ctrl *ctrl); /** v4l2_ctrl_cluster() - Mark all controls in the cluster as belonging to that cluster. * @ncontrols: The number of controls in this cluster. @@ -511,6 +525,29 @@ s32 v4l2_ctrl_g_ctrl(struct v4l2_ctrl *ctrl); */ int v4l2_ctrl_s_ctrl(struct v4l2_ctrl *ctrl, s32 val); +/** v4l2_ctrl_g_ctrl_int64() - Helper function to get a 64-bit control's value from within a driver. + * @ctrl: The control. + * + * This returns the control's value safely by going through the control + * framework. This function will lock the control's handler, so it cannot be + * used from within the &v4l2_ctrl_ops functions. + * + * This function is for 64-bit integer type controls only. + */ +s64 v4l2_ctrl_g_ctrl_int64(struct v4l2_ctrl *ctrl); + +/** v4l2_ctrl_s_ctrl_int64() - Helper function to set a 64-bit control's value from within a driver. + * @ctrl: The control. + * @val: The new value. + * + * This set the control's new value safely by going through the control + * framework. This function will lock the control's handler, so it cannot be + * used from within the &v4l2_ctrl_ops functions. + * + * This function is for 64-bit integer type controls only. + */ +int v4l2_ctrl_s_ctrl_int64(struct v4l2_ctrl *ctrl, s64 val); + /* Internal helper functions that deal with control events. */ extern const struct v4l2_subscribed_event_ops v4l2_ctrl_sub_ev_ops; void v4l2_ctrl_replace(struct v4l2_event *old, const struct v4l2_event *new); @@ -523,7 +560,7 @@ int v4l2_ctrl_log_status(struct file *file, void *fh); /* Can be used as a vidioc_subscribe_event function that just subscribes control events. */ int v4l2_ctrl_subscribe_event(struct v4l2_fh *fh, - struct v4l2_event_subscription *sub); + const struct v4l2_event_subscription *sub); /* Can be used as a poll function that just polls for control events. */ unsigned int v4l2_ctrl_poll(struct file *file, struct poll_table_struct *wait); diff --git a/include/media/v4l2-dev.h b/include/media/v4l2-dev.h index 5c416cdc88d5..95d1c91770f4 100644 --- a/include/media/v4l2-dev.h +++ b/include/media/v4l2-dev.h @@ -26,6 +26,12 @@ #define VFL_TYPE_SUBDEV 3 #define VFL_TYPE_MAX 4 +/* Is this a receiver, transmitter or mem-to-mem? */ +/* Ignored for VFL_TYPE_SUBDEV. */ +#define VFL_DIR_RX 0 +#define VFL_DIR_TX 1 +#define VFL_DIR_M2M 2 + struct v4l2_ioctl_callbacks; struct video_device; struct v4l2_device; @@ -39,9 +45,6 @@ struct v4l2_ctrl_handler; #define V4L2_FL_USES_V4L2_FH (1) /* Use the prio field of v4l2_fh for core priority checking */ #define V4L2_FL_USE_FH_PRIO (2) -/* If ioctl core locking is in use, then apply that also to all - file operations. Don't use this flag in new drivers! */ -#define V4L2_FL_LOCK_ALL_FOPS (3) /* Priority helper functions */ @@ -108,7 +111,8 @@ struct video_device /* device info */ char name[32]; - int vfl_type; + int vfl_type; /* device type */ + int vfl_dir; /* receiver, transmitter or m2m */ /* 'minor' is set to -1 if the registration failed */ int minor; u16 num; diff --git a/include/media/v4l2-event.h b/include/media/v4l2-event.h index 2885a810a128..e7c5d170a9cd 100644 --- a/include/media/v4l2-event.h +++ b/include/media/v4l2-event.h @@ -124,10 +124,10 @@ void v4l2_event_queue(struct video_device *vdev, const struct v4l2_event *ev); void v4l2_event_queue_fh(struct v4l2_fh *fh, const struct v4l2_event *ev); int v4l2_event_pending(struct v4l2_fh *fh); int v4l2_event_subscribe(struct v4l2_fh *fh, - struct v4l2_event_subscription *sub, unsigned elems, + const struct v4l2_event_subscription *sub, unsigned elems, const struct v4l2_subscribed_event_ops *ops); int v4l2_event_unsubscribe(struct v4l2_fh *fh, - struct v4l2_event_subscription *sub); + const struct v4l2_event_subscription *sub); void v4l2_event_unsubscribe_all(struct v4l2_fh *fh); #endif /* V4L2_EVENT_H */ diff --git a/include/media/v4l2-ioctl.h b/include/media/v4l2-ioctl.h index e614c9c15e56..e48b571ca37d 100644 --- a/include/media/v4l2-ioctl.h +++ b/include/media/v4l2-ioctl.h @@ -40,8 +40,6 @@ struct v4l2_ioctl_ops { struct v4l2_fmtdesc *f); int (*vidioc_enum_fmt_vid_out_mplane)(struct file *file, void *fh, struct v4l2_fmtdesc *f); - int (*vidioc_enum_fmt_type_private)(struct file *file, void *fh, - struct v4l2_fmtdesc *f); /* VIDIOC_G_FMT handlers */ int (*vidioc_g_fmt_vid_cap) (struct file *file, void *fh, @@ -64,8 +62,6 @@ struct v4l2_ioctl_ops { struct v4l2_format *f); int (*vidioc_g_fmt_vid_out_mplane)(struct file *file, void *fh, struct v4l2_format *f); - int (*vidioc_g_fmt_type_private)(struct file *file, void *fh, - struct v4l2_format *f); /* VIDIOC_S_FMT handlers */ int (*vidioc_s_fmt_vid_cap) (struct file *file, void *fh, @@ -88,8 +84,6 @@ struct v4l2_ioctl_ops { struct v4l2_format *f); int (*vidioc_s_fmt_vid_out_mplane)(struct file *file, void *fh, struct v4l2_format *f); - int (*vidioc_s_fmt_type_private)(struct file *file, void *fh, - struct v4l2_format *f); /* VIDIOC_TRY_FMT handlers */ int (*vidioc_try_fmt_vid_cap) (struct file *file, void *fh, @@ -112,8 +106,6 @@ struct v4l2_ioctl_ops { struct v4l2_format *f); int (*vidioc_try_fmt_vid_out_mplane)(struct file *file, void *fh, struct v4l2_format *f); - int (*vidioc_try_fmt_type_private)(struct file *file, void *fh, - struct v4l2_format *f); /* Buffer handlers */ int (*vidioc_reqbufs) (struct file *file, void *fh, struct v4l2_requestbuffers *b); @@ -128,7 +120,7 @@ struct v4l2_ioctl_ops { int (*vidioc_g_fbuf) (struct file *file, void *fh, struct v4l2_framebuffer *a); int (*vidioc_s_fbuf) (struct file *file, void *fh, - struct v4l2_framebuffer *a); + const struct v4l2_framebuffer *a); /* Stream on/off */ int (*vidioc_streamon) (struct file *file, void *fh, enum v4l2_buf_type i); @@ -175,7 +167,7 @@ struct v4l2_ioctl_ops { int (*vidioc_g_audio) (struct file *file, void *fh, struct v4l2_audio *a); int (*vidioc_s_audio) (struct file *file, void *fh, - struct v4l2_audio *a); + const struct v4l2_audio *a); /* Audio out ioctls */ int (*vidioc_enumaudout) (struct file *file, void *fh, @@ -183,18 +175,18 @@ struct v4l2_ioctl_ops { int (*vidioc_g_audout) (struct file *file, void *fh, struct v4l2_audioout *a); int (*vidioc_s_audout) (struct file *file, void *fh, - struct v4l2_audioout *a); + const struct v4l2_audioout *a); int (*vidioc_g_modulator) (struct file *file, void *fh, struct v4l2_modulator *a); int (*vidioc_s_modulator) (struct file *file, void *fh, - struct v4l2_modulator *a); + const struct v4l2_modulator *a); /* Crop ioctls */ int (*vidioc_cropcap) (struct file *file, void *fh, struct v4l2_cropcap *a); int (*vidioc_g_crop) (struct file *file, void *fh, struct v4l2_crop *a); int (*vidioc_s_crop) (struct file *file, void *fh, - struct v4l2_crop *a); + const struct v4l2_crop *a); int (*vidioc_g_selection) (struct file *file, void *fh, struct v4l2_selection *s); int (*vidioc_s_selection) (struct file *file, void *fh, @@ -203,7 +195,7 @@ struct v4l2_ioctl_ops { int (*vidioc_g_jpegcomp) (struct file *file, void *fh, struct v4l2_jpegcompression *a); int (*vidioc_s_jpegcomp) (struct file *file, void *fh, - struct v4l2_jpegcompression *a); + const struct v4l2_jpegcompression *a); int (*vidioc_g_enc_index) (struct file *file, void *fh, struct v4l2_enc_idx *a); int (*vidioc_encoder_cmd) (struct file *file, void *fh, @@ -241,7 +233,7 @@ struct v4l2_ioctl_ops { int (*vidioc_log_status) (struct file *file, void *fh); int (*vidioc_s_hw_freq_seek) (struct file *file, void *fh, - struct v4l2_hw_freq_seek *a); + const struct v4l2_hw_freq_seek *a); /* Debugging ioctls */ #ifdef CONFIG_VIDEO_ADV_DEBUG @@ -281,9 +273,9 @@ struct v4l2_ioctl_ops { struct v4l2_dv_timings_cap *cap); int (*vidioc_subscribe_event) (struct v4l2_fh *fh, - struct v4l2_event_subscription *sub); + const struct v4l2_event_subscription *sub); int (*vidioc_unsubscribe_event)(struct v4l2_fh *fh, - struct v4l2_event_subscription *sub); + const struct v4l2_event_subscription *sub); /* For other private ioctls */ long (*vidioc_default) (struct file *file, void *fh, diff --git a/include/media/v4l2-mem2mem.h b/include/media/v4l2-mem2mem.h index 16ac4733e80d..131cc4a53675 100644 --- a/include/media/v4l2-mem2mem.h +++ b/include/media/v4l2-mem2mem.h @@ -140,7 +140,7 @@ void v4l2_m2m_buf_queue(struct v4l2_m2m_ctx *m2m_ctx, struct vb2_buffer *vb); static inline unsigned int v4l2_m2m_num_src_bufs_ready(struct v4l2_m2m_ctx *m2m_ctx) { - return m2m_ctx->cap_q_ctx.num_rdy; + return m2m_ctx->out_q_ctx.num_rdy; } /** @@ -150,7 +150,7 @@ unsigned int v4l2_m2m_num_src_bufs_ready(struct v4l2_m2m_ctx *m2m_ctx) static inline unsigned int v4l2_m2m_num_dst_bufs_ready(struct v4l2_m2m_ctx *m2m_ctx) { - return m2m_ctx->out_q_ctx.num_rdy; + return m2m_ctx->cap_q_ctx.num_rdy; } void *v4l2_m2m_next_buf(struct v4l2_m2m_queue_ctx *q_ctx); diff --git a/include/media/v4l2-subdev.h b/include/media/v4l2-subdev.h index c35a3545e273..2ecd7377153b 100644 --- a/include/media/v4l2-subdev.h +++ b/include/media/v4l2-subdev.h @@ -120,7 +120,7 @@ struct v4l2_subdev_io_pin_config { each pin being configured. This function could be called at times other than just subdevice initialization. - init: initialize the sensor registors to some sort of reasonable default + init: initialize the sensor registers to some sort of reasonable default values. Do not use for new drivers and should be removed in existing drivers. @@ -194,7 +194,7 @@ struct v4l2_subdev_tuner_ops { int (*g_tuner)(struct v4l2_subdev *sd, struct v4l2_tuner *vt); int (*s_tuner)(struct v4l2_subdev *sd, struct v4l2_tuner *vt); int (*g_modulator)(struct v4l2_subdev *sd, struct v4l2_modulator *vm); - int (*s_modulator)(struct v4l2_subdev *sd, struct v4l2_modulator *vm); + int (*s_modulator)(struct v4l2_subdev *sd, const struct v4l2_modulator *vm); int (*s_type_addr)(struct v4l2_subdev *sd, struct tuner_setup *type); int (*s_config)(struct v4l2_subdev *sd, const struct v4l2_priv_tun_config *config); }; @@ -286,7 +286,7 @@ struct v4l2_subdev_video_ops { int (*s_stream)(struct v4l2_subdev *sd, int enable); int (*cropcap)(struct v4l2_subdev *sd, struct v4l2_cropcap *cc); int (*g_crop)(struct v4l2_subdev *sd, struct v4l2_crop *crop); - int (*s_crop)(struct v4l2_subdev *sd, struct v4l2_crop *crop); + int (*s_crop)(struct v4l2_subdev *sd, const struct v4l2_crop *crop); int (*g_parm)(struct v4l2_subdev *sd, struct v4l2_streamparm *param); int (*s_parm)(struct v4l2_subdev *sd, struct v4l2_streamparm *param); int (*g_frame_interval)(struct v4l2_subdev *sd, @@ -476,6 +476,8 @@ struct v4l2_subdev_pad_ops { struct v4l2_subdev_selection *sel); int (*set_selection)(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, struct v4l2_subdev_selection *sel); + int (*get_edid)(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid); + int (*set_edid)(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid); #ifdef CONFIG_MEDIA_CONTROLLER int (*link_validate)(struct v4l2_subdev *sd, struct media_link *link, struct v4l2_subdev_format *source_fmt, diff --git a/include/media/videobuf-dvb.h b/include/media/videobuf-dvb.h index bf365721d6b0..d63965a1faaf 100644 --- a/include/media/videobuf-dvb.h +++ b/include/media/videobuf-dvb.h @@ -45,9 +45,7 @@ int videobuf_dvb_register_bus(struct videobuf_dvb_frontends *f, void *adapter_priv, struct device *device, short *adapter_nr, - int mfe_shared, - int (*fe_ioctl_override)(struct dvb_frontend *, - unsigned int, void *, unsigned int)); + int mfe_shared); void videobuf_dvb_unregister_bus(struct videobuf_dvb_frontends *f); diff --git a/include/media/videobuf2-core.h b/include/media/videobuf2-core.h index 8dd9b6cc296b..e04252a9fea6 100644 --- a/include/media/videobuf2-core.h +++ b/include/media/videobuf2-core.h @@ -324,7 +324,7 @@ int vb2_reqbufs(struct vb2_queue *q, struct v4l2_requestbuffers *req); int vb2_create_bufs(struct vb2_queue *q, struct v4l2_create_buffers *create); int vb2_prepare_buf(struct vb2_queue *q, struct v4l2_buffer *b); -int vb2_queue_init(struct vb2_queue *q); +int __must_check vb2_queue_init(struct vb2_queue *q); void vb2_queue_release(struct vb2_queue *q); diff --git a/include/net/ip_fib.h b/include/net/ip_fib.h index 926142ed8d7a..9497be1ad4c0 100644 --- a/include/net/ip_fib.h +++ b/include/net/ip_fib.h @@ -102,6 +102,7 @@ struct fib_info { unsigned char fib_dead; unsigned char fib_protocol; unsigned char fib_scope; + unsigned char fib_type; __be32 fib_prefsrc; u32 fib_priority; u32 *fib_metrics; diff --git a/include/net/sctp/structs.h b/include/net/sctp/structs.h index 0fef00f5d3ce..64158aa1bb5f 100644 --- a/include/net/sctp/structs.h +++ b/include/net/sctp/structs.h @@ -1068,7 +1068,7 @@ void sctp_outq_init(struct sctp_association *, struct sctp_outq *); void sctp_outq_teardown(struct sctp_outq *); void sctp_outq_free(struct sctp_outq*); int sctp_outq_tail(struct sctp_outq *, struct sctp_chunk *chunk); -int sctp_outq_sack(struct sctp_outq *, struct sctp_sackhdr *); +int sctp_outq_sack(struct sctp_outq *, struct sctp_chunk *); int sctp_outq_is_empty(const struct sctp_outq *); void sctp_outq_restart(struct sctp_outq *); diff --git a/include/sound/ac97_codec.h b/include/sound/ac97_codec.h index fdeb8dceec0f..d315a08d6c6d 100644 --- a/include/sound/ac97_codec.h +++ b/include/sound/ac97_codec.h @@ -422,6 +422,7 @@ */ struct snd_ac97; +struct snd_pcm_chmap; struct snd_ac97_build_ops { int (*build_3d) (struct snd_ac97 *ac97); @@ -528,6 +529,8 @@ struct snd_ac97 { struct delayed_work power_work; #endif struct device dev; + + struct snd_pcm_chmap *chmaps[2]; /* channel-maps (optional) */ }; #define to_ac97_t(d) container_of(d, struct snd_ac97, dev) diff --git a/include/sound/ad1816a.h b/include/sound/ad1816a.h index a7d8dc782e7c..abdf609c5918 100644 --- a/include/sound/ad1816a.h +++ b/include/sound/ad1816a.h @@ -147,6 +147,9 @@ struct snd_ad1816a { unsigned int c_dma_size; struct snd_timer *timer; +#ifdef CONFIG_PM + unsigned short image[48]; +#endif }; @@ -165,11 +168,15 @@ struct snd_ad1816a { extern int snd_ad1816a_create(struct snd_card *card, unsigned long port, int irq, int dma1, int dma2, - struct snd_ad1816a **chip); + struct snd_ad1816a *chip); extern int snd_ad1816a_pcm(struct snd_ad1816a *chip, int device, struct snd_pcm **rpcm); extern int snd_ad1816a_mixer(struct snd_ad1816a *chip); extern int snd_ad1816a_timer(struct snd_ad1816a *chip, int device, struct snd_timer **rtimer); +#ifdef CONFIG_PM +extern void snd_ad1816a_suspend(struct snd_ad1816a *chip); +extern void snd_ad1816a_resume(struct snd_ad1816a *chip); +#endif #endif /* __SOUND_AD1816A_H */ diff --git a/include/sound/asound.h b/include/sound/asound.h index 0876a1e76aef..dfe7d441748c 100644 --- a/include/sound/asound.h +++ b/include/sound/asound.h @@ -472,6 +472,45 @@ enum { SNDRV_PCM_TSTAMP_TYPE_LAST = SNDRV_PCM_TSTAMP_TYPE_MONOTONIC, }; +/* channel positions */ +enum { + SNDRV_CHMAP_UNKNOWN = 0, + SNDRV_CHMAP_NA, /* N/A, silent */ + SNDRV_CHMAP_MONO, /* mono stream */ + /* this follows the alsa-lib mixer channel value + 3 */ + SNDRV_CHMAP_FL, /* front left */ + SNDRV_CHMAP_FR, /* front right */ + SNDRV_CHMAP_RL, /* rear left */ + SNDRV_CHMAP_RR, /* rear right */ + SNDRV_CHMAP_FC, /* front center */ + SNDRV_CHMAP_LFE, /* LFE */ + SNDRV_CHMAP_SL, /* side left */ + SNDRV_CHMAP_SR, /* side right */ + SNDRV_CHMAP_RC, /* rear center */ + /* new definitions */ + SNDRV_CHMAP_FLC, /* front left center */ + SNDRV_CHMAP_FRC, /* front right center */ + SNDRV_CHMAP_RLC, /* rear left center */ + SNDRV_CHMAP_RRC, /* rear right center */ + SNDRV_CHMAP_FLW, /* front left wide */ + SNDRV_CHMAP_FRW, /* front right wide */ + SNDRV_CHMAP_FLH, /* front left high */ + SNDRV_CHMAP_FCH, /* front center high */ + SNDRV_CHMAP_FRH, /* front right high */ + SNDRV_CHMAP_TC, /* top center */ + SNDRV_CHMAP_TFL, /* top front left */ + SNDRV_CHMAP_TFR, /* top front right */ + SNDRV_CHMAP_TFC, /* top front center */ + SNDRV_CHMAP_TRL, /* top rear left */ + SNDRV_CHMAP_TRR, /* top rear right */ + SNDRV_CHMAP_TRC, /* top rear center */ + SNDRV_CHMAP_LAST = SNDRV_CHMAP_TRC, +}; + +#define SNDRV_CHMAP_POSITION_MASK 0xffff +#define SNDRV_CHMAP_PHASE_INVERSE (0x01 << 16) +#define SNDRV_CHMAP_DRIVER_SPEC (0x02 << 16) + #define SNDRV_PCM_IOCTL_PVERSION _IOR('A', 0x00, int) #define SNDRV_PCM_IOCTL_INFO _IOR('A', 0x01, struct snd_pcm_info) #define SNDRV_PCM_IOCTL_TSTAMP _IOW('A', 0x02, int) diff --git a/include/sound/compress_driver.h b/include/sound/compress_driver.h index 48f2a1ff2bbc..f2912abacdf3 100644 --- a/include/sound/compress_driver.h +++ b/include/sound/compress_driver.h @@ -61,6 +61,7 @@ struct snd_compr_runtime { u64 total_bytes_available; u64 total_bytes_transferred; wait_queue_head_t sleep; + void *private_data; }; /** diff --git a/include/sound/compress_params.h b/include/sound/compress_params.h index da4a456de032..602dc6c45d1a 100644 --- a/include/sound/compress_params.h +++ b/include/sound/compress_params.h @@ -72,6 +72,7 @@ #define SND_AUDIOCODEC_IEC61937 ((__u32) 0x0000000B) #define SND_AUDIOCODEC_G723_1 ((__u32) 0x0000000C) #define SND_AUDIOCODEC_G729 ((__u32) 0x0000000D) +#define SND_AUDIOCODEC_MAX SND_AUDIOCODEC_G729 /* * Profile and modes are listed with bit masks. This allows for a diff --git a/include/sound/da9055.h b/include/sound/da9055.h new file mode 100644 index 000000000000..cf1241b64d89 --- /dev/null +++ b/include/sound/da9055.h @@ -0,0 +1,33 @@ +/* + * DA9055 ALSA Soc codec driver + * + * Copyright (c) 2012 Dialog Semiconductor + * + * Tested on (Samsung SMDK6410 board + DA9055 EVB) using I2S and I2C + * Written by David Chen <david.chen@diasemi.com> and + * Ashish Chavan <ashish.chavan@kpitcummins.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __SOUND_DA9055_H__ +#define __SOUND_DA9055_H__ + +enum da9055_micbias_voltage { + DA9055_MICBIAS_1_6V = 0, + DA9055_MICBIAS_1_8V = 1, + DA9055_MICBIAS_2_1V = 2, + DA9055_MICBIAS_2_2V = 3, +}; + +struct da9055_platform_data { + /* Selects which of the two MicBias pins acts as the bias source */ + bool micbias_source; + /* Selects the micbias voltage */ + enum da9055_micbias_voltage micbias; +}; + +#endif diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h index 4f865df42f0f..1a33f48ebe78 100644 --- a/include/sound/emu10k1.h +++ b/include/sound/emu10k1.h @@ -1788,7 +1788,7 @@ struct snd_emu10k1 { unsigned int efx_voices_mask[2]; unsigned int next_free_voice; -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP unsigned int *saved_ptr; unsigned int *saved_gpr; unsigned int *tram_val_saved; @@ -1856,7 +1856,7 @@ unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg); void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data); unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate); -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu); void snd_emu10k1_resume_init(struct snd_emu10k1 *emu); void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu); diff --git a/include/sound/initval.h b/include/sound/initval.h index f99a0d2ddfe7..ac62c67e6f42 100644 --- a/include/sound/initval.h +++ b/include/sound/initval.h @@ -50,6 +50,20 @@ #define SNDRV_DEFAULT_DMA_SIZE { [0 ... (SNDRV_CARDS-1)] = SNDRV_AUTO_DMA_SIZE } #define SNDRV_DEFAULT_PTR SNDRV_DEFAULT_STR +#ifdef SNDRV_LEGACY_FIND_FREE_IOPORT +static long snd_legacy_find_free_ioport(long *port_table, long size) +{ + while (*port_table != -1) { + if (request_region(*port_table, size, "ALSA test")) { + release_region(*port_table, size); + return *port_table; + } + port_table++; + } + return -1; +} +#endif + #ifdef SNDRV_LEGACY_FIND_FREE_IRQ #include <linux/interrupt.h> diff --git a/include/sound/memalloc.h b/include/sound/memalloc.h index c42506212649..844af65af626 100644 --- a/include/sound/memalloc.h +++ b/include/sound/memalloc.h @@ -98,8 +98,10 @@ static inline unsigned int snd_sgbuf_aligned_pages(size_t size) /* * return the physical address at the corresponding offset */ -static inline dma_addr_t snd_sgbuf_get_addr(struct snd_sg_buf *sgbuf, size_t offset) +static inline dma_addr_t snd_sgbuf_get_addr(struct snd_dma_buffer *dmab, + size_t offset) { + struct snd_sg_buf *sgbuf = dmab->private_data; dma_addr_t addr = sgbuf->table[offset >> PAGE_SHIFT].addr; addr &= PAGE_MASK; return addr + offset % PAGE_SIZE; @@ -108,10 +110,31 @@ static inline dma_addr_t snd_sgbuf_get_addr(struct snd_sg_buf *sgbuf, size_t off /* * return the virtual address at the corresponding offset */ -static inline void *snd_sgbuf_get_ptr(struct snd_sg_buf *sgbuf, size_t offset) +static inline void *snd_sgbuf_get_ptr(struct snd_dma_buffer *dmab, + size_t offset) { + struct snd_sg_buf *sgbuf = dmab->private_data; return sgbuf->table[offset >> PAGE_SHIFT].buf + offset % PAGE_SIZE; } + +unsigned int snd_sgbuf_get_chunk_size(struct snd_dma_buffer *dmab, + unsigned int ofs, unsigned int size); +#else +/* non-SG versions */ +static inline dma_addr_t snd_sgbuf_get_addr(struct snd_dma_buffer *dmab, + size_t offset) +{ + return dmab->addr + offset; +} + +static inline void *snd_sgbuf_get_ptr(struct snd_dma_buffer *dmab, + size_t offset) +{ + return dmab->area + offset; +} + +#define snd_sgbuf_get_chunk_size(dmab, ofs, size) (size) + #endif /* CONFIG_SND_DMA_SGBUF */ /* allocate/release a buffer */ diff --git a/include/sound/pcm.h b/include/sound/pcm.h index d0711bc8c914..6268a4192d5c 100644 --- a/include/sound/pcm.h +++ b/include/sound/pcm.h @@ -437,6 +437,7 @@ struct snd_pcm_str { struct snd_info_entry *proc_xrun_debug_entry; #endif #endif + struct snd_kcontrol *chmap_kctl; /* channel-mapping controls */ }; struct snd_pcm { @@ -982,53 +983,42 @@ static int snd_pcm_lib_alloc_vmalloc_32_buffer _snd_pcm_lib_alloc_vmalloc_buffer \ (subs, size, GFP_KERNEL | GFP_DMA32 | __GFP_ZERO) +#define snd_pcm_get_dma_buf(substream) ((substream)->runtime->dma_buffer_p) + #ifdef CONFIG_SND_DMA_SGBUF /* * SG-buffer handling */ #define snd_pcm_substream_sgbuf(substream) \ - ((substream)->runtime->dma_buffer_p->private_data) - -static inline dma_addr_t -snd_pcm_sgbuf_get_addr(struct snd_pcm_substream *substream, unsigned int ofs) -{ - struct snd_sg_buf *sg = snd_pcm_substream_sgbuf(substream); - return snd_sgbuf_get_addr(sg, ofs); -} - -static inline void * -snd_pcm_sgbuf_get_ptr(struct snd_pcm_substream *substream, unsigned int ofs) -{ - struct snd_sg_buf *sg = snd_pcm_substream_sgbuf(substream); - return snd_sgbuf_get_ptr(sg, ofs); -} + snd_pcm_get_dma_buf(substream)->private_data struct page *snd_pcm_sgbuf_ops_page(struct snd_pcm_substream *substream, unsigned long offset); -unsigned int snd_pcm_sgbuf_get_chunk_size(struct snd_pcm_substream *substream, - unsigned int ofs, unsigned int size); - #else /* !SND_DMA_SGBUF */ /* * fake using a continuous buffer */ +#define snd_pcm_sgbuf_ops_page NULL +#endif /* SND_DMA_SGBUF */ + static inline dma_addr_t snd_pcm_sgbuf_get_addr(struct snd_pcm_substream *substream, unsigned int ofs) { - return substream->runtime->dma_addr + ofs; + return snd_sgbuf_get_addr(snd_pcm_get_dma_buf(substream), ofs); } static inline void * snd_pcm_sgbuf_get_ptr(struct snd_pcm_substream *substream, unsigned int ofs) { - return substream->runtime->dma_area + ofs; + return snd_sgbuf_get_ptr(snd_pcm_get_dma_buf(substream), ofs); } -#define snd_pcm_sgbuf_ops_page NULL - -#define snd_pcm_sgbuf_get_chunk_size(subs, ofs, size) (size) - -#endif /* SND_DMA_SGBUF */ +static inline unsigned int +snd_pcm_sgbuf_get_chunk_size(struct snd_pcm_substream *substream, + unsigned int ofs, unsigned int size) +{ + return snd_sgbuf_get_chunk_size(snd_pcm_get_dma_buf(substream), ofs, size); +} /* handle mmap counter - PCM mmap callback should handle this counter properly */ static inline void snd_pcm_mmap_data_open(struct vm_area_struct *area) @@ -1086,4 +1076,51 @@ static inline const char *snd_pcm_stream_str(struct snd_pcm_substream *substream return "Capture"; } +/* + * PCM channel-mapping control API + */ +/* array element of channel maps */ +struct snd_pcm_chmap_elem { + unsigned char channels; + unsigned char map[15]; +}; + +/* channel map information; retrieved via snd_kcontrol_chip() */ +struct snd_pcm_chmap { + struct snd_pcm *pcm; /* assigned PCM instance */ + int stream; /* PLAYBACK or CAPTURE */ + struct snd_kcontrol *kctl; + const struct snd_pcm_chmap_elem *chmap; + unsigned int max_channels; + unsigned int channel_mask; /* optional: active channels bitmask */ + void *private_data; /* optional: private data pointer */ +}; + +/* get the PCM substream assigned to the given chmap info */ +static inline struct snd_pcm_substream * +snd_pcm_chmap_substream(struct snd_pcm_chmap *info, unsigned int idx) +{ + struct snd_pcm_substream *s; + for (s = info->pcm->streams[info->stream].substream; s; s = s->next) + if (s->number == idx) + return s; + return NULL; +} + +/* ALSA-standard channel maps (RL/RR prior to C/LFE) */ +extern const struct snd_pcm_chmap_elem snd_pcm_std_chmaps[]; +/* Other world's standard channel maps (C/LFE prior to RL/RR) */ +extern const struct snd_pcm_chmap_elem snd_pcm_alt_chmaps[]; + +/* bit masks to be passed to snd_pcm_chmap.channel_mask field */ +#define SND_PCM_CHMAP_MASK_24 ((1U << 2) | (1U << 4)) +#define SND_PCM_CHMAP_MASK_246 (SND_PCM_CHMAP_MASK_24 | (1U << 6)) +#define SND_PCM_CHMAP_MASK_2468 (SND_PCM_CHMAP_MASK_246 | (1U << 8)) + +int snd_pcm_add_chmap_ctls(struct snd_pcm *pcm, int stream, + const struct snd_pcm_chmap_elem *chmap, + int max_channels, + unsigned long private_value, + struct snd_pcm_chmap **info_ret); + #endif /* __SOUND_PCM_H */ diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h index 1f69e0af2941..628db7bca4fd 100644 --- a/include/sound/soc-dai.h +++ b/include/sound/soc-dai.h @@ -18,6 +18,7 @@ struct snd_pcm_substream; struct snd_soc_dapm_widget; +struct snd_compr_stream; /* * DAI hardware audio formats. @@ -205,6 +206,8 @@ struct snd_soc_dai_driver { int (*remove)(struct snd_soc_dai *dai); int (*suspend)(struct snd_soc_dai *dai); int (*resume)(struct snd_soc_dai *dai); + /* compress dai */ + bool compress_dai; /* ops */ const struct snd_soc_dai_ops *ops; diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h index abe373d57adc..e1ef63d4a5c4 100644 --- a/include/sound/soc-dapm.h +++ b/include/sound/soc-dapm.h @@ -244,10 +244,11 @@ struct device; { .id = snd_soc_dapm_supply, .name = wname, .reg = wreg, \ .shift = wshift, .invert = winvert, .event = wevent, \ .event_flags = wflags} -#define SND_SOC_DAPM_REGULATOR_SUPPLY(wname, wdelay) \ +#define SND_SOC_DAPM_REGULATOR_SUPPLY(wname, wdelay, wflags) \ { .id = snd_soc_dapm_regulator_supply, .name = wname, \ .reg = SND_SOC_NOPM, .shift = wdelay, .event = dapm_regulator_event, \ - .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD } + .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD, \ + .invert = wflags} /* dapm kcontrol types */ @@ -319,6 +320,9 @@ struct device; #define SND_SOC_DAPM_EVENT_OFF(e) \ (e & (SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD)) +/* regulator widget flags */ +#define SND_SOC_DAPM_REGULATOR_BYPASS 0x1 /* bypass when disabled */ + struct snd_soc_dapm_widget; enum snd_soc_dapm_type; struct snd_soc_dapm_path; @@ -412,6 +416,7 @@ void snd_soc_dapm_auto_nc_codec_pins(struct snd_soc_codec *codec); /* Mostly internal - should not normally be used */ void dapm_mark_dirty(struct snd_soc_dapm_widget *w, const char *reason); +void dapm_mark_io_dirty(struct snd_soc_dapm_context *dapm); /* dapm path query */ int snd_soc_dapm_dai_get_connected_widgets(struct snd_soc_dai *dai, int stream, @@ -510,7 +515,6 @@ struct snd_soc_dapm_widget { /* dapm control */ int reg; /* negative reg = no direct dapm */ unsigned char shift; /* bits to shift */ - unsigned int saved_value; /* widget saved value */ unsigned int value; /* widget current value */ unsigned int mask; /* non-shifted mask */ unsigned int on_val; /* on state value */ diff --git a/include/sound/soc.h b/include/sound/soc.h index e063380f63a2..91244a096c19 100644 --- a/include/sound/soc.h +++ b/include/sound/soc.h @@ -20,8 +20,10 @@ #include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/regmap.h> +#include <linux/log2.h> #include <sound/core.h> #include <sound/pcm.h> +#include <sound/compress_driver.h> #include <sound/control.h> #include <sound/ac97_codec.h> @@ -159,7 +161,8 @@ .platform_max = xmax} } #define SOC_ENUM_DOUBLE(xreg, xshift_l, xshift_r, xmax, xtexts) \ { .reg = xreg, .shift_l = xshift_l, .shift_r = xshift_r, \ - .max = xmax, .texts = xtexts } + .max = xmax, .texts = xtexts, \ + .mask = xmax ? roundup_pow_of_two(xmax) - 1 : 0} #define SOC_ENUM_SINGLE(xreg, xshift, xmax, xtexts) \ SOC_ENUM_DOUBLE(xreg, xshift, xshift, xmax, xtexts) #define SOC_ENUM_SINGLE_EXT(xmax, xtexts) \ @@ -399,6 +402,7 @@ int snd_soc_platform_read(struct snd_soc_platform *platform, int snd_soc_platform_write(struct snd_soc_platform *platform, unsigned int reg, unsigned int val); int soc_new_pcm(struct snd_soc_pcm_runtime *rtd, int num); +int soc_new_compress(struct snd_soc_pcm_runtime *rtd, int num); struct snd_pcm_substream *snd_soc_get_dai_substream(struct snd_soc_card *card, const char *dai_link, int stream); @@ -632,6 +636,13 @@ struct snd_soc_ops { int (*trigger)(struct snd_pcm_substream *, int); }; +struct snd_soc_compr_ops { + int (*startup)(struct snd_compr_stream *); + void (*shutdown)(struct snd_compr_stream *); + int (*set_params)(struct snd_compr_stream *); + int (*trigger)(struct snd_compr_stream *); +}; + /* SoC cache ops */ struct snd_soc_cache_ops { const char *name; @@ -787,9 +798,12 @@ struct snd_soc_platform_driver { snd_pcm_sframes_t (*delay)(struct snd_pcm_substream *, struct snd_soc_dai *); - /* platform stream ops */ + /* platform stream pcm ops */ struct snd_pcm_ops *ops; + /* platform stream compress ops */ + struct snd_compr_ops *compr_ops; + /* platform stream completion event */ int (*stream_event)(struct snd_soc_dapm_context *dapm, int event); @@ -891,6 +905,7 @@ struct snd_soc_dai_link { /* machine stream operations */ struct snd_soc_ops *ops; + struct snd_soc_compr_ops *compr_ops; }; struct snd_soc_codec_conf { @@ -1027,6 +1042,7 @@ struct snd_soc_pcm_runtime { /* runtime devices */ struct snd_pcm *pcm; + struct snd_compr *compr; struct snd_soc_codec *codec; struct snd_soc_platform *platform; struct snd_soc_dai *codec_dai; diff --git a/include/sound/tea575x-tuner.h b/include/sound/tea575x-tuner.h index fe8590cac5c2..098c4de44945 100644 --- a/include/sound/tea575x-tuner.h +++ b/include/sound/tea575x-tuner.h @@ -28,6 +28,7 @@ #include <media/v4l2-device.h> #define TEA575X_FMIF 10700 +#define TEA575X_AMIF 450 #define TEA575X_DATA (1 << 0) #define TEA575X_CLK (1 << 1) @@ -52,12 +53,14 @@ struct snd_tea575x { struct video_device vd; /* video device */ int radio_nr; /* radio_nr */ bool tea5759; /* 5759 chip is present */ + bool has_am; /* Device can tune to AM freqs */ bool cannot_read_data; /* Device cannot read the data pin */ bool cannot_mute; /* Device cannot mute */ bool mute; /* Device is muted? */ bool stereo; /* receiving stereo */ bool tuned; /* tuned to a station */ unsigned int val; /* hw value */ + u32 band; /* 0: FM, 1: FM-Japan, 2: AM */ u32 freq; /* frequency */ struct mutex mutex; struct snd_tea575x_ops *ops; @@ -70,5 +73,6 @@ struct snd_tea575x { int snd_tea575x_init(struct snd_tea575x *tea, struct module *owner); void snd_tea575x_exit(struct snd_tea575x *tea); +void snd_tea575x_set_freq(struct snd_tea575x *tea); #endif /* __SOUND_TEA575X_TUNER_H */ diff --git a/include/sound/tegra_wm8903.h b/include/sound/tegra_wm8903.h new file mode 100644 index 000000000000..57b202ee97c3 --- /dev/null +++ b/include/sound/tegra_wm8903.h @@ -0,0 +1,26 @@ +/* + * Copyright 2011 NVIDIA, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __SOUND_TEGRA_WM38903_H +#define __SOUND_TEGRA_WM38903_H + +struct tegra_wm8903_platform_data { + int gpio_spkr_en; + int gpio_hp_det; + int gpio_hp_mute; + int gpio_int_mic_en; + int gpio_ext_mic_en; +}; + +#endif diff --git a/include/sound/tlv.h b/include/sound/tlv.h index a64d8fe3f855..28c65e1ada21 100644 --- a/include/sound/tlv.h +++ b/include/sound/tlv.h @@ -86,4 +86,12 @@ #define TLV_DB_GAIN_MUTE -9999999 +/* + * channel-mapping TLV items + * TLV length must match with num_channels + */ +#define SNDRV_CTL_TLVT_CHMAP_FIXED 0x101 /* fixed channel position */ +#define SNDRV_CTL_TLVT_CHMAP_VAR 0x102 /* channels freely swappable */ +#define SNDRV_CTL_TLVT_CHMAP_PAIRED 0x103 /* pair-wise swappable */ + #endif /* __SOUND_TLV_H */ diff --git a/include/sound/version.h b/include/sound/version.h deleted file mode 100644 index cc75024c1089..000000000000 --- a/include/sound/version.h +++ /dev/null @@ -1,3 +0,0 @@ -/* include/version.h */ -#define CONFIG_SND_VERSION "1.0.25" -#define CONFIG_SND_DATE "" diff --git a/include/sound/wm0010.h b/include/sound/wm0010.h new file mode 100644 index 000000000000..3261e90815af --- /dev/null +++ b/include/sound/wm0010.h @@ -0,0 +1,27 @@ +/* + * wm0010.h -- Platform data for WM0010 DSP Driver + * + * Copyright 2012 Wolfson Microelectronics PLC. + * + * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef WM0010_PDATA_H +#define WM0010_PDATA_H + +struct wm0010_pdata { + int gpio_reset; + + /* Set if there is an inverter between the GPIO controlling + * the reset signal and the device. + */ + int reset_active_high; + int irq_flags; +}; + +#endif diff --git a/include/sound/wm8960.h b/include/sound/wm8960.h index 74e9a95529c5..e8ce8ee7d62d 100644 --- a/include/sound/wm8960.h +++ b/include/sound/wm8960.h @@ -18,7 +18,7 @@ struct wm8960_data { bool capless; /* Headphone outputs configured in capless mode */ - int dres; /* Discharge resistance for headphone outputs */ + bool shared_lrclk; /* DAC and ADC LRCLKs are wired together */ }; #endif diff --git a/include/sound/wm8993.h b/include/sound/wm8993.h index eee19f63c0d8..8016fd826f5a 100644 --- a/include/sound/wm8993.h +++ b/include/sound/wm8993.h @@ -32,6 +32,10 @@ struct wm8993_platform_data { unsigned int lineout1fb:1; unsigned int lineout2fb:1; + /* Delay to add for microphones to stabalise after power up */ + int micbias1_delay; + int micbias2_delay; + /* Microphone biases: 0=0.9*AVDD1 1=0.65*AVVD1 */ unsigned int micbias1_lvl:1; unsigned int micbias2_lvl:1; diff --git a/include/trace/events/ext4.h b/include/trace/events/ext4.h index 69d8a69ea831..d49b285385e8 100644 --- a/include/trace/events/ext4.h +++ b/include/trace/events/ext4.h @@ -26,19 +26,19 @@ TRACE_EVENT(ext4_free_inode, TP_STRUCT__entry( __field( dev_t, dev ) __field( ino_t, ino ) - __field( __u16, mode ) __field( uid_t, uid ) __field( gid_t, gid ) __field( __u64, blocks ) + __field( __u16, mode ) ), TP_fast_assign( __entry->dev = inode->i_sb->s_dev; __entry->ino = inode->i_ino; - __entry->mode = inode->i_mode; __entry->uid = i_uid_read(inode); __entry->gid = i_gid_read(inode); __entry->blocks = inode->i_blocks; + __entry->mode = inode->i_mode; ), TP_printk("dev %d,%d ino %lu mode 0%o uid %u gid %u blocks %llu", @@ -300,10 +300,10 @@ TRACE_EVENT(ext4_da_writepages, __field( long, pages_skipped ) __field( loff_t, range_start ) __field( loff_t, range_end ) + __field( pgoff_t, writeback_index ) __field( int, sync_mode ) __field( char, for_kupdate ) __field( char, range_cyclic ) - __field( pgoff_t, writeback_index ) ), TP_fast_assign( @@ -313,14 +313,14 @@ TRACE_EVENT(ext4_da_writepages, __entry->pages_skipped = wbc->pages_skipped; __entry->range_start = wbc->range_start; __entry->range_end = wbc->range_end; + __entry->writeback_index = inode->i_mapping->writeback_index; __entry->sync_mode = wbc->sync_mode; __entry->for_kupdate = wbc->for_kupdate; __entry->range_cyclic = wbc->range_cyclic; - __entry->writeback_index = inode->i_mapping->writeback_index; ), TP_printk("dev %d,%d ino %lu nr_to_write %ld pages_skipped %ld " - "range_start %lld range_end %lld sync_mode %d" + "range_start %lld range_end %lld sync_mode %d " "for_kupdate %d range_cyclic %d writeback_index %lu", MAJOR(__entry->dev), MINOR(__entry->dev), (unsigned long) __entry->ino, __entry->nr_to_write, @@ -382,8 +382,8 @@ TRACE_EVENT(ext4_da_writepages_result, __field( int, ret ) __field( int, pages_written ) __field( long, pages_skipped ) - __field( int, sync_mode ) __field( pgoff_t, writeback_index ) + __field( int, sync_mode ) ), TP_fast_assign( @@ -392,8 +392,8 @@ TRACE_EVENT(ext4_da_writepages_result, __entry->ret = ret; __entry->pages_written = pages_written; __entry->pages_skipped = wbc->pages_skipped; - __entry->sync_mode = wbc->sync_mode; __entry->writeback_index = inode->i_mapping->writeback_index; + __entry->sync_mode = wbc->sync_mode; ), TP_printk("dev %d,%d ino %lu ret %d pages_written %d pages_skipped %ld " @@ -411,16 +411,16 @@ DECLARE_EVENT_CLASS(ext4__page_op, TP_ARGS(page), TP_STRUCT__entry( - __field( pgoff_t, index ) - __field( ino_t, ino ) __field( dev_t, dev ) + __field( ino_t, ino ) + __field( pgoff_t, index ) ), TP_fast_assign( - __entry->index = page->index; - __entry->ino = page->mapping->host->i_ino; __entry->dev = page->mapping->host->i_sb->s_dev; + __entry->ino = page->mapping->host->i_ino; + __entry->index = page->index; ), TP_printk("dev %d,%d ino %lu page_index %lu", @@ -456,18 +456,18 @@ TRACE_EVENT(ext4_invalidatepage, TP_ARGS(page, offset), TP_STRUCT__entry( + __field( dev_t, dev ) + __field( ino_t, ino ) __field( pgoff_t, index ) __field( unsigned long, offset ) - __field( ino_t, ino ) - __field( dev_t, dev ) ), TP_fast_assign( + __entry->dev = page->mapping->host->i_sb->s_dev; + __entry->ino = page->mapping->host->i_ino; __entry->index = page->index; __entry->offset = offset; - __entry->ino = page->mapping->host->i_ino; - __entry->dev = page->mapping->host->i_sb->s_dev; ), TP_printk("dev %d,%d ino %lu page_index %lu offset %lu", @@ -510,8 +510,8 @@ DECLARE_EVENT_CLASS(ext4__mb_new_pa, __field( dev_t, dev ) __field( ino_t, ino ) __field( __u64, pa_pstart ) - __field( __u32, pa_len ) __field( __u64, pa_lstart ) + __field( __u32, pa_len ) ), @@ -519,8 +519,8 @@ DECLARE_EVENT_CLASS(ext4__mb_new_pa, __entry->dev = ac->ac_sb->s_dev; __entry->ino = ac->ac_inode->i_ino; __entry->pa_pstart = pa->pa_pstart; - __entry->pa_len = pa->pa_len; __entry->pa_lstart = pa->pa_lstart; + __entry->pa_len = pa->pa_len; ), TP_printk("dev %d,%d ino %lu pstart %llu len %u lstart %llu", @@ -645,7 +645,6 @@ TRACE_EVENT(ext4_request_blocks, TP_STRUCT__entry( __field( dev_t, dev ) __field( ino_t, ino ) - __field( unsigned int, flags ) __field( unsigned int, len ) __field( __u32, logical ) __field( __u32, lleft ) @@ -653,12 +652,12 @@ TRACE_EVENT(ext4_request_blocks, __field( __u64, goal ) __field( __u64, pleft ) __field( __u64, pright ) + __field( unsigned int, flags ) ), TP_fast_assign( __entry->dev = ar->inode->i_sb->s_dev; __entry->ino = ar->inode->i_ino; - __entry->flags = ar->flags; __entry->len = ar->len; __entry->logical = ar->logical; __entry->goal = ar->goal; @@ -666,6 +665,7 @@ TRACE_EVENT(ext4_request_blocks, __entry->lright = ar->lright; __entry->pleft = ar->pleft; __entry->pright = ar->pright; + __entry->flags = ar->flags; ), TP_printk("dev %d,%d ino %lu flags %u len %u lblk %u goal %llu " @@ -686,7 +686,6 @@ TRACE_EVENT(ext4_allocate_blocks, __field( dev_t, dev ) __field( ino_t, ino ) __field( __u64, block ) - __field( unsigned int, flags ) __field( unsigned int, len ) __field( __u32, logical ) __field( __u32, lleft ) @@ -694,13 +693,13 @@ TRACE_EVENT(ext4_allocate_blocks, __field( __u64, goal ) __field( __u64, pleft ) __field( __u64, pright ) + __field( unsigned int, flags ) ), TP_fast_assign( __entry->dev = ar->inode->i_sb->s_dev; __entry->ino = ar->inode->i_ino; __entry->block = block; - __entry->flags = ar->flags; __entry->len = ar->len; __entry->logical = ar->logical; __entry->goal = ar->goal; @@ -708,6 +707,7 @@ TRACE_EVENT(ext4_allocate_blocks, __entry->lright = ar->lright; __entry->pleft = ar->pleft; __entry->pright = ar->pright; + __entry->flags = ar->flags; ), TP_printk("dev %d,%d ino %lu flags %u len %u block %llu lblk %u " @@ -728,19 +728,19 @@ TRACE_EVENT(ext4_free_blocks, TP_STRUCT__entry( __field( dev_t, dev ) __field( ino_t, ino ) - __field( __u16, mode ) __field( __u64, block ) __field( unsigned long, count ) __field( int, flags ) + __field( __u16, mode ) ), TP_fast_assign( __entry->dev = inode->i_sb->s_dev; __entry->ino = inode->i_ino; - __entry->mode = inode->i_mode; __entry->block = block; __entry->count = count; __entry->flags = flags; + __entry->mode = inode->i_mode; ), TP_printk("dev %d,%d ino %lu mode 0%o block %llu count %lu flags %d", @@ -783,15 +783,15 @@ TRACE_EVENT(ext4_sync_file_exit, TP_ARGS(inode, ret), TP_STRUCT__entry( - __field( int, ret ) - __field( ino_t, ino ) __field( dev_t, dev ) + __field( ino_t, ino ) + __field( int, ret ) ), TP_fast_assign( - __entry->ret = ret; - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; + __entry->ino = inode->i_ino; + __entry->ret = ret; ), TP_printk("dev %d,%d ino %lu ret %d", @@ -854,12 +854,6 @@ TRACE_EVENT(ext4_mballoc_alloc, TP_STRUCT__entry( __field( dev_t, dev ) __field( ino_t, ino ) - __field( __u16, found ) - __field( __u16, groups ) - __field( __u16, buddy ) - __field( __u16, flags ) - __field( __u16, tail ) - __field( __u8, cr ) __field( __u32, orig_logical ) __field( int, orig_start ) __field( __u32, orig_group ) @@ -872,17 +866,17 @@ TRACE_EVENT(ext4_mballoc_alloc, __field( int, result_start ) __field( __u32, result_group ) __field( int, result_len ) + __field( __u16, found ) + __field( __u16, groups ) + __field( __u16, buddy ) + __field( __u16, flags ) + __field( __u16, tail ) + __field( __u8, cr ) ), TP_fast_assign( __entry->dev = ac->ac_inode->i_sb->s_dev; __entry->ino = ac->ac_inode->i_ino; - __entry->found = ac->ac_found; - __entry->flags = ac->ac_flags; - __entry->groups = ac->ac_groups_scanned; - __entry->buddy = ac->ac_buddy; - __entry->tail = ac->ac_tail; - __entry->cr = ac->ac_criteria; __entry->orig_logical = ac->ac_o_ex.fe_logical; __entry->orig_start = ac->ac_o_ex.fe_start; __entry->orig_group = ac->ac_o_ex.fe_group; @@ -895,6 +889,12 @@ TRACE_EVENT(ext4_mballoc_alloc, __entry->result_start = ac->ac_f_ex.fe_start; __entry->result_group = ac->ac_f_ex.fe_group; __entry->result_len = ac->ac_f_ex.fe_len; + __entry->found = ac->ac_found; + __entry->flags = ac->ac_flags; + __entry->groups = ac->ac_groups_scanned; + __entry->buddy = ac->ac_buddy; + __entry->tail = ac->ac_tail; + __entry->cr = ac->ac_criteria; ), TP_printk("dev %d,%d inode %lu orig %u/%d/%u@%u goal %u/%d/%u@%u " @@ -1015,17 +1015,17 @@ TRACE_EVENT(ext4_forget, TP_STRUCT__entry( __field( dev_t, dev ) __field( ino_t, ino ) - __field( __u16, mode ) - __field( int, is_metadata ) __field( __u64, block ) + __field( int, is_metadata ) + __field( __u16, mode ) ), TP_fast_assign( __entry->dev = inode->i_sb->s_dev; __entry->ino = inode->i_ino; - __entry->mode = inode->i_mode; - __entry->is_metadata = is_metadata; __entry->block = block; + __entry->is_metadata = is_metadata; + __entry->mode = inode->i_mode; ), TP_printk("dev %d,%d ino %lu mode 0%o is_metadata %d block %llu", @@ -1042,19 +1042,18 @@ TRACE_EVENT(ext4_da_update_reserve_space, TP_STRUCT__entry( __field( dev_t, dev ) __field( ino_t, ino ) - __field( __u16, mode ) __field( __u64, i_blocks ) __field( int, used_blocks ) __field( int, reserved_data_blocks ) __field( int, reserved_meta_blocks ) __field( int, allocated_meta_blocks ) __field( int, quota_claim ) + __field( __u16, mode ) ), TP_fast_assign( __entry->dev = inode->i_sb->s_dev; __entry->ino = inode->i_ino; - __entry->mode = inode->i_mode; __entry->i_blocks = inode->i_blocks; __entry->used_blocks = used_blocks; __entry->reserved_data_blocks = @@ -1064,6 +1063,7 @@ TRACE_EVENT(ext4_da_update_reserve_space, __entry->allocated_meta_blocks = EXT4_I(inode)->i_allocated_meta_blocks; __entry->quota_claim = quota_claim; + __entry->mode = inode->i_mode; ), TP_printk("dev %d,%d ino %lu mode 0%o i_blocks %llu used_blocks %d " @@ -1085,21 +1085,21 @@ TRACE_EVENT(ext4_da_reserve_space, TP_STRUCT__entry( __field( dev_t, dev ) __field( ino_t, ino ) - __field( __u16, mode ) __field( __u64, i_blocks ) __field( int, md_needed ) __field( int, reserved_data_blocks ) __field( int, reserved_meta_blocks ) + __field( __u16, mode ) ), TP_fast_assign( __entry->dev = inode->i_sb->s_dev; __entry->ino = inode->i_ino; - __entry->mode = inode->i_mode; __entry->i_blocks = inode->i_blocks; __entry->md_needed = md_needed; __entry->reserved_data_blocks = EXT4_I(inode)->i_reserved_data_blocks; __entry->reserved_meta_blocks = EXT4_I(inode)->i_reserved_meta_blocks; + __entry->mode = inode->i_mode; ), TP_printk("dev %d,%d ino %lu mode 0%o i_blocks %llu md_needed %d " @@ -1119,23 +1119,23 @@ TRACE_EVENT(ext4_da_release_space, TP_STRUCT__entry( __field( dev_t, dev ) __field( ino_t, ino ) - __field( __u16, mode ) __field( __u64, i_blocks ) __field( int, freed_blocks ) __field( int, reserved_data_blocks ) __field( int, reserved_meta_blocks ) __field( int, allocated_meta_blocks ) + __field( __u16, mode ) ), TP_fast_assign( __entry->dev = inode->i_sb->s_dev; __entry->ino = inode->i_ino; - __entry->mode = inode->i_mode; __entry->i_blocks = inode->i_blocks; __entry->freed_blocks = freed_blocks; __entry->reserved_data_blocks = EXT4_I(inode)->i_reserved_data_blocks; __entry->reserved_meta_blocks = EXT4_I(inode)->i_reserved_meta_blocks; __entry->allocated_meta_blocks = EXT4_I(inode)->i_allocated_meta_blocks; + __entry->mode = inode->i_mode; ), TP_printk("dev %d,%d ino %lu mode 0%o i_blocks %llu freed_blocks %d " @@ -1203,16 +1203,16 @@ TRACE_EVENT(ext4_direct_IO_enter, TP_ARGS(inode, offset, len, rw), TP_STRUCT__entry( - __field( ino_t, ino ) __field( dev_t, dev ) + __field( ino_t, ino ) __field( loff_t, pos ) __field( unsigned long, len ) __field( int, rw ) ), TP_fast_assign( - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; + __entry->ino = inode->i_ino; __entry->pos = offset; __entry->len = len; __entry->rw = rw; @@ -1231,8 +1231,8 @@ TRACE_EVENT(ext4_direct_IO_exit, TP_ARGS(inode, offset, len, rw, ret), TP_STRUCT__entry( - __field( ino_t, ino ) __field( dev_t, dev ) + __field( ino_t, ino ) __field( loff_t, pos ) __field( unsigned long, len ) __field( int, rw ) @@ -1240,8 +1240,8 @@ TRACE_EVENT(ext4_direct_IO_exit, ), TP_fast_assign( - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; + __entry->ino = inode->i_ino; __entry->pos = offset; __entry->len = len; __entry->rw = rw; @@ -1261,16 +1261,16 @@ TRACE_EVENT(ext4_fallocate_enter, TP_ARGS(inode, offset, len, mode), TP_STRUCT__entry( - __field( ino_t, ino ) __field( dev_t, dev ) + __field( ino_t, ino ) __field( loff_t, pos ) __field( loff_t, len ) __field( int, mode ) ), TP_fast_assign( - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; + __entry->ino = inode->i_ino; __entry->pos = offset; __entry->len = len; __entry->mode = mode; @@ -1289,16 +1289,16 @@ TRACE_EVENT(ext4_fallocate_exit, TP_ARGS(inode, offset, max_blocks, ret), TP_STRUCT__entry( - __field( ino_t, ino ) __field( dev_t, dev ) + __field( ino_t, ino ) __field( loff_t, pos ) __field( unsigned int, blocks ) __field( int, ret ) ), TP_fast_assign( - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; + __entry->ino = inode->i_ino; __entry->pos = offset; __entry->blocks = max_blocks; __entry->ret = ret; @@ -1317,17 +1317,17 @@ TRACE_EVENT(ext4_unlink_enter, TP_ARGS(parent, dentry), TP_STRUCT__entry( - __field( ino_t, parent ) + __field( dev_t, dev ) __field( ino_t, ino ) + __field( ino_t, parent ) __field( loff_t, size ) - __field( dev_t, dev ) ), TP_fast_assign( - __entry->parent = parent->i_ino; + __entry->dev = dentry->d_inode->i_sb->s_dev; __entry->ino = dentry->d_inode->i_ino; + __entry->parent = parent->i_ino; __entry->size = dentry->d_inode->i_size; - __entry->dev = dentry->d_inode->i_sb->s_dev; ), TP_printk("dev %d,%d ino %lu size %lld parent %lu", @@ -1342,14 +1342,14 @@ TRACE_EVENT(ext4_unlink_exit, TP_ARGS(dentry, ret), TP_STRUCT__entry( - __field( ino_t, ino ) __field( dev_t, dev ) + __field( ino_t, ino ) __field( int, ret ) ), TP_fast_assign( - __entry->ino = dentry->d_inode->i_ino; __entry->dev = dentry->d_inode->i_sb->s_dev; + __entry->ino = dentry->d_inode->i_ino; __entry->ret = ret; ), @@ -1365,14 +1365,14 @@ DECLARE_EVENT_CLASS(ext4__truncate, TP_ARGS(inode), TP_STRUCT__entry( - __field( ino_t, ino ) - __field( dev_t, dev ) + __field( dev_t, dev ) + __field( ino_t, ino ) __field( __u64, blocks ) ), TP_fast_assign( - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; + __entry->ino = inode->i_ino; __entry->blocks = inode->i_blocks; ), @@ -1403,8 +1403,8 @@ TRACE_EVENT(ext4_ext_convert_to_initialized_enter, TP_ARGS(inode, map, ux), TP_STRUCT__entry( - __field( ino_t, ino ) __field( dev_t, dev ) + __field( ino_t, ino ) __field( ext4_lblk_t, m_lblk ) __field( unsigned, m_len ) __field( ext4_lblk_t, u_lblk ) @@ -1413,8 +1413,8 @@ TRACE_EVENT(ext4_ext_convert_to_initialized_enter, ), TP_fast_assign( - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; + __entry->ino = inode->i_ino; __entry->m_lblk = map->m_lblk; __entry->m_len = map->m_len; __entry->u_lblk = le32_to_cpu(ux->ee_block); @@ -1441,8 +1441,8 @@ TRACE_EVENT(ext4_ext_convert_to_initialized_fastpath, TP_ARGS(inode, map, ux, ix), TP_STRUCT__entry( - __field( ino_t, ino ) __field( dev_t, dev ) + __field( ino_t, ino ) __field( ext4_lblk_t, m_lblk ) __field( unsigned, m_len ) __field( ext4_lblk_t, u_lblk ) @@ -1454,8 +1454,8 @@ TRACE_EVENT(ext4_ext_convert_to_initialized_fastpath, ), TP_fast_assign( - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; + __entry->ino = inode->i_ino; __entry->m_lblk = map->m_lblk; __entry->m_len = map->m_len; __entry->u_lblk = le32_to_cpu(ux->ee_block); @@ -1483,16 +1483,16 @@ DECLARE_EVENT_CLASS(ext4__map_blocks_enter, TP_ARGS(inode, lblk, len, flags), TP_STRUCT__entry( - __field( ino_t, ino ) - __field( dev_t, dev ) + __field( dev_t, dev ) + __field( ino_t, ino ) __field( ext4_lblk_t, lblk ) __field( unsigned int, len ) __field( unsigned int, flags ) ), TP_fast_assign( - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; + __entry->ino = inode->i_ino; __entry->lblk = lblk; __entry->len = len; __entry->flags = flags; @@ -1525,19 +1525,19 @@ DECLARE_EVENT_CLASS(ext4__map_blocks_exit, TP_ARGS(inode, lblk, pblk, len, ret), TP_STRUCT__entry( - __field( ino_t, ino ) __field( dev_t, dev ) - __field( ext4_lblk_t, lblk ) + __field( ino_t, ino ) __field( ext4_fsblk_t, pblk ) + __field( ext4_lblk_t, lblk ) __field( unsigned int, len ) __field( int, ret ) ), TP_fast_assign( - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; - __entry->lblk = lblk; + __entry->ino = inode->i_ino; __entry->pblk = pblk; + __entry->lblk = lblk; __entry->len = len; __entry->ret = ret; ), @@ -1569,17 +1569,17 @@ TRACE_EVENT(ext4_ext_load_extent, TP_ARGS(inode, lblk, pblk), TP_STRUCT__entry( - __field( ino_t, ino ) __field( dev_t, dev ) - __field( ext4_lblk_t, lblk ) + __field( ino_t, ino ) __field( ext4_fsblk_t, pblk ) + __field( ext4_lblk_t, lblk ) ), TP_fast_assign( - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; - __entry->lblk = lblk; + __entry->ino = inode->i_ino; __entry->pblk = pblk; + __entry->lblk = lblk; ), TP_printk("dev %d,%d ino %lu lblk %u pblk %llu", @@ -1594,13 +1594,13 @@ TRACE_EVENT(ext4_load_inode, TP_ARGS(inode), TP_STRUCT__entry( - __field( ino_t, ino ) __field( dev_t, dev ) + __field( ino_t, ino ) ), TP_fast_assign( - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; + __entry->ino = inode->i_ino; ), TP_printk("dev %d,%d ino %ld", @@ -1615,14 +1615,14 @@ TRACE_EVENT(ext4_journal_start, TP_STRUCT__entry( __field( dev_t, dev ) - __field( int, nblocks ) __field(unsigned long, ip ) + __field( int, nblocks ) ), TP_fast_assign( __entry->dev = sb->s_dev; - __entry->nblocks = nblocks; __entry->ip = IP; + __entry->nblocks = nblocks; ), TP_printk("dev %d,%d nblocks %d caller %pF", @@ -1686,23 +1686,23 @@ TRACE_EVENT(ext4_ext_handle_uninitialized_extents, TP_ARGS(inode, map, allocated, newblock), TP_STRUCT__entry( - __field( ino_t, ino ) __field( dev_t, dev ) + __field( ino_t, ino ) + __field( int, flags ) __field( ext4_lblk_t, lblk ) __field( ext4_fsblk_t, pblk ) __field( unsigned int, len ) - __field( int, flags ) __field( unsigned int, allocated ) __field( ext4_fsblk_t, newblk ) ), TP_fast_assign( - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; + __entry->ino = inode->i_ino; + __entry->flags = map->m_flags; __entry->lblk = map->m_lblk; __entry->pblk = map->m_pblk; __entry->len = map->m_len; - __entry->flags = map->m_flags; __entry->allocated = allocated; __entry->newblk = newblock; ), @@ -1724,19 +1724,19 @@ TRACE_EVENT(ext4_get_implied_cluster_alloc_exit, TP_STRUCT__entry( __field( dev_t, dev ) + __field( unsigned int, flags ) __field( ext4_lblk_t, lblk ) __field( ext4_fsblk_t, pblk ) __field( unsigned int, len ) - __field( unsigned int, flags ) __field( int, ret ) ), TP_fast_assign( __entry->dev = sb->s_dev; + __entry->flags = map->m_flags; __entry->lblk = map->m_lblk; __entry->pblk = map->m_pblk; __entry->len = map->m_len; - __entry->flags = map->m_flags; __entry->ret = ret; ), @@ -1753,16 +1753,16 @@ TRACE_EVENT(ext4_ext_put_in_cache, TP_ARGS(inode, lblk, len, start), TP_STRUCT__entry( - __field( ino_t, ino ) __field( dev_t, dev ) + __field( ino_t, ino ) __field( ext4_lblk_t, lblk ) __field( unsigned int, len ) __field( ext4_fsblk_t, start ) ), TP_fast_assign( - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; + __entry->ino = inode->i_ino; __entry->lblk = lblk; __entry->len = len; __entry->start = start; @@ -1782,15 +1782,15 @@ TRACE_EVENT(ext4_ext_in_cache, TP_ARGS(inode, lblk, ret), TP_STRUCT__entry( - __field( ino_t, ino ) __field( dev_t, dev ) + __field( ino_t, ino ) __field( ext4_lblk_t, lblk ) __field( int, ret ) ), TP_fast_assign( - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; + __entry->ino = inode->i_ino; __entry->lblk = lblk; __entry->ret = ret; ), @@ -1810,8 +1810,8 @@ TRACE_EVENT(ext4_find_delalloc_range, TP_ARGS(inode, from, to, reverse, found, found_blk), TP_STRUCT__entry( - __field( ino_t, ino ) __field( dev_t, dev ) + __field( ino_t, ino ) __field( ext4_lblk_t, from ) __field( ext4_lblk_t, to ) __field( int, reverse ) @@ -1820,8 +1820,8 @@ TRACE_EVENT(ext4_find_delalloc_range, ), TP_fast_assign( - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; + __entry->ino = inode->i_ino; __entry->from = from; __entry->to = to; __entry->reverse = reverse; @@ -1844,15 +1844,15 @@ TRACE_EVENT(ext4_get_reserved_cluster_alloc, TP_ARGS(inode, lblk, len), TP_STRUCT__entry( - __field( ino_t, ino ) __field( dev_t, dev ) + __field( ino_t, ino ) __field( ext4_lblk_t, lblk ) __field( unsigned int, len ) ), TP_fast_assign( - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; + __entry->ino = inode->i_ino; __entry->lblk = lblk; __entry->len = len; ), @@ -1871,18 +1871,18 @@ TRACE_EVENT(ext4_ext_show_extent, TP_ARGS(inode, lblk, pblk, len), TP_STRUCT__entry( - __field( ino_t, ino ) __field( dev_t, dev ) - __field( ext4_lblk_t, lblk ) + __field( ino_t, ino ) __field( ext4_fsblk_t, pblk ) + __field( ext4_lblk_t, lblk ) __field( unsigned short, len ) ), TP_fast_assign( - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; - __entry->lblk = lblk; + __entry->ino = inode->i_ino; __entry->pblk = pblk; + __entry->lblk = lblk; __entry->len = len; ), @@ -1902,25 +1902,25 @@ TRACE_EVENT(ext4_remove_blocks, TP_ARGS(inode, ex, from, to, partial_cluster), TP_STRUCT__entry( - __field( ino_t, ino ) __field( dev_t, dev ) - __field( ext4_lblk_t, ee_lblk ) - __field( ext4_fsblk_t, ee_pblk ) - __field( unsigned short, ee_len ) + __field( ino_t, ino ) __field( ext4_lblk_t, from ) __field( ext4_lblk_t, to ) __field( ext4_fsblk_t, partial ) + __field( ext4_fsblk_t, ee_pblk ) + __field( ext4_lblk_t, ee_lblk ) + __field( unsigned short, ee_len ) ), TP_fast_assign( - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; - __entry->ee_lblk = cpu_to_le32(ex->ee_block); - __entry->ee_pblk = ext4_ext_pblock(ex); - __entry->ee_len = ext4_ext_get_actual_len(ex); + __entry->ino = inode->i_ino; __entry->from = from; __entry->to = to; __entry->partial = partial_cluster; + __entry->ee_pblk = ext4_ext_pblock(ex); + __entry->ee_lblk = cpu_to_le32(ex->ee_block); + __entry->ee_len = ext4_ext_get_actual_len(ex); ), TP_printk("dev %d,%d ino %lu extent [%u(%llu), %u]" @@ -1942,23 +1942,23 @@ TRACE_EVENT(ext4_ext_rm_leaf, TP_ARGS(inode, start, ex, partial_cluster), TP_STRUCT__entry( - __field( ino_t, ino ) __field( dev_t, dev ) + __field( ino_t, ino ) + __field( ext4_fsblk_t, partial ) __field( ext4_lblk_t, start ) __field( ext4_lblk_t, ee_lblk ) __field( ext4_fsblk_t, ee_pblk ) __field( short, ee_len ) - __field( ext4_fsblk_t, partial ) ), TP_fast_assign( - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; + __entry->ino = inode->i_ino; + __entry->partial = partial_cluster; __entry->start = start; __entry->ee_lblk = le32_to_cpu(ex->ee_block); __entry->ee_pblk = ext4_ext_pblock(ex); __entry->ee_len = ext4_ext_get_actual_len(ex); - __entry->partial = partial_cluster; ), TP_printk("dev %d,%d ino %lu start_lblk %u last_extent [%u(%llu), %u]" @@ -1978,14 +1978,14 @@ TRACE_EVENT(ext4_ext_rm_idx, TP_ARGS(inode, pblk), TP_STRUCT__entry( - __field( ino_t, ino ) __field( dev_t, dev ) + __field( ino_t, ino ) __field( ext4_fsblk_t, pblk ) ), TP_fast_assign( - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; + __entry->ino = inode->i_ino; __entry->pblk = pblk; ), @@ -2001,15 +2001,15 @@ TRACE_EVENT(ext4_ext_remove_space, TP_ARGS(inode, start, depth), TP_STRUCT__entry( - __field( ino_t, ino ) __field( dev_t, dev ) + __field( ino_t, ino ) __field( ext4_lblk_t, start ) __field( int, depth ) ), TP_fast_assign( - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; + __entry->ino = inode->i_ino; __entry->start = start; __entry->depth = depth; ), @@ -2028,8 +2028,8 @@ TRACE_EVENT(ext4_ext_remove_space_done, TP_ARGS(inode, start, depth, partial, eh_entries), TP_STRUCT__entry( - __field( ino_t, ino ) __field( dev_t, dev ) + __field( ino_t, ino ) __field( ext4_lblk_t, start ) __field( int, depth ) __field( ext4_lblk_t, partial ) @@ -2037,8 +2037,8 @@ TRACE_EVENT(ext4_ext_remove_space_done, ), TP_fast_assign( - __entry->ino = inode->i_ino; __entry->dev = inode->i_sb->s_dev; + __entry->ino = inode->i_ino; __entry->start = start; __entry->depth = depth; __entry->partial = partial; diff --git a/include/uapi/drm/Kbuild b/include/uapi/drm/Kbuild index aafaa5aa54d4..ba99ce3f7372 100644 --- a/include/uapi/drm/Kbuild +++ b/include/uapi/drm/Kbuild @@ -1 +1,16 @@ # UAPI Header export list +header-y += drm.h +header-y += drm_fourcc.h +header-y += drm_mode.h +header-y += drm_sarea.h +header-y += exynos_drm.h +header-y += i810_drm.h +header-y += i915_drm.h +header-y += mga_drm.h +header-y += nouveau_drm.h +header-y += r128_drm.h +header-y += radeon_drm.h +header-y += savage_drm.h +header-y += sis_drm.h +header-y += via_drm.h +header-y += vmwgfx_drm.h diff --git a/include/drm/drm.h b/include/uapi/drm/drm.h index 1e3481edf062..1e3481edf062 100644 --- a/include/drm/drm.h +++ b/include/uapi/drm/drm.h diff --git a/include/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 646ae5f39f42..646ae5f39f42 100644 --- a/include/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h diff --git a/include/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index 3d6301b6ec16..3d6301b6ec16 100644 --- a/include/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h diff --git a/include/drm/drm_sarea.h b/include/uapi/drm/drm_sarea.h index 413a5642d49f..413a5642d49f 100644 --- a/include/drm/drm_sarea.h +++ b/include/uapi/drm/drm_sarea.h diff --git a/include/uapi/drm/exynos_drm.h b/include/uapi/drm/exynos_drm.h new file mode 100644 index 000000000000..c0494d586e23 --- /dev/null +++ b/include/uapi/drm/exynos_drm.h @@ -0,0 +1,203 @@ +/* exynos_drm.h + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * Authors: + * Inki Dae <inki.dae@samsung.com> + * Joonyoung Shim <jy0922.shim@samsung.com> + * Seung-Woo Kim <sw0312.kim@samsung.com> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _UAPI_EXYNOS_DRM_H_ +#define _UAPI_EXYNOS_DRM_H_ + +#include <drm/drm.h> + +/** + * User-desired buffer creation information structure. + * + * @size: user-desired memory allocation size. + * - this size value would be page-aligned internally. + * @flags: user request for setting memory type or cache attributes. + * @handle: returned a handle to created gem object. + * - this handle will be set by gem module of kernel side. + */ +struct drm_exynos_gem_create { + uint64_t size; + unsigned int flags; + unsigned int handle; +}; + +/** + * A structure for getting buffer offset. + * + * @handle: a pointer to gem object created. + * @pad: just padding to be 64-bit aligned. + * @offset: relatived offset value of the memory region allocated. + * - this value should be set by user. + */ +struct drm_exynos_gem_map_off { + unsigned int handle; + unsigned int pad; + uint64_t offset; +}; + +/** + * A structure for mapping buffer. + * + * @handle: a handle to gem object created. + * @pad: just padding to be 64-bit aligned. + * @size: memory size to be mapped. + * @mapped: having user virtual address mmaped. + * - this variable would be filled by exynos gem module + * of kernel side with user virtual address which is allocated + * by do_mmap(). + */ +struct drm_exynos_gem_mmap { + unsigned int handle; + unsigned int pad; + uint64_t size; + uint64_t mapped; +}; + +/** + * A structure to gem information. + * + * @handle: a handle to gem object created. + * @flags: flag value including memory type and cache attribute and + * this value would be set by driver. + * @size: size to memory region allocated by gem and this size would + * be set by driver. + */ +struct drm_exynos_gem_info { + unsigned int handle; + unsigned int flags; + uint64_t size; +}; + +/** + * A structure for user connection request of virtual display. + * + * @connection: indicate whether doing connetion or not by user. + * @extensions: if this value is 1 then the vidi driver would need additional + * 128bytes edid data. + * @edid: the edid data pointer from user side. + */ +struct drm_exynos_vidi_connection { + unsigned int connection; + unsigned int extensions; + uint64_t edid; +}; + +/* memory type definitions. */ +enum e_drm_exynos_gem_mem_type { + /* Physically Continuous memory and used as default. */ + EXYNOS_BO_CONTIG = 0 << 0, + /* Physically Non-Continuous memory. */ + EXYNOS_BO_NONCONTIG = 1 << 0, + /* non-cachable mapping and used as default. */ + EXYNOS_BO_NONCACHABLE = 0 << 1, + /* cachable mapping. */ + EXYNOS_BO_CACHABLE = 1 << 1, + /* write-combine mapping. */ + EXYNOS_BO_WC = 1 << 2, + EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE | + EXYNOS_BO_WC +}; + +struct drm_exynos_g2d_get_ver { + __u32 major; + __u32 minor; +}; + +struct drm_exynos_g2d_cmd { + __u32 offset; + __u32 data; +}; + +enum drm_exynos_g2d_event_type { + G2D_EVENT_NOT, + G2D_EVENT_NONSTOP, + G2D_EVENT_STOP, /* not yet */ +}; + +struct drm_exynos_g2d_set_cmdlist { + __u64 cmd; + __u64 cmd_gem; + __u32 cmd_nr; + __u32 cmd_gem_nr; + + /* for g2d event */ + __u64 event_type; + __u64 user_data; +}; + +struct drm_exynos_g2d_exec { + __u64 async; +}; + +#define DRM_EXYNOS_GEM_CREATE 0x00 +#define DRM_EXYNOS_GEM_MAP_OFFSET 0x01 +#define DRM_EXYNOS_GEM_MMAP 0x02 +/* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */ +#define DRM_EXYNOS_GEM_GET 0x04 +#define DRM_EXYNOS_VIDI_CONNECTION 0x07 + +/* G2D */ +#define DRM_EXYNOS_G2D_GET_VER 0x20 +#define DRM_EXYNOS_G2D_SET_CMDLIST 0x21 +#define DRM_EXYNOS_G2D_EXEC 0x22 + +#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create) + +#define DRM_IOCTL_EXYNOS_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_GEM_MAP_OFFSET, struct drm_exynos_gem_map_off) + +#define DRM_IOCTL_EXYNOS_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_GEM_MMAP, struct drm_exynos_gem_mmap) + +#define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info) + +#define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection) + +#define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver) +#define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist) +#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec) + +/* EXYNOS specific events */ +#define DRM_EXYNOS_G2D_EVENT 0x80000000 + +struct drm_exynos_g2d_event { + struct drm_event base; + __u64 user_data; + __u32 tv_sec; + __u32 tv_usec; + __u32 cmdlist_no; + __u32 reserved; +}; + +#endif /* _UAPI_EXYNOS_DRM_H_ */ diff --git a/include/drm/i810_drm.h b/include/uapi/drm/i810_drm.h index 7a10bb6f2c0f..7a10bb6f2c0f 100644 --- a/include/drm/i810_drm.h +++ b/include/uapi/drm/i810_drm.h diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h new file mode 100644 index 000000000000..4322b1e7d2ed --- /dev/null +++ b/include/uapi/drm/i915_drm.h @@ -0,0 +1,947 @@ +/* + * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _UAPI_I915_DRM_H_ +#define _UAPI_I915_DRM_H_ + +#include <drm/drm.h> + +/* Please note that modifications to all structs defined here are + * subject to backwards-compatibility constraints. + */ + + +/* Each region is a minimum of 16k, and there are at most 255 of them. + */ +#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use + * of chars for next/prev indices */ +#define I915_LOG_MIN_TEX_REGION_SIZE 14 + +typedef struct _drm_i915_init { + enum { + I915_INIT_DMA = 0x01, + I915_CLEANUP_DMA = 0x02, + I915_RESUME_DMA = 0x03 + } func; + unsigned int mmio_offset; + int sarea_priv_offset; + unsigned int ring_start; + unsigned int ring_end; + unsigned int ring_size; + unsigned int front_offset; + unsigned int back_offset; + unsigned int depth_offset; + unsigned int w; + unsigned int h; + unsigned int pitch; + unsigned int pitch_bits; + unsigned int back_pitch; + unsigned int depth_pitch; + unsigned int cpp; + unsigned int chipset; +} drm_i915_init_t; + +typedef struct _drm_i915_sarea { + struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; + int last_upload; /* last time texture was uploaded */ + int last_enqueue; /* last time a buffer was enqueued */ + int last_dispatch; /* age of the most recently dispatched buffer */ + int ctxOwner; /* last context to upload state */ + int texAge; + int pf_enabled; /* is pageflipping allowed? */ + int pf_active; + int pf_current_page; /* which buffer is being displayed? */ + int perf_boxes; /* performance boxes to be displayed */ + int width, height; /* screen size in pixels */ + + drm_handle_t front_handle; + int front_offset; + int front_size; + + drm_handle_t back_handle; + int back_offset; + int back_size; + + drm_handle_t depth_handle; + int depth_offset; + int depth_size; + + drm_handle_t tex_handle; + int tex_offset; + int tex_size; + int log_tex_granularity; + int pitch; + int rotation; /* 0, 90, 180 or 270 */ + int rotated_offset; + int rotated_size; + int rotated_pitch; + int virtualX, virtualY; + + unsigned int front_tiled; + unsigned int back_tiled; + unsigned int depth_tiled; + unsigned int rotated_tiled; + unsigned int rotated2_tiled; + + int pipeA_x; + int pipeA_y; + int pipeA_w; + int pipeA_h; + int pipeB_x; + int pipeB_y; + int pipeB_w; + int pipeB_h; + + /* fill out some space for old userspace triple buffer */ + drm_handle_t unused_handle; + __u32 unused1, unused2, unused3; + + /* buffer object handles for static buffers. May change + * over the lifetime of the client. + */ + __u32 front_bo_handle; + __u32 back_bo_handle; + __u32 unused_bo_handle; + __u32 depth_bo_handle; + +} drm_i915_sarea_t; + +/* due to userspace building against these headers we need some compat here */ +#define planeA_x pipeA_x +#define planeA_y pipeA_y +#define planeA_w pipeA_w +#define planeA_h pipeA_h +#define planeB_x pipeB_x +#define planeB_y pipeB_y +#define planeB_w pipeB_w +#define planeB_h pipeB_h + +/* Flags for perf_boxes + */ +#define I915_BOX_RING_EMPTY 0x1 +#define I915_BOX_FLIP 0x2 +#define I915_BOX_WAIT 0x4 +#define I915_BOX_TEXTURE_LOAD 0x8 +#define I915_BOX_LOST_CONTEXT 0x10 + +/* I915 specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ +#define DRM_I915_INIT 0x00 +#define DRM_I915_FLUSH 0x01 +#define DRM_I915_FLIP 0x02 +#define DRM_I915_BATCHBUFFER 0x03 +#define DRM_I915_IRQ_EMIT 0x04 +#define DRM_I915_IRQ_WAIT 0x05 +#define DRM_I915_GETPARAM 0x06 +#define DRM_I915_SETPARAM 0x07 +#define DRM_I915_ALLOC 0x08 +#define DRM_I915_FREE 0x09 +#define DRM_I915_INIT_HEAP 0x0a +#define DRM_I915_CMDBUFFER 0x0b +#define DRM_I915_DESTROY_HEAP 0x0c +#define DRM_I915_SET_VBLANK_PIPE 0x0d +#define DRM_I915_GET_VBLANK_PIPE 0x0e +#define DRM_I915_VBLANK_SWAP 0x0f +#define DRM_I915_HWS_ADDR 0x11 +#define DRM_I915_GEM_INIT 0x13 +#define DRM_I915_GEM_EXECBUFFER 0x14 +#define DRM_I915_GEM_PIN 0x15 +#define DRM_I915_GEM_UNPIN 0x16 +#define DRM_I915_GEM_BUSY 0x17 +#define DRM_I915_GEM_THROTTLE 0x18 +#define DRM_I915_GEM_ENTERVT 0x19 +#define DRM_I915_GEM_LEAVEVT 0x1a +#define DRM_I915_GEM_CREATE 0x1b +#define DRM_I915_GEM_PREAD 0x1c +#define DRM_I915_GEM_PWRITE 0x1d +#define DRM_I915_GEM_MMAP 0x1e +#define DRM_I915_GEM_SET_DOMAIN 0x1f +#define DRM_I915_GEM_SW_FINISH 0x20 +#define DRM_I915_GEM_SET_TILING 0x21 +#define DRM_I915_GEM_GET_TILING 0x22 +#define DRM_I915_GEM_GET_APERTURE 0x23 +#define DRM_I915_GEM_MMAP_GTT 0x24 +#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 +#define DRM_I915_GEM_MADVISE 0x26 +#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 +#define DRM_I915_OVERLAY_ATTRS 0x28 +#define DRM_I915_GEM_EXECBUFFER2 0x29 +#define DRM_I915_GET_SPRITE_COLORKEY 0x2a +#define DRM_I915_SET_SPRITE_COLORKEY 0x2b +#define DRM_I915_GEM_WAIT 0x2c +#define DRM_I915_GEM_CONTEXT_CREATE 0x2d +#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e +#define DRM_I915_GEM_SET_CACHING 0x2f +#define DRM_I915_GEM_GET_CACHING 0x30 +#define DRM_I915_REG_READ 0x31 + +#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) +#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) +#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) +#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) +#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) +#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) +#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) +#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) +#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) +#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) +#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) +#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) +#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) +#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) +#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) +#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) +#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) +#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) +#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) +#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) +#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) +#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) +#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) +#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) +#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) +#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) +#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) +#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) +#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) +#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) +#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) +#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) +#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) +#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) +#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) +#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) +#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) +#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) +#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) +#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) +#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) +#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) +#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) +#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) +#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) +#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) +#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) +#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) + +/* Allow drivers to submit batchbuffers directly to hardware, relying + * on the security mechanisms provided by hardware. + */ +typedef struct drm_i915_batchbuffer { + int start; /* agp offset */ + int used; /* nr bytes in use */ + int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ + int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ + int num_cliprects; /* mulitpass with multiple cliprects? */ + struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ +} drm_i915_batchbuffer_t; + +/* As above, but pass a pointer to userspace buffer which can be + * validated by the kernel prior to sending to hardware. + */ +typedef struct _drm_i915_cmdbuffer { + char __user *buf; /* pointer to userspace command buffer */ + int sz; /* nr bytes in buf */ + int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ + int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ + int num_cliprects; /* mulitpass with multiple cliprects? */ + struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ +} drm_i915_cmdbuffer_t; + +/* Userspace can request & wait on irq's: + */ +typedef struct drm_i915_irq_emit { + int __user *irq_seq; +} drm_i915_irq_emit_t; + +typedef struct drm_i915_irq_wait { + int irq_seq; +} drm_i915_irq_wait_t; + +/* Ioctl to query kernel params: + */ +#define I915_PARAM_IRQ_ACTIVE 1 +#define I915_PARAM_ALLOW_BATCHBUFFER 2 +#define I915_PARAM_LAST_DISPATCH 3 +#define I915_PARAM_CHIPSET_ID 4 +#define I915_PARAM_HAS_GEM 5 +#define I915_PARAM_NUM_FENCES_AVAIL 6 +#define I915_PARAM_HAS_OVERLAY 7 +#define I915_PARAM_HAS_PAGEFLIPPING 8 +#define I915_PARAM_HAS_EXECBUF2 9 +#define I915_PARAM_HAS_BSD 10 +#define I915_PARAM_HAS_BLT 11 +#define I915_PARAM_HAS_RELAXED_FENCING 12 +#define I915_PARAM_HAS_COHERENT_RINGS 13 +#define I915_PARAM_HAS_EXEC_CONSTANTS 14 +#define I915_PARAM_HAS_RELAXED_DELTA 15 +#define I915_PARAM_HAS_GEN7_SOL_RESET 16 +#define I915_PARAM_HAS_LLC 17 +#define I915_PARAM_HAS_ALIASING_PPGTT 18 +#define I915_PARAM_HAS_WAIT_TIMEOUT 19 +#define I915_PARAM_HAS_SEMAPHORES 20 +#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 +#define I915_PARAM_RSVD_FOR_FUTURE_USE 22 + +typedef struct drm_i915_getparam { + int param; + int __user *value; +} drm_i915_getparam_t; + +/* Ioctl to set kernel params: + */ +#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 +#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 +#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 +#define I915_SETPARAM_NUM_USED_FENCES 4 + +typedef struct drm_i915_setparam { + int param; + int value; +} drm_i915_setparam_t; + +/* A memory manager for regions of shared memory: + */ +#define I915_MEM_REGION_AGP 1 + +typedef struct drm_i915_mem_alloc { + int region; + int alignment; + int size; + int __user *region_offset; /* offset from start of fb or agp */ +} drm_i915_mem_alloc_t; + +typedef struct drm_i915_mem_free { + int region; + int region_offset; +} drm_i915_mem_free_t; + +typedef struct drm_i915_mem_init_heap { + int region; + int size; + int start; +} drm_i915_mem_init_heap_t; + +/* Allow memory manager to be torn down and re-initialized (eg on + * rotate): + */ +typedef struct drm_i915_mem_destroy_heap { + int region; +} drm_i915_mem_destroy_heap_t; + +/* Allow X server to configure which pipes to monitor for vblank signals + */ +#define DRM_I915_VBLANK_PIPE_A 1 +#define DRM_I915_VBLANK_PIPE_B 2 + +typedef struct drm_i915_vblank_pipe { + int pipe; +} drm_i915_vblank_pipe_t; + +/* Schedule buffer swap at given vertical blank: + */ +typedef struct drm_i915_vblank_swap { + drm_drawable_t drawable; + enum drm_vblank_seq_type seqtype; + unsigned int sequence; +} drm_i915_vblank_swap_t; + +typedef struct drm_i915_hws_addr { + __u64 addr; +} drm_i915_hws_addr_t; + +struct drm_i915_gem_init { + /** + * Beginning offset in the GTT to be managed by the DRM memory + * manager. + */ + __u64 gtt_start; + /** + * Ending offset in the GTT to be managed by the DRM memory + * manager. + */ + __u64 gtt_end; +}; + +struct drm_i915_gem_create { + /** + * Requested size for the object. + * + * The (page-aligned) allocated size for the object will be returned. + */ + __u64 size; + /** + * Returned handle for the object. + * + * Object handles are nonzero. + */ + __u32 handle; + __u32 pad; +}; + +struct drm_i915_gem_pread { + /** Handle for the object being read. */ + __u32 handle; + __u32 pad; + /** Offset into the object to read from */ + __u64 offset; + /** Length of data to read */ + __u64 size; + /** + * Pointer to write the data into. + * + * This is a fixed-size type for 32/64 compatibility. + */ + __u64 data_ptr; +}; + +struct drm_i915_gem_pwrite { + /** Handle for the object being written to. */ + __u32 handle; + __u32 pad; + /** Offset into the object to write to */ + __u64 offset; + /** Length of data to write */ + __u64 size; + /** + * Pointer to read the data from. + * + * This is a fixed-size type for 32/64 compatibility. + */ + __u64 data_ptr; +}; + +struct drm_i915_gem_mmap { + /** Handle for the object being mapped. */ + __u32 handle; + __u32 pad; + /** Offset in the object to map. */ + __u64 offset; + /** + * Length of data to map. + * + * The value will be page-aligned. + */ + __u64 size; + /** + * Returned pointer the data was mapped at. + * + * This is a fixed-size type for 32/64 compatibility. + */ + __u64 addr_ptr; +}; + +struct drm_i915_gem_mmap_gtt { + /** Handle for the object being mapped. */ + __u32 handle; + __u32 pad; + /** + * Fake offset to use for subsequent mmap call + * + * This is a fixed-size type for 32/64 compatibility. + */ + __u64 offset; +}; + +struct drm_i915_gem_set_domain { + /** Handle for the object */ + __u32 handle; + + /** New read domains */ + __u32 read_domains; + + /** New write domain */ + __u32 write_domain; +}; + +struct drm_i915_gem_sw_finish { + /** Handle for the object */ + __u32 handle; +}; + +struct drm_i915_gem_relocation_entry { + /** + * Handle of the buffer being pointed to by this relocation entry. + * + * It's appealing to make this be an index into the mm_validate_entry + * list to refer to the buffer, but this allows the driver to create + * a relocation list for state buffers and not re-write it per + * exec using the buffer. + */ + __u32 target_handle; + + /** + * Value to be added to the offset of the target buffer to make up + * the relocation entry. + */ + __u32 delta; + + /** Offset in the buffer the relocation entry will be written into */ + __u64 offset; + + /** + * Offset value of the target buffer that the relocation entry was last + * written as. + * + * If the buffer has the same offset as last time, we can skip syncing + * and writing the relocation. This value is written back out by + * the execbuffer ioctl when the relocation is written. + */ + __u64 presumed_offset; + + /** + * Target memory domains read by this operation. + */ + __u32 read_domains; + + /** + * Target memory domains written by this operation. + * + * Note that only one domain may be written by the whole + * execbuffer operation, so that where there are conflicts, + * the application will get -EINVAL back. + */ + __u32 write_domain; +}; + +/** @{ + * Intel memory domains + * + * Most of these just align with the various caches in + * the system and are used to flush and invalidate as + * objects end up cached in different domains. + */ +/** CPU cache */ +#define I915_GEM_DOMAIN_CPU 0x00000001 +/** Render cache, used by 2D and 3D drawing */ +#define I915_GEM_DOMAIN_RENDER 0x00000002 +/** Sampler cache, used by texture engine */ +#define I915_GEM_DOMAIN_SAMPLER 0x00000004 +/** Command queue, used to load batch buffers */ +#define I915_GEM_DOMAIN_COMMAND 0x00000008 +/** Instruction cache, used by shader programs */ +#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 +/** Vertex address cache */ +#define I915_GEM_DOMAIN_VERTEX 0x00000020 +/** GTT domain - aperture and scanout */ +#define I915_GEM_DOMAIN_GTT 0x00000040 +/** @} */ + +struct drm_i915_gem_exec_object { + /** + * User's handle for a buffer to be bound into the GTT for this + * operation. + */ + __u32 handle; + + /** Number of relocations to be performed on this buffer */ + __u32 relocation_count; + /** + * Pointer to array of struct drm_i915_gem_relocation_entry containing + * the relocations to be performed in this buffer. + */ + __u64 relocs_ptr; + + /** Required alignment in graphics aperture */ + __u64 alignment; + + /** + * Returned value of the updated offset of the object, for future + * presumed_offset writes. + */ + __u64 offset; +}; + +struct drm_i915_gem_execbuffer { + /** + * List of buffers to be validated with their relocations to be + * performend on them. + * + * This is a pointer to an array of struct drm_i915_gem_validate_entry. + * + * These buffers must be listed in an order such that all relocations + * a buffer is performing refer to buffers that have already appeared + * in the validate list. + */ + __u64 buffers_ptr; + __u32 buffer_count; + + /** Offset in the batchbuffer to start execution from. */ + __u32 batch_start_offset; + /** Bytes used in batchbuffer from batch_start_offset */ + __u32 batch_len; + __u32 DR1; + __u32 DR4; + __u32 num_cliprects; + /** This is a struct drm_clip_rect *cliprects */ + __u64 cliprects_ptr; +}; + +struct drm_i915_gem_exec_object2 { + /** + * User's handle for a buffer to be bound into the GTT for this + * operation. + */ + __u32 handle; + + /** Number of relocations to be performed on this buffer */ + __u32 relocation_count; + /** + * Pointer to array of struct drm_i915_gem_relocation_entry containing + * the relocations to be performed in this buffer. + */ + __u64 relocs_ptr; + + /** Required alignment in graphics aperture */ + __u64 alignment; + + /** + * Returned value of the updated offset of the object, for future + * presumed_offset writes. + */ + __u64 offset; + +#define EXEC_OBJECT_NEEDS_FENCE (1<<0) + __u64 flags; + __u64 rsvd1; + __u64 rsvd2; +}; + +struct drm_i915_gem_execbuffer2 { + /** + * List of gem_exec_object2 structs + */ + __u64 buffers_ptr; + __u32 buffer_count; + + /** Offset in the batchbuffer to start execution from. */ + __u32 batch_start_offset; + /** Bytes used in batchbuffer from batch_start_offset */ + __u32 batch_len; + __u32 DR1; + __u32 DR4; + __u32 num_cliprects; + /** This is a struct drm_clip_rect *cliprects */ + __u64 cliprects_ptr; +#define I915_EXEC_RING_MASK (7<<0) +#define I915_EXEC_DEFAULT (0<<0) +#define I915_EXEC_RENDER (1<<0) +#define I915_EXEC_BSD (2<<0) +#define I915_EXEC_BLT (3<<0) + +/* Used for switching the constants addressing mode on gen4+ RENDER ring. + * Gen6+ only supports relative addressing to dynamic state (default) and + * absolute addressing. + * + * These flags are ignored for the BSD and BLT rings. + */ +#define I915_EXEC_CONSTANTS_MASK (3<<6) +#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ +#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) +#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ + __u64 flags; + __u64 rsvd1; /* now used for context info */ + __u64 rsvd2; +}; + +/** Resets the SO write offset registers for transform feedback on gen7. */ +#define I915_EXEC_GEN7_SOL_RESET (1<<8) + +#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) +#define i915_execbuffer2_set_context_id(eb2, context) \ + (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK +#define i915_execbuffer2_get_context_id(eb2) \ + ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) + +struct drm_i915_gem_pin { + /** Handle of the buffer to be pinned. */ + __u32 handle; + __u32 pad; + + /** alignment required within the aperture */ + __u64 alignment; + + /** Returned GTT offset of the buffer. */ + __u64 offset; +}; + +struct drm_i915_gem_unpin { + /** Handle of the buffer to be unpinned. */ + __u32 handle; + __u32 pad; +}; + +struct drm_i915_gem_busy { + /** Handle of the buffer to check for busy */ + __u32 handle; + + /** Return busy status (1 if busy, 0 if idle). + * The high word is used to indicate on which rings the object + * currently resides: + * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) + */ + __u32 busy; +}; + +#define I915_CACHING_NONE 0 +#define I915_CACHING_CACHED 1 + +struct drm_i915_gem_caching { + /** + * Handle of the buffer to set/get the caching level of. */ + __u32 handle; + + /** + * Cacheing level to apply or return value + * + * bits0-15 are for generic caching control (i.e. the above defined + * values). bits16-31 are reserved for platform-specific variations + * (e.g. l3$ caching on gen7). */ + __u32 caching; +}; + +#define I915_TILING_NONE 0 +#define I915_TILING_X 1 +#define I915_TILING_Y 2 + +#define I915_BIT_6_SWIZZLE_NONE 0 +#define I915_BIT_6_SWIZZLE_9 1 +#define I915_BIT_6_SWIZZLE_9_10 2 +#define I915_BIT_6_SWIZZLE_9_11 3 +#define I915_BIT_6_SWIZZLE_9_10_11 4 +/* Not seen by userland */ +#define I915_BIT_6_SWIZZLE_UNKNOWN 5 +/* Seen by userland. */ +#define I915_BIT_6_SWIZZLE_9_17 6 +#define I915_BIT_6_SWIZZLE_9_10_17 7 + +struct drm_i915_gem_set_tiling { + /** Handle of the buffer to have its tiling state updated */ + __u32 handle; + + /** + * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, + * I915_TILING_Y). + * + * This value is to be set on request, and will be updated by the + * kernel on successful return with the actual chosen tiling layout. + * + * The tiling mode may be demoted to I915_TILING_NONE when the system + * has bit 6 swizzling that can't be managed correctly by GEM. + * + * Buffer contents become undefined when changing tiling_mode. + */ + __u32 tiling_mode; + + /** + * Stride in bytes for the object when in I915_TILING_X or + * I915_TILING_Y. + */ + __u32 stride; + + /** + * Returned address bit 6 swizzling required for CPU access through + * mmap mapping. + */ + __u32 swizzle_mode; +}; + +struct drm_i915_gem_get_tiling { + /** Handle of the buffer to get tiling state for. */ + __u32 handle; + + /** + * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, + * I915_TILING_Y). + */ + __u32 tiling_mode; + + /** + * Returned address bit 6 swizzling required for CPU access through + * mmap mapping. + */ + __u32 swizzle_mode; +}; + +struct drm_i915_gem_get_aperture { + /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ + __u64 aper_size; + + /** + * Available space in the aperture used by i915_gem_execbuffer, in + * bytes + */ + __u64 aper_available_size; +}; + +struct drm_i915_get_pipe_from_crtc_id { + /** ID of CRTC being requested **/ + __u32 crtc_id; + + /** pipe of requested CRTC **/ + __u32 pipe; +}; + +#define I915_MADV_WILLNEED 0 +#define I915_MADV_DONTNEED 1 +#define __I915_MADV_PURGED 2 /* internal state */ + +struct drm_i915_gem_madvise { + /** Handle of the buffer to change the backing store advice */ + __u32 handle; + + /* Advice: either the buffer will be needed again in the near future, + * or wont be and could be discarded under memory pressure. + */ + __u32 madv; + + /** Whether the backing store still exists. */ + __u32 retained; +}; + +/* flags */ +#define I915_OVERLAY_TYPE_MASK 0xff +#define I915_OVERLAY_YUV_PLANAR 0x01 +#define I915_OVERLAY_YUV_PACKED 0x02 +#define I915_OVERLAY_RGB 0x03 + +#define I915_OVERLAY_DEPTH_MASK 0xff00 +#define I915_OVERLAY_RGB24 0x1000 +#define I915_OVERLAY_RGB16 0x2000 +#define I915_OVERLAY_RGB15 0x3000 +#define I915_OVERLAY_YUV422 0x0100 +#define I915_OVERLAY_YUV411 0x0200 +#define I915_OVERLAY_YUV420 0x0300 +#define I915_OVERLAY_YUV410 0x0400 + +#define I915_OVERLAY_SWAP_MASK 0xff0000 +#define I915_OVERLAY_NO_SWAP 0x000000 +#define I915_OVERLAY_UV_SWAP 0x010000 +#define I915_OVERLAY_Y_SWAP 0x020000 +#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 + +#define I915_OVERLAY_FLAGS_MASK 0xff000000 +#define I915_OVERLAY_ENABLE 0x01000000 + +struct drm_intel_overlay_put_image { + /* various flags and src format description */ + __u32 flags; + /* source picture description */ + __u32 bo_handle; + /* stride values and offsets are in bytes, buffer relative */ + __u16 stride_Y; /* stride for packed formats */ + __u16 stride_UV; + __u32 offset_Y; /* offset for packet formats */ + __u32 offset_U; + __u32 offset_V; + /* in pixels */ + __u16 src_width; + __u16 src_height; + /* to compensate the scaling factors for partially covered surfaces */ + __u16 src_scan_width; + __u16 src_scan_height; + /* output crtc description */ + __u32 crtc_id; + __u16 dst_x; + __u16 dst_y; + __u16 dst_width; + __u16 dst_height; +}; + +/* flags */ +#define I915_OVERLAY_UPDATE_ATTRS (1<<0) +#define I915_OVERLAY_UPDATE_GAMMA (1<<1) +struct drm_intel_overlay_attrs { + __u32 flags; + __u32 color_key; + __s32 brightness; + __u32 contrast; + __u32 saturation; + __u32 gamma0; + __u32 gamma1; + __u32 gamma2; + __u32 gamma3; + __u32 gamma4; + __u32 gamma5; +}; + +/* + * Intel sprite handling + * + * Color keying works with a min/mask/max tuple. Both source and destination + * color keying is allowed. + * + * Source keying: + * Sprite pixels within the min & max values, masked against the color channels + * specified in the mask field, will be transparent. All other pixels will + * be displayed on top of the primary plane. For RGB surfaces, only the min + * and mask fields will be used; ranged compares are not allowed. + * + * Destination keying: + * Primary plane pixels that match the min value, masked against the color + * channels specified in the mask field, will be replaced by corresponding + * pixels from the sprite plane. + * + * Note that source & destination keying are exclusive; only one can be + * active on a given plane. + */ + +#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ +#define I915_SET_COLORKEY_DESTINATION (1<<1) +#define I915_SET_COLORKEY_SOURCE (1<<2) +struct drm_intel_sprite_colorkey { + __u32 plane_id; + __u32 min_value; + __u32 channel_mask; + __u32 max_value; + __u32 flags; +}; + +struct drm_i915_gem_wait { + /** Handle of BO we shall wait on */ + __u32 bo_handle; + __u32 flags; + /** Number of nanoseconds to wait, Returns time remaining. */ + __s64 timeout_ns; +}; + +struct drm_i915_gem_context_create { + /* output: id of new context*/ + __u32 ctx_id; + __u32 pad; +}; + +struct drm_i915_gem_context_destroy { + __u32 ctx_id; + __u32 pad; +}; + +struct drm_i915_reg_read { + __u64 offset; + __u64 val; /* Return value */ +}; +#endif /* _UAPI_I915_DRM_H_ */ diff --git a/include/drm/mga_drm.h b/include/uapi/drm/mga_drm.h index 2375bfd6e5e9..2375bfd6e5e9 100644 --- a/include/drm/mga_drm.h +++ b/include/uapi/drm/mga_drm.h diff --git a/include/drm/nouveau_drm.h b/include/uapi/drm/nouveau_drm.h index 2a5769fdf8ba..2a5769fdf8ba 100644 --- a/include/drm/nouveau_drm.h +++ b/include/uapi/drm/nouveau_drm.h diff --git a/include/drm/r128_drm.h b/include/uapi/drm/r128_drm.h index 8d8878b55f55..8d8878b55f55 100644 --- a/include/drm/r128_drm.h +++ b/include/uapi/drm/r128_drm.h diff --git a/include/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h index 4766c0f6a838..4766c0f6a838 100644 --- a/include/drm/radeon_drm.h +++ b/include/uapi/drm/radeon_drm.h diff --git a/include/drm/savage_drm.h b/include/uapi/drm/savage_drm.h index 818d49be2e6e..818d49be2e6e 100644 --- a/include/drm/savage_drm.h +++ b/include/uapi/drm/savage_drm.h diff --git a/include/drm/sis_drm.h b/include/uapi/drm/sis_drm.h index df3763222d73..df3763222d73 100644 --- a/include/drm/sis_drm.h +++ b/include/uapi/drm/sis_drm.h diff --git a/include/drm/via_drm.h b/include/uapi/drm/via_drm.h index 8b0533ccbd5a..8b0533ccbd5a 100644 --- a/include/drm/via_drm.h +++ b/include/uapi/drm/via_drm.h diff --git a/include/drm/vmwgfx_drm.h b/include/uapi/drm/vmwgfx_drm.h index bcb0912afe7a..bcb0912afe7a 100644 --- a/include/drm/vmwgfx_drm.h +++ b/include/uapi/drm/vmwgfx_drm.h diff --git a/include/xen/events.h b/include/xen/events.h index 04399b28e821..c6bfe01acf6b 100644 --- a/include/xen/events.h +++ b/include/xen/events.h @@ -109,4 +109,6 @@ int xen_irq_from_gsi(unsigned gsi); /* Determine whether to ignore this IRQ if it is passed to a guest. */ int xen_test_irq_shared(int irq); +/* initialize Xen IRQ subsystem */ +void xen_init_IRQ(void); #endif /* _XEN_EVENTS_H */ diff --git a/include/xen/interface/features.h b/include/xen/interface/features.h index b6ca39a069d8..131a6ccdba25 100644 --- a/include/xen/interface/features.h +++ b/include/xen/interface/features.h @@ -50,6 +50,9 @@ /* x86: pirq can be used by HVM guests */ #define XENFEAT_hvm_pirqs 10 +/* operation as Dom0 is supported */ +#define XENFEAT_dom0 11 + #define XENFEAT_NR_SUBMAPS 1 #endif /* __XEN_PUBLIC_FEATURES_H__ */ diff --git a/include/xen/interface/io/protocols.h b/include/xen/interface/io/protocols.h index 01fc8ae5f0b0..0eafaf254fff 100644 --- a/include/xen/interface/io/protocols.h +++ b/include/xen/interface/io/protocols.h @@ -5,6 +5,7 @@ #define XEN_IO_PROTO_ABI_X86_64 "x86_64-abi" #define XEN_IO_PROTO_ABI_IA64 "ia64-abi" #define XEN_IO_PROTO_ABI_POWERPC64 "powerpc64-abi" +#define XEN_IO_PROTO_ABI_ARM "arm-abi" #if defined(__i386__) # define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_X86_32 @@ -14,6 +15,8 @@ # define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_IA64 #elif defined(__powerpc64__) # define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_POWERPC64 +#elif defined(__arm__) +# define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_ARM #else # error arch fixup needed here #endif diff --git a/include/xen/interface/memory.h b/include/xen/interface/memory.h index d8e33a93ea4d..b66d04ce6957 100644 --- a/include/xen/interface/memory.h +++ b/include/xen/interface/memory.h @@ -34,7 +34,7 @@ struct xen_memory_reservation { GUEST_HANDLE(xen_pfn_t) extent_start; /* Number of extents, and size/alignment of each (2^extent_order pages). */ - unsigned long nr_extents; + xen_ulong_t nr_extents; unsigned int extent_order; /* @@ -92,7 +92,7 @@ struct xen_memory_exchange { * command will be non-zero. * 5. THIS FIELD MUST BE INITIALISED TO ZERO BY THE CALLER! */ - unsigned long nr_exchanged; + xen_ulong_t nr_exchanged; }; DEFINE_GUEST_HANDLE_STRUCT(xen_memory_exchange); @@ -148,8 +148,8 @@ DEFINE_GUEST_HANDLE_STRUCT(xen_machphys_mfn_list); */ #define XENMEM_machphys_mapping 12 struct xen_machphys_mapping { - unsigned long v_start, v_end; /* Start and end virtual addresses. */ - unsigned long max_mfn; /* Maximum MFN that can be looked up. */ + xen_ulong_t v_start, v_end; /* Start and end virtual addresses. */ + xen_ulong_t max_mfn; /* Maximum MFN that can be looked up. */ }; DEFINE_GUEST_HANDLE_STRUCT(xen_machphys_mapping_t); @@ -172,7 +172,7 @@ struct xen_add_to_physmap { unsigned int space; /* Index into source mapping space. */ - unsigned long idx; + xen_ulong_t idx; /* GPFN where the source mapping page should appear. */ xen_pfn_t gpfn; @@ -189,7 +189,7 @@ struct xen_translate_gpfn_list { domid_t domid; /* Length of list. */ - unsigned long nr_gpfns; + xen_ulong_t nr_gpfns; /* List of GPFNs to translate. */ GUEST_HANDLE(ulong) gpfn_list; diff --git a/include/xen/interface/physdev.h b/include/xen/interface/physdev.h index bfa1d50fe15b..1844d31f4552 100644 --- a/include/xen/interface/physdev.h +++ b/include/xen/interface/physdev.h @@ -56,7 +56,7 @@ struct physdev_eoi { #define PHYSDEVOP_pirq_eoi_gmfn_v2 28 struct physdev_pirq_eoi_gmfn { /* IN */ - unsigned long gmfn; + xen_ulong_t gmfn; }; /* diff --git a/include/xen/interface/version.h b/include/xen/interface/version.h index 5f5e551cf546..7ff6498679a3 100644 --- a/include/xen/interface/version.h +++ b/include/xen/interface/version.h @@ -45,7 +45,7 @@ struct xen_changeset_info { #define XENVER_platform_parameters 5 struct xen_platform_parameters { - unsigned long virt_start; + xen_ulong_t virt_start; }; #define XENVER_get_features 6 diff --git a/include/xen/xen.h b/include/xen/xen.h index a16402418d31..a74d4362c4f8 100644 --- a/include/xen/xen.h +++ b/include/xen/xen.h @@ -23,8 +23,8 @@ extern enum xen_domain_type xen_domain_type; #include <xen/interface/xen.h> #include <asm/xen/hypervisor.h> -#define xen_initial_domain() (xen_pv_domain() && \ - xen_start_info->flags & SIF_INITDOMAIN) +#define xen_initial_domain() (xen_domain() && \ + xen_start_info && xen_start_info->flags & SIF_INITDOMAIN) #else /* !CONFIG_XEN_DOM0 */ #define xen_initial_domain() (0) #endif /* CONFIG_XEN_DOM0 */ |