aboutsummaryrefslogtreecommitdiffstats
path: root/sound/soc/codecs/wm9713.c
diff options
context:
space:
mode:
Diffstat (limited to '')
-rw-r--r--sound/soc/codecs/wm9713.c9
1 files changed, 4 insertions, 5 deletions
diff --git a/sound/soc/codecs/wm9713.c b/sound/soc/codecs/wm9713.c
index 6497c1ea6228..5d2e54e06e30 100644
--- a/sound/soc/codecs/wm9713.c
+++ b/sound/soc/codecs/wm9713.c
@@ -755,7 +755,7 @@ static void pll_factors(struct snd_soc_component *component,
u64 Kpart;
unsigned int K, Ndiv, Nmod, target;
- /* The the PLL output is always 98.304MHz. */
+ /* The PLL output is always 98.304MHz. */
target = 98304000;
/* If the input frequency is over 14.4MHz then scale it down. */
@@ -807,7 +807,7 @@ static void pll_factors(struct snd_soc_component *component,
pll_div->k = K;
}
-/**
+/*
* Please note that changing the PLL input frequency may require
* resynchronisation with the AC97 controller.
*/
@@ -939,7 +939,7 @@ static int wm9713_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
- u16 gpio = snd_soc_component_read32(component, AC97_GPIO_CFG) & 0xffc5;
+ u16 gpio = snd_soc_component_read(component, AC97_GPIO_CFG) & 0xffc5;
u16 reg = 0x8000;
/* clock masters */
@@ -1134,7 +1134,7 @@ static struct snd_soc_dai_driver wm9713_dai[] = {
.rates = WM9713_PCM_RATES,
.formats = WM9713_PCM_FORMATS,},
.ops = &wm9713_dai_ops_voice,
- .symmetric_rates = 1,
+ .symmetric_rate = 1,
},
};
@@ -1257,7 +1257,6 @@ static const struct snd_soc_component_driver soc_component_dev_wm9713 = {
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
- .non_legacy_dai_naming = 1,
};
static int wm9713_probe(struct platform_device *pdev)