diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/powerpc/power9/translation.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/powerpc/power9/translation.json | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/tools/perf/pmu-events/arch/powerpc/power9/translation.json b/tools/perf/pmu-events/arch/powerpc/power9/translation.json index bc8e03d7a6b0..b27642676244 100644 --- a/tools/perf/pmu-events/arch/powerpc/power9/translation.json +++ b/tools/perf/pmu-events/arch/powerpc/power9/translation.json @@ -30,11 +30,6 @@ "BriefDescription": "Store finish count. Includes speculative activity" }, {, - "EventCode": "0x44042", - "EventName": "PM_INST_FROM_L3", - "BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)" - }, - {, "EventCode": "0x1504A", "EventName": "PM_IPTEG_FROM_RL2L3_SHR", "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request" @@ -125,6 +120,11 @@ "BriefDescription": "PMC1 Rewind Value saved" }, {, + "EventCode": "0x44042", + "EventName": "PM_INST_FROM_L3", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)" + }, + {, "EventCode": "0x200FE", "EventName": "PM_DATA_FROM_L2MISS", "BriefDescription": "Demand LD - L2 Miss (not L2 hit)" |