diff options
Diffstat (limited to '')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/bonnell/frontend.json | 98 |
1 files changed, 53 insertions, 45 deletions
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json index ef69540ab61d..21fe5fe229aa 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json @@ -1,83 +1,91 @@ [ { - "EventCode": "0x80", + "BriefDescription": "BACLEARS asserted.", "Counter": "0,1", - "UMask": "0x3", - "EventName": "ICACHE.ACCESSES", - "SampleAfterValue": "200000", - "BriefDescription": "Instruction fetches." + "EventCode": "0xE6", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "Cycles during which instruction fetches are stalled.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "ICACHE.HIT", - "SampleAfterValue": "200000", - "BriefDescription": "Icache hit" + "EventCode": "0x86", + "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "Decode stall due to IQ full", "Counter": "0,1", - "UMask": "0x2", - "EventName": "ICACHE.MISSES", - "SampleAfterValue": "200000", - "BriefDescription": "Icache miss" + "EventCode": "0x87", + "EventName": "DECODE_STALL.IQ_FULL", + "SampleAfterValue": "2000000", + "UMask": "0x2" }, { - "EventCode": "0x86", + "BriefDescription": "Decode stall due to PFB empty", "Counter": "0,1", - "UMask": "0x1", - "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED", + "EventCode": "0x87", + "EventName": "DECODE_STALL.PFB_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles during which instruction fetches are stalled." + "UMask": "0x1" }, { - "EventCode": "0x87", + "BriefDescription": "Instruction fetches.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "DECODE_STALL.PFB_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Decode stall due to PFB empty" + "EventCode": "0x80", + "EventName": "ICACHE.ACCESSES", + "SampleAfterValue": "200000", + "UMask": "0x3" }, { - "EventCode": "0x87", + "BriefDescription": "Icache hit", "Counter": "0,1", - "UMask": "0x2", - "EventName": "DECODE_STALL.IQ_FULL", - "SampleAfterValue": "2000000", - "BriefDescription": "Decode stall due to IQ full" + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "SampleAfterValue": "200000", + "UMask": "0x1" }, { - "EventCode": "0xAA", + "BriefDescription": "Icache miss", "Counter": "0,1", - "UMask": "0x1", - "EventName": "MACRO_INSTS.NON_CISC_DECODED", - "SampleAfterValue": "2000000", - "BriefDescription": "Non-CISC nacro instructions decoded" + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "SampleAfterValue": "200000", + "UMask": "0x2" }, { + "BriefDescription": "All Instructions decoded", + "Counter": "0,1", "EventCode": "0xAA", + "EventName": "MACRO_INSTS.ALL_DECODED", + "SampleAfterValue": "2000000", + "UMask": "0x3" + }, + { + "BriefDescription": "CISC macro instructions decoded", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0xAA", "EventName": "MACRO_INSTS.CISC_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "CISC macro instructions decoded" + "UMask": "0x2" }, { - "EventCode": "0xAA", + "BriefDescription": "Non-CISC nacro instructions decoded", "Counter": "0,1", - "UMask": "0x3", - "EventName": "MACRO_INSTS.ALL_DECODED", + "EventCode": "0xAA", + "EventName": "MACRO_INSTS.NON_CISC_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "All Instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0xA9", + "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.", "Counter": "0,1", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xA9", "EventName": "UOPS.MS_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.", - "CounterMask": "1" + "UMask": "0x1" } -]
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