diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json | 128 |
1 files changed, 64 insertions, 64 deletions
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json b/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json index 7bb817588721..e8512c585572 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json @@ -1,124 +1,124 @@ [ { - "EventCode": "0x8", + "BriefDescription": "Memory accesses that missed the DTLB.", "Counter": "0,1", - "UMask": "0x7", + "EventCode": "0x8", "EventName": "DATA_TLB_MISSES.DTLB_MISS", "SampleAfterValue": "200000", - "BriefDescription": "Memory accesses that missed the DTLB." + "UMask": "0x7" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB misses due to load operations.", "Counter": "0,1", - "UMask": "0x5", + "EventCode": "0x8", "EventName": "DATA_TLB_MISSES.DTLB_MISS_LD", "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses due to load operations." + "UMask": "0x5" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB misses due to store operations.", "Counter": "0,1", - "UMask": "0x9", - "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD", + "EventCode": "0x8", + "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST", "SampleAfterValue": "200000", - "BriefDescription": "L0 DTLB misses due to load operations." + "UMask": "0x6" }, { - "EventCode": "0x8", + "BriefDescription": "L0 DTLB misses due to load operations.", "Counter": "0,1", - "UMask": "0x6", - "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST", + "EventCode": "0x8", + "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD", "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses due to store operations." + "UMask": "0x9" }, { - "EventCode": "0x8", + "BriefDescription": "L0 DTLB misses due to store operations", "Counter": "0,1", - "UMask": "0xa", + "EventCode": "0x8", "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST", "SampleAfterValue": "200000", - "BriefDescription": "L0 DTLB misses due to store operations" + "UMask": "0xa" }, { - "EventCode": "0xC", + "BriefDescription": "ITLB flushes.", "Counter": "0,1", - "UMask": "0x3", - "EventName": "PAGE_WALKS.WALKS", + "EventCode": "0x82", + "EventName": "ITLB.FLUSH", "SampleAfterValue": "200000", - "BriefDescription": "Number of page-walks executed." + "UMask": "0x4" }, { - "EventCode": "0xC", + "BriefDescription": "ITLB hits.", "Counter": "0,1", - "UMask": "0x3", - "EventName": "PAGE_WALKS.CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Duration of page-walks in core cycles" + "EventCode": "0x82", + "EventName": "ITLB.HIT", + "SampleAfterValue": "200000", + "UMask": "0x1" }, { - "EventCode": "0xC", + "BriefDescription": "ITLB misses.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "PAGE_WALKS.D_SIDE_WALKS", + "EventCode": "0x82", + "EventName": "ITLB.MISSES", + "PEBS": "2", "SampleAfterValue": "200000", - "BriefDescription": "Number of D-side only page walks" + "UMask": "0x2" }, { - "EventCode": "0xC", + "BriefDescription": "Retired loads that miss the DTLB (precise event).", "Counter": "0,1", - "UMask": "0x1", - "EventName": "PAGE_WALKS.D_SIDE_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Duration of D-side only page walks" + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x4" }, { - "EventCode": "0xC", + "BriefDescription": "Duration of page-walks in core cycles", "Counter": "0,1", - "UMask": "0x2", - "EventName": "PAGE_WALKS.I_SIDE_WALKS", - "SampleAfterValue": "200000", - "BriefDescription": "Number of I-Side page walks" + "EventCode": "0xC", + "EventName": "PAGE_WALKS.CYCLES", + "SampleAfterValue": "2000000", + "UMask": "0x3" }, { - "EventCode": "0xC", + "BriefDescription": "Duration of D-side only page walks", "Counter": "0,1", - "UMask": "0x2", - "EventName": "PAGE_WALKS.I_SIDE_CYCLES", + "EventCode": "0xC", + "EventName": "PAGE_WALKS.D_SIDE_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Duration of I-Side page walks" + "UMask": "0x1" }, { - "EventCode": "0x82", + "BriefDescription": "Number of D-side only page walks", "Counter": "0,1", - "UMask": "0x1", - "EventName": "ITLB.HIT", + "EventCode": "0xC", + "EventName": "PAGE_WALKS.D_SIDE_WALKS", "SampleAfterValue": "200000", - "BriefDescription": "ITLB hits." + "UMask": "0x1" }, { - "EventCode": "0x82", + "BriefDescription": "Duration of I-Side page walks", "Counter": "0,1", - "UMask": "0x4", - "EventName": "ITLB.FLUSH", - "SampleAfterValue": "200000", - "BriefDescription": "ITLB flushes." + "EventCode": "0xC", + "EventName": "PAGE_WALKS.I_SIDE_CYCLES", + "SampleAfterValue": "2000000", + "UMask": "0x2" }, { - "PEBS": "2", - "EventCode": "0x82", + "BriefDescription": "Number of I-Side page walks", "Counter": "0,1", - "UMask": "0x2", - "EventName": "ITLB.MISSES", + "EventCode": "0xC", + "EventName": "PAGE_WALKS.I_SIDE_WALKS", "SampleAfterValue": "200000", - "BriefDescription": "ITLB misses." + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xCB", + "BriefDescription": "Number of page-walks executed.", "Counter": "0,1", - "UMask": "0x4", - "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "EventCode": "0xC", + "EventName": "PAGE_WALKS.WALKS", "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss the DTLB (precise event)." + "UMask": "0x3" } -]
\ No newline at end of file +] |