diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/broadwell/cache.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/broadwell/cache.json | 1630 |
1 files changed, 815 insertions, 815 deletions
diff --git a/tools/perf/pmu-events/arch/x86/broadwell/cache.json b/tools/perf/pmu-events/arch/x86/broadwell/cache.json index 0b080b0352d8..7938bf5689ab 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/cache.json @@ -56,10 +56,10 @@ "CounterHTOff": "0,1,2,3,4,5,6,7" }, { - "PublicDescription": "This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted.", + "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache.", "EventCode": "0x24", "Counter": "0,1,2,3", - "UMask": "0x41", + "UMask": "0xc1", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "SampleAfterValue": "200003", "BriefDescription": "Demand Data Read requests that hit L2 cache", @@ -68,7 +68,7 @@ { "EventCode": "0x24", "Counter": "0,1,2,3", - "UMask": "0x42", + "UMask": "0xc2", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200003", "BriefDescription": "RFO requests that hit L2 cache.", @@ -77,7 +77,7 @@ { "EventCode": "0x24", "Counter": "0,1,2,3", - "UMask": "0x44", + "UMask": "0xc4", "EventName": "L2_RQSTS.CODE_RD_HIT", "SampleAfterValue": "200003", "BriefDescription": "L2 cache hits when fetching instructions, code reads.", @@ -87,7 +87,7 @@ "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", "EventCode": "0x24", "Counter": "0,1,2,3", - "UMask": "0x50", + "UMask": "0xd0", "EventName": "L2_RQSTS.L2_PF_HIT", "SampleAfterValue": "200003", "BriefDescription": "L2 prefetch requests that hit L2 cache", @@ -433,7 +433,7 @@ }, { "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x41", @@ -445,7 +445,7 @@ }, { "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x42", @@ -771,2628 +771,2628 @@ "CounterHTOff": "0,1,2,3,4,5,6,7" }, { - "PublicDescription": "Counts demand data reads that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts demand data reads have any response type.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010001 ", + "MSRValue": "0x0000010001", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that have any response type.", + "BriefDescription": "Counts demand data reads have any response type.", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts demand data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020001 ", + "MSRValue": "0x0080020001", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_NONE", + "BriefDescription": "Counts demand data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts demand data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020001 ", + "MSRValue": "0x0100020001", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "BriefDescription": "Counts demand data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts demand data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020001 ", + "MSRValue": "0x0200020001", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_MISS", + "BriefDescription": "Counts demand data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts demand data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020001 ", + "MSRValue": "0x0400020001", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts demand data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts demand data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020001 ", + "MSRValue": "0x1000020001", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_HITM", + "BriefDescription": "Counts demand data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts demand data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f80020001 ", + "MSRValue": "0x3F80020001", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & ANY_SNOOP", + "BriefDescription": "Counts demand data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts demand data reads that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts demand data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803c0001 ", + "MSRValue": "0x00803C0001", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the L3 with no details on snoop-related information.", + "BriefDescription": "Counts demand data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts demand data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003c0001 ", + "MSRValue": "0x01003C0001", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "BriefDescription": "Counts demand data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts demand data reads that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts demand data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003c0001 ", + "MSRValue": "0x02003C0001", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the L3 with a snoop miss response.", + "BriefDescription": "Counts demand data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts demand data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003c0001 ", + "MSRValue": "0x04003C0001", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "BriefDescription": "Counts demand data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts demand data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0001 ", + "MSRValue": "0x10003C0001", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_DATA_RD & L3_HIT & SNOOP_HITM", + "BriefDescription": "Counts demand data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts demand data reads that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts demand data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0001 ", + "MSRValue": "0x3F803C0001", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the L3.", + "BriefDescription": "Counts demand data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand data writes (RFOs) that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand data writes (RFOs) have any response type.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010002 ", + "MSRValue": "0x0000010002", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs) that have any response type.", + "BriefDescription": "Counts all demand data writes (RFOs) have any response type.", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand data writes (RFOs)", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803c0002 ", + "MSRValue": "0x00803C0002", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 with no details on snoop-related information.", + "BriefDescription": "Counts all demand data writes (RFOs)", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand data writes (RFOs)", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003c0002 ", + "MSRValue": "0x01003C0002", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "BriefDescription": "Counts all demand data writes (RFOs)", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand data writes (RFOs)", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003c0002 ", + "MSRValue": "0x02003C0002", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 with a snoop miss response.", + "BriefDescription": "Counts all demand data writes (RFOs)", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand data writes (RFOs)", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003c0002 ", + "MSRValue": "0x04003C0002", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "BriefDescription": "Counts all demand data writes (RFOs)", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand data writes (RFOs)", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0002 ", + "MSRValue": "0x10003C0002", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_RFO & L3_HIT & SNOOP_HITM", + "BriefDescription": "Counts all demand data writes (RFOs)", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand data writes (RFOs)", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0002 ", + "MSRValue": "0x3F803C0002", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3.", + "BriefDescription": "Counts all demand data writes (RFOs)", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand code reads that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand code reads have any response type.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010004 ", + "MSRValue": "0x0000010004", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that have any response type.", + "BriefDescription": "Counts all demand code reads have any response type.", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020004 ", + "MSRValue": "0x0080020004", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_NONE", + "BriefDescription": "Counts all demand code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020004 ", + "MSRValue": "0x0100020004", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "BriefDescription": "Counts all demand code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020004 ", + "MSRValue": "0x0200020004", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_MISS", + "BriefDescription": "Counts all demand code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020004 ", + "MSRValue": "0x0400020004", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts all demand code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020004 ", + "MSRValue": "0x1000020004", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_HITM", + "BriefDescription": "Counts all demand code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f80020004 ", + "MSRValue": "0x3F80020004", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & ANY_SNOOP", + "BriefDescription": "Counts all demand code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand code reads that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803c0004 ", + "MSRValue": "0x00803C0004", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that hit in the L3 with no details on snoop-related information.", + "BriefDescription": "Counts all demand code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003c0004 ", + "MSRValue": "0x01003C0004", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "BriefDescription": "Counts all demand code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand code reads that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003c0004 ", + "MSRValue": "0x02003C0004", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that hit in the L3 with a snoop miss response.", + "BriefDescription": "Counts all demand code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003c0004 ", + "MSRValue": "0x04003C0004", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "BriefDescription": "Counts all demand code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0004 ", + "MSRValue": "0x10003C0004", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_CODE_RD & L3_HIT & SNOOP_HITM", + "BriefDescription": "Counts all demand code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand code reads that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0004 ", + "MSRValue": "0x3F803C0004", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that hit in the L3.", + "BriefDescription": "Counts all demand code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts writebacks (modified to exclusive) that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts writebacks (modified to exclusive) have any response type.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010008 ", + "MSRValue": "0x0000010008", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts writebacks (modified to exclusive) that have any response type.", + "BriefDescription": "Counts writebacks (modified to exclusive) have any response type.", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts writebacks (modified to exclusive)", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020008 ", + "MSRValue": "0x0080020008", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "COREWB & SUPPLIER_NONE & SNOOP_NONE", + "BriefDescription": "Counts writebacks (modified to exclusive)", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts writebacks (modified to exclusive)", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020008 ", + "MSRValue": "0x0100020008", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "COREWB & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "BriefDescription": "Counts writebacks (modified to exclusive)", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts writebacks (modified to exclusive)", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020008 ", + "MSRValue": "0x0200020008", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "COREWB & SUPPLIER_NONE & SNOOP_MISS", + "BriefDescription": "Counts writebacks (modified to exclusive)", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts writebacks (modified to exclusive)", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020008 ", + "MSRValue": "0x0400020008", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "COREWB & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts writebacks (modified to exclusive)", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts writebacks (modified to exclusive)", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020008 ", + "MSRValue": "0x1000020008", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "COREWB & SUPPLIER_NONE & SNOOP_HITM", + "BriefDescription": "Counts writebacks (modified to exclusive)", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts writebacks (modified to exclusive)", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f80020008 ", + "MSRValue": "0x3F80020008", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "COREWB & SUPPLIER_NONE & ANY_SNOOP", + "BriefDescription": "Counts writebacks (modified to exclusive)", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts writebacks (modified to exclusive) that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts writebacks (modified to exclusive)", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803c0008 ", + "MSRValue": "0x00803C0008", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3 with no details on snoop-related information.", + "BriefDescription": "Counts writebacks (modified to exclusive)", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts writebacks (modified to exclusive) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts writebacks (modified to exclusive)", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003c0008 ", + "MSRValue": "0x01003C0008", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "BriefDescription": "Counts writebacks (modified to exclusive)", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts writebacks (modified to exclusive) that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts writebacks (modified to exclusive)", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003c0008 ", + "MSRValue": "0x02003C0008", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3 with a snoop miss response.", + "BriefDescription": "Counts writebacks (modified to exclusive)", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts writebacks (modified to exclusive) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts writebacks (modified to exclusive)", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003c0008 ", + "MSRValue": "0x04003C0008", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "BriefDescription": "Counts writebacks (modified to exclusive)", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts writebacks (modified to exclusive)", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0008 ", + "MSRValue": "0x10003C0008", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "COREWB & L3_HIT & SNOOP_HITM", + "BriefDescription": "Counts writebacks (modified to exclusive)", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts writebacks (modified to exclusive) that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts writebacks (modified to exclusive)", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0008 ", + "MSRValue": "0x3F803C0008", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3.", + "BriefDescription": "Counts writebacks (modified to exclusive)", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts prefetch (that bring data to L2) data reads that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to L2) data reads have any response type.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010010 ", + "MSRValue": "0x0000010010", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that have any response type.", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads have any response type.", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to L2) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020010 ", + "MSRValue": "0x0080020010", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L2_DATA_RD & SUPPLIER_NONE & SNOOP_NONE", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to L2) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020010 ", + "MSRValue": "0x0100020010", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L2_DATA_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to L2) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020010 ", + "MSRValue": "0x0200020010", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L2_DATA_RD & SUPPLIER_NONE & SNOOP_MISS", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to L2) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020010 ", + "MSRValue": "0x0400020010", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L2_DATA_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to L2) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020010 ", + "MSRValue": "0x1000020010", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L2_DATA_RD & SUPPLIER_NONE & SNOOP_HITM", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to L2) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f80020010 ", + "MSRValue": "0x3F80020010", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L2_DATA_RD & SUPPLIER_NONE & ANY_SNOOP", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to L2) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803c0010 ", + "MSRValue": "0x00803C0010", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 with no details on snoop-related information.", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to L2) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003c0010 ", + "MSRValue": "0x01003C0010", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to L2) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003c0010 ", + "MSRValue": "0x02003C0010", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 with a snoop miss response.", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to L2) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003c0010 ", + "MSRValue": "0x04003C0010", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to L2) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0010 ", + "MSRValue": "0x10003C0010", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L2_DATA_RD & L3_HIT & SNOOP_HITM", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to L2) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0010 ", + "MSRValue": "0x3F803C0010", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3.", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010020 ", + "MSRValue": "0x0000010020", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that have any response type.", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type.", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020020 ", + "MSRValue": "0x0080020020", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L2_RFO & SUPPLIER_NONE & SNOOP_NONE", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020020 ", + "MSRValue": "0x0100020020", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L2_RFO & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020020 ", + "MSRValue": "0x0200020020", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L2_RFO & SUPPLIER_NONE & SNOOP_MISS", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020020 ", + "MSRValue": "0x0400020020", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L2_RFO & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020020 ", + "MSRValue": "0x1000020020", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L2_RFO & SUPPLIER_NONE & SNOOP_HITM", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f80020020 ", + "MSRValue": "0x3F80020020", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L2_RFO & SUPPLIER_NONE & ANY_SNOOP", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803c0020 ", + "MSRValue": "0x00803C0020", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 with no details on snoop-related information.", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003c0020 ", + "MSRValue": "0x01003C0020", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003c0020 ", + "MSRValue": "0x02003C0020", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 with a snoop miss response.", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003c0020 ", + "MSRValue": "0x04003C0020", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0020 ", + "MSRValue": "0x10003C0020", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L2_RFO & L3_HIT & SNOOP_HITM", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0020 ", + "MSRValue": "0x3F803C0020", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3.", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads have any response type.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010040 ", + "MSRValue": "0x0000010040", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that have any response type.", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads have any response type.", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020040 ", + "MSRValue": "0x0080020040", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L2_CODE_RD & SUPPLIER_NONE & SNOOP_NONE", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020040 ", + "MSRValue": "0x0100020040", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L2_CODE_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020040 ", + "MSRValue": "0x0200020040", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L2_CODE_RD & SUPPLIER_NONE & SNOOP_MISS", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020040 ", + "MSRValue": "0x0400020040", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L2_CODE_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020040 ", + "MSRValue": "0x1000020040", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L2_CODE_RD & SUPPLIER_NONE & SNOOP_HITM", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f80020040 ", + "MSRValue": "0x3F80020040", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L2_CODE_RD & SUPPLIER_NONE & ANY_SNOOP", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803c0040 ", + "MSRValue": "0x00803C0040", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 with no details on snoop-related information.", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003c0040 ", + "MSRValue": "0x01003C0040", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003c0040 ", + "MSRValue": "0x02003C0040", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 with a snoop miss response.", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003c0040 ", + "MSRValue": "0x04003C0040", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0040 ", + "MSRValue": "0x10003C0040", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L2_CODE_RD & L3_HIT & SNOOP_HITM", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0040 ", + "MSRValue": "0x3F803C0040", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3.", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010080 ", + "MSRValue": "0x0000010080", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that have any response type.", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020080 ", + "MSRValue": "0x0080020080", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_NONE", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020080 ", + "MSRValue": "0x0100020080", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020080 ", + "MSRValue": "0x0200020080", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_MISS", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020080 ", + "MSRValue": "0x0400020080", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020080 ", + "MSRValue": "0x1000020080", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_HITM", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f80020080 ", + "MSRValue": "0x3F80020080", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & ANY_SNOOP", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803c0080 ", + "MSRValue": "0x00803C0080", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 with no details on snoop-related information.", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003c0080 ", + "MSRValue": "0x01003C0080", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003c0080 ", + "MSRValue": "0x02003C0080", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 with a snoop miss response.", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003c0080 ", + "MSRValue": "0x04003C0080", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0080 ", + "MSRValue": "0x10003C0080", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L3_DATA_RD & L3_HIT & SNOOP_HITM", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0080 ", + "MSRValue": "0x3F803C0080", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3.", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010100 ", + "MSRValue": "0x0000010100", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that have any response type.", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020100 ", + "MSRValue": "0x0080020100", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_NONE", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020100 ", + "MSRValue": "0x0100020100", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020100 ", + "MSRValue": "0x0200020100", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_MISS", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020100 ", + "MSRValue": "0x0400020100", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020100 ", + "MSRValue": "0x1000020100", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_HITM", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f80020100 ", + "MSRValue": "0x3F80020100", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & ANY_SNOOP", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803c0100 ", + "MSRValue": "0x00803C0100", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 with no details on snoop-related information.", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003c0100 ", + "MSRValue": "0x01003C0100", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003c0100 ", + "MSRValue": "0x02003C0100", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 with a snoop miss response.", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003c0100 ", + "MSRValue": "0x04003C0100", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0100 ", + "MSRValue": "0x10003C0100", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L3_RFO & L3_HIT & SNOOP_HITM", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0100 ", + "MSRValue": "0x3F803C0100", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3.", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads have any response type.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010200 ", + "MSRValue": "0x0000010200", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that have any response type.", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads have any response type.", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020200 ", + "MSRValue": "0x0080020200", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L3_CODE_RD & SUPPLIER_NONE & SNOOP_NONE", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020200 ", + "MSRValue": "0x0100020200", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L3_CODE_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020200 ", + "MSRValue": "0x0200020200", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L3_CODE_RD & SUPPLIER_NONE & SNOOP_MISS", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020200 ", + "MSRValue": "0x0400020200", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L3_CODE_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020200 ", + "MSRValue": "0x1000020200", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L3_CODE_RD & SUPPLIER_NONE & SNOOP_HITM", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f80020200 ", + "MSRValue": "0x3F80020200", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L3_CODE_RD & SUPPLIER_NONE & ANY_SNOOP", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803c0200 ", + "MSRValue": "0x00803C0200", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 with no details on snoop-related information.", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003c0200 ", + "MSRValue": "0x01003C0200", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003c0200 ", + "MSRValue": "0x02003C0200", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 with a snoop miss response.", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003c0200 ", + "MSRValue": "0x04003C0200", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0200 ", + "MSRValue": "0x10003C0200", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "PF_L3_CODE_RD & L3_HIT & SNOOP_HITM", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0200 ", + "MSRValue": "0x3F803C0200", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3.", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts any other requests that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests have any response type.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000018000 ", + "MSRValue": "0x0000018000", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts any other requests that have any response type.", + "BriefDescription": "Counts any other requests have any response type.", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080028000 ", + "MSRValue": "0x0080028000", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "OTHER & SUPPLIER_NONE & SNOOP_NONE", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100028000 ", + "MSRValue": "0x0100028000", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "OTHER & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200028000 ", + "MSRValue": "0x0200028000", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "OTHER & SUPPLIER_NONE & SNOOP_MISS", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400028000 ", + "MSRValue": "0x0400028000", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "OTHER & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000028000 ", + "MSRValue": "0x1000028000", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "OTHER & SUPPLIER_NONE & SNOOP_HITM", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f80028000 ", + "MSRValue": "0x3F80028000", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "OTHER & SUPPLIER_NONE & ANY_SNOOP", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts any other requests that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803c8000 ", + "MSRValue": "0x00803C8000", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts any other requests that hit in the L3 with no details on snoop-related information.", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts any other requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003c8000 ", + "MSRValue": "0x01003C8000", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts any other requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts any other requests that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003c8000 ", + "MSRValue": "0x02003C8000", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts any other requests that hit in the L3 with a snoop miss response.", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts any other requests that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003c8000 ", + "MSRValue": "0x04003C8000", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts any other requests that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c8000 ", + "MSRValue": "0x10003C8000", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "OTHER & L3_HIT & SNOOP_HITM", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts any other requests that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c8000 ", + "MSRValue": "0x3F803C8000", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts any other requests that hit in the L3.", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch data reads that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch data reads have any response type.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010090 ", + "MSRValue": "0x0000010090", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads that have any response type.", + "BriefDescription": "Counts all prefetch data reads have any response type.", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020090 ", + "MSRValue": "0x0080020090", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_NONE", + "BriefDescription": "Counts all prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020090 ", + "MSRValue": "0x0100020090", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "BriefDescription": "Counts all prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020090 ", + "MSRValue": "0x0200020090", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_MISS", + "BriefDescription": "Counts all prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020090 ", + "MSRValue": "0x0400020090", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts all prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020090 ", + "MSRValue": "0x1000020090", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_HITM", + "BriefDescription": "Counts all prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f80020090 ", + "MSRValue": "0x3F80020090", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & ANY_SNOOP", + "BriefDescription": "Counts all prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch data reads that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803c0090 ", + "MSRValue": "0x00803C0090", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads that hit in the L3 with no details on snoop-related information.", + "BriefDescription": "Counts all prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003c0090 ", + "MSRValue": "0x01003C0090", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "BriefDescription": "Counts all prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch data reads that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003c0090 ", + "MSRValue": "0x02003C0090", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads that hit in the L3 with a snoop miss response.", + "BriefDescription": "Counts all prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003c0090 ", + "MSRValue": "0x04003C0090", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "BriefDescription": "Counts all prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0090 ", + "MSRValue": "0x10003C0090", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_PF_DATA_RD & L3_HIT & SNOOP_HITM", + "BriefDescription": "Counts all prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch data reads that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0090 ", + "MSRValue": "0x3F803C0090", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads that hit in the L3.", + "BriefDescription": "Counts all prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts prefetch RFOs that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch RFOs have any response type.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010120 ", + "MSRValue": "0x0000010120", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs that have any response type.", + "BriefDescription": "Counts prefetch RFOs have any response type.", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020120 ", + "MSRValue": "0x0080020120", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & SNOOP_NONE", + "BriefDescription": "Counts prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020120 ", + "MSRValue": "0x0100020120", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "BriefDescription": "Counts prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020120 ", + "MSRValue": "0x0200020120", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & SNOOP_MISS", + "BriefDescription": "Counts prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020120 ", + "MSRValue": "0x0400020120", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020120 ", + "MSRValue": "0x1000020120", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & SNOOP_HITM", + "BriefDescription": "Counts prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f80020120 ", + "MSRValue": "0x3F80020120", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & ANY_SNOOP", + "BriefDescription": "Counts prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts prefetch RFOs that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803c0120 ", + "MSRValue": "0x00803C0120", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs that hit in the L3 with no details on snoop-related information.", + "BriefDescription": "Counts prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003c0120 ", + "MSRValue": "0x01003C0120", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "BriefDescription": "Counts prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts prefetch RFOs that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003c0120 ", + "MSRValue": "0x02003C0120", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs that hit in the L3 with a snoop miss response.", + "BriefDescription": "Counts prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003c0120 ", + "MSRValue": "0x04003C0120", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "BriefDescription": "Counts prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0120 ", + "MSRValue": "0x10003C0120", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_PF_RFO & L3_HIT & SNOOP_HITM", + "BriefDescription": "Counts prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts prefetch RFOs that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0120 ", + "MSRValue": "0x3F803C0120", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs that hit in the L3.", + "BriefDescription": "Counts prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch code reads that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch code reads have any response type.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010240 ", + "MSRValue": "0x0000010240", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads that have any response type.", + "BriefDescription": "Counts all prefetch code reads have any response type.", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020240 ", + "MSRValue": "0x0080020240", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_PF_CODE_RD & SUPPLIER_NONE & SNOOP_NONE", + "BriefDescription": "Counts all prefetch code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020240 ", + "MSRValue": "0x0100020240", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_PF_CODE_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "BriefDescription": "Counts all prefetch code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020240 ", + "MSRValue": "0x0200020240", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_PF_CODE_RD & SUPPLIER_NONE & SNOOP_MISS", + "BriefDescription": "Counts all prefetch code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020240 ", + "MSRValue": "0x0400020240", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_PF_CODE_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts all prefetch code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020240 ", + "MSRValue": "0x1000020240", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_PF_CODE_RD & SUPPLIER_NONE & SNOOP_HITM", + "BriefDescription": "Counts all prefetch code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f80020240 ", + "MSRValue": "0x3F80020240", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_PF_CODE_RD & SUPPLIER_NONE & ANY_SNOOP", + "BriefDescription": "Counts all prefetch code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch code reads that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803c0240 ", + "MSRValue": "0x00803C0240", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads that hit in the L3 with no details on snoop-related information.", + "BriefDescription": "Counts all prefetch code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003c0240 ", + "MSRValue": "0x01003C0240", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "BriefDescription": "Counts all prefetch code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch code reads that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003c0240 ", + "MSRValue": "0x02003C0240", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads that hit in the L3 with a snoop miss response.", + "BriefDescription": "Counts all prefetch code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003c0240 ", + "MSRValue": "0x04003C0240", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "BriefDescription": "Counts all prefetch code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0240 ", + "MSRValue": "0x10003C0240", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_PF_CODE_RD & L3_HIT & SNOOP_HITM", + "BriefDescription": "Counts all prefetch code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all prefetch code reads that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0240 ", + "MSRValue": "0x3F803C0240", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads that hit in the L3.", + "BriefDescription": "Counts all prefetch code reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand & prefetch data reads that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch data reads have any response type.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010091 ", + "MSRValue": "0x0000010091", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads that have any response type.", + "BriefDescription": "Counts all demand & prefetch data reads have any response type.", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020091 ", + "MSRValue": "0x0080020091", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & SNOOP_NONE", + "BriefDescription": "Counts all demand & prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020091 ", + "MSRValue": "0x0100020091", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "BriefDescription": "Counts all demand & prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020091 ", + "MSRValue": "0x0200020091", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & SNOOP_MISS", + "BriefDescription": "Counts all demand & prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020091 ", + "MSRValue": "0x0400020091", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts all demand & prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020091 ", + "MSRValue": "0x1000020091", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & SNOOP_HITM", + "BriefDescription": "Counts all demand & prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f80020091 ", + "MSRValue": "0x3F80020091", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & ANY_SNOOP", + "BriefDescription": "Counts all demand & prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803c0091 ", + "MSRValue": "0x00803C0091", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 with no details on snoop-related information.", + "BriefDescription": "Counts all demand & prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003c0091 ", + "MSRValue": "0x01003C0091", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "BriefDescription": "Counts all demand & prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003c0091 ", + "MSRValue": "0x02003C0091", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 with a snoop miss response.", + "BriefDescription": "Counts all demand & prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003c0091 ", + "MSRValue": "0x04003C0091", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "BriefDescription": "Counts all demand & prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0091 ", + "MSRValue": "0x10003C0091", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_DATA_RD & L3_HIT & SNOOP_HITM", + "BriefDescription": "Counts all demand & prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0091 ", + "MSRValue": "0x3F803C0091", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3.", + "BriefDescription": "Counts all demand & prefetch data reads", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand & prefetch RFOs that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch RFOs have any response type.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010122 ", + "MSRValue": "0x0000010122", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs that have any response type.", + "BriefDescription": "Counts all demand & prefetch RFOs have any response type.", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020122 ", + "MSRValue": "0x0080020122", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_RFO & SUPPLIER_NONE & SNOOP_NONE", + "BriefDescription": "Counts all demand & prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020122 ", + "MSRValue": "0x0100020122", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_RFO & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "BriefDescription": "Counts all demand & prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020122 ", + "MSRValue": "0x0200020122", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_RFO & SUPPLIER_NONE & SNOOP_MISS", + "BriefDescription": "Counts all demand & prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020122 ", + "MSRValue": "0x0400020122", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_RFO & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts all demand & prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020122 ", + "MSRValue": "0x1000020122", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_RFO & SUPPLIER_NONE & SNOOP_HITM", + "BriefDescription": "Counts all demand & prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f80020122 ", + "MSRValue": "0x3F80020122", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_RFO & SUPPLIER_NONE & ANY_SNOOP", + "BriefDescription": "Counts all demand & prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803c0122 ", + "MSRValue": "0x00803C0122", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 with no details on snoop-related information.", + "BriefDescription": "Counts all demand & prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003c0122 ", + "MSRValue": "0x01003C0122", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "BriefDescription": "Counts all demand & prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003c0122 ", + "MSRValue": "0x02003C0122", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 with a snoop miss response.", + "BriefDescription": "Counts all demand & prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003c0122 ", + "MSRValue": "0x04003C0122", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "BriefDescription": "Counts all demand & prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0122 ", + "MSRValue": "0x10003C0122", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "ALL_RFO & L3_HIT & SNOOP_HITM", + "BriefDescription": "Counts all demand & prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch RFOs", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0122 ", + "MSRValue": "0x3F803C0122", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3.", + "BriefDescription": "Counts all demand & prefetch RFOs", "Offcore": "1", "CounterHTOff": "0,1,2,3" } |