diff options
Diffstat (limited to '')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/broadwell/memory.json | 4302 |
1 files changed, 2155 insertions, 2147 deletions
diff --git a/tools/perf/pmu-events/arch/x86/broadwell/memory.json b/tools/perf/pmu-events/arch/x86/broadwell/memory.json index b6b5247d3d5a..2a7797738159 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/memory.json @@ -1,3045 +1,3053 @@ [ { - "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", - "EventCode": "0x05", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MISALIGN_MEM_REF.LOADS", - "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", - "EventCode": "0x05", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MISALIGN_MEM_REF.STORES", - "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times a TSX line had a cache conflict.", - "EventCode": "0x54", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "TX_MEM.ABORT_CONFLICT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a TSX line had a cache conflict", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", - "EventCode": "0x54", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", - "EventCode": "0x54", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", - "EventCode": "0x54", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", - "EventCode": "0x54", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", - "EventCode": "0x54", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times we could not allocate Lock Buffer.", - "EventCode": "0x54", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times we could not allocate Lock Buffer", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "TX_EXEC.MISC1", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "TX_EXEC.MISC2", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "TX_EXEC.MISC3", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "RTM region detected inside HLE.", - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "TX_EXEC.MISC4", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "TX_EXEC.MISC5", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "SampleAfterValue": "100003", - "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", - "EventCode": "0xc8", + "BriefDescription": "Number of times HLE abort was triggered", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "HLE_RETIRED.START", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times HLE commit succeeded.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "HLE_RETIRED.COMMIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times HLE commit succeeded", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "PublicDescription": "Number of times HLE abort was triggered (PEBS).", - "EventCode": "0xc8", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "HLE_RETIRED.ABORTED", + "PEBS": "1", + "PublicDescription": "Number of times HLE abort was triggered.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times HLE abort was triggered (PEBS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).", - "EventCode": "0xc8", + "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3", - "UMask": "0x8", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC1", + "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.", - "EventCode": "0xc8", + "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions", "Counter": "0,1,2,3", - "UMask": "0x10", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC2", + "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "Number of times a disallowed operation caused an HLE abort.", - "EventCode": "0xc8", + "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions", "Counter": "0,1,2,3", - "UMask": "0x20", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC3", + "PublicDescription": "Number of times a disallowed operation caused an HLE abort.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "PublicDescription": "Number of times HLE caused a fault.", - "EventCode": "0xc8", + "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", "Counter": "0,1,2,3", - "UMask": "0x40", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC4", + "PublicDescription": "Number of times HLE caused a fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.", - "EventCode": "0xc8", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "HLE_RETIRED.ABORTED_MISC5", - "SampleAfterValue": "2000003", "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", - "EventCode": "0xc9", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RTM_RETIRED.START", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of times RTM commit succeeded.", - "EventCode": "0xc9", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "RTM_RETIRED.COMMIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times RTM commit succeeded", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "PublicDescription": "Number of times RTM abort was triggered (PEBS).", - "EventCode": "0xc9", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "RTM_RETIRED.ABORTED", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times RTM abort was triggered (PEBS)", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", - "EventCode": "0xc9", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "RTM_RETIRED.ABORTED_MISC1", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", - "EventCode": "0xc9", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "RTM_RETIRED.ABORTED_MISC2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", - "CounterHTOff": "0,1,2,3" + "UMask": "0x80" }, { - "PublicDescription": "Number of times a disallowed operation caused an RTM abort.", - "EventCode": "0xc9", + "BriefDescription": "Number of times HLE commit succeeded", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "RTM_RETIRED.ABORTED_MISC3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.COMMIT", + "PublicDescription": "Number of times HLE commit succeeded.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "PublicDescription": "Number of times a RTM caused a fault.", - "EventCode": "0xc9", + "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "RTM_RETIRED.ABORTED_MISC4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.START", + "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", - "EventCode": "0xc9", + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "RTM_RETIRED.ABORTED_MISC5", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency value being above four.", - "EventCode": "0xCD", - "MSRValue": "0x4", + "BriefDescription": "Randomly selected loads with latency value being above 128", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", - "SampleAfterValue": "100003", - "BriefDescription": "Randomly selected loads with latency value being above 4", + "MSRValue": "0x80", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above 128.", + "SampleAfterValue": "1009", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency value being above eight.", - "EventCode": "0xCD", - "MSRValue": "0x8", + "BriefDescription": "Randomly selected loads with latency value being above 16", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "MSRIndex": "0x3F6", - "SampleAfterValue": "50021", - "BriefDescription": "Randomly selected loads with latency value being above 8", + "MSRValue": "0x10", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above 16.", + "SampleAfterValue": "20011", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency value being above 16.", - "EventCode": "0xCD", - "MSRValue": "0x10", + "BriefDescription": "Randomly selected loads with latency value being above 256", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", - "SampleAfterValue": "20011", - "BriefDescription": "Randomly selected loads with latency value being above 16", + "MSRValue": "0x100", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above 256.", + "SampleAfterValue": "503", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency value being above 32.", - "EventCode": "0xCD", - "MSRValue": "0x20", + "BriefDescription": "Randomly selected loads with latency value being above 32", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above 32.", "SampleAfterValue": "100007", - "BriefDescription": "Randomly selected loads with latency value being above 32", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency value being above 64.", - "EventCode": "0xCD", - "MSRValue": "0x40", + "BriefDescription": "Randomly selected loads with latency value being above 4", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "MSRIndex": "0x3F6", - "SampleAfterValue": "2003", - "BriefDescription": "Randomly selected loads with latency value being above 64", + "MSRValue": "0x4", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above four.", + "SampleAfterValue": "100003", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency value being above 128.", - "EventCode": "0xCD", - "MSRValue": "0x80", + "BriefDescription": "Randomly selected loads with latency value being above 512", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", - "SampleAfterValue": "1009", - "BriefDescription": "Randomly selected loads with latency value being above 128", + "MSRValue": "0x200", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above 512.", + "SampleAfterValue": "101", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency value being above 256.", - "EventCode": "0xCD", - "MSRValue": "0x100", + "BriefDescription": "Randomly selected loads with latency value being above 64", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "MSRIndex": "0x3F6", - "SampleAfterValue": "503", - "BriefDescription": "Randomly selected loads with latency value being above 256", + "MSRValue": "0x40", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above 64.", + "SampleAfterValue": "2003", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency value being above 512.", - "EventCode": "0xCD", - "MSRValue": "0x200", + "BriefDescription": "Randomly selected loads with latency value being above 8", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "MSRIndex": "0x3F6", - "SampleAfterValue": "101", - "BriefDescription": "Randomly selected loads with latency value being above 512", + "MSRValue": "0x8", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above eight.", + "SampleAfterValue": "50021", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2000020001", + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.LOADS", + "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - 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"EventCode": "0xB7, 0xBB", - "MSRValue": "0x0204000240", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00BC000200", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0404000240", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", - 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"PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x023C000091", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2004000080", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x043C000091", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0104000080", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2000020122", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000020080", "Offcore": "1", - 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"MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x023C000100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0204000122", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00BC000100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0404000122", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x013C000100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1004000122", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F84000100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2004000122", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1004000100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F84000122", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0404000100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00BC000122", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0204000100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x013C000122", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0084000100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x023C000122", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2004000100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x043C000122", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0104000100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000020100", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of times RTM abort was triggered", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED", + "PEBS": "1", + "PublicDescription": "Number of times RTM abort was triggered .", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC1", + "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC2", + "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC3", + "PublicDescription": "Number of times a disallowed operation caused an RTM abort.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC4", + "PublicDescription": "Number of times a RTM caused a fault.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of times RTM commit succeeded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.COMMIT", + "PublicDescription": "Number of times RTM commit succeeded.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.START", + "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC2", + "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC3", + "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC4", + "PublicDescription": "RTM region detected inside HLE.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC5", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of times a TSX line had a cache conflict", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CONFLICT", + "PublicDescription": "Number of times a TSX line had a cache conflict.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", + "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times we could not allocate Lock Buffer", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "PublicDescription": "Number of times we could not allocate Lock Buffer.", + "SampleAfterValue": "2000003", + "UMask": "0x40" } -]
\ No newline at end of file +] |