diff options
Diffstat (limited to '')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/broadwellde/memory.json | 610 |
1 files changed, 305 insertions, 305 deletions
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/memory.json b/tools/perf/pmu-events/arch/x86/broadwellde/memory.json index e44f73c24ac8..a3a5cc6dab42 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/memory.json @@ -1,432 +1,432 @@ [ { - "EventCode": "0x05", - "UMask": "0x1", - "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", + "BriefDescription": "Number of times HLE abort was triggered (PEBS)", "Counter": "0,1,2,3", - "EventName": "MISALIGN_MEM_REF.LOADS", - "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED", + "PEBS": "1", + "PublicDescription": "Number of times HLE abort was triggered (PEBS).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x05", - "UMask": "0x2", - "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", + "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3", - "EventName": "MISALIGN_MEM_REF.STORES", - "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC1", + "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x54", - "UMask": "0x1", - "BriefDescription": "Number of times a TSX line had a cache conflict", + "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_CONFLICT", - "PublicDescription": "Number of times a TSX line had a cache conflict.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC2", + "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x54", - "UMask": "0x2", - "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", + "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", - "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC3", + "PublicDescription": "Number of times a disallowed operation caused an HLE abort.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x54", - "UMask": "0x4", - "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", + "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", - "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC4", + "PublicDescription": "Number of times HLE caused a fault.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x54", - "UMask": "0x8", - "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", + "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", - "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "EventCode": "0x54", - "UMask": "0x10", - "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", + "BriefDescription": "Number of times HLE commit succeeded", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", - "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.COMMIT", + "PublicDescription": "Number of times HLE commit succeeded.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x54", - "UMask": "0x20", - "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", + "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", - "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.START", + "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x54", - "UMask": "0x40", - "BriefDescription": "Number of times we could not allocate Lock Buffer", + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", "Counter": "0,1,2,3", - "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", - "PublicDescription": "Number of times we could not allocate Lock Buffer.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x5d", - "UMask": "0x1", - "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Loads with latency value being above 128", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above 128.", + "SampleAfterValue": "1009", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0x5d", - "UMask": "0x2", - "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC2", - "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Loads with latency value being above 16", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above 16.", + "SampleAfterValue": "20011", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0x5d", - "UMask": "0x4", - "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC3", - "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Loads with latency value being above 256", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above 256.", + "SampleAfterValue": "503", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0x5d", - "UMask": "0x8", - "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC4", - "PublicDescription": "RTM region detected inside HLE.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Loads with latency value being above 32", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above 32.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0x5d", - "UMask": "0x10", - "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC5", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Loads with latency value being above 4", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above four.", + "SampleAfterValue": "100003", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xC3", - "UMask": "0x2", - "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", - "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Loads with latency value being above 512", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above 512.", + "SampleAfterValue": "101", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xc8", - "UMask": "0x1", - "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", - "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.START", - "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Loads with latency value being above 64", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above 64.", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xc8", - "UMask": "0x2", - "BriefDescription": "Number of times HLE commit succeeded", + "BriefDescription": "Loads with latency value being above 8", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above eight.", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.COMMIT", - "PublicDescription": "Number of times HLE commit succeeded.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.LOADS", + "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xc8", - "UMask": "0x4", - "BriefDescription": "Number of times HLE abort was triggered (PEBS)", - "PEBS": "1", + "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED", - "PublicDescription": "Number of times HLE abort was triggered (PEBS).", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.STORES", + "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xc8", - "UMask": "0x8", - "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "BriefDescription": "Number of times RTM abort was triggered (PEBS)", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED_MISC1", - "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED", + "PEBS": "1", + "PublicDescription": "Number of times RTM abort was triggered (PEBS).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xc8", - "UMask": "0x10", - "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions", + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED_MISC2", - "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC1", + "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xc8", - "UMask": "0x20", - "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions", + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED_MISC3", - "PublicDescription": "Number of times a disallowed operation caused an HLE abort.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC2", + "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xc8", - "UMask": "0x40", - "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED_MISC4", - "PublicDescription": "Number of times HLE caused a fault.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC3", + "PublicDescription": "Number of times a disallowed operation caused an RTM abort.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xc8", - "UMask": "0x80", - "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", + "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED_MISC5", - "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC4", + "PublicDescription": "Number of times a RTM caused a fault.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0xc9", - "UMask": "0x1", - "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", + "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.START", - "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x80" }, { - "EventCode": "0xc9", - "UMask": "0x2", "BriefDescription": "Number of times RTM commit succeeded", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", "EventName": "RTM_RETIRED.COMMIT", "PublicDescription": "Number of times RTM commit succeeded.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xc9", - "UMask": "0x4", - "BriefDescription": "Number of times RTM abort was triggered (PEBS)", - "PEBS": "1", + "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED", - "PublicDescription": "Number of times RTM abort was triggered (PEBS).", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.START", + "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xc9", - "UMask": "0x8", - "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", + "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC1", - "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xc9", - "UMask": "0x10", - "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC2", - "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC2", + "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xc9", - "UMask": "0x20", - "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", + "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC3", - "PublicDescription": "Number of times a disallowed operation caused an RTM abort.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC3", + "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xc9", - "UMask": "0x40", - "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", + "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC4", - "PublicDescription": "Number of times a RTM caused a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC4", + "PublicDescription": "RTM region detected inside HLE.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "EventCode": "0xc9", - "UMask": "0x80", - "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", + "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC5", - "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC5", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 4", - "PEBS": "2", - "MSRValue": "0x4", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value being above four.", - "TakenAlone": "1", - "SampleAfterValue": "100003", - "CounterHTOff": "3" + "UMask": "0x10" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 8", - "PEBS": "2", - "MSRValue": "0x8", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value being above eight.", - "TakenAlone": "1", - "SampleAfterValue": "50021", - "CounterHTOff": "3" + "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 16", - "PEBS": "2", - "MSRValue": "0x10", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value being above 16.", - "TakenAlone": "1", - "SampleAfterValue": "20011", - "CounterHTOff": "3" + "BriefDescription": "Number of times a TSX line had a cache conflict", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CONFLICT", + "PublicDescription": "Number of times a TSX line had a cache conflict.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 32", - "PEBS": "2", - "MSRValue": "0x20", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value being above 32.", - "TakenAlone": "1", - "SampleAfterValue": "100007", - "CounterHTOff": "3" + "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 64", - "PEBS": "2", - "MSRValue": "0x40", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value being above 64.", - "TakenAlone": "1", - "SampleAfterValue": "2003", - "CounterHTOff": "3" + "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 128", - "PEBS": "2", - "MSRValue": "0x80", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value being above 128.", - "TakenAlone": "1", - "SampleAfterValue": "1009", - "CounterHTOff": "3" + "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", + "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 256", - "PEBS": "2", - "MSRValue": "0x100", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value being above 256.", - "TakenAlone": "1", - "SampleAfterValue": "503", - "CounterHTOff": "3" + "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 512", - "PEBS": "2", - "MSRValue": "0x200", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value being above 512.", - "TakenAlone": "1", - "SampleAfterValue": "101", - "CounterHTOff": "3" + "BriefDescription": "Number of times we could not allocate Lock Buffer", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "PublicDescription": "Number of times we could not allocate Lock Buffer.", + "SampleAfterValue": "2000003", + "UMask": "0x40" } -]
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