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Diffstat (limited to '')
13 files changed, 14836 insertions, 2823 deletions
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json b/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json index 1eb0415fa11a..e89fa536ca03 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json @@ -1,331 +1,937 @@ [ { "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)", - "MetricGroup": "TopdownL1", - "MetricName": "Frontend_Bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", + "MetricGroup": "PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", + "ScaleUnit": "100%" }, { - "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", - "MetricGroup": "TopdownL1_SMT", - "MetricName": "Frontend_Bound_SMT", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", + "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS", + "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", + "MetricExpr": "ICACHE.IFDATA_STALL / CLKS", + "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", + "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ITLB_MISSES.WALK_COMPLETED) / CLKS", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", + "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / CLKS", + "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", + "MetricName": "tma_branch_resteers", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)", + "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group", + "MetricName": "tma_mispredicts_resteers", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ", + "MetricExpr": "MACHINE_CLEARS.COUNT * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)", + "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group", + "MetricName": "tma_clears_resteers", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", + "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers", + "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_branch_resteers_group", + "MetricName": "tma_unknown_branches", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: BACLEARS.ANY", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group", + "MetricName": "tma_dsb_switches", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", + "MetricExpr": "ILD_STALL.LCP / CLKS", + "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", + "MetricName": "tma_lcp", + "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", + "MetricExpr": "2 * IDQ.MS_SWITCHES / CLKS", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group", + "MetricName": "tma_ms_switches", + "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", + "MetricExpr": "tma_frontend_bound - tma_fetch_latency", + "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_bandwidth", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", + "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group", + "MetricName": "tma_mite", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", + "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2", + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group", + "MetricName": "tma_dsb", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "ScaleUnit": "100%" }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)", - "MetricGroup": "TopdownL1", - "MetricName": "Bad_Speculation", - "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example." + "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_bad_speculation", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", + "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation", + "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group", + "MetricName": "tma_branch_mispredicts", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "ScaleUnit": "100%" }, { - "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", - "MetricGroup": "TopdownL1_SMT", - "MetricName": "Bad_Speculation_SMT", - "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU." + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", + "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", + "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group", + "MetricName": "tma_machine_clears", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT", + "ScaleUnit": "100%" }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )", - "MetricGroup": "TopdownL1", - "MetricName": "Backend_Bound", - "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound." + "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", + "MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound", + "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", + "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CLKS, 0)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", + "MetricName": "tma_l1_bound", + "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS;MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", + "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * DTLB_LOAD_MISSES.WALK_COMPLETED) / CLKS", + "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group", + "MetricName": "tma_dtlb_load", + "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", + "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS", + "MetricGroup": "TopdownL4;tma_l1_bound_group", + "MetricName": "tma_store_fwd_blk", + "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", + "MetricExpr": "(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS", + "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group", + "MetricName": "tma_lock_latency", + "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", + "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS", + "MetricGroup": "TopdownL4;tma_l1_bound_group", + "MetricName": "tma_split_loads", + "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", + "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS", + "MetricGroup": "TopdownL4;tma_l1_bound_group", + "MetricName": "tma_4k_aliasing", + "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", + "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / CLKS", + "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group", + "MetricName": "tma_fb_full", + "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", + "MetricName": "tma_l2_bound", + "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", + "MetricExpr": "(MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", + "MetricName": "tma_l3_bound", + "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", + "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CLKS", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group", + "MetricName": "tma_contested_accesses", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", + "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS", + "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group", + "MetricName": "tma_data_sharing", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", + "MetricExpr": "41 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS", + "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group", + "MetricName": "tma_l3_hit_latency", + "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", + "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group", + "MetricName": "tma_sq_full", + "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", + "MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS))) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", + "MetricName": "tma_dram_bound", + "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / CLKS", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group", + "MetricName": "tma_mem_bandwidth", + "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group", + "MetricName": "tma_mem_latency", + "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory", + "MetricExpr": "200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS", + "MetricGroup": "Server;TopdownL5;tma_mem_latency_group", + "MetricName": "tma_local_dram", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory", + "MetricExpr": "310 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS", + "MetricGroup": "Server;Snoop;TopdownL5;tma_mem_latency_group", + "MetricName": "tma_remote_dram", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues", + "MetricExpr": "(200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CLKS", + "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_mem_latency_group", + "MetricName": "tma_remote_cache", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", + "MetricExpr": "RESOURCE_STALLS.SB / CLKS", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", + "MetricName": "tma_store_bound", + "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", + "MetricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES))) + (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group", + "MetricName": "tma_store_latency", + "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", + "MetricExpr": "(200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / CLKS", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group", + "MetricName": "tma_false_sharing", + "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents rate of split store accesses", + "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / CORE_CLKS", + "MetricGroup": "TopdownL4;tma_store_bound_group", + "MetricName": "tma_split_stores", + "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_UOPS_RETIRED.SPLIT_STORES_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", + "MetricExpr": "(8 * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * DTLB_STORE_MISSES.WALK_COMPLETED) / CLKS", + "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group", + "MetricName": "tma_dtlb_store", + "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", + "MetricExpr": "tma_backend_bound - tma_memory_bound", + "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", + "MetricExpr": "ARITH.FPU_DIV_ACTIVE / CORE_CLKS", + "MetricGroup": "TopdownL3;tma_core_bound_group", + "MetricName": "tma_divider", + "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", + "MetricExpr": "((CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS", + "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@) / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else 0) / CORE_CLKS", + "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_0", + "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS", + "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_1", + "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", + "ScaleUnit": "100%" }, { - "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )", - "MetricGroup": "TopdownL1_SMT", - "MetricName": "Backend_Bound_SMT", - "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU." + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS", + "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_2", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", + "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS", + "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_3m", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 * CORE_CLKS)", + "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", + "MetricName": "tma_alu_op_utilization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED_PORT.PORT_0", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS", + "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group", + "MetricName": "tma_port_0", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_1", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS", + "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", + "MetricName": "tma_port_1", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) Sample with: UOPS_DISPATCHED.PORT_5", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS", + "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", + "MetricName": "tma_port_5", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_6", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS", + "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", + "MetricName": "tma_port_6", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)", + "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", + "MetricName": "tma_load_op_utilization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_2", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS", + "MetricGroup": "TopdownL6;tma_load_op_utilization_group", + "MetricName": "tma_port_2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_3", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS", + "MetricGroup": "TopdownL6;tma_load_op_utilization_group", + "MetricName": "tma_port_3", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS", + "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", + "MetricName": "tma_store_op_utilization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data) Sample with: UOPS_DISPATCHED_PORT.PORT_4", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS", + "MetricGroup": "TopdownL6;tma_store_op_utilization_group", + "MetricName": "tma_port_4", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address) Sample with: UOPS_DISPATCHED_PORT.PORT_7", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS", + "MetricGroup": "TopdownL6;tma_store_op_utilization_group", + "MetricName": "tma_port_7", + "ScaleUnit": "100%" }, { "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)", - "MetricGroup": "TopdownL1", - "MetricName": "Retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. " + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", + "ScaleUnit": "100%" }, { - "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", - "MetricGroup": "TopdownL1_SMT", - "MetricName": "Retiring_SMT", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. SMT version; use when SMT is enabled and measuring per logical CPU." + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", + "MetricExpr": "tma_retiring - tma_heavy_operations", + "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_light_operations", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions Per Cycle (per Logical Processor)", - "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopDownL1", - "MetricName": "IPC" + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", + "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", + "MetricGroup": "HPC;TopdownL3;tma_light_operations_group", + "MetricName": "tma_fp_arith", + "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", - "MetricName": "UPI" + "BriefDescription": "This metric serves as an approximation of legacy x87 usage", + "MetricExpr": "INST_RETIRED.X87 * UPI / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group", + "MetricName": "tma_x87_use", + "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fetch_BW;PGO", - "MetricName": "IpTB" + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", + "MetricName": "tma_fp_scalar", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;PGO", - "MetricName": "BpTB" + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", + "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", + "MetricName": "tma_fp_vector", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely (includes speculatively fetches) consumed by program instructions", - "MetricExpr": "min( 1 , IDQ.MITE_UOPS / ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )", - "MetricGroup": "PGO;IcMiss", - "MetricName": "IFetch_Line_Utilization" + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group", + "MetricName": "tma_fp_vector_128b", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", - "MetricGroup": "DSB;Fetch_BW", - "MetricName": "DSB_Coverage" + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group", + "MetricName": "tma_fp_vector_256b", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences", + "MetricExpr": "tma_microcode_sequencer", + "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_heavy_operations", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS", + "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group", + "MetricName": "tma_microcode_sequencer", + "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", + "MetricExpr": "100 * OTHER_ASSISTS.ANY_WB_ASSIST / SLOTS", + "MetricGroup": "TopdownL4;tma_microcode_sequencer_group", + "MetricName": "tma_assists", + "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", + "MetricGroup": "TopdownL4;tma_microcode_sequencer_group", + "MetricName": "tma_cisc", + "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / CLKS", + "MetricGroup": "Ret;Summary", + "MetricName": "IPC" + }, + { + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "UPI" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / (INST_RETIRED.ANY / cycles)", - "MetricGroup": "Pipeline;Summary", + "MetricExpr": "1 / IPC", + "MetricGroup": "Mem;Pipeline", "MetricName": "CPI" }, { "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core)", - "MetricExpr": "4 * cycles", - "MetricGroup": "TopDownL1", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CORE_CLKS", + "MetricGroup": "tma_L1_group", "MetricName": "SLOTS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core)", - "MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "TopDownL1_SMT", - "MetricName": "SLOTS_SMT" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." + }, + { + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS", + "MetricGroup": "Ret;SMT;tma_L1_group", + "MetricName": "CoreIPC" + }, + { + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS", + "MetricGroup": "Flops;Ret", + "MetricName": "FLOPc" + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", + "MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "FP_Arith_Utilization", + "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." + }, + { + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", + "MetricExpr": "UOPS_EXECUTED.THREAD / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", + "MetricName": "ILP" }, { - "BriefDescription": "Instructions per Load (lower number means higher occurance rate)", + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS", + "MetricGroup": "SMT", + "MetricName": "CORE_CLKS" + }, + { + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricGroup": "Instruction_Type", - "MetricName": "IpL" + "MetricGroup": "InsType", + "MetricName": "IpLoad" }, { - "BriefDescription": "Instructions per Store (lower number means higher occurance rate)", + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricGroup": "Instruction_Type", - "MetricName": "IpS" + "MetricGroup": "InsType", + "MetricName": "IpStore" }, { - "BriefDescription": "Instructions per Branch (lower number means higher occurance rate)", + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Instruction_Type", - "MetricName": "IpB" + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "IpBranch" }, { - "BriefDescription": "Instruction per (near) call (lower number means higher occurance rate)", + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "IpCall" }, { - "BriefDescription": "Total number of retired Instructions", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary", - "MetricName": "Instructions" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / cycles", - "MetricGroup": "SMT", - "MetricName": "CoreIPC" + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "BpTkBranch" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "SMT", - "MetricName": "CoreIPC_SMT" + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", + "MetricGroup": "Flops;InsType", + "MetricName": "IpFLOP" }, { - "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) / cycles", - "MetricGroup": "FLOPS", - "MetricName": "FLOPc" + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." }, { - "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "FLOPS_SMT", - "MetricName": "FLOPc_SMT" + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_SP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)", - "MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", - "MetricGroup": "Pipeline", - "MetricName": "ILP" + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_DP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TopDown slots wasted per non-speculative branch misprediction (jeclear)", - "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * cycles)) * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / cycles) / (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * cycles)) ) * (4 * cycles) / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", - "MetricName": "Branch_Misprediction_Cost" + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX128", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX256", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;tma_L1_group", + "MetricName": "Instructions" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TopDown slots wasted per non-speculative branch misprediction (jeclear)", - "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / cycles) / (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts_SMT", - "MetricName": "Branch_Misprediction_Cost_SMT" + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "Retire" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", + "BriefDescription": "", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "Execute" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))", + "MetricGroup": "DSB;Fed;FetchBW", + "MetricName": "DSB_Coverage" + }, + { + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { - "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", - "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", - "MetricGroup": "SMT", - "MetricName": "CORE_CLKS" + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "Branch_Misprediction_Cost" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )", - "MetricGroup": "Memory_Bound;Memory_Lat", + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb)", + "MetricGroup": "Mem;MemoryBound;MemoryLat", "MetricName": "Load_Miss_Real_Latency" }, { "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "Memory_Bound;Memory_BW", + "MetricGroup": "Mem;MemoryBW;MemoryBound", "MetricName": "MLP" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * cycles )", - "MetricGroup": "TLB", - "MetricName": "Page_Walks_Utilization" + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "L1MPKI" + }, + { + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Backend;CacheMisses;Mem", + "MetricName": "L2MPKI" + }, + { + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem;Offcore", + "MetricName": "L2MPKI_All" + }, + { + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "L2MPKI_Load" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "L2HPKI_All" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "L2HPKI_Load" + }, + { + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "L3MPKI" }, { "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) )", - "MetricGroup": "TLB_SMT", - "MetricName": "Page_Walks_Utilization_SMT" + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * (DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED)) / (2 * CORE_CLKS)", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" }, { - "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]", + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { - "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]", + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L1MPKI" + "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "L1D_Cache_Fill_BW", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW_1T" }, { - "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L2MPKI" - }, - { - "BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)", - "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L2MPKI_All" + "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "L2_Cache_Fill_BW", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW_1T" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", - "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L2HPKI_All" + "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "L3_Cache_Fill_BW", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW_1T" }, { - "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L3MPKI" + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "0", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "L3_Cache_Access_BW_1T" }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", - "MetricGroup": "Summary", + "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, { + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time", + "MetricGroup": "Power;Summary", + "MetricName": "Average_Frequency" + }, + { "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "( (( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) / 1000000000 ) / duration_time", - "MetricGroup": "FLOPS;Summary", - "MetricName": "GFLOPs" + "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1000000000) / duration_time", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "GFLOPs", + "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." }, { "BriefDescription": "Average Frequency Utilization relative nominal frequency", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC", + "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", "MetricGroup": "Power", "MetricName": "Turbo_Utilization" }, { "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", - "MetricGroup": "SMT;Summary", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0", + "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, { + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, + { "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", - "MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) / 1000000000 ) / duration_time", - "MetricGroup": "Memory_BW", + "MetricExpr": "(64 * (uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@) / 1000000000) / duration_time", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, { "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches", - "MetricExpr": "1000000000 * ( cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x35\\,umask\\=0x3\\,filter_opc\\=0x182@ ) / ( cbox_0@event\\=0x0@ / duration_time )", - "MetricGroup": "Memory_Lat", - "MetricName": "DRAM_Read_Latency" + "MetricExpr": "1000000000 * (cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x35\\,umask\\=0x3\\,filter_opc\\=0x182@) / (Socket_CLKS / duration_time)", + "MetricGroup": "Mem;MemoryLat;SoC", + "MetricName": "MEM_Read_Latency" }, { "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", "MetricExpr": "cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182\\,thresh\\=1@", - "MetricGroup": "Memory_BW", - "MetricName": "DRAM_Parallel_Reads" + "MetricGroup": "Mem;MemoryBW;SoC", + "MetricName": "MEM_Parallel_Reads" }, { "BriefDescription": "Socket actual clocks when any core is active on that socket", "MetricExpr": "cbox_0@event\\=0x0@", - "MetricGroup": "", + "MetricGroup": "SoC", "MetricName": "Socket_CLKS" }, { + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "IpFarBranch" + }, + { "BriefDescription": "C3 residency percent per core", "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", @@ -366,5 +972,235 @@ "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C7_Pkg_Residency" + }, + { + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" + }, + { + "BriefDescription": "CPU operating frequency (in GHz)", + "MetricExpr": "(( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ ) / 1000000000) / duration_time", + "MetricGroup": "", + "MetricName": "cpu_operating_frequency", + "ScaleUnit": "1GHz" + }, + { + "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions", + "MetricExpr": "MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "loads_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions", + "MetricExpr": "MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "stores_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions", + "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1d_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions", + "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L1_HIT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1d_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions", + "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions", + "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_HIT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions", + "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions", + "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_data_read_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions", + "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_code_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x192@ ) / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x181@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x191@ ) / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds", + "MetricExpr": "( 1000000000 * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ ) / ( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time", + "MetricGroup": "", + "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds", + "MetricExpr": "( 1000000000 * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ ) / ( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time", + "MetricGroup": "", + "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds", + "MetricExpr": "( 1000000000 * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ ) / ( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time", + "MetricGroup": "", + "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "itlb_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "itlb_large_page_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "dtlb_load_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "dtlb_store_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "MetricExpr": "100 * cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / ( cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ )", + "MetricGroup": "", + "MetricName": "numa_reads_addressed_to_local_dram", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "MetricExpr": "100 * cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / ( cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ )", + "MetricGroup": "", + "MetricName": "numa_reads_addressed_to_remote_dram", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uncore operating frequency in GHz", + "MetricExpr": "( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) / 1000000000) / duration_time", + "MetricGroup": "", + "MetricName": "uncore_frequency", + "ScaleUnit": "1GHz" + }, + { + "BriefDescription": "Intel(R) Quick Path Interconnect (QPI) data transmit bandwidth (MB/sec)", + "MetricExpr": "( UNC_Q_TxL_FLITS_G0.DATA * 8 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "qpi_data_transmit_bw", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory read bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory write bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory bandwidth (MB/sec)", + "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "memory_bandwidth_total", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", + "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x19e@ * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "io_bandwidth_disk_or_network_writes", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "MetricExpr": "(( cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x1c8\\,filter_tid\\=0x3e@ + cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x180\\,filter_tid\\=0x3e@ ) * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "io_bandwidth_disk_or_network_reads", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "100 * ( IDQ.DSB_UOPS / UOPS_ISSUED.ANY )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_decoded_icache", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "100 * ( IDQ.MITE_UOPS / UOPS_ISSUED.ANY )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "100 * ( IDQ.MS_UOPS / UOPS_ISSUED.ANY )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_microcode_sequencer", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uops delivered from loop stream detector(LSD) as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "100 * ( LSD.UOPS / UOPS_ISSUED.ANY )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_loop_stream_detector", + "ScaleUnit": "1%" } ] diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/cache.json b/tools/perf/pmu-events/arch/x86/broadwellx/cache.json index 75a3098d5775..2efc4c0ee740 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/cache.json @@ -1,966 +1,964 @@ [ { - "EventCode": "0x24", - "UMask": "0x21", - "BriefDescription": "Demand Data Read miss L2, no rejects", + "BriefDescription": "L1D data line replacements", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", - "PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.REPLACEMENT", + "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x24", - "UMask": "0x22", - "BriefDescription": "RFO requests that miss L2 cache.", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.RFO_MISS", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x24", - "UMask": "0x24", - "BriefDescription": "L2 cache misses when fetching instructions.", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.CODE_RD_MISS", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "L1D miss oustandings duration in cycles", + "Counter": "2", + "CounterHTOff": "2", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", + "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x24", - "UMask": "0x27", - "BriefDescription": "Demand requests that miss L2 cache.", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "PublicDescription": "This event counts duration of L1D miss outstanding in cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Not rejected writebacks that hit L2 cache", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_DEMAND_RQSTS.WB_HIT", + "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x50" }, { - "EventCode": "0x24", - "UMask": "0x30", - "BriefDescription": "L2 prefetch requests that miss L2 cache", + "BriefDescription": "L2 cache lines filling L2", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.L2_PF_MISS", - "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.ALL", + "PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x7" }, { - "EventCode": "0x24", - "UMask": "0x3f", - "BriefDescription": "All requests that miss L2 cache.", + "BriefDescription": "L2 cache lines in E state filling L2", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.MISS", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.E", + "PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0x24", - "UMask": "0xc1", - "BriefDescription": "Demand Data Read requests that hit L2 cache", + "BriefDescription": "L2 cache lines in I state filling L2", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.I", + "PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x24", - "UMask": "0xc2", - "BriefDescription": "RFO requests that hit L2 cache.", + "BriefDescription": "L2 cache lines in S state filling L2", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.RFO_HIT", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.S", + "PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x24", - "UMask": "0xc4", - "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "BriefDescription": "Clean L2 cache lines evicted by demand.", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.CODE_RD_HIT", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "SampleAfterValue": "100003", + "UMask": "0x5" }, { - "EventCode": "0x24", - "UMask": "0xd0", - "BriefDescription": "L2 prefetch requests that hit L2 cache", + "BriefDescription": "L2 code requests", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.L2_PF_HIT", - "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PublicDescription": "This event counts the total number of L2 code requests.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe4" }, { - "EventCode": "0x24", - "UMask": "0xe1", "BriefDescription": "Demand Data Read requests", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe1" }, { - "EventCode": "0x24", - "UMask": "0xe2", - "BriefDescription": "RFO requests to L2 cache", + "BriefDescription": "Demand requests that miss L2 cache.", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_RFO", - "PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", - "UMask": "0xe4", - "BriefDescription": "L2 code requests", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_CODE_RD", - "PublicDescription": "This event counts the total number of L2 code requests.", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x27" }, { - "EventCode": "0x24", - "UMask": "0xe7", "BriefDescription": "Demand requests to L2 cache.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe7" }, { - "EventCode": "0x24", - "UMask": "0xf8", "BriefDescription": "Requests from L2 hardware prefetchers", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_PF", "PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xf8" }, { - "EventCode": "0x24", - "UMask": "0xff", - "BriefDescription": "All L2 requests.", + "BriefDescription": "RFO requests to L2 cache", "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.REFERENCES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe2" }, { - "EventCode": "0x27", - "UMask": "0x50", - "BriefDescription": "Not rejected writebacks that hit L2 cache", + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", "Counter": "0,1,2,3", - "EventName": "L2_DEMAND_RQSTS.WB_HIT", - "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc4" }, { - "EventCode": "0x2E", - "UMask": "0x41", - "BriefDescription": "Core-originated cacheable demand requests missed L3", + "BriefDescription": "L2 cache misses when fetching instructions.", "Counter": "0,1,2,3", - "EventName": "LONGEST_LAT_CACHE.MISS", - "PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "SampleAfterValue": "200003", + "UMask": "0x24" }, { - "EventCode": "0x2E", - "UMask": "0x4f", - "BriefDescription": "Core-originated cacheable demand requests that refer to L3", + "BriefDescription": "Demand Data Read requests that hit L2 cache", "Counter": "0,1,2,3", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "EventCode": "0x48", - "UMask": "0x1", - "BriefDescription": "L1D miss oustandings duration in cycles", - "Counter": "2", - "EventName": "L1D_PEND_MISS.PENDING", - "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" + "BriefDescription": "Demand Data Read miss L2, no rejects", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", + "SampleAfterValue": "200003", + "UMask": "0x21" }, { - "EventCode": "0x48", - "UMask": "0x1", - "BriefDescription": "Cycles with L1D load Misses outstanding.", - "Counter": "2", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts duration of L1D miss outstanding in cycles.", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" + "BriefDescription": "L2 prefetch requests that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.L2_PF_HIT", + "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", + "SampleAfterValue": "200003", + "UMask": "0xd0" }, { - "EventCode": "0x48", - "UMask": "0x1", - "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", - "Counter": "2", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", - "AnyThread": "1", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" + "BriefDescription": "L2 prefetch requests that miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.L2_PF_MISS", + "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x30" }, { - "EventCode": "0x48", - "UMask": "0x2", - "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "BriefDescription": "All requests that miss L2 cache.", "Counter": "0,1,2,3", - "EventName": "L1D_PEND_MISS.FB_FULL", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.MISS", + "SampleAfterValue": "200003", + "UMask": "0x3f" }, { - "EventCode": "0x51", - "UMask": "0x1", - "BriefDescription": "L1D data line replacements", + "BriefDescription": "All L2 requests.", "Counter": "0,1,2,3", - "EventName": "L1D.REPLACEMENT", - "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.REFERENCES", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "EventCode": "0x60", - "UMask": "0x1", - "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "BriefDescription": "RFO requests that hit L2 cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is counted from the promotion point.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200003", + "UMask": "0xc2" }, { - "EventCode": "0x60", - "UMask": "0x1", - "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "BriefDescription": "RFO requests that miss L2 cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", - "CounterMask": "1", - "Errata": "BDM76", - "PublicDescription": "This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200003", + "UMask": "0x22" }, { - "EventCode": "0x60", - "UMask": "0x1", - "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", - "CounterMask": "6", - "Errata": "BDM76", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_PF", + "PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.", + "SampleAfterValue": "200003", + "UMask": "0x8" }, { - "EventCode": "0x60", - "UMask": "0x2", - "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "BriefDescription": "Transactions accessing L2 pipe", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_REQUESTS", + "PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.", + "SampleAfterValue": "200003", + "UMask": "0x80" }, { - "EventCode": "0x60", - "UMask": "0x4", - "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", + "BriefDescription": "L2 cache accesses when fetching instructions", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.CODE_RD", + "PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.", + "SampleAfterValue": "200003", + "UMask": "0x4" }, { - "EventCode": "0x60", - "UMask": "0x4", - "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "BriefDescription": "Demand Data Read requests that access L2 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", - "CounterMask": "1", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "EventCode": "0x60", - "UMask": "0x8", - "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", + "BriefDescription": "L1D writebacks that access L2 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L1D_WB", + "PublicDescription": "This event counts L1D writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x10" }, { - "EventCode": "0x60", - "UMask": "0x8", - "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "BriefDescription": "L2 fill requests that access L2 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", - "CounterMask": "1", - "Errata": "BDM76", - "PublicDescription": "This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_FILL", + "PublicDescription": "This event counts L2 fill requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x20" }, { - "EventCode": "0x63", - "UMask": "0x2", - "BriefDescription": "Cycles when L1D is locked", + "BriefDescription": "L2 writebacks that access L2 cache", "Counter": "0,1,2,3", - "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", - "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "This event counts L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x40" }, { - "EventCode": "0xB0", - "UMask": "0x1", - "BriefDescription": "Demand Data Read requests sent to uncore", + "BriefDescription": "RFO requests that access L2 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", - "PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.RFO", + "PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { - "EventCode": "0xB0", - "UMask": "0x2", - "BriefDescription": "Cacheable and noncachaeble code read requests", + "BriefDescription": "Cycles when L1D is locked", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0xB0", - "UMask": "0x4", - "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "BriefDescription": "Core-originated cacheable demand requests missed L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", - "PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x41" }, { - "EventCode": "0xB0", - "UMask": "0x8", - "BriefDescription": "Demand and prefetch data reads", + "BriefDescription": "Core-originated cacheable demand requests that refer to L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", - "PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4f" }, { - "EventCode": "0xb2", - "UMask": "0x1", - "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", + "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", - "PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.", + "SampleAfterValue": "20011", + "UMask": "0x2" }, { - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).", + "SampleAfterValue": "20011", + "UMask": "0x4" }, { - "EventCode": "0xD0", - "UMask": "0x11", - "BriefDescription": "Retired load uops that miss the STLB.", + "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", - "PublicDescription": "This event counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "This event counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.", + "SampleAfterValue": "20011", + "UMask": "0x1" }, { - "EventCode": "0xD0", - "UMask": "0x12", - "BriefDescription": "Retired store uops that miss the STLB.", + "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", - "PublicDescription": "This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", + "PublicDescription": "This event counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.", "SampleAfterValue": "100003", - "L1_Hit_Indication": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "EventCode": "0xD0", - "UMask": "0x21", - "BriefDescription": "Retired load uops with locked access.", + "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "BDE70, BDM100", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "Errata": "BDM35", - "PublicDescription": "This event counts load uops with locked access retired to the architected path.", + "PublicDescription": "Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI).", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xD0", - "UMask": "0x41", - "BriefDescription": "Retired load uops that split across a cacheline boundary.", + "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "BDE70", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "SampleAfterValue": "100007", + "UMask": "0x4" }, { - "EventCode": "0xD0", - "UMask": "0x42", - "BriefDescription": "Retired store uops that split across a cacheline boundary.", + "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "BDE70", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", - "SampleAfterValue": "100003", - "L1_Hit_Indication": "1", - "CounterHTOff": "0,1,2,3" + "SampleAfterValue": "100007", + "UMask": "0x20" }, { - "EventCode": "0xD0", - "UMask": "0x81", - "BriefDescription": "All retired load uops.", + "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "BDE70", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "PublicDescription": "This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "SampleAfterValue": "100007", + "UMask": "0x10" }, { - "EventCode": "0xD0", - "UMask": "0x82", - "BriefDescription": "All retired store uops.", + "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "PublicDescription": "This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.", - "SampleAfterValue": "2000003", - "L1_Hit_Indication": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "This event counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.", + "SampleAfterValue": "100003", + "UMask": "0x40" }, { - "EventCode": "0xD1", - "UMask": "0x1", "BriefDescription": "Retired load uops with L1 cache hits as data sources.", - "Data_LA": "1", - "PEBS": "1", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PEBS": "1", "PublicDescription": "This event counts retired load uops which data sources were hits in the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xD1", - "UMask": "0x2", - "BriefDescription": "Retired load uops with L2 cache hits as data sources.", + "BriefDescription": "Retired load uops misses in L1 cache as data sources.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", - "Errata": "BDM35", - "PublicDescription": "This event counts retired load uops which data sources were hits in the mid-level (L2) cache.", + "PublicDescription": "This event counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "EventCode": "0xD1", - "UMask": "0x4", - "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.", - "Data_LA": "1", - "PEBS": "1", + "BriefDescription": "Retired load uops with L2 cache hits as data sources.", "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", - "Errata": "BDM100", - "PublicDescription": "This event counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.", - "SampleAfterValue": "50021", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x8", - "BriefDescription": "Retired load uops misses in L1 cache as data sources.", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "BDM35", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", - "PublicDescription": "This event counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.", + "PublicDescription": "This event counts retired load uops which data sources were hits in the mid-level (L2) cache.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xD1", - "UMask": "0x10", "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", - "Data_LA": "1", - "PEBS": "1", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PEBS": "1", "PublicDescription": "This event counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.", "SampleAfterValue": "50021", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0xD1", - "UMask": "0x20", - "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", + "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.", + "SampleAfterValue": "50021", + "UMask": "0x4" + }, + { + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", "Errata": "BDM100, BDE70", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", + "PEBS": "1", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "EventCode": "0xD1", - "UMask": "0x40", - "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", + "BriefDescription": "All retired load uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", - "PublicDescription": "This event counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.", + "SampleAfterValue": "2000003", + "UMask": "0x81" }, { - "EventCode": "0xD2", - "UMask": "0x1", - "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "BriefDescription": "All retired store uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "L1_Hit_Indication": "1", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", - "Errata": "BDM100", - "PublicDescription": "This event counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.", - "SampleAfterValue": "20011", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.", + "SampleAfterValue": "2000003", + "UMask": "0x82" }, { - "EventCode": "0xD2", - "UMask": "0x2", - "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", + "BriefDescription": "Retired load uops with locked access.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "Errata": "BDM35", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", - "Errata": "BDM100", - "PublicDescription": "This event counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.", - "SampleAfterValue": "20011", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "This event counts load uops with locked access retired to the architected path.", + "SampleAfterValue": "100007", + "UMask": "0x21" }, { - "EventCode": "0xD2", - "UMask": "0x4", - "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", + "BriefDescription": "Retired load uops that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", - "Errata": "BDM100", - "PublicDescription": "This event counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).", - "SampleAfterValue": "20011", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "SampleAfterValue": "100003", + "UMask": "0x41" }, { - "EventCode": "0xD2", - "UMask": "0x8", - "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", + "BriefDescription": "Retired store uops that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "L1_Hit_Indication": "1", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", - "Errata": "BDM100", - "PublicDescription": "This event counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.", + "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x42" }, { - "EventCode": "0xD3", - "UMask": "0x1", - "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", + "BriefDescription": "Retired load uops that miss the STLB.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", - "Errata": "BDE70, BDM100", - "PublicDescription": "Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI).", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "This event counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x11" }, { - "EventCode": "0xD3", - "UMask": "0x4", - "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)", + "BriefDescription": "Retired store uops that miss the STLB.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "L1_Hit_Indication": "1", "PEBS": "1", + "PublicDescription": "This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x12" + }, + { + "BriefDescription": "Demand and prefetch data reads", "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", - "Errata": "BDE70", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "EventCode": "0xD3", - "UMask": "0x10", - "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM", - "Data_LA": "1", - "PEBS": "1", + "BriefDescription": "Any memory transaction that reached the SQ.", "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", - "Errata": "BDE70", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "PublicDescription": "This event counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, and so on.", + "SampleAfterValue": "100003", + "UMask": "0x80" }, { - "EventCode": "0xD3", - "UMask": "0x20", - "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache", - "Data_LA": "1", - "PEBS": "1", + "BriefDescription": "Cacheable and noncachaeble code read requests", "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", - "Errata": "BDE70", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xF0", - "UMask": "0x1", - "BriefDescription": "Demand Data Read requests that access L2 cache", + "BriefDescription": "Demand Data Read requests sent to uncore", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.DEMAND_DATA_RD", - "PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xF0", - "UMask": "0x2", - "BriefDescription": "RFO requests that access L2 cache", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.RFO", - "PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0xF0", - "UMask": "0x4", - "BriefDescription": "L2 cache accesses when fetching instructions", + "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.CODE_RD", - "PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xF0", - "UMask": "0x8", - "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.ALL_PF", - "PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "PublicDescription": "This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xF0", - "UMask": "0x10", - "BriefDescription": "L1D writebacks that access L2 cache", + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.L1D_WB", - "PublicDescription": "This event counts L1D writebacks that access L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "PublicDescription": "This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xF0", - "UMask": "0x20", - "BriefDescription": "L2 fill requests that access L2 cache", + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.L2_FILL", - "PublicDescription": "This event counts L2 fill requests that access L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "PublicDescription": "This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xF0", - "UMask": "0x40", - "BriefDescription": "L2 writebacks that access L2 cache", + "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.L2_WB", - "PublicDescription": "This event counts L2 writebacks that access L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "PublicDescription": "This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xF0", - "UMask": "0x80", - "BriefDescription": "Transactions accessing L2 pipe", + "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", "Counter": "0,1,2,3", - "EventName": "L2_TRANS.ALL_REQUESTS", - "PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PublicDescription": "This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0xF1", - "UMask": "0x1", - "BriefDescription": "L2 cache lines in I state filling L2", + "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.I", - "PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "PublicDescription": "This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is counted from the promotion point.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xF1", - "UMask": "0x2", - "BriefDescription": "L2 cache lines in S state filling L2", + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.S", - "PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xF1", - "UMask": "0x4", - "BriefDescription": "L2 cache lines in E state filling L2", + "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.E", - "PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "PublicDescription": "This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xF1", - "UMask": "0x7", - "BriefDescription": "L2 cache lines filling L2", + "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.ALL", - "PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xF2", - "UMask": "0x5", - "BriefDescription": "Clean L2 cache lines evicted by demand.", + "BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "Counter": "0,1,2,3", - "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0244", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xf4", - "UMask": "0x10", - "BriefDescription": "Split locks in SQ", + "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "Counter": "0,1,2,3", - "EventName": "SQ_MISC.SPLIT_LOCK", - "PublicDescription": "This event counts the number of split locks in the super queue.", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0091", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all requests hit in the L3", - "MSRValue": "0x3F803C8FFF", + "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all requests hit in the L3", + "MSRValue": "0x4003C0091", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "MSRValue": "0x10003C07F7", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "MSRValue": "0x10003C07F7", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "MSRValue": "0x04003C07F7", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "MSRValue": "0x4003C07F7", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "MSRValue": "0x04003C0244", + "BriefDescription": "Counts all requests hit in the L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "MSRValue": "0x3F803C8FFF", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "MSRValue": "0x10003C0122", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "MSRValue": "0x10003C0122", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "MSRValue": "0x04003C0122", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "MSRValue": "0x4003C0122", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "MSRValue": "0x10003C0091", + "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "MSRValue": "0x3F803C0002", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "MSRValue": "0x04003C0091", + "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "MSRValue": "0x10003C0002", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3", - "MSRValue": "0x3F803C0200", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3", + "MSRValue": "0x3F803C0200", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3", - "MSRValue": "0x3F803C0100", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { + "MSRValue": "0x3F803C0100", "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "MSRValue": "0x10003C0002", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3", - "MSRValue": "0x3F803C0002", + "BriefDescription": "Split locks in SQ", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf4", + "EventName": "SQ_MISC.SPLIT_LOCK", + "PublicDescription": "This event counts the number of split locks in the super queue.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" } -]
\ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json b/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json index ba0e0c4e74eb..93bbc8600321 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json @@ -1,165 +1,200 @@ [ { - "EventCode": "0xC1", - "UMask": "0x8", - "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", - "EventName": "OTHER_ASSISTS.AVX_TO_SSE", - "Errata": "BDM30", - "PublicDescription": "This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xC1", - "UMask": "0x10", - "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", "Counter": "0,1,2,3", - "EventName": "OTHER_ASSISTS.SSE_TO_AVX", - "Errata": "BDM30", - "PublicDescription": "This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xC7", - "UMask": "0x1", - "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0xC7", - "UMask": "0x2", - "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "EventCode": "0xC7", - "UMask": "0x3", - "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single precision?)", + "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", + "SampleAfterValue": "2000006", + "UMask": "0x15" }, { - "EventCode": "0xC7", - "UMask": "0x4", - "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.PACKED", + "SampleAfterValue": "2000004", + "UMask": "0x3c" }, { - "EventCode": "0xC7", - "UMask": "0x8", - "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation. Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x3" }, { - "EventCode": "0xC7", - "UMask": "0x10", - "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xC7", - "UMask": "0x15", - "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", - "SampleAfterValue": "2000006", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xc7", - "UMask": "0x20", - "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xC7", - "UMask": "0x2a", - "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SINGLE", "SampleAfterValue": "2000005", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2a" }, { - "EventCode": "0xC7", - "UMask": "0x3c", - "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single-precision?)", + "BriefDescription": "Cycles with any input/output SSE or FP assist", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.PACKED", - "SampleAfterValue": "2000004", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.ANY", + "PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.", + "SampleAfterValue": "100003", + "UMask": "0x1e" }, { - "EventCode": "0xCA", - "UMask": "0x2", - "BriefDescription": "Number of X87 assists due to output value.", + "BriefDescription": "Number of SIMD FP assists due to input values", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.X87_OUTPUT", - "PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_INPUT", + "PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { + "BriefDescription": "Number of SIMD FP assists due to Output values", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xCA", - "UMask": "0x4", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { "BriefDescription": "Number of X87 assists due to input value.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_INPUT", "PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xCA", - "UMask": "0x8", - "BriefDescription": "Number of SIMD FP assists due to Output values", + "BriefDescription": "Number of X87 assists due to output value.", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.SIMD_OUTPUT", - "PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_OUTPUT", + "PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xCA", - "UMask": "0x10", - "BriefDescription": "Number of SIMD FP assists due to input values", + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.SIMD_INPUT", - "PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM30", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "PublicDescription": "This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xCA", - "UMask": "0x1e", - "BriefDescription": "Cycles with any input/output SSE or FP assist", + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.ANY", - "CounterMask": "1", - "PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM30", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "PublicDescription": "This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" + }, + { + "BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF", + "PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.", + "SampleAfterValue": "2000003", + "UMask": "0x3" } -]
\ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json b/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json index 72781e1e3362..37ce8034b2ed 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json @@ -1,286 +1,295 @@ [ { - "EventCode": "0x79", - "UMask": "0x2", - "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", "Counter": "0,1,2,3", - "EventName": "IDQ.EMPTY", - "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xe6", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "100003", + "UMask": "0x1f" }, { - "EventCode": "0x79", - "UMask": "0x4", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", "Counter": "0,1,2,3", - "EventName": "IDQ.MITE_UOPS", - "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x79", - "UMask": "0x4", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches", "Counter": "0,1,2,3", - "EventName": "IDQ.MITE_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x79", - "UMask": "0x8", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", "Counter": "0,1,2,3", - "EventName": "IDQ.DSB_UOPS", - "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.IFDATA_STALL", + "PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x79", - "UMask": "0x8", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.", "Counter": "0,1,2,3", - "EventName": "IDQ.DSB_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { - "EventCode": "0x79", - "UMask": "0x10", - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_DSB_UOPS", - "PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x18" }, { - "EventCode": "0x79", - "UMask": "0x10", - "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_DSB_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x18" }, { - "EdgeDetect": "1", - "EventCode": "0x79", - "UMask": "0x10", - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Cycles MITE is delivering 4 Uops", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_DSB_OCCUR", - "CounterMask": "1", - "PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x24" }, { - "EventCode": "0x79", - "UMask": "0x18", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", + "BriefDescription": "Cycles MITE is delivering any Uop", "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", - "CounterMask": "4", - "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x24" }, { - "EventCode": "0x79", - "UMask": "0x18", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES", + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x79", - "UMask": "0x20", - "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_MITE_UOPS", - "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x79", - "UMask": "0x24", - "BriefDescription": "Cycles MITE is delivering 4 Uops", + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", - "CounterMask": "4", - "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.EMPTY", + "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x79", - "UMask": "0x24", - "BriefDescription": "Cycles MITE is delivering any Uop", + "EventName": "IDQ.MITE_ALL_UOPS", + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x3c" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES", + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x79", - "UMask": "0x30", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_UOPS", - "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x79", - "UMask": "0x30", "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES", "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "EdgeDetect": "1", - "EventCode": "0x79", - "UMask": "0x30", - "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "EventName": "IDQ.MS_SWITCHES", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_CYCLES", + "PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", "EventCode": "0x79", - "UMask": "0x3c", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "EventName": "IDQ.MS_DSB_OCCUR", + "PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "EventName": "IDQ.MITE_ALL_UOPS", - "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_UOPS", + "PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x80", - "UMask": "0x1", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches", + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "EventName": "ICACHE.HIT", - "PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_MITE_UOPS", + "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x80", - "UMask": "0x2", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.", + "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", "Counter": "0,1,2,3", - "EventName": "ICACHE.MISSES", - "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", + "SampleAfterValue": "2000003", + "UMask": "0x30" }, { - "EventCode": "0x80", - "UMask": "0x4", - "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "EventName": "ICACHE.IFDATA_STALL", - "PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", + "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "EventCode": "0x9C", - "UMask": "0x1", "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", - "UMask": "0x1", "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "CounterHTOff": "0,1,2,3", "CounterMask": "4", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", "PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", "EventCode": "0x9C", - "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3", "CounterMask": "3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", "PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", - "UMask": "0x1", "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3", "CounterMask": "2", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", - "UMask": "0x1", "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "CounterHTOff": "0,1,2,3", "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "Invert": "1", "EventCode": "0x9C", - "UMask": "0x1", - "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", - "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xAB", - "UMask": "0x2", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", - "Counter": "0,1,2,3", - "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", - "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } -]
\ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/memory.json b/tools/perf/pmu-events/arch/x86/broadwellx/memory.json index ecb413bb67ca..545f61f691b9 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/memory.json @@ -1,679 +1,668 @@ [ { - "EventCode": "0x05", - "UMask": "0x1", - "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", - "Counter": "0,1,2,3", - "EventName": "MISALIGN_MEM_REF.LOADS", - "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x05", - "UMask": "0x2", - "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", - "Counter": "0,1,2,3", - "EventName": "MISALIGN_MEM_REF.STORES", - "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x1", - "BriefDescription": "Number of times a TSX line had a cache conflict", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_CONFLICT", - "PublicDescription": "Number of times a TSX line had a cache conflict.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x2", - "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", - "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x4", - "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", - "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x8", - "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", - "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x10", - "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", - "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x20", - "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", - "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x40", - "BriefDescription": "Number of times we could not allocate Lock Buffer", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", - "PublicDescription": "Number of times we could not allocate Lock Buffer.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x1", - "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x2", - "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC2", - "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x4", - "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC3", - "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x8", - "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC4", - "PublicDescription": "RTM region detected inside HLE.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x10", - "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC5", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC3", - "UMask": "0x2", - "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", - "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xc8", - "UMask": "0x1", - "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", - "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.START", - "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xc8", - "UMask": "0x2", - "BriefDescription": "Number of times HLE commit succeeded", - "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.COMMIT", - "PublicDescription": "Number of times HLE commit succeeded.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xc8", - "UMask": "0x4", "BriefDescription": "Number of times HLE abort was triggered", - "PEBS": "1", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED", + "PEBS": "1", "PublicDescription": "Number of times HLE abort was triggered.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xc8", - "UMask": "0x8", "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC1", "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xc8", - "UMask": "0x10", "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC2", "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xc8", - "UMask": "0x20", "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC3", "PublicDescription": "Number of times a disallowed operation caused an HLE abort.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xc8", - "UMask": "0x40", "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC4", "PublicDescription": "Number of times HLE caused a fault.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0xc8", - "UMask": "0x80", "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC5", "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xc9", - "UMask": "0x1", - "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", - "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.START", - "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x80" }, { - "EventCode": "0xc9", - "UMask": "0x2", - "BriefDescription": "Number of times RTM commit succeeded", - "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.COMMIT", - "PublicDescription": "Number of times RTM commit succeeded.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xc9", - "UMask": "0x4", - "BriefDescription": "Number of times RTM abort was triggered", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED", - "PublicDescription": "Number of times RTM abort was triggered .", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xc9", - "UMask": "0x8", - "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", - "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC1", - "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xc9", - "UMask": "0x10", - "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", - "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC2", - "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xc9", - "UMask": "0x20", - "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", + "BriefDescription": "Number of times HLE commit succeeded", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC3", - "PublicDescription": "Number of times a disallowed operation caused an RTM abort.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.COMMIT", + "PublicDescription": "Number of times HLE commit succeeded.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xc9", - "UMask": "0x40", - "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", + "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC4", - "PublicDescription": "Number of times a RTM caused a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.START", + "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xc9", - "UMask": "0x80", - "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC5", - "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 4", - "PEBS": "2", - "MSRValue": "0x4", + "BriefDescription": "Randomly selected loads with latency value being above 128", "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "PublicDescription": "Counts randomly selected loads with latency value being above four.", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above 128.", + "SampleAfterValue": "1009", "TakenAlone": "1", - "SampleAfterValue": "100003", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 8", - "PEBS": "2", - "MSRValue": "0x8", + "BriefDescription": "Randomly selected loads with latency value being above 16", "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "PublicDescription": "Counts randomly selected loads with latency value being above eight.", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above 16.", + "SampleAfterValue": "20011", "TakenAlone": "1", - "SampleAfterValue": "50021", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 16", - "PEBS": "2", - "MSRValue": "0x10", + "BriefDescription": "Randomly selected loads with latency value being above 256", "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "MSRIndex": "0x3F6", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "PublicDescription": "Counts randomly selected loads with latency value being above 16.", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above 256.", + "SampleAfterValue": "503", "TakenAlone": "1", - "SampleAfterValue": "20011", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", "BriefDescription": "Randomly selected loads with latency value being above 32", - "PEBS": "2", - "MSRValue": "0x20", "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "BDM100, BDM35", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", + "MSRValue": "0x20", + "PEBS": "2", "PublicDescription": "Counts randomly selected loads with latency value being above 32.", - "TakenAlone": "1", "SampleAfterValue": "100007", - "CounterHTOff": "3" + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 64", - "PEBS": "2", - "MSRValue": "0x40", + "BriefDescription": "Randomly selected loads with latency value being above 4", "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "PublicDescription": "Counts randomly selected loads with latency value being above 64.", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above four.", + "SampleAfterValue": "100003", "TakenAlone": "1", - "SampleAfterValue": "2003", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 128", - "PEBS": "2", - "MSRValue": "0x80", + "BriefDescription": "Randomly selected loads with latency value being above 512", "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", - "MSRIndex": "0x3F6", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "PublicDescription": "Counts randomly selected loads with latency value being above 128.", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above 512.", + "SampleAfterValue": "101", "TakenAlone": "1", - "SampleAfterValue": "1009", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 256", - "PEBS": "2", - "MSRValue": "0x100", + "BriefDescription": "Randomly selected loads with latency value being above 64", "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", - "MSRIndex": "0x3F6", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "PublicDescription": "Counts randomly selected loads with latency value being above 256.", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above 64.", + "SampleAfterValue": "2003", "TakenAlone": "1", - "SampleAfterValue": "503", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 512", - "PEBS": "2", - "MSRValue": "0x200", + "BriefDescription": "Randomly selected loads with latency value being above 8", "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", - "MSRIndex": "0x3F6", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "PublicDescription": "Counts randomly selected loads with latency value being above 512.", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above eight.", + "SampleAfterValue": "50021", "TakenAlone": "1", - "SampleAfterValue": "101", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all requests miss in the L3", - "MSRValue": "0x3FBFC08FFF", + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.LOADS", + "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.STORES", + "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts all demand & prefetch code reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all requests miss in the L3", + "MSRValue": "0x3FBFC00244", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache", - "MSRValue": "0x087FC007F7", + "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache", + "MSRValue": "0x604000244", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache", - "MSRValue": "0x103FC007F7", + "BriefDescription": "Counts all demand & prefetch data reads miss in the L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache", + "MSRValue": "0x3FBFC00091", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram", - "MSRValue": "0x063BC007F7", + "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram", + "MSRValue": "0x604000091", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram", - "MSRValue": "0x06040007F7", + "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram", + "MSRValue": "0x63BC00091", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { + "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC00091", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x87FC00091", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3", - "MSRValue": "0x3FBFC007F7", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3", + "MSRValue": "0x3FBFC007F7", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", - "MSRValue": "0x0604000244", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", + "MSRValue": "0x6040007F7", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch code reads miss in the L3", - "MSRValue": "0x3FBFC00244", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch code reads miss in the L3", + "MSRValue": "0x63BC007F7", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", - "MSRValue": "0x0604000122", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", + "MSRValue": "0x103FC007F7", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3", - "MSRValue": "0x3FBFC00122", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch RFOs miss in the L3", + "MSRValue": "0x87FC007F7", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache", - "MSRValue": "0x087FC00091", + "BriefDescription": "Counts all requests miss in the L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache", + "MSRValue": "0x3FBFC08FFF", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache", - "MSRValue": "0x103FC00091", + "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache", + "MSRValue": "0x3FBFC00122", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram", - "MSRValue": "0x063BC00091", + "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram", + "MSRValue": "0x604000122", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", - "MSRValue": "0x0604000091", + "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", + "MSRValue": "0x3FBFC00002", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss in the L3", - "MSRValue": "0x3FBFC00091", + "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss in the L3", + "MSRValue": "0x103FC00002", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", - "MSRValue": "0x3FBFC00200", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", + "MSRValue": "0x3FBFC00200", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", - "MSRValue": "0x3FBFC00100", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", + "MSRValue": "0x3FBFC00100", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache", - "MSRValue": "0x103FC00002", + "BriefDescription": "Number of times RTM abort was triggered", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED", + "PEBS": "1", + "PublicDescription": "Number of times RTM abort was triggered .", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3", - "MSRValue": "0x3FBFC00002", + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC1", + "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC2", + "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC3", + "PublicDescription": "Number of times a disallowed operation caused an RTM abort.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC4", + "PublicDescription": "Number of times a RTM caused a fault.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of times RTM commit succeeded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.COMMIT", + "PublicDescription": "Number of times RTM commit succeeded.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.START", + "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC2", + "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC3", + "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC4", + "PublicDescription": "RTM region detected inside HLE.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC5", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of times a TSX line had a cache conflict", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CONFLICT", + "PublicDescription": "Number of times a TSX line had a cache conflict.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", + "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times we could not allocate Lock Buffer", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "PublicDescription": "Number of times we could not allocate Lock Buffer.", + "SampleAfterValue": "2000003", + "UMask": "0x40" } -]
\ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/other.json b/tools/perf/pmu-events/arch/x86/broadwellx/other.json index 4475249ea9da..917d145d5227 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/other.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/other.json @@ -1,44 +1,44 @@ [ { - "EventCode": "0x5C", - "UMask": "0x1", "BriefDescription": "Unhalted core cycles when the thread is in ring 0", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EdgeDetect": "1", - "EventCode": "0x5C", - "UMask": "0x1", "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", "Counter": "0,1,2,3", - "EventName": "CPL_CYCLES.RING0_TRANS", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5C", + "EventName": "CPL_CYCLES.RING0_TRANS", "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x5C", - "UMask": "0x2", "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x63", - "UMask": "0x1", "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } -]
\ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json b/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json index c2f6932a5817..f0f30081d683 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json @@ -1,1423 +1,1380 @@ [ { - "UMask": "0x1", - "BriefDescription": "Instructions retired from execution.", - "Counter": "Fixed counter 0", - "EventName": "INST_RETIRED.ANY", - "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 0" - }, - { - "UMask": "0x2", - "BriefDescription": "Core cycles when the thread is not in halt state", - "Counter": "Fixed counter 1", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 1" - }, - { - "UMask": "0x2", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "Counter": "Fixed counter 1", - "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 1" - }, - { - "UMask": "0x3", - "BriefDescription": "Reference cycles when the core is not in halt state.", - "Counter": "Fixed counter 2", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 2" - }, - { - "EventCode": "0x03", - "UMask": "0x2", - "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding", - "Counter": "0,1,2,3", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x03", - "UMask": "0x8", - "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", - "Counter": "0,1,2,3", - "EventName": "LD_BLOCKS.NO_SR", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x07", - "UMask": "0x1", - "BriefDescription": "False dependencies in MOB due to partial compare", - "Counter": "0,1,2,3", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "UMask": "0x3", - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)", + "BriefDescription": "Cycles when divider is busy executing divide operations", "Counter": "0,1,2,3", - "EventName": "INT_MISC.RECOVERY_CYCLES", - "CounterMask": "1", - "PublicDescription": "Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x14", + "EventName": "ARITH.FPU_DIV_ACTIVE", + "PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x0D", - "UMask": "0x3", - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "BriefDescription": "Speculative and retired branches", "Counter": "0,1,2,3", - "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", - "AnyThread": "1", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "PublicDescription": "This event counts both taken and not taken speculative and retired branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "EventCode": "0x0D", - "UMask": "0x8", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread", + "BriefDescription": "Speculative and retired macro-conditional branches", "Counter": "0,1,2,3", - "EventName": "INT_MISC.RAT_STALL_CYCLES", - "PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "EventCode": "0x0E", - "UMask": "0x1", - "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", + "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects", "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.ANY", - "PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.", + "SampleAfterValue": "200003", + "UMask": "0xc2" }, { - "Invert": "1", - "EventCode": "0x0E", - "UMask": "0x1", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", + "BriefDescription": "Speculative and retired direct near calls", "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.", + "SampleAfterValue": "200003", + "UMask": "0xd0" }, { - "EventCode": "0x0E", - "UMask": "0x10", - "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.", + "BriefDescription": "Speculative and retired indirect branches excluding calls and returns", "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.FLAGS_MERGE", - "PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.", + "SampleAfterValue": "200003", + "UMask": "0xc4" }, { - "EventCode": "0x0E", - "UMask": "0x20", - "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "BriefDescription": "Speculative and retired indirect return branches.", "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.SLOW_LEA", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.", + "SampleAfterValue": "200003", + "UMask": "0xc8" }, { - "EventCode": "0x0E", - "UMask": "0x40", - "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.", + "BriefDescription": "Not taken macro-conditional branches", "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.SINGLE_MUL", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "This event counts not taken macro-conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0x41" }, { - "EventCode": "0x14", - "UMask": "0x1", - "BriefDescription": "Cycles when divider is busy executing divide operations", + "BriefDescription": "Taken speculative and retired macro-conditional branches", "Counter": "0,1,2,3", - "EventName": "ARITH.FPU_DIV_ACTIVE", - "PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0x81" }, { - "EventCode": "0x3C", - "UMask": "0x0", - "BriefDescription": "Thread cycles when thread is not in halt state", + "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.", + "SampleAfterValue": "200003", + "UMask": "0x82" }, { - "EventCode": "0x3C", - "UMask": "0x0", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "BriefDescription": "Taken speculative and retired direct near calls", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "PublicDescription": "This event counts taken speculative and retired direct near calls.", + "SampleAfterValue": "200003", + "UMask": "0x90" }, { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", - "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.", + "SampleAfterValue": "200003", + "UMask": "0x84" }, { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "BriefDescription": "Taken speculative and retired indirect calls", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.", + "SampleAfterValue": "200003", + "UMask": "0xa0" }, { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", - "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.", + "SampleAfterValue": "200003", + "UMask": "0x88" }, { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "BriefDescription": "All (macro) branch instructions retired.", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PublicDescription": "This event counts all (macro) branch instructions retired.", + "SampleAfterValue": "400009" }, { - "EventCode": "0x3c", - "UMask": "0x2", - "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "Errata": "BDW98", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "EventCode": "0x3C", - "UMask": "0x2", - "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "BriefDescription": "Conditional branch instructions retired.", "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", + "PublicDescription": "This event counts conditional branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "EventCode": "0x4c", - "UMask": "0x1", - "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", + "BriefDescription": "Far branch instructions retired.", "Counter": "0,1,2,3", - "EventName": "LOAD_HIT_PRE.SW_PF", - "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDW98", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PublicDescription": "This event counts far branch instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x40" }, { - "EventCode": "0x4C", - "UMask": "0x2", - "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", + "BriefDescription": "Direct and indirect near call instructions retired.", "Counter": "0,1,2,3", - "EventName": "LOAD_HIT_PRE.HW_PF", - "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "PublicDescription": "This event counts both direct and indirect near call instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "EventCode": "0x58", - "UMask": "0x1", - "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", + "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).", "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", + "PEBS": "1", + "PublicDescription": "This event counts both direct and indirect macro near call instructions retired (captured in ring 3).", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "EventCode": "0x58", - "UMask": "0x2", - "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", + "BriefDescription": "Return instructions retired.", "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "PublicDescription": "This event counts return instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x8" }, { - "EventCode": "0x58", - "UMask": "0x4", - "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", + "BriefDescription": "Taken branch instructions retired.", "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "This event counts taken branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "EventCode": "0x58", - "UMask": "0x8", - "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", + "BriefDescription": "Not taken branch instructions retired.", "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "PublicDescription": "This event counts not taken branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x10" }, { - "EventCode": "0x5E", - "UMask": "0x1", - "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", "Counter": "0,1,2,3", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "EdgeDetect": "1", - "Invert": "1", - "EventCode": "0x5E", - "UMask": "0x1", - "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", "Counter": "0,1,2,3", - "EventName": "RS_EVENTS.EMPTY_END", - "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc1" }, { - "EventCode": "0x87", - "UMask": "0x1", - "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "BriefDescription": "Mispredicted indirect branches excluding calls and returns", "Counter": "0,1,2,3", - "EventName": "ILD_STALL.LCP", - "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.", + "SampleAfterValue": "200003", + "UMask": "0xc4" }, { - "EventCode": "0x88", - "UMask": "0x41", - "BriefDescription": "Not taken macro-conditional branches", + "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", - "PublicDescription": "This event counts not taken macro-conditional branch instructions.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x41" }, { - "EventCode": "0x88", - "UMask": "0x81", - "BriefDescription": "Taken speculative and retired macro-conditional branches", + "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", - "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x81" }, { - "EventCode": "0x88", - "UMask": "0x82", - "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", - "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x84" }, { - "EventCode": "0x88", - "UMask": "0x84", - "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns", + "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xa0" }, { - "EventCode": "0x88", - "UMask": "0x88", - "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", - "PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x88" }, { - "EventCode": "0x88", - "UMask": "0x90", - "BriefDescription": "Taken speculative and retired direct near calls", + "BriefDescription": "All mispredicted macro branch instructions retired.", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", - "PublicDescription": "This event counts taken speculative and retired direct near calls.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PublicDescription": "This event counts all mispredicted macro branch instructions retired.", + "SampleAfterValue": "400009" }, { - "EventCode": "0x88", - "UMask": "0xa0", - "BriefDescription": "Taken speculative and retired indirect calls", + "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "EventCode": "0x88", - "UMask": "0xc1", - "BriefDescription": "Speculative and retired macro-conditional branches", + "BriefDescription": "Mispredicted conditional branch instructions retired.", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", - "PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", + "PublicDescription": "This event counts mispredicted conditional branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "EventCode": "0x88", - "UMask": "0xc2", - "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects", + "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", - "PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "Number of near branch instructions retired that were mispredicted and taken.", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "EventCode": "0x88", - "UMask": "0xc4", - "BriefDescription": "Speculative and retired indirect branches excluding calls and returns", + "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.RET", + "PEBS": "1", + "PublicDescription": "This event counts mispredicted return instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x8" }, { - "EventCode": "0x88", - "UMask": "0xc8", - "BriefDescription": "Speculative and retired indirect return branches.", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", - "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0x3c", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x88", - "UMask": "0xd0", - "BriefDescription": "Speculative and retired direct near calls", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", - "PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x88", - "UMask": "0xff", - "BriefDescription": "Speculative and retired branches", + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_BRANCHES", - "PublicDescription": "This event counts both taken and not taken speculative and retired branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x89", - "UMask": "0x41", - "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", - "PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x89", - "UMask": "0x81", - "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches", - "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", - "PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Reference cycles when the core is not in halt state.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "SampleAfterValue": "2000003", + "UMask": "0x3" }, { - "EventCode": "0x89", - "UMask": "0x84", - "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x89", - "UMask": "0x88", - "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic", + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", - "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x89", - "UMask": "0xa0", - "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", - "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Core cycles when the thread is not in halt state", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x89", - "UMask": "0xc1", - "BriefDescription": "Speculative and retired mispredicted macro conditional branches", - "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", - "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x89", - "UMask": "0xc4", - "BriefDescription": "Mispredicted indirect branches excluding calls and returns", + "BriefDescription": "Thread cycles when thread is not in halt state", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", + "SampleAfterValue": "2000003" }, { - "EventCode": "0x89", - "UMask": "0xff", - "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.ALL_BRANCHES", - "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003" }, { - "EventCode": "0xA0", - "UMask": "0x3", - "BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports", - "Counter": "0,1,2,3", - "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF", - "PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "EventCode": "0xA1", - "UMask": "0x1", - "BriefDescription": "Cycles per thread when uops are executed in port 0", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xA1", - "UMask": "0x1", - "BriefDescription": "Cycles per core when uops are exectuted in port 0.", + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", - "AnyThread": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x1", - "BriefDescription": "Cycles per thread when uops are executed in port 0", + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_0", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "PublicDescription": "Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x2", - "BriefDescription": "Cycles per thread when uops are executed in port 1", + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xA1", - "UMask": "0x2", - "BriefDescription": "Cycles per core when uops are exectuted in port 1.", + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", - "AnyThread": "1", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xA1", - "UMask": "0x2", - "BriefDescription": "Cycles per thread when uops are executed in port 1", + "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_1", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xA1", - "UMask": "0x4", - "BriefDescription": "Cycles per thread when uops are executed in port 2", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "EventCode": "0xA1", - "UMask": "0x4", - "BriefDescription": "Cycles per core when uops are dispatched to port 2.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", - "AnyThread": "1", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "EventCode": "0xA1", - "UMask": "0x4", - "BriefDescription": "Cycles per thread when uops are executed in port 2", + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_2", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" }, { - "EventCode": "0xA1", - "UMask": "0x8", - "BriefDescription": "Cycles per thread when uops are executed in port 3", + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" }, { - "EventCode": "0xA1", - "UMask": "0x8", - "BriefDescription": "Cycles per core when uops are dispatched to port 3.", + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", - "AnyThread": "1", + "CounterHTOff": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x6" }, { - "EventCode": "0xA1", - "UMask": "0x8", - "BriefDescription": "Cycles per thread when uops are executed in port 3", + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_3", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x6" }, { - "EventCode": "0xA1", - "UMask": "0x10", - "BriefDescription": "Cycles per thread when uops are executed in port 4", + "BriefDescription": "Total execution stalls.", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xA1", - "UMask": "0x10", - "BriefDescription": "Cycles per core when uops are exectuted in port 4.", + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", - "AnyThread": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x10", - "BriefDescription": "Cycles per thread when uops are executed in port 4", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_4", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", + "CounterHTOff": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x20", - "BriefDescription": "Cycles per thread when uops are executed in port 5", + "BriefDescription": "Number of instructions retired. General Counter - architectural event", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM61", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PublicDescription": "This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).", + "SampleAfterValue": "2000003" }, { - "EventCode": "0xA1", - "UMask": "0x20", - "BriefDescription": "Cycles per core when uops are exectuted in port 5.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", - "AnyThread": "1", + "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", + "Counter": "1", + "CounterHTOff": "1", + "Errata": "BDM11, BDM55", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "2", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts instructions retired.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "UMask": "0x20", - "BriefDescription": "Cycles per thread when uops are executed in port 5", + "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions:", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_5", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.X87", + "PublicDescription": "This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xA1", - "UMask": "0x40", - "BriefDescription": "Cycles per thread when uops are executed in port 6", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_6", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0D", + "EventName": "INT_MISC.RAT_STALL_CYCLES", + "PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xA1", - "UMask": "0x40", - "BriefDescription": "Cycles per core when uops are exectuted in port 6.", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", - "AnyThread": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "PublicDescription": "Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "EventCode": "0xA1", - "UMask": "0x40", - "BriefDescription": "Cycles per thread when uops are executed in port 6", + "AnyThread": "1", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_6", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "EventCode": "0xA1", - "UMask": "0x80", - "BriefDescription": "Cycles per thread when uops are executed in port 7", + "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_7", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "EventCode": "0xA1", - "UMask": "0x80", - "BriefDescription": "Cycles per core when uops are dispatched to port 7.", + "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xA1", - "UMask": "0x80", - "BriefDescription": "Cycles per thread when uops are executed in port 7", + "BriefDescription": "False dependencies in MOB due to partial compare", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_7", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xa2", - "UMask": "0x1", - "BriefDescription": "Resource-related stall cycles", + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.ANY", - "PublicDescription": "This event counts resource-related stall cycles.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.HW_PF", + "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xA2", - "UMask": "0x4", - "BriefDescription": "Cycles stalled due to no eligible RS entry available.", + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.RS", - "PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PRE.SW_PF", + "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA2", - "UMask": "0x8", - "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.SB", - "PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_4_UOPS", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA2", - "UMask": "0x10", - "BriefDescription": "Cycles stalled due to re-order buffer full.", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.ROB", - "PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA3", - "UMask": "0x1", - "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "BriefDescription": "Number of Uops delivered by the LSD.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", - "CounterMask": "1", - "PublicDescription": "Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA8", + "EventName": "LSD.UOPS", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA3", - "UMask": "0x1", - "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "BriefDescription": "Number of machine clears (nukes) of any type.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EdgeDetect": "1", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA3", - "UMask": "0x2", - "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", - "CounterMask": "2", - "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem).", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.CYCLES", + "PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA3", - "UMask": "0x2", - "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", - "CounterMask": "2", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.", + "SampleAfterValue": "100003", + "UMask": "0x20" }, { - "EventCode": "0xA3", - "UMask": "0x4", - "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.", + "BriefDescription": "Self-modifying code (SMC) detected.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", - "CounterMask": "4", - "PublicDescription": "Counts number of cycles nothing is executed on any execution port.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0xA3", - "UMask": "0x4", - "BriefDescription": "Total execution stalls.", + "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", - "CounterMask": "4", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x1" }, { - "EventCode": "0xA3", - "UMask": "0x5", - "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", - "CounterMask": "5", - "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x4" }, { - "EventCode": "0xA3", - "UMask": "0x5", - "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", - "CounterMask": "5", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "SampleAfterValue": "100003", + "UMask": "0x40" }, { - "EventCode": "0xA3", - "UMask": "0x6", - "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "BriefDescription": "Resource-related stall cycles", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", - "CounterMask": "6", - "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xa2", + "EventName": "RESOURCE_STALLS.ANY", + "PublicDescription": "This event counts resource-related stall cycles.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xA3", - "UMask": "0x6", - "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "BriefDescription": "Cycles stalled due to re-order buffer full.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", - "CounterMask": "6", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ROB", + "PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xA3", - "UMask": "0x8", - "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", - "CounterMask": "8", - "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache.", + "BriefDescription": "Cycles stalled due to no eligible RS entry available.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.RS", + "PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.", "SampleAfterValue": "2000003", - "CounterHTOff": "2" + "UMask": "0x4" }, { - "EventCode": "0xA3", - "UMask": "0x8", - "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", - "CounterMask": "8", + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.SB", + "PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.", "SampleAfterValue": "2000003", - "CounterHTOff": "2" + "UMask": "0x8" }, { - "EventCode": "0xA3", - "UMask": "0xc", - "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", - "CounterMask": "12", - "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache.", + "BriefDescription": "Count cases of saving new LBR", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCC", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.", "SampleAfterValue": "2000003", - "CounterHTOff": "2" + "UMask": "0x20" }, { - "EventCode": "0xA3", - "UMask": "0xc", - "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", - "CounterMask": "12", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.", "SampleAfterValue": "2000003", - "CounterHTOff": "2" + "UMask": "0x1" }, { - "EventCode": "0xA8", - "UMask": "0x1", - "BriefDescription": "Number of Uops delivered by the LSD.", + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", "Counter": "0,1,2,3", - "EventName": "LSD.UOPS", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "EventCode": "0xA8", - "UMask": "0x1", - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "BriefDescription": "Cycles per thread when uops are executed in port 0", "Counter": "0,1,2,3", - "EventName": "LSD.CYCLES_4_UOPS", - "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA8", - "UMask": "0x1", - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "BriefDescription": "Cycles per thread when uops are executed in port 1", "Counter": "0,1,2,3", - "EventName": "LSD.CYCLES_ACTIVE", - "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "BriefDescription": "Cycles per thread when uops are executed in port 2", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.THREAD", - "PublicDescription": "Number of uops to be executed per-thread each cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "Invert": "1", - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "BriefDescription": "Cycles per thread when uops are executed in port 3", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 1 uop was executed per-thread.", + "BriefDescription": "Cycles per thread when uops are executed in port 4", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", - "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 2 uops were executed per-thread.", + "BriefDescription": "Cycles per thread when uops are executed in port 5", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", - "CounterMask": "2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 3 uops were executed per-thread.", + "BriefDescription": "Cycles per thread when uops are executed in port 6", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", - "CounterMask": "3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_6", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x40" }, { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 4 uops were executed per-thread.", + "BriefDescription": "Cycles per thread when uops are executed in port 7", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", - "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_7", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x80" }, { - "EventCode": "0xB1", - "UMask": "0x2", "BriefDescription": "Number of uops executed on the core.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE", "PublicDescription": "Number of uops executed from any thread.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xb1", - "UMask": "0x2", "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xb1", - "UMask": "0x2", "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "2", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xb1", - "UMask": "0x2", "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "3", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xb1", - "UMask": "0x2", "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "Invert": "1", - "EventCode": "0xb1", - "UMask": "0x2", "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Invert": "1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xC0", - "UMask": "0x0", - "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "BriefDescription": "Cycles where at least 1 uop was executed per-thread.", "Counter": "0,1,2,3", - "EventName": "INST_RETIRED.ANY_P", - "Errata": "BDM61", - "PublicDescription": "This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xC0", - "UMask": "0x1", - "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", - "PEBS": "2", - "Counter": "1", - "EventName": "INST_RETIRED.PREC_DIST", - "Errata": "BDM11, BDM55", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts instructions retired.", + "BriefDescription": "Cycles where at least 2 uops were executed per-thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", "SampleAfterValue": "2000003", - "CounterHTOff": "1" + "UMask": "0x1" }, { - "EventCode": "0xC0", - "UMask": "0x2", - "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions:", + "BriefDescription": "Cycles where at least 3 uops were executed per-thread.", "Counter": "0,1,2,3", - "EventName": "INST_RETIRED.X87", - "PublicDescription": "This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xC1", - "UMask": "0x40", - "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", + "BriefDescription": "Cycles where at least 4 uops were executed per-thread.", "Counter": "0,1,2,3", - "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Actually retired uops.", - "Data_LA": "1", - "PEBS": "1", + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.ALL", - "PublicDescription": "This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "Invert": "1", - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Cycles without actually retired uops.", + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.STALL_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles without actually retired uops.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.THREAD", + "PublicDescription": "Number of uops to be executed per-thread each cycle.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Invert": "1", - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Cycles with less than 10 actually retired uops.", + "BriefDescription": "Cycles per thread when uops are executed in port 0", "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", - "CounterMask": "10", - "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xC2", - "UMask": "0x2", - "BriefDescription": "Retirement slots used.", - "PEBS": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in port 0.", "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", - "PublicDescription": "This event counts the number of retirement slots used.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xC3", - "UMask": "0x1", - "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.", + "BriefDescription": "Cycles per thread when uops are executed in port 1", "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.CYCLES", - "PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EdgeDetect": "1", - "EventCode": "0xC3", - "UMask": "0x1", - "BriefDescription": "Number of machine clears (nukes) of any type.", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in port 1.", "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.COUNT", - "CounterMask": "1", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0xC3", - "UMask": "0x4", - "BriefDescription": "Self-modifying code (SMC) detected.", + "BriefDescription": "Cycles per thread when uops are executed in port 2", "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.SMC", - "PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xC3", - "UMask": "0x20", - "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 2.", "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.MASKMOV", - "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xC4", - "UMask": "0x0", - "BriefDescription": "All (macro) branch instructions retired.", + "BriefDescription": "Cycles per thread when uops are executed in port 3", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "PublicDescription": "This event counts all (macro) branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xC4", - "UMask": "0x1", - "BriefDescription": "Conditional branch instructions retired.", - "PEBS": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 3.", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.CONDITIONAL", - "PublicDescription": "This event counts conditional branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xC4", - "UMask": "0x2", - "BriefDescription": "Direct and indirect near call instructions retired.", - "PEBS": "1", + "BriefDescription": "Cycles per thread when uops are executed in port 4", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "PublicDescription": "This event counts both direct and indirect near call instructions retired.", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0xC4", - "UMask": "0x2", - "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).", - "PEBS": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in port 4.", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", - "PublicDescription": "This event counts both direct and indirect macro near call instructions retired (captured in ring 3).", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0xC4", - "UMask": "0x4", - "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)", - "PEBS": "2", + "BriefDescription": "Cycles per thread when uops are executed in port 5", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", - "Errata": "BDW98", - "PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "EventCode": "0xC4", - "UMask": "0x8", - "BriefDescription": "Return instructions retired.", - "PEBS": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in port 5.", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "PublicDescription": "This event counts return instructions retired.", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "EventCode": "0xC4", - "UMask": "0x10", - "BriefDescription": "Not taken branch instructions retired.", + "BriefDescription": "Cycles per thread when uops are executed in port 6", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "PublicDescription": "This event counts not taken branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "EventCode": "0xC4", - "UMask": "0x20", - "BriefDescription": "Taken branch instructions retired.", - "PEBS": "1", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in port 6.", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "PublicDescription": "This event counts taken branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "EventCode": "0xC4", - "UMask": "0x40", - "BriefDescription": "Far branch instructions retired.", + "BriefDescription": "Cycles per thread when uops are executed in port 7", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "Errata": "BDW98", - "PublicDescription": "This event counts far branch instructions retired.", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { - "EventCode": "0xC5", - "UMask": "0x0", - "BriefDescription": "All mispredicted macro branch instructions retired.", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 7.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "PublicDescription": "This event counts all mispredicted macro branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { - "EventCode": "0xC5", - "UMask": "0x1", - "BriefDescription": "Mispredicted conditional branch instructions retired.", - "PEBS": "1", + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "PublicDescription": "This event counts mispredicted conditional branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xC5", - "UMask": "0x4", - "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)", - "PEBS": "2", + "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", - "PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0xC5", - "UMask": "0x8", - "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", - "PEBS": "1", + "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.RET", - "PublicDescription": "This event counts mispredicted return instructions retired.", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "EventCode": "0xC5", - "UMask": "0x20", - "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", + "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", + "PublicDescription": "This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retirement slots used.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "PublicDescription": "Number of near branch instructions retired that were mispredicted and taken.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", + "PublicDescription": "This event counts the number of retirement slots used.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0xCC", - "UMask": "0x20", - "BriefDescription": "Count cases of saving new LBR", + "BriefDescription": "Cycles without actually retired uops.", "Counter": "0,1,2,3", - "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", - "PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles without actually retired uops.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xe6", - "UMask": "0x1f", - "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", + "BriefDescription": "Cycles with less than 10 actually retired uops.", "Counter": "0,1,2,3", - "EventName": "BACLEARS.ANY", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "CounterMask": "16", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } -]
\ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json index 58ed6d33d1f4..449fa723d0aa 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json @@ -1,12 +1,63 @@ [ { - "BriefDescription": "Uncore cache clock ticks", + "BriefDescription": "Bounce Control", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_C_BOUNCE_CONTROL", + "PerPkg": "1", + "Unit": "CBO" + }, + { + "BriefDescription": "Uncore Clocks", "Counter": "0,1,2,3", "EventName": "UNC_C_CLOCKTICKS", "PerPkg": "1", "Unit": "CBO" }, { + "BriefDescription": "Counter 0 Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x1F", + "EventName": "UNC_C_COUNTER0_OCCUPANCY", + "PerPkg": "1", + "Unit": "CBO" + }, + { + "BriefDescription": "FaST wire asserted", + "Counter": "0,1", + "EventCode": "0x9", + "EventName": "UNC_C_FAST_ASSERTED", + "PerPkg": "1", + "Unit": "CBO" + }, + { + "BriefDescription": "Cache Lookups; Data Read Request", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.DATA_READ", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "CBO" + }, + { + "BriefDescription": "Cache Lookups; Write Requests", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.WRITE", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "CBO" + }, + { + "BriefDescription": "Cache Lookups; External Snoop Request", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "CBO" + }, + { "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)", "Counter": "0,1,2,3", "EventCode": "0x34", @@ -18,6 +69,24 @@ "Unit": "CBO" }, { + "BriefDescription": "Cache Lookups; Lookups that Match NID", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.NID", + "PerPkg": "1", + "UMask": "0x41", + "Unit": "CBO" + }, + { + "BriefDescription": "Cache Lookups; Any Read Request", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.READ", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CBO" + }, + { "BriefDescription": "M line evictions from LLC (writebacks to memory)", "Counter": "0,1,2,3", "EventCode": "0x37", @@ -28,6 +97,865 @@ "Unit": "CBO" }, { + "BriefDescription": "Lines Victimized; Lines in E state", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.E_STATE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Lines Victimized; Lines in S State", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.I_STATE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Lines Victimized", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.F_STATE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "Lines Victimized; Victimized Lines that Match NID", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.NID", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CBO" + }, + { + "BriefDescription": "Lines Victimized", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.MISS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Cbo Misc; Silent Snoop Eviction", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_C_MISC.RSPI_WAS_FSE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Cbo Misc; Write Combining Aliasing", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_C_MISC.WC_ALIASING", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Cbo Misc", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_C_MISC.STARTED", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Cbo Misc; RFO HitS", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_C_MISC.RFO_HIT_S", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "Cbo Misc; Clean Victim with raw CV=0", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_C_MISC.CVZERO_PREFETCH_VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=0", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_C_MISC.CVZERO_PREFETCH_MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CBO" + }, + { + "BriefDescription": "AD Ring In Use; Up and Even", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_C_RING_AD_USED.UP_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "AD Ring In Use; Up and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_C_RING_AD_USED.UP_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "AD Ring In Use; Down and Even", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_C_RING_AD_USED.DOWN_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "AD Ring In Use; Down and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_C_RING_AD_USED.DOWN_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "AD Ring In Use; Up", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_C_RING_AD_USED.UP", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "CBO" + }, + { + "BriefDescription": "AD Ring In Use; Down", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_C_RING_AD_USED.DOWN", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "CBO" + }, + { + "BriefDescription": "AD Ring In Use; All", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_C_RING_AD_USED.ALL", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "CBO" + }, + { + "BriefDescription": "AK Ring In Use; Up and Even", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_C_RING_AK_USED.UP_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "AK Ring In Use; Up and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_C_RING_AK_USED.UP_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "AK Ring In Use; Down and Even", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_C_RING_AK_USED.DOWN_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "AK Ring In Use; Down and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_C_RING_AK_USED.DOWN_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "AK Ring In Use; Up", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_C_RING_AK_USED.UP", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "CBO" + }, + { + "BriefDescription": "AK Ring In Use; Down", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_C_RING_AK_USED.DOWN", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "CBO" + }, + { + "BriefDescription": "AK Ring In Use; All", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_C_RING_AK_USED.ALL", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Up and Even", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_C_RING_BL_USED.UP_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Up and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_C_RING_BL_USED.UP_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Down and Even", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_C_RING_BL_USED.DOWN_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Down and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_C_RING_BL_USED.DOWN_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Up", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_C_RING_BL_USED.UP", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Down", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_C_RING_BL_USED.DOWN", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Down", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_C_RING_BL_USED.ALL", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "CBO" + }, + { + "BriefDescription": "Number of LLC responses that bounced on the Ring.; AD", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_C_RING_BOUNCES.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Number of LLC responses that bounced on the Ring.; AK", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_C_RING_BOUNCES.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Number of LLC responses that bounced on the Ring.; BL", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_C_RING_BOUNCES.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_C_RING_BOUNCES.IV", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Any", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_C_RING_IV_USED.ANY", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Any", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_C_RING_IV_USED.UP", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Down", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_C_RING_IV_USED.DOWN", + "PerPkg": "1", + "UMask": "0xCC", + "Unit": "CBO" + }, + { + "BriefDescription": "BL Ring in Use; Any", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_C_RING_IV_USED.DN", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "CBO" + }, + { + "BriefDescription": "Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_C_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_C_RxR_EXT_STARVED.IRQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_C_RxR_EXT_STARVED.IPQ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Arbiter Blocking Cycles; PRQ", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_C_RxR_EXT_STARVED.PRQ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Allocations; IRQ", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_C_RxR_INSERTS.IRQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Allocations; IRQ Rejected", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_C_RxR_INSERTS.IRQ_REJ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Allocations; IPQ", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_C_RxR_INSERTS.IPQ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Allocations; PRQ", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_C_RxR_INSERTS.PRQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Allocations; PRQ", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_C_RxR_INSERTS.PRQ_REJ", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CBO" + }, + { + "BriefDescription": "Probe Queue Retries; Any Reject", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_C_RxR_IPQ_RETRY.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Probe Queue Retries; No Egress Credits", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_C_RxR_IPQ_RETRY.FULL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Probe Queue Retries; Address Conflict", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Probe Queue Retries; No QPI Credits", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Probe Queue Retries; No AD Sbo Credits", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_C_RxR_IPQ_RETRY2.AD_SBO", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Probe Queue Retries; Target Node Filter", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_C_RxR_IPQ_RETRY2.TARGET", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; Any Reject", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; No Egress Credits", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.FULL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; Address Conflict", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; No RTIDs", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.RTID", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_C_RxR_IRQ_RETRY.NID", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; No AD Sbo Credits", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_C_RxR_IRQ_RETRY2.AD_SBO", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; No BL Sbo Credits", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_C_RxR_IRQ_RETRY2.BL_SBO", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Request Queue Rejects; Target Node Filter", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_C_RxR_IRQ_RETRY2.TARGET", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries; Any Reject", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries; No Egress Credits", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.FULL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries; No RTIDs", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries; No QPI Credits", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries; No IIO Credits", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_C_RxR_ISMQ_RETRY.NID", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Request Queue Rejects; No AD Sbo Credits", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_C_RxR_ISMQ_RETRY2.AD_SBO", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Request Queue Rejects; No BL Sbo Credits", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_C_RxR_ISMQ_RETRY2.BL_SBO", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "ISMQ Request Queue Rejects; Target Node Filter", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_C_RxR_ISMQ_RETRY2.TARGET", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Occupancy; IRQ", + "EventCode": "0x11", + "EventName": "UNC_C_RxR_OCCUPANCY.IRQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Occupancy; IRQ Rejected", + "EventCode": "0x11", + "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Occupancy; IPQ", + "EventCode": "0x11", + "EventName": "UNC_C_RxR_OCCUPANCY.IPQ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Occupancy; PRQ Rejects", + "EventCode": "0x11", + "EventName": "UNC_C_RxR_OCCUPANCY.PRQ_REJ", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CBO" + }, + { + "BriefDescription": "SBo Credits Acquired; For AD Ring", + "Counter": "0,1,2,3", + "EventCode": "0x3D", + "EventName": "UNC_C_SBO_CREDITS_ACQUIRED.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "SBo Credits Acquired; For BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x3D", + "EventName": "UNC_C_SBO_CREDITS_ACQUIRED.BL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "SBo Credits Occupancy; For AD Ring", + "EventCode": "0x3E", + "EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "SBo Credits Occupancy; For BL Ring", + "EventCode": "0x3E", + "EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.BL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Opcode Match", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.OPCODE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE", + "Filter": "filter_opc=0x180,filter_tid=0x3e", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "L2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "LLC_REFERENCES.CODE_LLC_PREFETCH", + "Filter": "filter_opc=0x181", + "PerPkg": "1", + "ScaleUnit": "64Bytes", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "LLC_REFERENCES.STREAMING_FULL", + "Filter": "filter_opc=0x18c", + "PerPkg": "1", + "ScaleUnit": "64Bytes", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", + "Filter": "filter_opc=0x18d", + "PerPkg": "1", + "ScaleUnit": "64Bytes", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "PCIe read current. Derived from unc_c_tor_inserts.opcode", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "LLC_REFERENCES.PCIE_READ", + "Filter": "filter_opc=0x19e", + "PerPkg": "1", + "ScaleUnit": "64Bytes", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "LLC_REFERENCES.PCIE_WRITE", + "Filter": "filter_opc=0x1c8,filter_tid=0x3e", + "PerPkg": "1", + "ScaleUnit": "64Bytes", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Evictions", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.EVICTION", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; All", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.ALL", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Writebacks", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Miss Opcode Match", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "CBO" + }, + { "BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode", "Counter": "0,1,2,3", "EventCode": "0x35", @@ -138,71 +1066,156 @@ "Unit": "CBO" }, { - "BriefDescription": "PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode", + "BriefDescription": "TOR Inserts; NID and Opcode Matched", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE", - "Filter": "filter_opc=0x180,filter_tid=0x3e", + "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0x41", "Unit": "CBO" }, { - "BriefDescription": "L2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode", + "BriefDescription": "TOR Inserts; NID Matched Evictions", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "LLC_REFERENCES.CODE_LLC_PREFETCH", - "Filter": "filter_opc=0x181", + "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", + "UMask": "0x44", "Unit": "CBO" }, { - "BriefDescription": "Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode", + "BriefDescription": "TOR Inserts; NID Matched", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "LLC_REFERENCES.STREAMING_FULL", - "Filter": "filter_opc=0x18c", + "EventName": "UNC_C_TOR_INSERTS.NID_ALL", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", + "UMask": "0x48", "Unit": "CBO" }, { - "BriefDescription": "Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode", + "BriefDescription": "TOR Inserts; NID Matched Writebacks", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", - "Filter": "filter_opc=0x18d", + "EventName": "UNC_C_TOR_INSERTS.NID_WB", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", + "UMask": "0x50", "Unit": "CBO" }, { - "BriefDescription": "PCIe read current. Derived from unc_c_tor_inserts.opcode", + "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "LLC_REFERENCES.PCIE_READ", - "Filter": "filter_opc=0x19e", + "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", + "UMask": "0x43", "Unit": "CBO" }, { - "BriefDescription": "PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode", + "BriefDescription": "TOR Inserts; NID Matched Miss All", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "LLC_REFERENCES.PCIE_WRITE", - "Filter": "filter_opc=0x1c8,filter_tid=0x3e", + "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL", + "PerPkg": "1", + "UMask": "0x4A", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Misses to Local Memory", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL", + "PerPkg": "1", + "UMask": "0x2A", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Misses to Remote Memory", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE", + "PerPkg": "1", + "UMask": "0x8A", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Local Memory", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOCAL", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Remote Memory", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.REMOTE", + "PerPkg": "1", + "UMask": "0x88", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE", + "PerPkg": "1", + "UMask": "0x23", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE", + "PerPkg": "1", + "UMask": "0x83", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE", + "PerPkg": "1", + "UMask": "0x81", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Opcode Match", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE", "PerPkg": "1", - "ScaleUnit": "64Bytes", "UMask": "0x1", "Unit": "CBO" }, { + "BriefDescription": "TOR Occupancy; Evictions", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.EVICTION", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Any", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CBO" + }, + { "BriefDescription": "Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LLC_DATA_READ", @@ -212,7 +1225,1090 @@ "Unit": "CBO" }, { - "BriefDescription": "read requests to home agent", + "BriefDescription": "Occupancy counter for LLC data reads (demand and L2 prefetch)", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE", + "Filter": "filter_opc=0x182", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Miss All", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID and Opcode Matched", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE", + "PerPkg": "1", + "UMask": "0x41", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID Matched Evictions", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID Matched", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL", + "PerPkg": "1", + "UMask": "0x48", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE", + "PerPkg": "1", + "UMask": "0x43", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID Matched", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL", + "PerPkg": "1", + "UMask": "0x4A", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL", + "PerPkg": "1", + "UMask": "0x2A", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE", + "PerPkg": "1", + "UMask": "0x8A", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE", + "PerPkg": "1", + "UMask": "0x88", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcode Matched", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE", + "PerPkg": "1", + "UMask": "0x23", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opcode Matched", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE", + "PerPkg": "1", + "UMask": "0x83", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Remote Memory - Opcode Matched", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE", + "PerPkg": "1", + "UMask": "0x81", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; Writebacks", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "TOR Occupancy; NID Matched Writebacks", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB", + "PerPkg": "1", + "UMask": "0x50", + "Unit": "CBO" + }, + { + "BriefDescription": "Onto AD Ring", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_C_TxR_ADS_USED.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Onto AK Ring", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_C_TxR_ADS_USED.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Onto BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_C_TxR_ADS_USED.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; AD - Cachebo", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.AD_CACHE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; AK - Cachebo", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.AK_CACHE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; BL - Cacheno", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.BL_CACHE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; IV - Cachebo", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.IV_CACHE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; AD - Corebo", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.AD_CORE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; AK - Corebo", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.AK_CORE", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CBO" + }, + { + "BriefDescription": "Egress Allocations; BL - Corebo", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_C_TxR_INSERTS.BL_CORE", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CBO" + }, + { + "BriefDescription": "LRU Queue; LRU Age 0", + "Counter": "0,1,2,3", + "EventCode": "0x3C", + "EventName": "UNC_C_QLRU.AGE0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "LRU Queue; LRU Age 1", + "Counter": "0,1,2,3", + "EventCode": "0x3C", + "EventName": "UNC_C_QLRU.AGE1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "LRU Queue; LRU Age 2", + "Counter": "0,1,2,3", + "EventCode": "0x3C", + "EventName": "UNC_C_QLRU.AGE2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "LRU Queue; LRU Age 3", + "Counter": "0,1,2,3", + "EventCode": "0x3C", + "EventName": "UNC_C_QLRU.AGE3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "LRU Queue; LRU Bits Decremented", + "Counter": "0,1,2,3", + "EventCode": "0x3C", + "EventName": "UNC_C_QLRU.LRU_DECREMENT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "LRU Queue; Non-0 Aged Victim", + "Counter": "0,1,2,3", + "EventCode": "0x3C", + "EventName": "UNC_C_QLRU.VICTIM_NON_ZERO", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CBO" + }, + { + "BriefDescription": "AD", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_C_RING_SINK_STARVED.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "AK", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_C_RING_SINK_STARVED.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "IV", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_C_RING_SINK_STARVED.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "BL", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_C_RING_SINK_STARVED.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Internal Starvation Cycles; IRQ", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_C_RxR_INT_STARVED.IRQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Internal Starvation Cycles; IPQ", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_C_RxR_INT_STARVED.IPQ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_C_RxR_INT_STARVED.ISMQ", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "Ingress Internal Starvation Cycles; PRQ", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_C_RxR_INT_STARVED.PRQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "Injection Starvation; Onto AK Ring", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_C_TxR_STARVED.AK_BOTH", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CBO" + }, + { + "BriefDescription": "Injection Starvation; Onto BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_C_TxR_STARVED.BL_BOTH", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CBO" + }, + { + "BriefDescription": "Injection Starvation; Onto IV Ring", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_C_TxR_STARVED.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CBO" + }, + { + "BriefDescription": "Injection Starvation; Onto AD Ring (to core)", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_C_TxR_STARVED.AD_CORE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CBO" + }, + { + "BriefDescription": "QPI Address/Opcode Match; Address & Opcode Match", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_ADDR_OPC_MATCH.FILT", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "QPI Address/Opcode Match; Address", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_ADDR_OPC_MATCH.ADDR", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "QPI Address/Opcode Match; Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_ADDR_OPC_MATCH.OPC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "QPI Address/Opcode Match; AD Opcodes", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_ADDR_OPC_MATCH.AD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "QPI Address/Opcode Match; BL Opcodes", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_ADDR_OPC_MATCH.BL", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "QPI Address/Opcode Match; AK Opcodes", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_H_ADDR_OPC_MATCH.AK", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "BT Cycles Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x42", + "EventName": "UNC_H_BT_CYCLES_NE", + "PerPkg": "1", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Bypass; Taken", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_H_BYPASS_IMC.TAKEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Bypass; Not Taken", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "uclks", + "Counter": "0,1,2,3", + "EventName": "UNC_H_CLOCKTICKS", + "PerPkg": "1", + "Unit": "HA" + }, + { + "BriefDescription": "Direct2Core Messages Sent", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_H_DIRECT2CORE_COUNT", + "PerPkg": "1", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles when Direct2Core was Disabled", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED", + "PerPkg": "1", + "Unit": "HA" + }, + { + "BriefDescription": "Number of Reads that had Direct2Core Overridden", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE", + "PerPkg": "1", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Lat Opt Return", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_H_DIRECTORY_LAT_OPT", + "PerPkg": "1", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Lookups; Snoop Needed", + "Counter": "0,1,2,3", + "EventCode": "0xC", + "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Lookups; Snoop Not Needed", + "Counter": "0,1,2,3", + "EventCode": "0xC", + "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Updates; Directory Set", + "Counter": "0,1,2,3", + "EventCode": "0xD", + "EventName": "UNC_H_DIRECTORY_UPDATE.SET", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Updates; Directory Clear", + "Counter": "0,1,2,3", + "EventCode": "0xD", + "EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Directory Updates; Any Directory Update", + "Counter": "0,1,2,3", + "EventCode": "0xD", + "EventName": "UNC_H_DIRECTORY_UPDATE.ANY", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.WBMTOI", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is AckCnfltWbI", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.RSPFWDS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.RSP", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.ALLOCS", + "PerPkg": "1", + "UMask": "0x70", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.EVICTS", + "PerPkg": "1", + "UMask": "0x42", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; Invalidations", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.INVALS", + "PerPkg": "1", + "UMask": "0x26", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; All Requests", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.ALL", + "PerPkg": "1", + "UMask": "0xFF", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; HOM Requests", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_H_HITME_HIT.HOM", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "HA" + }, + { + "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "HA" + }, + { + "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; All Requests", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL", + "PerPkg": "1", + "UMask": "0xFF", + "Unit": "HA" + }, + { + "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoI", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.WBMTOI", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.RSPFWDS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.RSP", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed; Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.ALLOCS", + "PerPkg": "1", + "UMask": "0x70", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed; Invalidations", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.INVALS", + "PerPkg": "1", + "UMask": "0x26", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed; All Requests", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.ALL", + "PerPkg": "1", + "UMask": "0xFF", + "Unit": "HA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed; HOM Requests", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_H_HITME_LOOKUP.HOM", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 1", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Normal Priority Reads Issued; Normal Priority", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_H_IMC_READS.NORMAL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Retry Events", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_H_IMC_RETRY", + "PerPkg": "1", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH", + "Counter": "0,1,2,3", + "EventCode": "0x1A", + "EventName": "UNC_H_IMC_WRITES.FULL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH", + "Counter": "0,1,2,3", + "EventCode": "0x1A", + "EventName": "UNC_H_IMC_WRITES.PARTIAL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full Line", + "Counter": "0,1,2,3", + "EventCode": "0x1A", + "EventName": "UNC_H_IMC_WRITES.FULL_ISOCH", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial", + "Counter": "0,1,2,3", + "EventCode": "0x1A", + "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes", + "Counter": "0,1,2,3", + "EventCode": "0x1A", + "EventName": "UNC_H_IMC_WRITES.ALL", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Snoop Broadcast; Local Reads", + "Counter": "0,1,2,3", + "EventCode": "0x53", + "EventName": "UNC_H_OSB.READS_LOCAL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Snoop Broadcast; Local InvItoE", + "Counter": "0,1,2,3", + "EventCode": "0x53", + "EventName": "UNC_H_OSB.INVITOE_LOCAL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Snoop Broadcast; Remote", + "Counter": "0,1,2,3", + "EventCode": "0x53", + "EventName": "UNC_H_OSB.REMOTE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Snoop Broadcast; Cancelled", + "Counter": "0,1,2,3", + "EventCode": "0x53", + "EventName": "UNC_H_OSB.CANCELLED", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Snoop Broadcast; Reads Local - Useful", + "Counter": "0,1,2,3", + "EventCode": "0x53", + "EventName": "UNC_H_OSB.READS_LOCAL_USEFUL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Snoop Broadcast; Remote - Useful", + "Counter": "0,1,2,3", + "EventCode": "0x53", + "EventName": "UNC_H_OSB.REMOTE_USEFUL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Early Data Return; All", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "UNC_H_OSB_EDR.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Early Data Return; Reads to Local I", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "UNC_H_OSB_EDR.READS_LOCAL_I", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Early Data Return; Reads to Remote I", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Early Data Return; Reads to Local S", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "OSB Early Data Return; Reads to Remote S", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "UNC_H_OSB_EDR.READS_REMOTE_S", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Read and Write Requests; Reads", "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.READS", @@ -221,7 +2317,16 @@ "Unit": "HA" }, { - "BriefDescription": "read requests to local home agent", + "BriefDescription": "Read and Write Requests; Writes", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_H_REQUESTS.WRITES", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "HA" + }, + { + "BriefDescription": "Read and Write Requests; Local Reads", "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.READS_LOCAL", @@ -230,7 +2335,7 @@ "Unit": "HA" }, { - "BriefDescription": "read requests to remote home agent", + "BriefDescription": "Read and Write Requests; Remote Reads", "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.READS_REMOTE", @@ -239,49 +2344,391 @@ "Unit": "HA" }, { - "BriefDescription": "write requests to home agent", + "BriefDescription": "Read and Write Requests; Local Writes", "Counter": "0,1,2,3", "EventCode": "0x1", - "EventName": "UNC_H_REQUESTS.WRITES", + "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", "PerPkg": "1", - "UMask": "0xC", + "UMask": "0x4", "Unit": "HA" }, { - "BriefDescription": "write requests to local home agent", + "BriefDescription": "Read and Write Requests; Remote Writes", "Counter": "0,1,2,3", "EventCode": "0x1", - "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", + "EventName": "UNC_H_REQUESTS.WRITES_REMOTE", "PerPkg": "1", - "UMask": "0x4", + "UMask": "0x8", "Unit": "HA" }, { - "BriefDescription": "write requests to remote home agent", + "BriefDescription": "Read and Write Requests; Local InvItoEs", "Counter": "0,1,2,3", "EventCode": "0x1", - "EventName": "UNC_H_REQUESTS.WRITES_REMOTE", + "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Read and Write Requests; Remote InvItoEs", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x3E", + "EventName": "UNC_H_RING_AD_USED.CW_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x3E", + "EventName": "UNC_H_RING_AD_USED.CW_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x3E", + "EventName": "UNC_H_RING_AD_USED.CCW_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x3E", + "EventName": "UNC_H_RING_AD_USED.CCW_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Clockwise", + "Counter": "0,1,2,3", + "EventCode": "0x3E", + "EventName": "UNC_H_RING_AD_USED.CW", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "HA AD Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", + "EventCode": "0x3E", + "EventName": "UNC_H_RING_AD_USED.CCW", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x3F", + "EventName": "UNC_H_RING_AK_USED.CW_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x3F", + "EventName": "UNC_H_RING_AK_USED.CW_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x3F", + "EventName": "UNC_H_RING_AK_USED.CCW_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x3F", + "EventName": "UNC_H_RING_AK_USED.CCW_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Clockwise", + "Counter": "0,1,2,3", + "EventCode": "0x3F", + "EventName": "UNC_H_RING_AK_USED.CW", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", + "EventCode": "0x3F", + "EventName": "UNC_H_RING_AK_USED.CCW", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CW_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CW_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CCW_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CCW_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Clockwise", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CW", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.CCW", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3", "PerPkg": "1", "UMask": "0x8", "Unit": "HA" }, { - "BriefDescription": "Conflict requests (requests for same address from multiple agents simultaneously)", + "BriefDescription": "SBo0 Credits Acquired; For AD Ring", + "Counter": "0,1,2,3", + "EventCode": "0x68", + "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "SBo0 Credits Acquired; For BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x68", + "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.BL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", + "Counter": "0,1,2,3", + "EventCode": "0x6A", + "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x6A", + "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.BL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "SBo1 Credits Acquired; For AD Ring", + "Counter": "0,1,2,3", + "EventCode": "0x69", + "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "SBo1 Credits Acquired; For BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x69", + "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.BL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "SBo1 Credits Occupancy; For AD Ring", + "Counter": "0,1,2,3", + "EventCode": "0x6B", + "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "SBo1 Credits Occupancy; For BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x6B", + "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.BL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Data beat the Snoop Responses; Local Requests", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Data beat the Snoop Responses; Remote Requests", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles with Snoops Outstanding; Local Requests", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_H_SNOOP_CYCLES_NE.LOCAL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles with Snoops Outstanding; Remote Requests", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_H_SNOOP_CYCLES_NE.REMOTE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Cycles with Snoops Outstanding; All Requests", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_H_SNOOP_CYCLES_NE.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Snoops Outstanding Accumulator; Local Requests", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_H_SNOOP_OCCUPANCY.LOCAL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Snoops Outstanding Accumulator; Remote Requests", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_H_SNOOP_OCCUPANCY.REMOTE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received; RspI", "Counter": "0,1,2,3", "EventCode": "0x21", - "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", + "EventName": "UNC_H_SNOOP_RESP.RSPI", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x1", "Unit": "HA" }, { - "BriefDescription": "M line forwarded from remote cache along with writeback to memory", + "BriefDescription": "Shared line response from remote cache", "Counter": "0,1,2,3", "EventCode": "0x21", - "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", + "EventName": "UNC_H_SNOOP_RESP.RSPS", "PerPkg": "1", "ScaleUnit": "64Bytes", - "UMask": "0x20", + "UMask": "0x2", "Unit": "HA" }, { @@ -295,23 +2742,905 @@ "Unit": "HA" }, { - "BriefDescription": "Shared line response from remote cache", + "BriefDescription": "Shared line forwarded from remote cache", "Counter": "0,1,2,3", "EventCode": "0x21", - "EventName": "UNC_H_SNOOP_RESP.RSPS", + "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", "PerPkg": "1", "ScaleUnit": "64Bytes", - "UMask": "0x2", + "UMask": "0x8", "Unit": "HA" }, { - "BriefDescription": "Shared line forwarded from remote cache", + "BriefDescription": "Snoop Responses Received; Rsp*WB", "Counter": "0,1,2,3", "EventCode": "0x21", - "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", + "EventName": "UNC_H_SNOOP_RESP.RSP_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "M line forwarded from remote cache along with writeback to memory", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", "PerPkg": "1", "ScaleUnit": "64Bytes", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received; RSPCNFLCT*", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspI", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspS", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspIFwd", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspSFwd", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; Rsp*WB", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspCnflct", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "Snoop Responses Received Local; Other", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "HA" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", + "Counter": "0,1,2,3", + "EventCode": "0x6C", + "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", + "Counter": "0,1,2,3", + "EventCode": "0x6C", + "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x6C", + "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x6C", + "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 0", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 1", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 2", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 3", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 4", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 5", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 6", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 7", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_H_TAD_REQUESTS_G0.REGION7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 8", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_H_TAD_REQUESTS_G1.REGION8", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 9", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_H_TAD_REQUESTS_G1.REGION9", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Cycles Full; Cycles GP Completely Used", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_H_TRACKER_CYCLES_FULL.GP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Cycles Full; Cycles Completely Used", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_H_TRACKER_CYCLES_FULL.ALL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Cycles Not Empty; Local Requests", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Cycles Not Empty; Remote Requests", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Cycles Not Empty; All Requests", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_H_TRACKER_CYCLES_NE.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Occupancy Accumultor; Local Read Requests", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Occupancy Accumultor; Remote Read Requests", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Occupancy Accumultor; Local Write Requests", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Occupancy Accumultor; Remote Write Requests", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE Requests", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "HA" + }, + { + "BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE Requests", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "HA" + }, + { + "BriefDescription": "Data Pending Occupancy Accumultor; Local Requests", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Data Pending Occupancy Accumultor; Remote Requests", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Full; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Full; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Full; All", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Full; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Full; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Full; All", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_H_TxR_BL.DRS_CACHE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_H_TxR_BL.DRS_CORE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_H_TxR_BL.DRS_QPI", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Full; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x36", + "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Full; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x36", + "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Full; All", + "Counter": "0,1,2,3", + "EventCode": "0x36", + "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "Injection Starvation; For AK Ring", + "Counter": "0,1,2,3", + "EventCode": "0x6D", + "EventName": "UNC_H_TxR_STARVED.AK", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "Injection Starvation; For BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x6D", + "EventName": "UNC_H_TxR_STARVED.BL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "HA" + }, + { + "BriefDescription": "IOT Backpressure", + "Counter": "0,1,2", + "EventCode": "0x61", + "EventName": "UNC_H_IOT_BACKPRESSURE.SAT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "IOT Backpressure", + "Counter": "0,1,2", + "EventCode": "0x61", + "EventName": "UNC_H_IOT_BACKPRESSURE.HUB", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", + "EventCode": "0x64", + "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", + "EventCode": "0x64", + "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Hi", + "Counter": "0,1,2", + "EventCode": "0x65", + "EventName": "UNC_H_IOT_CTS_HI.CTS2", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Hi", + "Counter": "0,1,2", + "EventCode": "0x65", + "EventName": "UNC_H_IOT_CTS_HI.CTS3", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", + "EventCode": "0x62", + "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", + "EventCode": "0x62", + "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "HA" + }, + { + "BriefDescription": "Outbound NDR Ring Transactions; Non-data Responses", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "UNC_H_TxR_AD.HOM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Not Empty; All", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_H_TxR_AD_INSERTS.SCHED0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_H_TxR_AD_INSERTS.SCHED1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AD Egress Allocations; All", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_H_TxR_AD_INSERTS.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Not Empty; All", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_H_TxR_AK_INSERTS.SCHED0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_H_TxR_AK_INSERTS.SCHED1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "AK Egress Allocations; All", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_H_TxR_AK_INSERTS.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Not Empty; All", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_H_TxR_BL_INSERTS.SCHED0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_H_TxR_BL_INSERTS.SCHED1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "BL Egress Allocations; All", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_H_TxR_BL_INSERTS.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "HA" + }, + { + "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 3", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3", + "PerPkg": "1", "UMask": "0x8", "Unit": "HA" + }, + { + "BriefDescription": "HA AK Ring in Use; All", + "Counter": "0,1,2,3", + "EventCode": "0x3F", + "EventName": "UNC_H_RING_AK_USED.ALL", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "HA" + }, + { + "BriefDescription": "HA BL Ring in Use; All", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_H_RING_BL_USED.ALL", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "HA" } ] diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json index 824961318c1e..cb1916f52607 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json @@ -1,6 +1,6 @@ [ { - "BriefDescription": "QPI clock ticks", + "BriefDescription": "Number of qfclks", "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_Q_CLOCKTICKS", @@ -8,6 +8,691 @@ "Unit": "QPI LL" }, { + "BriefDescription": "Count of CTO Events", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_Q_CTO_COUNT", + "ExtSel": "1", + "PerPkg": "1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Success", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Invalid", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_MISS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Cycles in L1", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_Q_L1_POWER_CYCLES", + "PerPkg": "1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Cycles in L0p", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_Q_RxL0P_POWER_CYCLES", + "PerPkg": "1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Cycles in L0", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "UNC_Q_RxL0_POWER_CYCLES", + "PerPkg": "1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Bypassed", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_Q_RxL_BYPASSED", + "PerPkg": "1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN0 Credit Consumed; DRS", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN0 Credit Consumed; NCB", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN0 Credit Consumed; NCS", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN0 Credit Consumed; HOM", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN0 Credit Consumed; SNP", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN0 Credit Consumed; NDR", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN1 Credit Consumed; DRS", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN1 Credit Consumed; NCB", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN1 Credit Consumed; NCS", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN1 Credit Consumed; HOM", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN1 Credit Consumed; SNP", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VN1 Credit Consumed; NDR", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VNA Credit Consumed", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA", + "ExtSel": "1", + "PerPkg": "1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_Q_RxL_CYCLES_NE", + "PerPkg": "1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 0; Idle and Null Flits", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_RxL_FLITS_G0.IDLE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 1; SNP Flits", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.SNP", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 1; HOM Request Flits", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 1; HOM Flits", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.HOM", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 1; DRS Data Flits", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 1; DRS Header Flits", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.DRS", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x18", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NCB", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NCS", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_Q_RxL_INSERTS", + "PerPkg": "1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_Q_RxL_INSERTS_DRS.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_Q_RxL_INSERTS_DRS.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0xC", + "EventName": "UNC_Q_RxL_INSERTS_HOM.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0xC", + "EventName": "UNC_Q_RxL_INSERTS_HOM.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_Q_RxL_INSERTS_NCB.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_Q_RxL_INSERTS_NCB.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0xB", + "EventName": "UNC_Q_RxL_INSERTS_NCS.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0xB", + "EventName": "UNC_Q_RxL_INSERTS_NCS.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0xE", + "EventName": "UNC_Q_RxL_INSERTS_NDR.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0xE", + "EventName": "UNC_Q_RxL_INSERTS_NDR.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0xD", + "EventName": "UNC_Q_RxL_INSERTS_SNP.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0xD", + "EventName": "UNC_Q_RxL_INSERTS_SNP.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets", + "Counter": "0,1,2,3", + "EventCode": "0xB", + "EventName": "UNC_Q_RxL_OCCUPANCY", + "PerPkg": "1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - DRS; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - DRS; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - HOM; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - HOM; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - NCB; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - NCB; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - NCS; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - NCS; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - NDR; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x1A", + "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - NDR; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x1A", + "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - SNP; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - SNP; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Cycles in L0p", + "Counter": "0,1,2,3", + "EventCode": "0xD", + "EventName": "UNC_Q_TxL0P_POWER_CYCLES", + "PerPkg": "1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Cycles in L0", + "Counter": "0,1,2,3", + "EventCode": "0xC", + "EventName": "UNC_Q_TxL0_POWER_CYCLES", + "PerPkg": "1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Tx Flit Buffer Bypassed", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_Q_TxL_BYPASSED", + "PerPkg": "1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Tx Flit Buffer Cycles not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_Q_TxL_CYCLES_NE", + "PerPkg": "1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G0.DATA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { "BriefDescription": "Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data", "Counter": "0,1,2,3", "EventName": "QPI_DATA_BANDWIDTH_TX", @@ -17,6 +702,14 @@ "Unit": "QPI LL" }, { + "BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { "BriefDescription": "Number of non data (control) flits transmitted . Derived from unc_q_txl_flits_g0.non_data", "Counter": "0,1,2,3", "EventName": "QPI_CTL_BANDWIDTH_TX", @@ -24,5 +717,736 @@ "ScaleUnit": "8Bytes", "UMask": "0x4", "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 1; SNP Flits", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G1.SNP", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 1; HOM Flits", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G1.HOM", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)", + "Counter": "0,1,2,3", + "EventName": "UNC_Q_TxL_FLITS_G1.DRS", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x18", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Coherent data Tx Flits", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Coherent non-data Tx Flits", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NCB", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NCS", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Tx Flit Buffer Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_Q_TxL_INSERTS", + "PerPkg": "1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Tx Flit Buffer Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_Q_TxL_OCCUPANCY", + "PerPkg": "1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED", + "ExtSel": "1", + "PerPkg": "1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY", + "ExtSel": "1", + "PerPkg": "1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for Shared VN", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x1F", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x1F", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for Shared VN", + "Counter": "0,1,2,3", + "EventCode": "0x1F", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VNA Credits Returned", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_Q_VNA_CREDIT_RETURNS", + "ExtSel": "1", + "PerPkg": "1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "VNA Credits Pending Return - Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY", + "ExtSel": "1", + "PerPkg": "1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "CRC Errors Detected; LinkInit", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN0", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN0", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN1", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN1", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - HOM", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_DRS", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - SNP", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCB", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NDR", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCS", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - DRS", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCB", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_SNP", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCS", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; Egress Credits", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; GV", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.GV", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - HOM", + "Counter": "0,1,2,3", + "EventCode": "0x3A", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_DRS", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - SNP", + "Counter": "0,1,2,3", + "EventCode": "0x3A", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCB", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NDR", + "Counter": "0,1,2,3", + "EventCode": "0x3A", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCS", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - DRS", + "Counter": "0,1,2,3", + "EventCode": "0x3A", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCB", + "Counter": "0,1,2,3", + "EventCode": "0x3A", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_SNP", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCS", + "Counter": "0,1,2,3", + "EventCode": "0x3A", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR", + "ExtSel": "1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "QPI LL" + }, + { + "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI LL" } ] diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json index 66eed399724c..05fab7d2723e 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json @@ -1,5 +1,86 @@ [ { + "BriefDescription": "DRAM Activate Count; Activate due to Read", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_M_ACT_COUNT.RD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Activate Count; Activate due to Write", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_M_ACT_COUNT.WR", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Activate Count; Activate due to Write", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_M_ACT_COUNT.BYP", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "ACT command issued by 2 cycle bypass", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_M_BYP_CMDS.ACT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "CAS command issued by 2 cycle bypass", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_M_BYP_CMDS.CAS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "PRE command issued by 2 cycle bypass", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_M_BYP_CMDS.PRE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_REG", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd", "Counter": "0,1,2,3", "EventCode": "0x4", @@ -10,6 +91,33 @@ "Unit": "iMC" }, { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.WR_WMM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.WR_RMM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.WR", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr", "Counter": "0,1,2,3", "EventCode": "0x4", @@ -20,44 +128,313 @@ "Unit": "iMC" }, { - "BriefDescription": "Memory controller clock ticks", + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)", "Counter": "0,1,2,3", - "EventName": "UNC_M_CLOCKTICKS", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.ALL", "PerPkg": "1", + "UMask": "0xF", "Unit": "iMC" }, { - "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode", + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_WMM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_RMM", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M_CLOCKTICKS_P", + "Counter": "0,1,2,3", + "EventName": "UNC_M_DCLOCKTICKS", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge All Commands", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_M_DRAM_PRE_ALL", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_M_DRAM_REFRESH.PANIC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_M_DRAM_REFRESH.HIGH", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "ECC Correctable Errors", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Cycles in a Major Mode; Read Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.READ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Cycles in a Major Mode; Write Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.WRITE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Cycles in a Major Mode; Partial Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.PARTIAL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.ISOCH", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "Channel DLLOFF Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_M_POWER_CHANNEL_DLLOFF", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Channel PPD Cycles", "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M_POWER_CHANNEL_PPD", - "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.", - "MetricName": "power_channel_ppd %", "PerPkg": "1", "Unit": "iMC" }, { - "BriefDescription": "Cycles all ranks are in critical thermal throttle", + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Critical Throttle Cycles", "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", - "MetricExpr": "(UNC_M_POWER_CRITICAL_THROTTLE_CYCLES / UNC_M_CLOCKTICKS) * 100.", - "MetricName": "power_critical_throttle_cycles %", "PerPkg": "1", "Unit": "iMC" }, { - "BriefDescription": "Cycles Memory is in self refresh power mode", + "BriefDescription": "UNC_M_POWER_PCU_THROTTLING", + "Counter": "0,1,2,3", + "EventCode": "0x42", + "EventName": "UNC_M_POWER_PCU_THROTTLING", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Clock-Enabled Self-Refresh", "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M_POWER_SELF_REFRESH", - "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.", - "MetricName": "power_self_refresh %", "PerPkg": "1", "Unit": "iMC" }, { - "BriefDescription": "Pre-charges due to page misses", + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Preemption Count; Read over Read Preemption", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Preemption Count; Read over Write Preemption", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands.; Precharges due to page miss", "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", @@ -66,7 +443,16 @@ "Unit": "iMC" }, { - "BriefDescription": "Pre-charge for reads", + "BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands.; Precharge due to read", "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.RD", @@ -75,12 +461,2445 @@ "Unit": "iMC" }, { - "BriefDescription": "Pre-charge for writes", + "BriefDescription": "DRAM Precharge commands.; Precharge due to write", "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.WR", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_M_PRE_COUNT.BYP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS issued with LOW priority", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M_RD_CAS_PRIO.LOW", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS issued with MEDIUM priority", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M_RD_CAS_PRIO.MED", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS issued with HIGH priority", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M_RD_CAS_PRIO.HIGH", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M_RD_CAS_PRIO.PANIC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_M_RPQ_CYCLES_NE", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_M_RPQ_INSERTS", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "VMSE MXB write buffer occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_M_VMSE_WR_PUSH.WMM", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_M_VMSE_WR_PUSH.RMM", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter", + "Counter": "0,1,2,3", + "EventCode": "0xC0", + "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Transition from WMM to RMM because of low threshold", + "Counter": "0,1,2,3", + "EventCode": "0xC0", + "EventName": "UNC_M_WMM_TO_RMM.STARVE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Transition from WMM to RMM because of low threshold", + "Counter": "0,1,2,3", + "EventCode": "0xC0", + "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Full Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_M_WPQ_CYCLES_FULL", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_M_WPQ_CYCLES_NE", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_M_WPQ_READ_HIT", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_M_WPQ_WRITE_HIT", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Not getting the requested Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_M_WRONG_MM", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "Clockticks in the Memory Controller using one of the programmable counters", + "Counter": "0,1,2,3", + "EventName": "UNC_M_CLOCKTICKS_P", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter", + "Counter": "FIXED", + "EventCode": "0xff", + "EventName": "UNC_M_CLOCKTICKS", + "PerPkg": "1", + "Unit": "iMC" } ] diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json new file mode 100644 index 000000000000..289a726c9ac3 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json @@ -0,0 +1,3252 @@ +[ + { + "BriefDescription": "Total Write Cache Occupancy; Any Source", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Total Write Cache Occupancy; Select Source", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Clocks in the IRP", + "Counter": "0,1", + "EventName": "UNC_I_CLOCKTICKS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; PCIRdCur", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; CRd", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.CRD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; DRd", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.DRD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; RFO", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.RFO", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; PCIItoM", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.PCITOM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; PCIDCAHin5t", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; WbMtoI", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.WBMTOI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; CLFlush", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Fastpath Requests", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.FAST_REQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Fastpath Rejects", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.FAST_REJ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.2ND_RD_INSERT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.2ND_WR_INSERT", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.FAST_XFER", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.PF_ACK_HINT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Prefetch TimeOut", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.PF_TIMEOUT", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SLOW_I", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SLOW_S", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SLOW_E", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SLOW_M", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.LOST_FWD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Received Invalid", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Received Valid", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Data Throttled", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.DATA_THROTTLE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "AK Ingress Occupancy", + "Counter": "0,1", + "EventCode": "0xA", + "EventName": "UNC_I_RxR_AK_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "UNC_I_RxR_BL_DRS_CYCLES_FULL", + "Counter": "0,1", + "EventCode": "0x4", + "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL Ingress Occupancy - DRS", + "Counter": "0,1", + "EventCode": "0x1", + "EventName": "UNC_I_RxR_BL_DRS_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "UNC_I_RxR_BL_DRS_OCCUPANCY", + "Counter": "0,1", + "EventCode": "0x7", + "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "UNC_I_RxR_BL_NCB_CYCLES_FULL", + "Counter": "0,1", + "EventCode": "0x5", + "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL Ingress Occupancy - NCB", + "Counter": "0,1", + "EventCode": "0x2", + "EventName": "UNC_I_RxR_BL_NCB_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "UNC_I_RxR_BL_NCB_OCCUPANCY", + "Counter": "0,1", + "EventCode": "0x8", + "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "UNC_I_RxR_BL_NCS_CYCLES_FULL", + "Counter": "0,1", + "EventCode": "0x6", + "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL Ingress Occupancy - NCS", + "Counter": "0,1", + "EventCode": "0x3", + "EventName": "UNC_I_RxR_BL_NCS_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "UNC_I_RxR_BL_NCS_OCCUPANCY", + "Counter": "0,1", + "EventCode": "0x9", + "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Miss", + "Counter": "0,1", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.MISS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Hit I", + "Counter": "0,1", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.HIT_I", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Hit E or S", + "Counter": "0,1", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.HIT_ES", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Hit M", + "Counter": "0,1", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.HIT_M", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; SnpCode", + "Counter": "0,1", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.SNPCODE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; SnpData", + "Counter": "0,1", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.SNPDATA", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; SnpInv", + "Counter": "0,1", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.SNPINV", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Reads", + "Counter": "0,1", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.READS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Writes", + "Counter": "0,1", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.WRITES", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Read Prefetches", + "Counter": "0,1", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.RD_PREF", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Write Prefetches", + "Counter": "0,1", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Atomic", + "Counter": "0,1", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.ATOMIC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Other", + "Counter": "0,1", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.OTHER", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Select Source", + "Counter": "0,1", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "No AD Egress Credit Stalls", + "Counter": "0,1", + "EventCode": "0x18", + "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "No BL Egress Credit Stalls", + "Counter": "0,1", + "EventCode": "0x19", + "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", + "EventCode": "0xE", + "EventName": "UNC_I_TxR_DATA_INSERTS_NCB", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", + "EventCode": "0xF", + "EventName": "UNC_I_TxR_DATA_INSERTS_NCS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Request Queue Occupancy", + "Counter": "0,1", + "EventCode": "0xD", + "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Number of uclks in domain", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_R2_CLOCKTICKS", + "PerPkg": "1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI0", + "Counter": "0,1", + "EventCode": "0x2D", + "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI1", + "Counter": "0,1", + "EventCode": "0x2D", + "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", + "Counter": "0,1", + "EventCode": "0x2D", + "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", + "Counter": "0,1", + "EventCode": "0x2D", + "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "AK Ingress Bounced; Up", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_R2_RING_AK_BOUNCES.UP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "AK Ingress Bounced; Dn", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_R2_RING_AK_BOUNCES.DN", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Clockwise", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_R2_RING_IV_USED.CW", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_R2_RING_IV_USED.CCW", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Any", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_R2_RING_IV_USED.ANY", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NCB", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_R2_RxR_CYCLES_NE.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NCS", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_R2_RxR_CYCLES_NE.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Allocations; NCB", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R2_RxR_INSERTS.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Allocations; NCS", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R2_RxR_INSERTS.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; DRS", + "EventCode": "0x13", + "EventName": "UNC_R2_RxR_OCCUPANCY.DRS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "SBo0 Credits Acquired; For AD Ring", + "Counter": "0,1", + "EventCode": "0x28", + "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "SBo0 Credits Acquired; For BL Ring", + "Counter": "0,1", + "EventCode": "0x28", + "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", + "Counter": "0,1", + "EventCode": "0x2C", + "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", + "Counter": "0,1", + "EventCode": "0x2C", + "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", + "Counter": "0,1", + "EventCode": "0x2C", + "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", + "Counter": "0,1", + "EventCode": "0x2C", + "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; AD", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; AK", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; BL", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; AD", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; AK", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; BL", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; AD CCW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.DN_AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; BL CCW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.DN_BL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; AK CCW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.DN_AK", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; AK CCW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.UP_AD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; BL CCW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.UP_BL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; BL CW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.UP_AK", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; DRS", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; NCB", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; NCS", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; DRS", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.DRS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; NCB", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; NCS", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", + "EventCode": "0x2A", + "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", + "EventCode": "0x2A", + "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.BL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; All", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.ALL", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; All", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.ALL", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; All", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.ALL", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Number of uclks in domain", + "Counter": "0,1,2", + "EventCode": "0x1", + "EventName": "UNC_R3_CLOCKTICKS", + "PerPkg": "1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO_15_17", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "R3QPI" + }, + { + "BriefDescription": "HA/R2 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2D", + "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "HA/R2 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2D", + "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "HA/R2 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2D", + "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "HA/R2 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2D", + "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x20", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x20", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x20", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x20", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x20", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x20", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x20", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x21", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x21", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x21", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x21", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2E", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2E", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2E", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", + "EventCode": "0x2E", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x2F", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x2F", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x2F", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x2F", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x2F", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x2F", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", + "EventCode": "0x2F", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Clockwise and Even", + "Counter": "0,1,2", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CW_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd", + "Counter": "0,1,2", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CW_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CCW_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CCW_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Clockwise", + "Counter": "0,1,2", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CW", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Counterclockwise", + "Counter": "0,1,2", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CCW", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Clockwise and Even", + "Counter": "0,1,2", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CW_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd", + "Counter": "0,1,2", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CW_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CCW_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CCW_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Clockwise", + "Counter": "0,1,2", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CW", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Counterclockwise", + "Counter": "0,1,2", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CCW", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Clockwise and Even", + "Counter": "0,1,2", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CW_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd", + "Counter": "0,1,2", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CW_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CCW_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CCW_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Clockwise", + "Counter": "0,1,2", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CW", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Counterclockwise", + "Counter": "0,1,2", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CCW", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 IV Ring in Use; Clockwise", + "Counter": "0,1,2", + "EventCode": "0xA", + "EventName": "UNC_R3_RING_IV_USED.CW", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 IV Ring in Use; Any", + "Counter": "0,1,2", + "EventCode": "0xA", + "EventName": "UNC_R3_RING_IV_USED.ANY", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ring Stop Starved; AK", + "Counter": "0,1,2", + "EventCode": "0xE", + "EventName": "UNC_R3_RING_SINK_STARVED.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; HOM", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.HOM", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; SNP", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.SNP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NDR", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.NDR", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Cycles Not Empty; HOM", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.HOM", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Cycles Not Empty; SNP", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.SNP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Cycles Not Empty; NDR", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NDR", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Cycles Not Empty; DRS", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.DRS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Cycles Not Empty; NCB", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Cycles Not Empty; NCS", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; HOM", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.HOM", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; SNP", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.SNP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; NDR", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.NDR", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; DRS", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.DRS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; NCB", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; NCS", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Allocations; HOM", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_R3_RxR_INSERTS_VN1.HOM", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Allocations; SNP", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_R3_RxR_INSERTS_VN1.SNP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Allocations; NDR", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_R3_RxR_INSERTS_VN1.NDR", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Allocations; DRS", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_R3_RxR_INSERTS_VN1.DRS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Allocations; NCB", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_R3_RxR_INSERTS_VN1.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Allocations; NCS", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_R3_RxR_INSERTS_VN1.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Occupancy Accumulator; HOM", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.HOM", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Occupancy Accumulator; SNP", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.SNP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Occupancy Accumulator; NDR", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NDR", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Occupancy Accumulator; DRS", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.DRS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Occupancy Accumulator; NCB", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Occupancy Accumulator; NCS", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "SBo0 Credits Acquired; For AD Ring", + "Counter": "0,1", + "EventCode": "0x28", + "EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "SBo0 Credits Acquired; For BL Ring", + "Counter": "0,1", + "EventCode": "0x28", + "EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.BL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "SBo1 Credits Acquired; For AD Ring", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "SBo1 Credits Acquired; For BL Ring", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.BL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", + "Counter": "0,1", + "EventCode": "0x2C", + "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", + "Counter": "0,1", + "EventCode": "0x2C", + "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", + "Counter": "0,1", + "EventCode": "0x2C", + "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", + "Counter": "0,1", + "EventCode": "0x2C", + "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_BL", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Egress CCW NACK; AD CCW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK.DN_AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Egress CCW NACK; BL CCW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK.DN_BL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Egress CCW NACK; AK CCW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK.DN_AK", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Egress CCW NACK; AK CCW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK.UP_AD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Egress CCW NACK; BL CCW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK.UP_BL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Egress CCW NACK; BL CW", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK.UP_AK", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class", + "Counter": "0,1", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class", + "Counter": "0,1", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class", + "Counter": "0,1", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class", + "Counter": "0,1", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class", + "Counter": "0,1", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class", + "Counter": "0,1", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; HOM Message Class", + "Counter": "0,1", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.HOM", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; SNP Message Class", + "Counter": "0,1", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.SNP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; NDR Message Class", + "Counter": "0,1", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.NDR", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; DRS Message Class", + "Counter": "0,1", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.DRS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; NCB Message Class", + "Counter": "0,1", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; NCS Message Class", + "Counter": "0,1", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Message Class", + "Counter": "0,1", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Message Class", + "Counter": "0,1", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Message Class", + "Counter": "0,1", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Message Class", + "Counter": "0,1", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCB Message Class", + "Counter": "0,1", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCS Message Class", + "Counter": "0,1", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; HOM Message Class", + "Counter": "0,1", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.HOM", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; SNP Message Class", + "Counter": "0,1", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.SNP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; NDR Message Class", + "Counter": "0,1", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.NDR", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; DRS Message Class", + "Counter": "0,1", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.DRS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; NCB Message Class", + "Counter": "0,1", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; NCS Message Class", + "Counter": "0,1", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA credit Acquisitions; HOM Message Class", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA credit Acquisitions; HOM Message Class", + "Counter": "0,1", + "EventCode": "0x33", + "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; HOM Message Class", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; SNP Message Class", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; NDR Message Class", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; DRS Message Class", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; NCB Message Class", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; NCS Message Class", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "IOT Backpressure", + "Counter": "0,1,2", + "EventCode": "0xB", + "EventName": "UNC_R3_IOT_BACKPRESSURE.SAT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "IOT Backpressure", + "Counter": "0,1,2", + "EventCode": "0xB", + "EventName": "UNC_R3_IOT_BACKPRESSURE.HUB", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Hi", + "Counter": "0,1,2", + "EventCode": "0xD", + "EventName": "UNC_R3_IOT_CTS_HI.CTS2", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Hi", + "Counter": "0,1,2", + "EventCode": "0xD", + "EventName": "UNC_R3_IOT_CTS_HI.CTS3", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", + "EventCode": "0xC", + "EventName": "UNC_R3_IOT_CTS_LO.CTS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", + "EventCode": "0xC", + "EventName": "UNC_R3_IOT_CTS_LO.CTS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", + "EventCode": "0x2A", + "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", + "EventCode": "0x2A", + "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.BL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "SBo1 Credits Occupancy; For AD Ring", + "EventCode": "0x2B", + "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "SBo1 Credits Occupancy; For BL Ring", + "EventCode": "0x2B", + "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.BL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; All", + "Counter": "0,1,2", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.ALL", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; All", + "Counter": "0,1,2", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.ALL", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; All", + "Counter": "0,1,2", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.ALL", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Bounce Control", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_S_BOUNCE_CONTROL", + "PerPkg": "1", + "Unit": "SBO" + }, + { + "BriefDescription": "Uncore Clocks", + "Counter": "0,1,2,3", + "EventName": "UNC_S_CLOCKTICKS", + "PerPkg": "1", + "Unit": "SBO" + }, + { + "BriefDescription": "FaST wire asserted", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_S_FAST_ASSERTED", + "PerPkg": "1", + "Unit": "SBO" + }, + { + "BriefDescription": "AD Ring In Use; Up and Even", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_S_RING_AD_USED.UP_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "SBO" + }, + { + "BriefDescription": "AD Ring In Use; Up and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_S_RING_AD_USED.UP_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "SBO" + }, + { + "BriefDescription": "AD Ring In Use; Down and Event", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_S_RING_AD_USED.DOWN_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "SBO" + }, + { + "BriefDescription": "AD Ring In Use; Down and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_S_RING_AD_USED.DOWN_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "SBO" + }, + { + "BriefDescription": "AD Ring In Use; Up", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_S_RING_AD_USED.UP", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "SBO" + }, + { + "BriefDescription": "AD Ring In Use; Down", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_S_RING_AD_USED.DOWN", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "SBO" + }, + { + "BriefDescription": "AK Ring In Use; Up and Even", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_S_RING_AK_USED.UP_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "SBO" + }, + { + "BriefDescription": "AK Ring In Use; Up and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_S_RING_AK_USED.UP_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "SBO" + }, + { + "BriefDescription": "AK Ring In Use; Down and Event", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_S_RING_AK_USED.DOWN_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "SBO" + }, + { + "BriefDescription": "AK Ring In Use; Down and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_S_RING_AK_USED.DOWN_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "SBO" + }, + { + "BriefDescription": "AK Ring In Use; Up", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_S_RING_AK_USED.UP", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "SBO" + }, + { + "BriefDescription": "AK Ring In Use; Down", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_S_RING_AK_USED.DOWN", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "SBO" + }, + { + "BriefDescription": "BL Ring in Use; Up and Even", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_S_RING_BL_USED.UP_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "SBO" + }, + { + "BriefDescription": "BL Ring in Use; Up and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_S_RING_BL_USED.UP_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "SBO" + }, + { + "BriefDescription": "BL Ring in Use; Down and Event", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_S_RING_BL_USED.DOWN_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "SBO" + }, + { + "BriefDescription": "BL Ring in Use; Down and Odd", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_S_RING_BL_USED.DOWN_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "SBO" + }, + { + "BriefDescription": "BL Ring in Use; Up", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_S_RING_BL_USED.UP", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "SBO" + }, + { + "BriefDescription": "BL Ring in Use; Down", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_S_RING_BL_USED.DOWN", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "SBO" + }, + { + "BriefDescription": "Number of LLC responses that bounced on the Ring", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_S_RING_BOUNCES.AD_CACHE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "SBO" + }, + { + "BriefDescription": "Number of LLC responses that bounced on the Ring.; Acknowledgements to core", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_S_RING_BOUNCES.AK_CORE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "SBO" + }, + { + "BriefDescription": "Number of LLC responses that bounced on the Ring.; Data Responses to core", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_S_RING_BOUNCES.BL_CORE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "SBO" + }, + { + "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_S_RING_BOUNCES.IV_CORE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "SBO" + }, + { + "BriefDescription": "BL Ring in Use; Any", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_S_RING_IV_USED.UP", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "SBO" + }, + { + "BriefDescription": "BL Ring in Use; Any", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_S_RING_IV_USED.DN", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "SBO" + }, + { + "BriefDescription": "Bypass; AD - Credits", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_S_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "SBO" + }, + { + "BriefDescription": "Bypass; AD - Bounces", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_S_RxR_BYPASS.AD_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "SBO" + }, + { + "BriefDescription": "Bypass; BL - Credits", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_S_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "SBO" + }, + { + "BriefDescription": "Bypass; BL - Bounces", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_S_RxR_BYPASS.BL_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "SBO" + }, + { + "BriefDescription": "Bypass; AK", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_S_RxR_BYPASS.AK", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "SBO" + }, + { + "BriefDescription": "Bypass; IV", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_S_RxR_BYPASS.IV", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "SBO" + }, + { + "BriefDescription": "Ingress Allocations; AD - Credits", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_S_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "SBO" + }, + { + "BriefDescription": "Ingress Allocations; AD - Bounces", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_S_RxR_INSERTS.AD_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "SBO" + }, + { + "BriefDescription": "Ingress Allocations; BL - Credits", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_S_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "SBO" + }, + { + "BriefDescription": "Ingress Allocations; BL - Bounces", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_S_RxR_INSERTS.BL_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "SBO" + }, + { + "BriefDescription": "Ingress Allocations; AK", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_S_RxR_INSERTS.AK", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "SBO" + }, + { + "BriefDescription": "Ingress Allocations; IV", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_S_RxR_INSERTS.IV", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "SBO" + }, + { + "BriefDescription": "Ingress Occupancy; AD - Credits", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_S_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "SBO" + }, + { + "BriefDescription": "Ingress Occupancy; AD - Bounces", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_S_RxR_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "SBO" + }, + { + "BriefDescription": "Ingress Occupancy; BL - Credits", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_S_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "SBO" + }, + { + "BriefDescription": "Ingress Occupancy; BL - Bounces", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_S_RxR_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "SBO" + }, + { + "BriefDescription": "Ingress Occupancy; AK", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_S_RxR_OCCUPANCY.AK", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "SBO" + }, + { + "BriefDescription": "Ingress Occupancy; IV", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_S_RxR_OCCUPANCY.IV", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "SBO" + }, + { + "BriefDescription": "UNC_S_TxR_ADS_USED.AD", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_S_TxR_ADS_USED.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "SBO" + }, + { + "BriefDescription": "UNC_S_TxR_ADS_USED.AK", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_S_TxR_ADS_USED.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "SBO" + }, + { + "BriefDescription": "UNC_S_TxR_ADS_USED.BL", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_S_TxR_ADS_USED.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "SBO" + }, + { + "BriefDescription": "Egress Allocations; AD - Credits", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_S_TxR_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "SBO" + }, + { + "BriefDescription": "Egress Allocations; AD - Bounces", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_S_TxR_INSERTS.AD_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "SBO" + }, + { + "BriefDescription": "Egress Allocations; BL - Credits", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_S_TxR_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "SBO" + }, + { + "BriefDescription": "Egress Allocations; BL - Bounces", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_S_TxR_INSERTS.BL_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "SBO" + }, + { + "BriefDescription": "Egress Allocations; AK", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_S_TxR_INSERTS.AK", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "SBO" + }, + { + "BriefDescription": "Egress Allocations; IV", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_S_TxR_INSERTS.IV", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "SBO" + }, + { + "BriefDescription": "Egress Occupancy; AD - Credits", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_S_TxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "SBO" + }, + { + "BriefDescription": "Egress Occupancy; AD - Bounces", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_S_TxR_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "SBO" + }, + { + "BriefDescription": "Egress Occupancy; BL - Credits", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_S_TxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "SBO" + }, + { + "BriefDescription": "Egress Occupancy; BL - Bounces", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_S_TxR_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "SBO" + }, + { + "BriefDescription": "Egress Occupancy; AK", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_S_TxR_OCCUPANCY.AK", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "SBO" + }, + { + "BriefDescription": "Egress Occupancy; IV", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_S_TxR_OCCUPANCY.IV", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "SBO" + }, + { + "BriefDescription": "UNC_S_RING_SINK_STARVED.AD_CACHE", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_S_RING_SINK_STARVED.AD_CACHE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "SBO" + }, + { + "BriefDescription": "UNC_S_RING_SINK_STARVED.AK_CORE", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_S_RING_SINK_STARVED.AK_CORE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "SBO" + }, + { + "BriefDescription": "UNC_S_RING_SINK_STARVED.BL_CORE", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_S_RING_SINK_STARVED.BL_CORE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "SBO" + }, + { + "BriefDescription": "UNC_S_RING_SINK_STARVED.IV_CORE", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_S_RING_SINK_STARVED.IV_CORE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "SBO" + }, + { + "BriefDescription": "Injection Starvation; AD - Credits", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_S_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "SBO" + }, + { + "BriefDescription": "Injection Starvation; AD - Bounces", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_S_RxR_BUSY_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "SBO" + }, + { + "BriefDescription": "Injection Starvation; BL - Credits", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_S_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "SBO" + }, + { + "BriefDescription": "Injection Starvation; BL - Bounces", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_S_RxR_BUSY_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "SBO" + }, + { + "BriefDescription": "Injection Starvation; AD - Credits", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_S_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "SBO" + }, + { + "BriefDescription": "Injection Starvation; AD - Bounces", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_S_RxR_CRD_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "SBO" + }, + { + "BriefDescription": "Injection Starvation; BL - Credits", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_S_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "SBO" + }, + { + "BriefDescription": "Injection Starvation; BL - Bounces", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_S_RxR_CRD_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "SBO" + }, + { + "BriefDescription": "Injection Starvation; AK", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_S_RxR_CRD_STARVED.AK", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "SBO" + }, + { + "BriefDescription": "Injection Starvation; IV", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_S_RxR_CRD_STARVED.IV", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "SBO" + }, + { + "BriefDescription": "Injection Starvation; IVF Credit", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_S_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "SBO" + }, + { + "BriefDescription": "Injection Starvation; Onto AD Ring", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_S_TxR_STARVED.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "SBO" + }, + { + "BriefDescription": "Injection Starvation; Onto AK Ring", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_S_TxR_STARVED.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "SBO" + }, + { + "BriefDescription": "Injection Starvation; Onto BL Ring", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_S_TxR_STARVED.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "SBO" + }, + { + "BriefDescription": "Injection Starvation; Onto IV Ring", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_S_TxR_STARVED.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "SBO" + }, + { + "BriefDescription": "AD Ring In Use; All", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_S_RING_AD_USED.ALL", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "SBO" + }, + { + "BriefDescription": "AK Ring In Use; All", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_S_RING_AK_USED.ALL", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "SBO" + }, + { + "BriefDescription": "BL Ring in Use; All", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_S_RING_BL_USED.ALL", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "SBO" + }, + { + "BriefDescription": "VLW Received", + "Counter": "0,1", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", + "Counter": "0,1", + "EventCode": "0x45", + "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "RACU Request", + "Counter": "0,1", + "EventCode": "0x46", + "EventName": "UNC_U_RACU_REQUESTS", + "PerPkg": "1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "Counter": "0,1", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.ENABLE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "Counter": "0,1", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.DISABLE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "Counter": "0,1", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "Counter": "0,1", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Monitor T0", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Monitor T1", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Livelock", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.LIVELOCK", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; LTError", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.LTERROR", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Correctable Machine Check", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.CMC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.UMC", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Trap", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.TRAP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Other", + "Counter": "0,1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.OTHER", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UBOX" + }, + { + "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", + "Counter": "FIXED", + "EventCode": "0xff", + "EventName": "UNC_U_CLOCKTICKS", + "PerPkg": "1", + "Unit": "UBOX" + } +] diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json index dd1b95655d1d..3ffb70ff573d 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json @@ -1,91 +1,456 @@ [ { - "BriefDescription": "PCU clock ticks. Use to get percentages of PCU cycles events", + "BriefDescription": "pclk Cycles", "Counter": "0,1,2,3", "EventName": "UNC_P_CLOCKTICKS", "PerPkg": "1", "Unit": "PCU" }, { - "BriefDescription": "This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details", + "BriefDescription": "Core C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", - "Filter": "occ_sel=1", - "MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C0 / UNC_P_CLOCKTICKS) * 100.", - "MetricName": "power_state_occupancy.cores_c0 %", + "EventCode": "0x60", + "EventName": "UNC_P_CORE0_TRANSITION_CYCLES", "PerPkg": "1", "Unit": "PCU" }, { - "BriefDescription": "This is an occupancy event that tracks the number of cores that are in C3. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details", + "BriefDescription": "Core C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", - "Filter": "occ_sel=2", - "MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C3 / UNC_P_CLOCKTICKS) * 100.", - "MetricName": "power_state_occupancy.cores_c3 %", + "EventCode": "0x6A", + "EventName": "UNC_P_CORE10_TRANSITION_CYCLES", "PerPkg": "1", "Unit": "PCU" }, { - "BriefDescription": "This is an occupancy event that tracks the number of cores that are in C6. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events ", + "BriefDescription": "Core C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", - "Filter": "occ_sel=3", - "MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C6 / UNC_P_CLOCKTICKS) * 100.", - "MetricName": "power_state_occupancy.cores_c6 %", + "EventCode": "0x6B", + "EventName": "UNC_P_CORE11_TRANSITION_CYCLES", "PerPkg": "1", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip", + "BriefDescription": "Core C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0xA", - "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", - "MetricExpr": "(UNC_P_PROCHOT_EXTERNAL_CYCLES / UNC_P_CLOCKTICKS) * 100.", - "MetricName": "prochot_external_cycles %", + "EventCode": "0x6C", + "EventName": "UNC_P_CORE12_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x6D", + "EventName": "UNC_P_CORE13_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x6E", + "EventName": "UNC_P_CORE14_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x6F", + "EventName": "UNC_P_CORE15_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_P_CORE16_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_P_CORE17_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x61", + "EventName": "UNC_P_CORE1_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x62", + "EventName": "UNC_P_CORE2_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x63", + "EventName": "UNC_P_CORE3_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x64", + "EventName": "UNC_P_CORE4_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x65", + "EventName": "UNC_P_CORE5_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x66", + "EventName": "UNC_P_CORE6_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x67", + "EventName": "UNC_P_CORE7_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x68", + "EventName": "UNC_P_CORE8_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x69", + "EventName": "UNC_P_CORE9_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x30", + "EventName": "UNC_P_DEMOTIONS_CORE0", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_P_DEMOTIONS_CORE1", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x3A", + "EventName": "UNC_P_DEMOTIONS_CORE10", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x3B", + "EventName": "UNC_P_DEMOTIONS_CORE11", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x3C", + "EventName": "UNC_P_DEMOTIONS_CORE12", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x3D", + "EventName": "UNC_P_DEMOTIONS_CORE13", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x3E", + "EventName": "UNC_P_DEMOTIONS_CORE14", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x3F", + "EventName": "UNC_P_DEMOTIONS_CORE15", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_P_DEMOTIONS_CORE16", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_P_DEMOTIONS_CORE17", "PerPkg": "1", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles when temperature is the upper limit on frequency", + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_P_DEMOTIONS_CORE2", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_P_DEMOTIONS_CORE3", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_P_DEMOTIONS_CORE4", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_P_DEMOTIONS_CORE5", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x36", + "EventName": "UNC_P_DEMOTIONS_CORE6", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_P_DEMOTIONS_CORE7", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_P_DEMOTIONS_CORE8", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_P_DEMOTIONS_CORE9", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Thermal Strongest Upper Limit Cycles", "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", - "MetricExpr": "(UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES / UNC_P_CLOCKTICKS) * 100.", - "MetricName": "freq_max_limit_thermal_cycles %", "PerPkg": "1", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles when the OS is the upper limit on frequency", + "BriefDescription": "OS Strongest Upper Limit Cycles", "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_P_FREQ_MAX_OS_CYCLES", - "MetricExpr": "(UNC_P_FREQ_MAX_OS_CYCLES / UNC_P_CLOCKTICKS) * 100.", - "MetricName": "freq_max_os_cycles %", "PerPkg": "1", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles when power is the upper limit on frequency", + "BriefDescription": "Power Strongest Upper Limit Cycles", "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", - "MetricExpr": "(UNC_P_FREQ_MAX_POWER_CYCLES / UNC_P_CLOCKTICKS) * 100.", - "MetricName": "freq_max_power_cycles %", "PerPkg": "1", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles when current is the upper limit on frequency", + "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Cycles spent changing Frequency", "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_P_FREQ_TRANS_CYCLES", - "MetricExpr": "(UNC_P_FREQ_TRANS_CYCLES / UNC_P_CLOCKTICKS) * 100.", - "MetricName": "freq_trans_cycles %", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Memory Phase Shedding Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Number of cores in C-State; C0 and C1", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Number of cores in C-State; C3", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Number of cores in C-State; C6 and C7", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "External Prochot", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Internal Prochot", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Total Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "UNC_P_UFS_TRANSITIONS_RING_GV", + "Counter": "0,1,2,3", + "EventCode": "0x79", + "EventName": "UNC_P_UFS_TRANSITIONS_RING_GV", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "VR Hot", + "Counter": "0,1,2,3", + "EventCode": "0x42", + "EventName": "UNC_P_VR_HOT_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C0", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C2E", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C3", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C6", + "Counter": "0,1,2,3", + "EventCode": "0x2D", + "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C7 State Residency", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C1E", + "Counter": "0,1,2,3", + "EventCode": "0x4E", + "EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES", "PerPkg": "1", "Unit": "PCU" } diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json b/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json index 7d79c707c6d1..6a6de8790f25 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json @@ -1,388 +1,388 @@ [ { - "EventCode": "0x08", - "UMask": "0x1", "BriefDescription": "Load misses in all DTLB levels that cause page walks", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x08", - "UMask": "0x2", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", + "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", - "Errata": "BDM69", - "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "EventCode": "0x08", - "UMask": "0x4", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", + "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", - "Errata": "BDM69", - "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x08", - "UMask": "0x8", - "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", + "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", - "Errata": "BDM69", - "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x08", - "UMask": "0xe", "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "EventCode": "0x08", - "UMask": "0x10", - "BriefDescription": "Cycles when PMH is busy with page walks", + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x08", - "UMask": "0x20", - "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x08", - "UMask": "0x40", - "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x08", - "UMask": "0x60", - "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.", + "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x49", - "UMask": "0x1", "BriefDescription": "Store misses in all DTLB levels that cause page walks", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x49", - "UMask": "0x2", - "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", + "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "EventCode": "0x49", - "UMask": "0x4", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", + "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x49", - "UMask": "0x8", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)", + "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x49", - "UMask": "0xe", "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "EventCode": "0x49", - "UMask": "0x10", - "BriefDescription": "Cycles when PMH is busy with page walks", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x49", - "UMask": "0x20", - "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x49", - "UMask": "0x40", - "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).", + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x49", - "UMask": "0x60", - "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", + "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x4F", - "UMask": "0x10", "BriefDescription": "Cycle count for an Extended Page table walk.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" + }, + { + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAE", + "EventName": "ITLB.ITLB_FLUSH", + "PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "EventCode": "0x85", - "UMask": "0x1", "BriefDescription": "Misses at all ITLB levels that cause page walks", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x85", - "UMask": "0x2", - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "EventCode": "0x85", - "UMask": "0x4", - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT_2M", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x85", - "UMask": "0x8", - "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", + "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT_4K", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x85", - "UMask": "0xe", "BriefDescription": "Misses in all ITLB levels that cause completed page walks.", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "EventCode": "0x85", - "UMask": "0x10", - "BriefDescription": "Cycles when PMH is busy with page walks", + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { "EventCode": "0x85", - "UMask": "0x20", - "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.STLB_HIT_4K", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x85", - "UMask": "0x40", - "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.STLB_HIT_2M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x85", - "UMask": "0x60", - "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.STLB_HIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xAE", - "UMask": "0x1", - "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", + "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "EventName": "ITLB.ITLB_FLUSH", - "PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_DURATION", + "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", + "SampleAfterValue": "100003", + "UMask": "0x10" }, { - "EventCode": "0xBC", - "UMask": "0x11", "BriefDescription": "Number of DTLB page walker hits in the L1+FB.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_L1", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_L1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x11" }, { - "EventCode": "0xBC", - "UMask": "0x12", "BriefDescription": "Number of DTLB page walker hits in the L2.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_L2", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_L2", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x12" }, { - "EventCode": "0xBC", - "UMask": "0x14", "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_L3", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_L3", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x14" }, { - "EventCode": "0xBC", - "UMask": "0x18", "BriefDescription": "Number of DTLB page walker hits in Memory.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x18" }, { - "EventCode": "0xBC", - "UMask": "0x21", "BriefDescription": "Number of ITLB page walker hits in the L1+FB.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.ITLB_L1", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x21" }, { - "EventCode": "0xBC", - "UMask": "0x22", "BriefDescription": "Number of ITLB page walker hits in the L2.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.ITLB_L2", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L2", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x22" }, { - "EventCode": "0xBC", - "UMask": "0x24", "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.ITLB_L3", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L3", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x24" }, { - "EventCode": "0xBD", - "UMask": "0x1", "BriefDescription": "DTLB flush attempts of the thread-specific entries", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xBD", - "UMask": "0x20", "BriefDescription": "STLB flush attempts", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" } -]
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