diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/haswellx/memory.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/haswellx/memory.json | 172 |
1 files changed, 86 insertions, 86 deletions
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/memory.json b/tools/perf/pmu-events/arch/x86/haswellx/memory.json index 56b0f24b8029..a42d5ce86b6f 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/memory.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/memory.json @@ -291,7 +291,7 @@ { "EventCode": "0xCD", "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 4.", + "BriefDescription": "Randomly selected loads with latency value being above 4.", "PEBS": "2", "MSRValue": "0x4", "Counter": "3", @@ -305,7 +305,7 @@ { "EventCode": "0xCD", "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 8.", + "BriefDescription": "Randomly selected loads with latency value being above 8.", "PEBS": "2", "MSRValue": "0x8", "Counter": "3", @@ -319,7 +319,7 @@ { "EventCode": "0xCD", "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 16.", + "BriefDescription": "Randomly selected loads with latency value being above 16.", "PEBS": "2", "MSRValue": "0x10", "Counter": "3", @@ -333,7 +333,7 @@ { "EventCode": "0xCD", "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 32.", + "BriefDescription": "Randomly selected loads with latency value being above 32.", "PEBS": "2", "MSRValue": "0x20", "Counter": "3", @@ -347,7 +347,7 @@ { "EventCode": "0xCD", "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 64.", + "BriefDescription": "Randomly selected loads with latency value being above 64.", "PEBS": "2", "MSRValue": "0x40", "Counter": "3", @@ -361,7 +361,7 @@ { "EventCode": "0xCD", "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 128.", + "BriefDescription": "Randomly selected loads with latency value being above 128.", "PEBS": "2", "MSRValue": "0x80", "Counter": "3", @@ -375,7 +375,7 @@ { "EventCode": "0xCD", "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 256.", + "BriefDescription": "Randomly selected loads with latency value being above 256.", "PEBS": "2", "MSRValue": "0x100", "Counter": "3", @@ -389,7 +389,7 @@ { "EventCode": "0xCD", "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 512.", + "BriefDescription": "Randomly selected loads with latency value being above 512.", "PEBS": "2", "MSRValue": "0x200", "Counter": "3", @@ -404,12 +404,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts demand data reads that miss in the L3", - "MSRValue": "0x3fbfc00001", + "BriefDescription": "Counts demand data reads miss in the L3", + "MSRValue": "0x3FBFC00001", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts demand data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts demand data reads miss in the L3", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -417,12 +417,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram", + "BriefDescription": "Counts demand data reads miss the L3 and the data is returned from local dram", "MSRValue": "0x0600400001", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts demand data reads miss the L3 and the data is returned from local dram", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -430,12 +430,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3", - "MSRValue": "0x3fbfc00002", + "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3", + "MSRValue": "0x3FBFC00002", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand data writes (RFOs) miss in the L3", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -443,12 +443,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram", + "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram", "MSRValue": "0x0600400002", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -456,12 +456,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache", - "MSRValue": "0x103fc00002", + "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache", + "MSRValue": "0x103FC00002", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -469,12 +469,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all demand code reads that miss in the L3", - "MSRValue": "0x3fbfc00004", + "BriefDescription": "Counts all demand code reads miss in the L3", + "MSRValue": "0x3FBFC00004", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand code reads miss in the L3", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -482,12 +482,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram", + "BriefDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram", "MSRValue": "0x0600400004", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -495,12 +495,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3", - "MSRValue": "0x3fbfc00010", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3", + "MSRValue": "0x3FBFC00010", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -508,12 +508,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3", - "MSRValue": "0x3fbfc00020", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3", + "MSRValue": "0x3FBFC00020", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -521,12 +521,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the L3", - "MSRValue": "0x3fbfc00040", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3", + "MSRValue": "0x3FBFC00040", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -534,12 +534,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3", - "MSRValue": "0x3fbfc00080", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3", + "MSRValue": "0x3FBFC00080", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -547,12 +547,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3", - "MSRValue": "0x3fbfc00100", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", + "MSRValue": "0x3FBFC00100", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -560,12 +560,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3", - "MSRValue": "0x3fbfc00200", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", + "MSRValue": "0x3FBFC00200", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -573,12 +573,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3", - "MSRValue": "0x3fbfc00091", + "BriefDescription": "Counts all demand & prefetch data reads miss in the L3", + "MSRValue": "0x3FBFC00091", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch data reads miss in the L3", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -586,12 +586,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram", + "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", "MSRValue": "0x0600400091", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -599,12 +599,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram", - "MSRValue": "0x063f800091", + "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram", + "MSRValue": "0x063F800091", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -612,12 +612,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache", - "MSRValue": "0x103fc00091", + "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache", + "MSRValue": "0x103FC00091", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -625,12 +625,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache", - "MSRValue": "0x083fc00091", + "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache", + "MSRValue": "0x083FC00091", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -638,12 +638,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3", - "MSRValue": "0x3fbfc00122", + "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3", + "MSRValue": "0x3FBFC00122", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch RFOs miss in the L3", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -651,12 +651,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram", + "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", "MSRValue": "0x0600400122", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -664,12 +664,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch code reads that miss in the L3", - "MSRValue": "0x3fbfc00244", + "BriefDescription": "Counts all demand & prefetch code reads miss in the L3", + "MSRValue": "0x3FBFC00244", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch code reads miss in the L3", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -677,12 +677,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram", + "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", "MSRValue": "0x0600400244", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -690,12 +690,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3", - "MSRValue": "0x3fbfc007f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3", + "MSRValue": "0x3FBFC007F7", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -703,12 +703,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram", - "MSRValue": "0x06004007f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram", + "MSRValue": "0x06004007F7", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -716,12 +716,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from remote dram", - "MSRValue": "0x063f8007f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram", + "MSRValue": "0x063F8007F7", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from remote dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -729,12 +729,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the modified data is transferred from remote cache", - "MSRValue": "0x103fc007f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache", + "MSRValue": "0x103FC007F7", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -742,12 +742,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and clean or shared data is transferred from remote cache", - "MSRValue": "0x083fc007f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache", + "MSRValue": "0x083FC007F7", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and clean or shared data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" }, @@ -755,12 +755,12 @@ "Offcore": "1", "EventCode": "0xB7, 0xBB", "UMask": "0x1", - "BriefDescription": "Counts all requests that miss in the L3", - "MSRValue": "0x3fbfc08fff", + "BriefDescription": "Counts all requests miss in the L3", + "MSRValue": "0x3FBFC08FFF", "Counter": "0,1,2,3", "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all requests that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts all requests miss in the L3", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" } |