diff options
Diffstat (limited to '')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/icelake/memory.json | 591 |
1 files changed, 291 insertions, 300 deletions
diff --git a/tools/perf/pmu-events/arch/x86/icelake/memory.json b/tools/perf/pmu-events/arch/x86/icelake/memory.json index 3701bd93a462..a6f43cbc2d0a 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/memory.json +++ b/tools/perf/pmu-events/arch/x86/icelake/memory.json @@ -1,15 +1,27 @@ [ { - "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", + "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_CONFLICT", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", - "SampleAfterValue": "100003", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x2" + }, + { + "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x6" }, { "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", @@ -23,50 +35,15 @@ "UMask": "0x4" }, { - "BriefDescription": "Counts demand data reads that was not supplied by the L3 cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFFC00001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", + "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "MSRIndex": "0x3F6", - "MSRValue": "0x10", - "PEBS": "2", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_EVENTS", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "20011", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that was not supplied by the L3 cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFFC00010", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts).", "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" + "UMask": "0x80" }, { "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", @@ -80,203 +57,261 @@ "UMask": "0x8" }, { - "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", + "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", "SampleAfterValue": "100003", - "Speculative": "1", "UMask": "0x20" }, { - "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", + "BriefDescription": "Number of times an HLE execution successfully committed", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.COMMIT", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of times HLE commit succeeded.", "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x8" + "UMask": "0x2" }, { - "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded", + "BriefDescription": "Number of times an HLE execution started.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x5d", - "EventName": "TX_EXEC.MISC3", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.START", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.", + "PublicDescription": "Counts the number of times we entered an HLE region. Does not count nested transactions.", "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x4" + "UMask": "0x1" }, { - "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region", + "BriefDescription": "Number of machine clears due to memory ordering conflicts.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x5d", - "EventName": "TX_EXEC.MISC2", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.", + "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x2" }, { - "BriefDescription": "Cycles where data return is pending for a Demand Data Read request who miss L3 cache.", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x10" + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "1009", + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache.", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFFC00002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "20011", + "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", - "MSRValue": "0x200", + "MSRValue": "0x100", "PEBS": "2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "101", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "503", "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Number of times an RTM execution successfully committed", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.COMMIT", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times RTM commit succeeded.", - "SampleAfterValue": "100003", - "UMask": "0x2" + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc8", - "EventName": "HLE_RETIRED.ABORTED_EVENTS", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts).", - "SampleAfterValue": "100003", - "UMask": "0x80" + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "101", + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Number of times an HLE execution successfully committed", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc8", - "EventName": "HLE_RETIRED.COMMIT", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times HLE commit succeeded.", - "SampleAfterValue": "100003", - "UMask": "0x2" + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that was not supplied by the L3 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00004", + "Offcore": "1", + "PEBScounters": "0,1,2,3", "SampleAfterValue": "100003", - "UMask": "0x40" + "Speculative": "1", + "UMask": "0x1" }, { - "BriefDescription": "Number of machine clears due to memory ordering conflicts.", + "BriefDescription": "Counts demand data reads that was not supplied by the L3 cache.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc3", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00001", + "Offcore": "1", + "PEBScounters": "0,1,2,3", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x1" }, { - "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00002", + "Offcore": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x10" + "UMask": "0x1" }, { - "BriefDescription": "Counts streaming stores that was not supplied by the L3 cache.", + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that was not supplied by the L3 cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.STREAMING_WR.L3_MISS", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFFC00800", + "MSRValue": "0x3FFFC00400", "Offcore": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that was not supplied by the L3 cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_CAPACITY_READ", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00010", + "Offcore": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x80" + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that was not supplied by the L3 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_RFO.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00020", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" }, { "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that was not supplied by the L3 cache.", @@ -288,60 +323,58 @@ "MSRValue": "0x3FFFC08000", "Offcore": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that was not supplied by the L3 cache.", + "BriefDescription": "Counts streaming stores that was not supplied by the L3 cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_MISS", + "EventName": "OCR.STREAMING_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFFC00020", + "MSRValue": "0x3FFFC00800", "Offcore": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Demand Data Read requests who miss L3 cache", + "BriefDescription": "Counts demand data read requests that miss the L3 cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", "PEBScounters": "0,1,2,3", - "PublicDescription": "Demand Data Read requests who miss L3 cache.", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x10" }, { - "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", + "BriefDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "2", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", "PEBScounters": "0,1,2,3", + "PublicDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.", "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x10" }, { - "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", + "BriefDescription": "Number of times an RTM execution aborted.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", - "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", + "EventName": "RTM_RETIRED.ABORTED", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.", + "PublicDescription": "Counts the number of times RTM abort was triggered.", "SampleAfterValue": "100003", - "UMask": "0x20" + "UMask": "0x4" }, { "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", @@ -355,208 +388,154 @@ "UMask": "0x80" }, { - "BriefDescription": "Number of times an HLE execution started.", + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc8", - "EventName": "HLE_RETIRED.START", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MEM", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times we entered an HLE region. Does not count nested transactions.", + "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", "SampleAfterValue": "100003", - "UMask": "0x1" + "UMask": "0x8" }, { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", + "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", - "MSRValue": "0x4", - "PEBS": "2", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", + "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.", "SampleAfterValue": "100003", - "TakenAlone": "1", - "UMask": "0x1" + "UMask": "0x40" }, { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", - "MSRIndex": "0x3F6", - "MSRValue": "0x80", - "PEBS": "2", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "1009", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times we could not allocate Lock Buffer.", + "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.", "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x40" + "UMask": "0x20" }, { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", + "BriefDescription": "Number of times an RTM execution successfully committed", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", - "MSRValue": "0x8", - "PEBS": "2", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.COMMIT", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "50021", - "TakenAlone": "1", - "UMask": "0x1" + "PublicDescription": "Counts the number of times RTM commit succeeded.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", + "BriefDescription": "Number of times an RTM execution started.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", - "MSRIndex": "0x3F6", - "MSRValue": "0x100", - "PEBS": "2", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.START", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "503", - "TakenAlone": "1", + "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", + "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "6", - "EventCode": "0xa3", - "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x6" - }, - { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", + "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", - "MSRValue": "0x40", - "PEBS": "2", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "2003", - "TakenAlone": "1", - "UMask": "0x1" + "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" }, { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", + "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", - "MSRValue": "0x20", - "PEBS": "2", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC3", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" + "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x4" }, { - "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", + "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.ABORTED_MEM", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_READ", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", "SampleAfterValue": "100003", - "UMask": "0x8" + "Speculative": "1", + "UMask": "0x80" }, { - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that was not supplied by the L3 cache.", + "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFFC00400", - "Offcore": "1", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x2" }, { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that was not supplied by the L3 cache.", + "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFFC00004", - "Offcore": "1", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CONFLICT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Number of times an RTM execution aborted.", + "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.ABORTED", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times RTM abort was triggered.", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", "SampleAfterValue": "100003", - "UMask": "0x4" + "Speculative": "1", + "UMask": "0x10" }, { - "BriefDescription": "Number of times an RTM execution started.", + "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.START", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", "SampleAfterValue": "100003", - "UMask": "0x1" + "Speculative": "1", + "UMask": "0x8" }, { - "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", + "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc8", - "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", "SampleAfterValue": "100003", + "Speculative": "1", "UMask": "0x20" }, { @@ -570,5 +549,17 @@ "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x4" + }, + { + "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times we could not allocate Lock Buffer.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x40" } -]
\ No newline at end of file +] |