diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json | 247 |
1 files changed, 128 insertions, 119 deletions
diff --git a/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json b/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json index 7180a900c175..58809e16bf98 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json @@ -1,236 +1,245 @@ [ { + "BriefDescription": "Loads that miss the DTLB and hit the STLB.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", - "EventCode": "0x08", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", - "SampleAfterValue": "2000003", - "BriefDescription": "Page walks completed due to a demand data load to a 4K page." - }, - { - "CollectPEBSRecord": "2", - "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.", "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x4", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PEBScounters": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", - "SampleAfterValue": "2000003", - "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page." + "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x20" }, { + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts demand data loads that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.", - "EventCode": "0x08", "Counter": "0,1,2,3", - "UMask": "0xe", + "CounterMask": "1", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", "PEBScounters": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.", "SampleAfterValue": "100003", - "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)" + "Speculative": "1", + "UMask": "0x10" }, { + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.", - "EventCode": "0x08", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PEBScounters": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle." + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0xe" }, { + "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.", - "EventCode": "0x08", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PEBScounters": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "SampleAfterValue": "100003", - "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", - "CounterMask": "1" + "Speculative": "1", + "UMask": "0x4" }, { + "BriefDescription": "Page walks completed due to a demand data load to a 4K page.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", - "EventCode": "0x08", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PEBScounters": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Loads that miss the DTLB and hit the STLB." + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" }, { + "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", - "EventCode": "0x49", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PEBScounters": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.", "SampleAfterValue": "100003", - "BriefDescription": "Page walks completed due to a demand data store to a 4K page." + "Speculative": "1", + "UMask": "0x10" }, { + "BriefDescription": "Stores that miss the DTLB and hit the STLB.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.", - "EventCode": "0x49", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", "PEBScounters": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", "SampleAfterValue": "100003", - "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page." + "Speculative": "1", + "UMask": "0x20" }, { + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts demand data stores that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.", - "EventCode": "0x49", "Counter": "0,1,2,3", - "UMask": "0xe", + "CounterMask": "1", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", "PEBScounters": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)" + "Speculative": "1", + "UMask": "0x10" }, { + "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.", - "EventCode": "0x49", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PEBScounters": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle." + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0xe" }, { + "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.", - "EventCode": "0x49", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PEBScounters": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "SampleAfterValue": "100003", - "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.", - "CounterMask": "1" + "Speculative": "1", + "UMask": "0x4" }, { + "BriefDescription": "Page walks completed due to a demand data store to a 4K page.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", - "EventCode": "0x49", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PEBScounters": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "SampleAfterValue": "100003", - "BriefDescription": "Stores that miss the DTLB and hit the STLB." + "Speculative": "1", + "UMask": "0x2" }, { + "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts completed page walks (4K page size) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.", - "EventCode": "0x85", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PEBScounters": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.", "SampleAfterValue": "100003", - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)" + "Speculative": "1", + "UMask": "0x10" }, { + "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts code misses in all ITLB (Instruction TLB) levels that caused a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", - "EventCode": "0x85", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT", "PEBScounters": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).", "SampleAfterValue": "100003", - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)" + "Speculative": "1", + "UMask": "0x20" }, { + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts completed page walks (2M and 4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", - "EventCode": "0x85", "Counter": "0,1,2,3", - "UMask": "0xe", + "CounterMask": "1", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_ACTIVE", "PEBScounters": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.", "SampleAfterValue": "100003", - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)" + "Speculative": "1", + "UMask": "0x10" }, { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.", - "EventCode": "0x85", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", "PEBScounters": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_PENDING", + "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", "SampleAfterValue": "100003", - "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle." + "Speculative": "1", + "UMask": "0xe" }, { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.", - "EventCode": "0x85", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PEBScounters": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_ACTIVE", + "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", "SampleAfterValue": "100003", - "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.", - "CounterMask": "1" + "Speculative": "1", + "UMask": "0x4" }, { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).", - "EventCode": "0x85", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PEBScounters": "0,1,2,3", - "EventName": "ITLB_MISSES.STLB_HIT", + "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", "SampleAfterValue": "100003", - "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB." + "Speculative": "1", + "UMask": "0x2" }, { + "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).", - "EventCode": "0xAE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_PENDING", "PEBScounters": "0,1,2,3", - "EventName": "ITLB.ITLB_FLUSH", - "SampleAfterValue": "100007", - "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages." + "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x10" }, { + "BriefDescription": "DTLB flush attempts of the thread-specific entries", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.", - "EventCode": "0xBD", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.", "SampleAfterValue": "100007", - "BriefDescription": "DTLB flush attempts of the thread-specific entries" + "Speculative": "1", + "UMask": "0x1" }, { + "BriefDescription": "STLB flush attempts", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", - "EventCode": "0xBD", "Counter": "0,1,2,3", - "UMask": "0x20", - "PEBScounters": "0,1,2,3", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", "SampleAfterValue": "100007", - "BriefDescription": "STLB flush attempts" + "Speculative": "1", + "UMask": "0x20" } -]
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