diff options
Diffstat (limited to '')
-rw-r--r-- | tools/perf/pmu-events/arch/x86/jaketown/memory.json | 480 |
1 files changed, 240 insertions, 240 deletions
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/memory.json b/tools/perf/pmu-events/arch/x86/jaketown/memory.json index 27e636428f4f..23756ca9b7da 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/memory.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/memory.json @@ -1,422 +1,422 @@ [ { - "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.", - "EventCode": "0xC3", + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.", "SampleAfterValue": "100003", - "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x4", + "BriefDescription": "Loads with latency value being above 128.", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", - "SampleAfterValue": "100003", - "BriefDescription": "Loads with latency value being above 4 .", + "MSRValue": "0x80", + "PEBS": "2", + "SampleAfterValue": "1009", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x8", + "BriefDescription": "Loads with latency value being above 16.", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "MSRIndex": "0x3F6", - "SampleAfterValue": "50021", - "BriefDescription": "Loads with latency value being above 8.", + "MSRValue": "0x10", + "PEBS": "2", + "SampleAfterValue": "20011", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x10", + "BriefDescription": "Loads with latency value being above 256.", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", - "SampleAfterValue": "20011", - "BriefDescription": "Loads with latency value being above 16.", + "MSRValue": "0x100", + "PEBS": "2", + "SampleAfterValue": "503", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x20", + "BriefDescription": "Loads with latency value being above 32.", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", "SampleAfterValue": "100007", - "BriefDescription": "Loads with latency value being above 32.", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x40", + "BriefDescription": "Loads with latency value being above 4 .", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "MSRIndex": "0x3F6", - "SampleAfterValue": "2003", - "BriefDescription": "Loads with latency value being above 64.", + "MSRValue": "0x4", + "PEBS": "2", + "SampleAfterValue": "100003", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x80", + "BriefDescription": "Loads with latency value being above 512.", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", - "SampleAfterValue": "1009", - "BriefDescription": "Loads with latency value being above 128.", + "MSRValue": "0x200", + "PEBS": "2", + "SampleAfterValue": "101", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x100", + "BriefDescription": "Loads with latency value being above 64.", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "MSRIndex": "0x3F6", - "SampleAfterValue": "503", - "BriefDescription": "Loads with latency value being above 256.", + "MSRValue": "0x40", + "PEBS": "2", + "SampleAfterValue": "2003", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x200", + "BriefDescription": "Loads with latency value being above 8.", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "MSRIndex": "0x3F6", - "SampleAfterValue": "101", - "BriefDescription": "Loads with latency value being above 512.", + "MSRValue": "0x8", + "PEBS": "2", + "SampleAfterValue": "50021", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", + "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).", "Counter": "3", - "UMask": "0x2", + "CounterHTOff": "3", + "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).", + "PEBS": "2", "PRECISE_STORE": "1", + "SampleAfterValue": "2000003", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x2" }, { - "EventCode": "0x05", + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.LOADS", "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x05", + "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.STORES", "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20004", + "BriefDescription": "This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC20077", "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x600400077", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { + "BriefDescription": "This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x600400004", + "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.REMOTE_HITM_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x187FC20077", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads that miss the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20004", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x600400004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67f800004", + "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from remote dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67f800004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from remote dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x87f820004", + "BriefDescription": "Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x107fc00004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LLC and the data forwarded from remote cache", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x107fc00004", + "BriefDescription": "Counts all demand code reads that miss the LLC and the data forwarded from remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x87f820004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67fc00001", + "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote & local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67fc00001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote & local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20001", + "BriefDescription": "Counts demand data reads that miss in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x600400001", + "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x600400001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67f800001", + "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67f800001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x87f820001", + "BriefDescription": "Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x107fc00001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC and the data forwarded from remote cache", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x107fc00001", + "BriefDescription": "Counts demand data reads that miss the LLC and the data forwarded from remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x87f820001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20040", + "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20040", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67fc00010", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67fc00010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20010", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x600400010", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x600400010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67f800010", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x87f820010", - "Counter": "0,1,2,3", - "UMask": "0x1", + "MSRValue": "0x67f800010", "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6,0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x107fc00010", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20200", - "Counter": "0,1,2,3", - "UMask": "0x1", + "MSRValue": "0x107fc00010", "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20080", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x600400077", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.LOCAL_DRAM", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x87f820010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC20077", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20200", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x187FC20077", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.REMOTE_HITM_HIT_FORWARD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" } -]
\ No newline at end of file +] |