diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/sandybridge/memory.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/sandybridge/memory.json | 68 |
1 files changed, 34 insertions, 34 deletions
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/memory.json b/tools/perf/pmu-events/arch/x86/sandybridge/memory.json index e6dfa89d00f3..78c1a987f9a2 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/memory.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/memory.json @@ -1,5 +1,32 @@ [ { + "EventCode": "0x05", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MISALIGN_MEM_REF.LOADS", + "SampleAfterValue": "2000003", + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x05", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MISALIGN_MEM_REF.STORES", + "SampleAfterValue": "2000003", + "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xBE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "PAGE_WALKS.LLC_MISS", + "SampleAfterValue": "100003", + "BriefDescription": "Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.", "EventCode": "0xC3", "Counter": "0,1,2,3", @@ -126,33 +153,6 @@ "CounterHTOff": "3" }, { - "EventCode": "0xBE", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "PAGE_WALKS.LLC_MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x05", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MISALIGN_MEM_REF.LOADS", - "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x05", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MISALIGN_MEM_REF.STORES", - "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { "EventCode": "0xB7, 0xBB", "MSRValue": "0x300400244", "Counter": "0,1,2,3", @@ -367,7 +367,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", "SampleAfterValue": "100003", - "BriefDescription": " REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", "CounterHTOff": "0,1,2,3" }, { @@ -379,7 +379,7 @@ "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS_LOCAL.ANY_LLC_HIT", "MSRIndex": "0x1a6,0x1a7", "SampleAfterValue": "100003", - "BriefDescription": " REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT", + "BriefDescription": "REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT", "CounterHTOff": "0,1,2,3" }, { @@ -391,7 +391,7 @@ "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", "SampleAfterValue": "100003", - "BriefDescription": " REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", "CounterHTOff": "0,1,2,3" }, { @@ -403,7 +403,7 @@ "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", "SampleAfterValue": "100003", - "BriefDescription": " REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", "CounterHTOff": "0,1,2,3" }, { @@ -415,7 +415,7 @@ "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", "SampleAfterValue": "100003", - "BriefDescription": " REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", "CounterHTOff": "0,1,2,3" }, { @@ -427,7 +427,7 @@ "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", "SampleAfterValue": "100003", - "BriefDescription": " REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", + "BriefDescription": "REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", "CounterHTOff": "0,1,2,3" }, { @@ -439,7 +439,7 @@ "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", "SampleAfterValue": "100003", - "BriefDescription": " REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", + "BriefDescription": "REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", "CounterHTOff": "0,1,2,3" } ]
\ No newline at end of file |