diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/skylakex/memory.json')
-rw-r--r-- | tools/perf/pmu-events/arch/x86/skylakex/memory.json | 1903 |
1 files changed, 919 insertions, 984 deletions
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/memory.json b/tools/perf/pmu-events/arch/x86/skylakex/memory.json index 48a9cdf81307..a570fe3e7a2d 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/memory.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/memory.json @@ -1,1396 +1,1331 @@ [ { - "EventCode": "0x54", - "UMask": "0x1", - "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", + "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_CONFLICT", - "PublicDescription": "Number of times a TSX line had a cache conflict.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x54", - "UMask": "0x2", - "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.", + "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_CAPACITY", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x6" }, { - "EventCode": "0x54", - "UMask": "0x4", - "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", + "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", - "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.ABORTED", + "PEBS": "1", + "PublicDescription": "Number of times HLE abort was triggered.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x54", - "UMask": "0x8", - "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", + "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", - "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.ABORTED_EVENTS", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "EventCode": "0x54", - "UMask": "0x10", - "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", + "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", - "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.ABORTED_MEM", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x54", - "UMask": "0x20", - "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", + "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", - "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", + "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x54", - "UMask": "0x40", - "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", + "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", "Counter": "0,1,2,3", - "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", - "PublicDescription": "Number of times we could not allocate Lock Buffer.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.ABORTED_TIMER", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x5d", - "UMask": "0x1", - "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", + "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x5d", - "UMask": "0x2", - "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", + "BriefDescription": "Number of times an HLE execution successfully committed", "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC2", - "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.COMMIT", + "PublicDescription": "Number of times HLE commit succeeded.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x5d", - "UMask": "0x4", - "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", + "BriefDescription": "Number of times an HLE execution started.", "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC3", - "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.START", + "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x5d", - "UMask": "0x8", - "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC4", - "PublicDescription": "RTM region detected inside HLE.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "SKL089", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x5d", - "UMask": "0x10", - "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC5", - "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "1009", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0x60", - "UMask": "0x10", - "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "20011", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0x60", - "UMask": "0x10", - "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", - "CounterMask": "6", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "503", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0x60", - "UMask": "0x10", - "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xA3", - "UMask": "0x2", - "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", - "CounterMask": "2", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "100003", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xA3", - "UMask": "0x6", - "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", - "CounterMask": "6", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "101", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xB0", - "UMask": "0x10", - "BriefDescription": "Demand Data Read requests who miss L3 cache", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", - "PublicDescription": "Demand Data Read requests who miss L3 cache.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xC3", - "UMask": "0x2", - "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "Errata": "SKL089", - "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1" }, { - "EventCode": "0xC8", - "UMask": "0x1", - "BriefDescription": "Number of times an HLE execution started.", + "BriefDescription": "Demand Data Read requests who miss L3 cache", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.START", - "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "PublicDescription": "Demand Data Read requests who miss L3 cache.", + "SampleAfterValue": "100003", + "UMask": "0x10" }, { - "EventCode": "0xC8", - "UMask": "0x2", - "BriefDescription": "Number of times an HLE execution successfully committed", + "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.COMMIT", - "PublicDescription": "Number of times HLE commit succeeded.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xC8", - "UMask": "0x4", - "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", - "PEBS": "1", + "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED", - "PublicDescription": "Number of times HLE abort was triggered. (PEBS)", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xC8", - "UMask": "0x8", - "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED_MEM", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xC8", - "UMask": "0x10", - "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", + "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED_TIMER", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBC000491", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xC8", - "UMask": "0x20", - "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", + "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", - "PublicDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC00491", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xC8", - "UMask": "0x40", - "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", + "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", - "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x83FC00491", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xC8", - "UMask": "0x80", - "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", + "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram.", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED_EVENTS", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63FC00491", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xC9", - "UMask": "0x1", - "BriefDescription": "Number of times an RTM execution started.", + "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram.", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.START", - "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x604000491", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xC9", - "UMask": "0x2", - "BriefDescription": "Number of times an RTM execution successfully committed", + "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram.", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.COMMIT", - "PublicDescription": "Number of times RTM commit succeeded.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63B800491", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xC9", - "UMask": "0x4", - "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", - "PEBS": "1", + "BriefDescription": "Counts all prefetch data reads that miss in the L3.", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED", - "PublicDescription": "Number of times RTM abort was triggered. (PEBS)", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBC000490", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xC9", - "UMask": "0x8", - "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", + "BriefDescription": "Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MEM", - "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC00490", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xC9", - "UMask": "0x10", - "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", + "BriefDescription": "Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_TIMER", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x83FC00490", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xC9", - "UMask": "0x20", - "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", + "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram.", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", - "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63FC00490", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xC9", - "UMask": "0x40", - "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", + "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local dram.", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", - "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x604000490", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xC9", - "UMask": "0x80", - "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", + "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from remote dram.", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_EVENTS", - "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63B800490", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", - "PEBS": "2", - "MSRValue": "0x200", + "BriefDescription": "Counts prefetch RFOs that miss in the L3.", "Counter": "0,1,2,3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", - "MSRIndex": "0x3F6", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", - "TakenAlone": "1", - "SampleAfterValue": "101", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBC000120", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", - "PEBS": "2", - "MSRValue": "0x100", + "BriefDescription": "Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", - "MSRIndex": "0x3F6", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", - "TakenAlone": "1", - "SampleAfterValue": "503", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC00120", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", - "PEBS": "2", - "MSRValue": "0x80", + "BriefDescription": "Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", - "MSRIndex": "0x3F6", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", - "TakenAlone": "1", - "SampleAfterValue": "1009", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x83FC00120", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", - "PEBS": "2", - "MSRValue": "0x40", + "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram.", "Counter": "0,1,2,3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", - "TakenAlone": "1", - "SampleAfterValue": "2003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63FC00120", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", - "PEBS": "2", - "MSRValue": "0x20", + "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local dram.", "Counter": "0,1,2,3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", - "TakenAlone": "1", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x604000120", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", - "PEBS": "2", - "MSRValue": "0x10", + "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from remote dram.", "Counter": "0,1,2,3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "MSRIndex": "0x3F6", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", - "TakenAlone": "1", - "SampleAfterValue": "20011", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63B800120", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", - "PEBS": "2", - "MSRValue": "0x8", + "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3.", "Counter": "0,1,2,3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", - "TakenAlone": "1", - "SampleAfterValue": "50021", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBC000122", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", - "PEBS": "2", - "MSRValue": "0x4", + "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", - "TakenAlone": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC00122", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts demand data reads TBD TBD", - "MSRValue": "0x3FBC000001", + "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts demand data reads TBD TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x83FC00122", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts demand data reads TBD", - "MSRValue": "0x083FC00001", + "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts demand data reads TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63FC00122", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts demand data reads TBD", - "MSRValue": "0x103FC00001", + "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts demand data reads TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x604000122", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts demand data reads TBD", - "MSRValue": "0x063FC00001", + "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts demand data reads TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63B800122", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts demand data reads TBD", - "MSRValue": "0x063B800001", + "BriefDescription": "Counts all demand code reads that miss in the L3.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts demand data reads TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBC000004", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts demand data reads TBD", - "MSRValue": "0x0604000001", + "BriefDescription": "Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts demand data reads TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC00004", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", - "MSRValue": "0x3FBC000002", + "BriefDescription": "Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) TBD TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x83FC00004", + "Offcore": "1", "SampleAfterValue": "100003", - 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"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x604000004", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", - "MSRValue": "0x063FC00002", + "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from remote dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63B800004", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", - "MSRValue": "0x063B800002", + "BriefDescription": "Counts demand data reads that miss in the L3.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBC000001", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) TBD", - "MSRValue": "0x0604000002", + "BriefDescription": "Counts demand data reads that miss the L3 and the modified data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC00001", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD TBD", - "MSRValue": "0x3FBC000004", + "BriefDescription": "Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x83FC00001", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD", - "MSRValue": "0x083FC00004", + "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local or remote dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63FC00001", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD", - "MSRValue": "0x103FC00004", + "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x604000001", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD", - "MSRValue": "0x063FC00004", + "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from remote dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63B800001", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD", - "MSRValue": "0x063B800004", + "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBC000002", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD", - "MSRValue": "0x0604000004", + "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC00002", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", - "MSRValue": "0x3FBC000010", + "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x83FC00002", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", - "MSRValue": "0x083FC00010", + "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63FC00002", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", - "MSRValue": "0x103FC00010", + "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x604000002", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", - "MSRValue": "0x063FC00010", + "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63B800002", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", - "MSRValue": "0x063B800010", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBC000400", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", - "MSRValue": "0x0604000010", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts prefetch (that bring data to L2) data reads TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC00400", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", - "MSRValue": "0x3FBC000020", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x83FC00400", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", - "MSRValue": "0x083FC00020", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63FC00400", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", - "MSRValue": "0x103FC00020", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x604000400", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", - "MSRValue": "0x063FC00020", + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63B800400", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", - "MSRValue": "0x063B800020", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBC000010", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", - "MSRValue": "0x0604000020", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC00010", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", - "MSRValue": "0x3FBC000080", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x83FC00010", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", - "MSRValue": "0x083FC00080", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63FC00010", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", - "MSRValue": "0x103FC00080", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x604000010", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", - "MSRValue": "0x063FC00080", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63B800010", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", - "MSRValue": "0x063B800080", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBC000020", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", - "MSRValue": "0x0604000080", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC00020", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", - "MSRValue": "0x3FBC000100", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x83FC00020", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", - "MSRValue": "0x083FC00100", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63FC00020", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", - "MSRValue": "0x103FC00100", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x604000020", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", - "MSRValue": "0x063FC00100", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63B800020", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", - "MSRValue": "0x063B800100", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBC000080", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", - "MSRValue": "0x0604000100", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC00080", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", - "MSRValue": "0x3FBC000400", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x83FC00080", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", - "MSRValue": "0x083FC00400", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63FC00080", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", - "MSRValue": "0x103FC00400", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x604000080", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", - "MSRValue": "0x063FC00400", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63B800080", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", - "MSRValue": "0x063B800400", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBC000100", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", - "MSRValue": "0x0604000400", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC00100", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD TBD", - "MSRValue": "0x3FBC000490", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x83FC00100", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD", - "MSRValue": "0x083FC00490", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63FC00100", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD", - "MSRValue": "0x103FC00490", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x604000100", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD", - "MSRValue": "0x063FC00490", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x63B800100", + "Offcore": "1", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD", - "MSRValue": "0x063B800490", + "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.ABORTED", + "PEBS": "1", + "PublicDescription": "Number of times RTM abort was triggered.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD", - "MSRValue": "0x0604000490", + "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.ABORTED_EVENTS", + "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD TBD", - "MSRValue": "0x3FBC000120", + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD TBD", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.ABORTED_MEM", + "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD", - "MSRValue": "0x083FC00120", + "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", + "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD", - "MSRValue": "0x103FC00120", + "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.ABORTED_TIMER", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD", - "MSRValue": "0x063FC00120", + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", + "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD", - "MSRValue": "0x063B800120", + "BriefDescription": "Number of times an RTM execution successfully committed", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.COMMIT", + "PublicDescription": "Number of times RTM commit succeeded.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD", - "MSRValue": "0x0604000120", + "BriefDescription": "Number of times an RTM execution started.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.START", + "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD TBD", - "MSRValue": "0x3FBC000491", + "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD TBD", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD", - "MSRValue": "0x083FC00491", + "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC2", + "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD", - "MSRValue": "0x103FC00491", + "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC3", + "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD", - "MSRValue": "0x063FC00491", + "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC4", + "PublicDescription": "RTM region detected inside HLE.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD", - "MSRValue": "0x063B800491", + "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC5", + "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD", - "MSRValue": "0x0604000491", + "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD TBD", - "MSRValue": "0x3FBC000122", + "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD TBD", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CONFLICT", + "PublicDescription": "Number of times a TSX line had a cache conflict.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD", - "MSRValue": "0x083FC00122", + "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD", - "MSRValue": "0x103FC00122", + "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD", - "MSRValue": "0x063FC00122", + "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", + "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD", - "MSRValue": "0x063B800122", + "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "TBD TBD", - "MSRValue": "0x0604000122", + "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "PublicDescription": "TBD TBD", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "PublicDescription": "Number of times we could not allocate Lock Buffer.", + "SampleAfterValue": "2000003", + "UMask": "0x40" } -]
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