diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/skylakex/other.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/skylakex/other.json | 96 |
1 files changed, 62 insertions, 34 deletions
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/other.json b/tools/perf/pmu-events/arch/x86/skylakex/other.json index 8b344259176f..403805e7e581 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/other.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/other.json @@ -40,77 +40,105 @@ "UMask": "0x40" }, { - "BriefDescription": "Number of hardware interrupts received by the processor.", + "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xCB", - "EventName": "HW_INTERRUPTS.RECEIVED", - "PublicDescription": "Counts the number of hardware interruptions received by the processor.", - "SampleAfterValue": "203", - "UMask": "0x1" + "EventCode": "0xEF", + "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly", + "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDM", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xFE", - "EventName": "IDI_MISC.WB_DOWNGRADE", - "PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.", - "SampleAfterValue": "100003", - "UMask": "0x4" + "EventCode": "0xEF", + "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly", + "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xFE", - "EventName": "IDI_MISC.WB_UPGRADE", - "PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.", - "SampleAfterValue": "100003", + "EventCode": "0xEF", + "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", + "SampleAfterValue": "2000003", "UMask": "0x2" }, { + "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITI", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x09", - "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", + "EventCode": "0xEF", + "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.NTA", + "EventCode": "0xEF", + "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", "SampleAfterValue": "2000003", - "UMask": "0x1" + "UMask": "0x40" }, { - "BriefDescription": "Number of PREFETCHW instructions executed.", + "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDM", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "EventCode": "0xEF", + "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM", "SampleAfterValue": "2000003", "UMask": "0x8" }, { - "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T0", + "EventCode": "0xEF", + "EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of hardware interrupts received by the processor.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCB", + "EventName": "HW_INTERRUPTS.RECEIVED", + "PublicDescription": "Counts the number of hardware interruptions received by the processor.", + "SampleAfterValue": "203", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xFE", + "EventName": "IDI_MISC.WB_DOWNGRADE", + "PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xFE", + "EventName": "IDI_MISC.WB_UPGRADE", + "PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.", + "SampleAfterValue": "100003", "UMask": "0x2" }, { - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "BriefDescription": "MEMORY_DISAMBIGUATION.HISTORY_RESET", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "EventCode": "0x09", + "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", "SampleAfterValue": "2000003", - "UMask": "0x4" + "UMask": "0x1" } -]
\ No newline at end of file +] |