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2020-01-07clk: divider: Add support for specifying parents via DT/pointersStephen Boyd2-94/+152
2020-01-07clk: clarify that clk_set_rate() does updates from top to bottomMartin Blumenstingl1-0/+3
2020-01-07clk: meson: meson8b: make the CCF use the glitch-free mali muxMartin Blumenstingl1-4/+7
2020-01-06clk: gate: Add support for specifying parents via DT/pointersStephen Boyd2-20/+74
2020-01-06clk: mux: Add support for specifying parents via DT/pointersStephen Boyd4-62/+60
2020-01-06clk: asm9260: Use parent accuracy in fixed rate clkStephen Boyd1-4/+4
2020-01-06clk: fixed-rate: Document that accuracy isn't a rateStephen Boyd1-1/+1
2020-01-06clk: fixed-rate: Add clk flags for parent accuracyStephen Boyd2-1/+12
2020-01-05clk: Add support for setting clk_rate via debugfsGeert Uytterhoeven1-1/+37
2020-01-05clk: at91: sam9x60: fix programmable clock prescalerEugen Hristev1-0/+1
2020-01-05clk: at91: sam9x60-pll: adapt PMC_PLL_ACR default valueEugen Hristev1-2/+6
2020-01-05clk: fixed-rate: Add support for specifying parents via DT/pointersStephen Boyd2-42/+114
2020-01-05clk: fixed-rate: Document accuracy memberStephen Boyd1-0/+1
2020-01-05clk: fixed-rate: Move to_clk_fixed_rate() to C fileStephen Boyd2-2/+2
2020-01-05clk: fixed-rate: Remove clk_register_fixed_rate_with_accuracy()Stephen Boyd2-19/+7
2020-01-05clk: fixed-rate: Convert to clk_hw based APIsStephen Boyd1-16/+15
2020-01-05clk: gpio: Use DT way of specifying parentsStephen Boyd2-151/+59
2020-01-04clk: Fix Kconfig indentationKrzysztof Kozlowski5-27/+27
2020-01-04clk: ux500: Fix up the SGA clock for some variantsLinus Walleij1-0/+2
2020-01-04clk: Warn about critical clks that fail to enableStephen Boyd1-1/+6
2020-01-04clk: uniphier: Add SCSSI clock gate for each channelKunihiko Hayashi1-5/+8
2020-01-04clk: Use parent node pointer during registration if necessaryStephen Boyd1-2/+25
2020-01-04clk: sunxi: a23/a33: Export the MIPI PLLMaxime Ripard2-1/+5
2020-01-04clk: sunxi: a31: Export the MIPI PLLMaxime Ripard2-1/+5
2020-01-04clk: sunxi-ng: a64: export CLK_CPUX clock for DVFSVasily Khoruzhick2-1/+1
2020-01-04clk: sunxi-ng: add mux and pll notifiers for A64 CPU clockIcenowy Zheng1-1/+27
2020-01-03clk: sunxi-ng: r40: Export MBUS clockChen-Yu Tsai2-5/+1
2019-12-26clk: Don't try to enable critical clocks if prepare failedGuenter Roeck1-2/+8
2019-12-24clk: bm1800: Remove set but not used variable 'fref'YueHaibing1-2/+1
2019-12-24clk: tegra: Fix double-free in tegra_clk_init()Dmitry Osipenko1-1/+3
2019-12-23clk: samsung: exynos5420: Keep top G3D clocks enabledMarek Szyprowski1-0/+8
2019-12-23clk: add terminate callback to clk_opsJerome Brunet2-1/+9
2019-12-23clk: let init callback return an error codeJerome Brunet14-35/+72
2019-12-23clk: actually call the clock init before any other callback of the clockJerome Brunet1-11/+15
2019-12-20dt-bindings: clock: renesas: cpg-mssr: Fix r8a774b1 typoBiju Das1-1/+1
2019-12-20clk: renesas: r7s9210: Add SPIBSC clockChris Brandt1-0/+1
2019-12-20clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocksSergei Shtylyov1-2/+4
2019-12-18clk: qcom: Avoid SMMU/cx gdsc corner casesJeffrey Hugo1-0/+2
2019-12-18clk: qcom: gcc-sc7180: Fix setting flag for votable GDSCsMatthias Kaehlcke1-2/+4
2019-12-18clk: Move clk_core_reparent_orphans() under CONFIG_OFOlof Johansson1-7/+7
2019-12-16clk: at91: fix possible deadlockAlexandre Belloni6-6/+6
2019-12-16clk: meson: pll: Fix by 0 division in __pll_params_to_rate()Remi Pommarel1-0/+9
2019-12-16clk: meson: g12a: fix missing uart2 in regmap tableJerome Brunet1-0/+1
2019-12-13clk: renesas: Remove use of ARCH_R8A7796Geert Uytterhoeven1-1/+1
2019-12-12clk: walk orphan list on clock provider registrationJerome Brunet1-22/+40
2019-12-11clk: meson: meson8b: use of_clk_hw_register to register the clocksMartin Blumenstingl1-1/+1
2019-12-11clk: meson: meson8b: don't register the XTAL clock when provided via OFMartin Blumenstingl1-3/+9
2019-12-11clk: meson: meson8b: change references to the XTAL clock to use [fw_]nameMartin Blumenstingl1-34/+44
2019-12-11clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifierMartin Blumenstingl1-13/+8
2019-12-11clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controllerMartin Blumenstingl2-1/+150