| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2015-02-20 | MIPS: OCTEON: irq: add CIB and other fixes |   David Daney | 2 | -268/+822 |
| 2015-02-20 | MIPS: OCTEON: Don't do acknowledge operations for level triggered irqs. | David Daney | 1 | -2/+43 |
| 2015-02-20 | MIPS: OCTEON: More OCTEONIII support |   Chandrakala Chavva | 4 | -2/+326 |
| 2015-02-20 | MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits. |   Chad Reese | 1 | -20/+0 |
| 2015-02-20 | MIPS: OCTEON: Core-15169 Workaround and general CVMSEG cleanup. | David Daney | 2 | -6/+17 |
| 2015-02-20 | MIPS: OCTEON: Update octeon-model.h code for new SoCs. | David Daney | 5 | -27/+90 |
| 2015-02-20 | MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX | David Daney | 3 | -4/+8 |
| 2015-02-20 | MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.h | David Daney | 1 | -30/+105 |
| 2015-02-20 | MIPS: OCTEON: Implement the core-16057 workaround | David Daney | 1 | -0/+22 |
| 2015-02-20 | MIPS: OCTEON: Delete unused COP2 saving code |   Aleksey Makarov | 1 | -26/+0 |
| 2015-02-20 | MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register | Chandrakala Chavva | 1 | -3/+3 |
| 2015-02-20 | MIPS: OCTEON: Save and restore CP2 SHA3 state | David Daney | 3 | -11/+35 |
| 2015-02-20 | MIPS: OCTEON: Fix FP context save. | David Daney | 1 | -12/+7 |
| 2015-02-20 | MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUs | David Daney | 4 | -30/+148 |
| 2015-02-20 | MIPS: boot: Provide more uImage options |   Markos Chandras | 2 | -2/+55 |
| 2015-02-20 | MIPS: Remove unneeded #ifdef __KERNEL__ from asm/processor.h | David Daney | 1 | -6/+0 |
| 2015-02-20 | MIPS: ip22-gio: Remove legacy suspend/resume support |   Lars-Peter Clausen | 2 | -26/+0 |
| 2015-02-20 | mips: pci: Add ifdef around pci_proc_domain |   Zubair Lutfullah Kakakhel | 1 | -0/+2 |
| 2015-02-20 | MIPS: Alchemy: Fix cpu clock calculation |   Manuel Lauss | 1 | -0/+2 |
| 2015-02-20 | MIPS: Alchemy: remove declaration for set_cpuspec | Manuel Lauss | 1 | -1/+0 |
| 2015-02-20 | MIPS: Alchemy: preset loops_per_jiffy based on CPU clock | Manuel Lauss | 2 | -0/+9 |
| 2015-02-20 | MIPS: Alchemy: fix Au1000/Au1500 LRCLK calculation | Manuel Lauss | 1 | -5/+14 |
| 2015-02-20 | MIPS: Add set/clear CP0 macros for PageGrain register |   Steven J. Hill | 3 | -4/+5 |
| 2015-02-19 | MIPS: Usage and cosmetic cleanups of page table bits. | Steven J. Hill | 2 | -62/+38 |
| 2015-02-19 | Merge branch 'mipsr6-for-3.20' of git://git.linux-mips.org/pub/scm/mchandras/linux into mips-for-linux-next |   Ralf Baechle | 65 | -413/+4403 |
| 2015-02-19 | MIPS: Export MSA functions used by lose_fpu(1) for KVM |   James Hogan | 1 | -0/+4 |
| 2015-02-19 | MIPS: Export FP functions used by lose_fpu(1) for KVM | James Hogan | 1 | -0/+6 |
| 2015-02-19 | MIPS: BCM3384: Fix outdated use of mips_cpu_intc_init() |   Kevin Cernekee | 1 | -1/+1 |
| 2015-02-19 | MIPS: Provide correct siginfo_t.si_stime |   Petr Malat | 2 | -37/+3 |
| 2015-02-19 | MIPS: Makefile: Move the ASEs checks after setting the core's CFLAGS | Markos Chandras | 1 | -18/+17 |
| 2015-02-19 | MIPS: Makefile: Pass -march option on Loongson3A cores | Ralf Baechle | 1 | -0/+10 |
| 2015-02-17 | MIPS: Add Malta QEMU 32R6 defconfig | Markos Chandras | 1 | -0/+193 |
| 2015-02-17 | MIPS: Malta: Add support for building MIPS R6 kernel | Markos Chandras | 1 | -0/+2 |
| 2015-02-17 | MIPS: kernel: elf: Improve the overall ABI and FPU mode checks | Markos Chandras | 3 | -130/+192 |
| 2015-02-17 | MIPS: asm: fpu: Allow 64-bit FPU on MIPS32 R6 | Markos Chandras | 1 | -1/+2 |
| 2015-02-17 | MIPS: kernel: process: Do not allow FR=0 on MIPS R6 | Markos Chandras | 1 | -0/+4 |
| 2015-02-17 | MIPS: Handle MIPS IV, V and R2 FPU instructions on MIPS R6 as well | Markos Chandras | 2 | -5/+6 |
| 2015-02-17 | MIPS: Make use of the ERETNC instruction on MIPS R6 | Markos Chandras | 5 | -4/+28 |
| 2015-02-17 | MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6 |   Leonid Yegoshin | 8 | -5/+2518 |
| 2015-02-17 | MIPS: asm: mipsregs: Add support for the LLADDR register | Markos Chandras | 1 | -0/+2 |
| 2015-02-17 | MIPS: Add LLB bit and related feature for the Config 5 CP0 register | Markos Chandras | 4 | -0/+7 |
| 2015-02-17 | MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructions | Markos Chandras | 3 | -1/+20 |
| 2015-02-17 | MIPS: Emulate the new MIPS R6 BEQZC and JIC instructions | Markos Chandras | 3 | -1/+16 |
| 2015-02-17 | MIPS: Emulate the new MIPS R6 BALC instruction | Markos Chandras | 3 | -1/+19 |
| 2015-02-17 | MIPS: Emulate the new MIPS R6 BNVC, BNEC and BNEZLAC instructions | Markos Chandras | 3 | -2/+7 |
| 2015-02-17 | MIPS: Emulate the new MIPS R6 BOVC, BEQC and BEQZALC instructions | Markos Chandras | 3 | -1/+21 |
| 2015-02-17 | MIPS: Emulate the new MIPS R6 branch compact (BC) instruction | Markos Chandras | 3 | -1/+23 |
| 2015-02-17 | MIPS: Emulate the new MIPS R6 B{L,G}T{Z,}{AL,}C instructions | Markos Chandras | 2 | -0/+47 |
| 2015-02-17 | MIPS: Emulate the new MIPS R6 B{L,G}Ε{Z,}{AL,}C instructions | Markos Chandras | 2 | -0/+55 |
| 2015-02-17 | MIPS: Emulate the BC1{EQ,NE}Z FPU instructions | Markos Chandras | 3 | -30/+101 |
