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2022-09-04gpio: exar: access MPIO registers on cascaded chipsQingtao Cao1-5/+35
When EXAR xr17v35x chips are cascaded in order to access the MPIO registers (part of the Device Configuration Registers) of the secondary chips, an offset needs to be applied based on the number of primary chip's UART channels. Signed-off-by: Qingtao Cao <qingtao.cao@digi.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
2022-09-04gpiolib: make fwnode_get_named_gpiod() staticDmitry Torokhov2-79/+66
There are no external users of fwnode_get_named_gpiod() anymore, so let's stop exporting it and mark it as static. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
2022-09-04Linux 6.0-rc4Linus Torvalds1-1/+1
2022-09-04cgroup: add pids.peak interface for pids controllerJosh Don1-2/+35
pids.peak tracks the high watermark of usage for number of pids. This helps give a better baseline on which to set pids.max. Polling pids.current isn't really feasible, since it would potentially miss short-lived spikes. This interface is analogous to memory.peak. Signed-off-by: Josh Don <joshdon@google.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2022-09-04cgroup: Remove data-race around cgrp_dfl_visibleTejun Heo1-2/+2
There's a seemingly harmless data-race around cgrp_dfl_visible detected by kernel concurrency sanitizer. Let's remove it by throwing WRITE/READ_ONCE at it. Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: Abhishek Shah <abhishek.shah@columbia.edu> Cc: Gabriel Ryan <gabe@cs.columbia.edu> Reviewed-by: Christian Brauner (Microsoft) <brauner@kernel.org> Link: https://lore.kernel.org/netdev/20220819072256.fn7ctciefy4fc4cu@wittgenstein/
2022-09-04Merge tag 'powerpc-6.0-4' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linuxLinus Torvalds6-69/+89
Pull powerpc fixes from Michael Ellerman: - Fix handling of PCI domains in /proc on 32-bit systems using the recently added support for numbering buses from zero for each domain. - A fix and a revert for some changes to use READ/WRITE_ONCE() which caused problems with KASAN enabled due to sanitisation calls being introduced in low-level paths that can't cope with it. - Fix build errors on 32-bit caused by the syscall table being misaligned sometimes. - Two fixes to get IBM Cell native machines booting again, which had bit-rotted while my QS22 was temporarily out of action. - Fix the papr_scm driver to not assume the order of events returned by the hypervisor is stable, and a related compile fix. Thanks to Aneesh Kumar K.V, Christophe Leroy, Jordan Niethe, Kajol Jain, Masahiro Yamada, Nathan Chancellor, Pali Rohár, Vaibhav Jain, and Zhouyi Zhou. * tag 'powerpc-6.0-4' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: powerpc/papr_scm: Ensure rc is always initialized in papr_scm_pmu_register() Revert "powerpc/irq: Don't open code irq_soft_mask helpers" powerpc: Fix hard_irq_disable() with sanitizer powerpc/rtas: Fix RTAS MSR[HV] handling for Cell Revert "powerpc: Remove unused FW_FEATURE_NATIVE references" powerpc: align syscall table for ppc32 powerpc/pci: Enable PCI domains in /proc when PCI bus numbers are not unique powerpc/papr_scm: Fix nvdimm event mappings
2022-09-04Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds14-103/+151
Pull kvm fixes from Paolo Bonzini: "s390: - PCI interpretation compile fixes RISC-V: - fix unused variable warnings in vcpu_timer.c - move extern sbi_ext declarations to a header x86: - check validity of argument to KVM_SET_MP_STATE - use guest's global_ctrl to completely disable guest PEBS - fix a memory leak on memory allocation failure - mask off unsupported and unknown bits of IA32_ARCH_CAPABILITIES - fix build failure with Clang integrated assembler - fix MSR interception - always flush TLBs when enabling dirty logging" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: x86: check validity of argument to KVM_SET_MP_STATE perf/x86/core: Completely disable guest PEBS via guest's global_ctrl KVM: x86: fix memoryleak in kvm_arch_vcpu_create() KVM: x86: Mask off unsupported and unknown bits of IA32_ARCH_CAPABILITIES KVM: s390: pci: Hook to access KVM lowlevel from VFIO riscv: kvm: move extern sbi_ext declarations to a header riscv: kvm: vcpu_timer: fix unused variable warnings KVM: selftests: Fix ambiguous mov in KVM_ASM_SAFE() KVM: selftests: Fix KVM_EXCEPTION_MAGIC build with Clang KVM: VMX: Heed the 'msr' argument in msr_write_intercepted() kvm: x86: mmu: Always flush TLBs when enabling dirty logging kvm: x86: mmu: Drop the need_remote_flush() function
2022-09-04Makefile.extrawarn: re-enable -Wformat for clang; take 2Nick Desaulniers1-0/+12
-Wformat was recently re-enabled for builds with clang, then quickly re-disabled, due to concerns stemming from the frequency of default argument promotion related warning instances. commit 258fafcd0683 ("Makefile.extrawarn: re-enable -Wformat for clang") commit 21f9c8a13bb2 ("Revert "Makefile.extrawarn: re-enable -Wformat for clang"") ISO WG14 has ratified N2562 to address default argument promotion explicitly for printf, as part of the upcoming ISO C2X standard. The behavior of clang was changed in clang-16 to not warn for the cited cases in all language modes. Add a version check, so that users of clang-16 now get the full effect of -Wformat. For older clang versions, re-enable flags under the -Wformat group that way users still get some useful checks related to format strings, without noisy default argument promotion warnings. I intentionally omitted -Wformat-y2k and -Wformat-security from being re-enabled, which are also part of -Wformat in clang-16. Link: https://github.com/ClangBuiltLinux/linux/issues/378 Link: https://github.com/llvm/llvm-project/issues/57102 Link: https://www.open-std.org/jtc1/sc22/wg14/www/docs/n2562.pdf Suggested-by: Justin Stitt <jstitt007@gmail.com> Suggested-by: Nathan Chancellor <nathan@kernel.org> Suggested-by: Youngmin Nam <youngmin.nam@samsung.com> Signed-off-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2022-09-04dt-bindings: dma: mediatek,uart-dma: Add binding for MT6795 SoCAngeloGioacchino Del Regno1-0/+1
Add mediatek,mt6795-uart-dma to the compatibles list to support the MT6795 Helio X10 SoC's UART APDMA. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220729104441.39177-2-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04dmaengine: xilinx_dma: Report error in case of dma_set_mask_and_coherent API failureSwati Agarwal1-1/+5
The driver does not handle the failure case while calling dma_set_mask_and_coherent API. In case of failure, capture the return value of API and then report an error. Addresses-coverity: Unchecked return value (CHECKED_RETURN) Signed-off-by: Swati Agarwal <swati.agarwal@xilinx.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/20220817061125.4720-4-swati.agarwal@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04dmaengine: xilinx_dma: cleanup for fetching xlnx,num-fstores propertySwati Agarwal1-1/+1
Free the allocated resources for missing xlnx,num-fstores property. Signed-off-by: Swati Agarwal <swati.agarwal@xilinx.com> Link: https://lore.kernel.org/r/20220817061125.4720-3-swati.agarwal@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04dmaengine: xilinx_dma: Fix devm_platform_ioremap_resource error handlingSwati Agarwal1-6/+7
Add missing cleanup in devm_platform_ioremap_resource(). When probe fails remove dma channel resources and disable clocks in accordance with the order of resources allocated . Signed-off-by: Swati Agarwal <swati.agarwal@xilinx.com> Link: https://lore.kernel.org/r/20220817061125.4720-2-swati.agarwal@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04dmaengine: hsu: Include headers we are direct user ofAndy Shevchenko5-4/+18
For the sake of integrity, include headers we are direct user of. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220713172235.22611-4-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04dmaengine: hsu: Use GENMASK() consistentlyAndy Shevchenko1-3/+4
For the masks replace chain of BIT() macros by GENMASK(). While at it, explicitly include bits.h. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220713172235.22611-3-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04dmaengine: hsu: using for_each_set_bit to simplify the codeAndy Shevchenko1-11/+8
It's more cleanly to use for_each_set_bit() instead of opencoding it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220713172235.22611-2-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04dmaengine: hsu: Finish conversion to managed resourcesAndy Shevchenko1-15/+12
With help of devm_add_action_or_reset() we may finish conversion the driver to use managed resources. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220713172235.22611-1-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04dmaengine: stm32-mdma: add support to be triggered by STM32 DMAAmelie Delaunay1-1/+69
STM32 MDMA can be triggered by STM32 DMA channels transfer complete. In case of non-null struct dma_slave_config .peripheral_size, it means the DMA client wants the DMA to trigger the MDMA. stm32-mdma driver gets the request id, the mask_addr, and the mask_data in struct stm32_mdma_dma_config passed by DMA with struct dma_slave_config .peripheral_config/.peripheral_size. Then, as DMA is configured in Double-Buffer mode, and MDMA channel will transfer data from/to SRAM to/from DDR, then bursts are optimized. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20220829154646.29867-7-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04dmaengine: stm32-dma: add support to trigger STM32 MDMAAmelie Delaunay1-1/+46
STM32 MDMA can be triggered by STM32 DMA channels transfer complete. The "request line number" triggering STM32 MDMA is the STM32 DMAMUX channel id set by stm32-dmamux driver in dma_spec->args[3]. stm32-dma driver fills the struct stm32_dma_mdma_config used to configure the MDMA with struct dma_slave_config .peripheral_config/.peripheral_size. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20220829154646.29867-6-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04dmaengine: stm32-dmamux: set dmamux channel id in dma features bitfieldAmelie Delaunay1-1/+1
STM32 DMAMUX is used with STM32 DMA1 and DMA2: - DMAMUX channels 0 to 7 are connected to DMA1 channels 0 to 7 - DMAMUX channels 8 to 15 are connected to DMA2 channels 0 to 7 STM32 MDMA can be triggered by DMA1 and DMA2 channels transfer complete, and the "request line number" is the DMAMUX channel id (e.g. DMA2 channel 0 triggers MDMA with request line 8). To well configure MDMA, set DMAMUX channel id in DMA features bitfield, so that DMA can update struct dma_slave_config peripheral_config properly. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20220829154646.29867-5-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04docs: arm: stm32: introduce STM32 DMA-MDMA chaining featureAmelie Delaunay2-0/+416
STM32 DMA-MDMA chaining feature is available on STM32 SoCs which embed STM32 DMAMUX, DMA and MDMA controllers. It is the case on STM32MP1 SoCs but also on STM32H7 SoCs. But focus is on STM32MP1 SoCs, using DDR. This documentation aims to explain how to use STM32 DMA-MDMA chaining feature in drivers of STM32 peripheral having request lines on STM32 DMA. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20220829154646.29867-4-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04dmaengine: stm32-dma: use bitfield helpersAmelie Delaunay1-35/+25
Use the FIELD_{GET,PREP}() helpers, instead of defining custom macros implementing the same operations. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20220829154646.29867-3-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04dmaengine: stm32-dma: introduce 3 helpers to address channel flagsAmelie Delaunay1-17/+12
Channels 0 to 3 flags are described in DMA_LISR and DMA_LIFCR (L as Low). Channels 4 to 7 flags are described in DMA_HISR and DMA_HIFCR (H as High). Macro STM32_DMA_ISR(n) returns the interrupt status register offset for the channel id (n). Macro STM32_DMA_IFCR(n) returns the interrupt flag clear register offset for the channel id (n). If chan->id % 4 = 2 or 3, then its flags are left-shifted by 16 bits. If chan->id % 4 = 1 or 3, then its flags are additionally left-shifted by 6 bits. If chan->id % 4 = 0, then its flags are not shifted. Macro STM32_DMA_FLAGS_SHIFT(n) returns the required shift to get or set the channel flags mask. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20220829154646.29867-2-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04MAINTAINERS: Add myself as maintainer for hisi_dmaJie Hai1-0/+1
Add myself as a maintainer for hisi_dma. Signed-off-by: Jie Hai <haijie1@huawei.com> Acked-by: Zhou Wang <wangzhou1@hisilicon.com> Link: https://lore.kernel.org/r/20220830062251.52993-8-haijie1@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04dmaengine: hisilicon: Dump regs to debugfsJie Hai1-2/+236
This patch adds dump of registers with debugfs for HIP08 and HIP09 DMA driver. Signed-off-by: Jie Hai <haijie1@huawei.com> Acked-by: Zhou Wang <wangzhou1@hisilicon.com> Link: https://lore.kernel.org/r/20220830062251.52993-7-haijie1@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04dmaengine: hisilicon: Adapt DMA driver to HiSilicon IP09Jie Hai1-78/+295
The HiSilicon IP08 and HiSilicon IP09 are DMA iEPs, they have the same pci device id but different pci revision. Unfortunately, they have different register layouts, so the origin driver cannot run on HiSilicon IP09 correctly. This patch enables the driver to adapt to HiSilicon IP09. HiSilicon IP09 offers 4 channels, each channel has a send queue, a complete queue and an interrupt to help to do tasks. This DMA engine can do memory copy between memory blocks. Signed-off-by: Jie Hai <haijie1@huawei.com> Acked-by: Zhou Wang <wangzhou1@hisilicon.com> Link: https://lore.kernel.org/r/20220830062251.52993-6-haijie1@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04dmaengine: hisilicon: Use macros instead of magic numberJie Hai1-6/+13
readl_relaxed_poll_timeout() uses magic numbers 10 and 1000, which indicate maximum time to sleep between reads in us and timeout in us, respectively. Use macros HISI_DMA_POLL_Q_STS_DELAY_US and HISI_DMA_POLL_Q_STS_TIME_OUT_US instead of these two numbers. Signed-off-by: Jie Hai <haijie1@huawei.com> Acked-by: Zhou Wang <wangzhou1@hisilicon.com> Link: https://lore.kernel.org/r/20220830062251.52993-5-haijie1@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04dmaengine: hisilicon: Add multi-thread support for a DMA channelJie Hai1-4/+2
When we get a DMA channel and try to use it in multiple threads it will cause oops and hanging the system. % echo 100 > /sys/module/dmatest/parameters/threads_per_chan % echo 100 > /sys/module/dmatest/parameters/iterations % echo 1 > /sys/module/dmatest/parameters/run [383493.327077] Unable to handle kernel paging request at virtual address dead000000000108 [383493.335103] Mem abort info: [383493.335103] ESR = 0x96000044 [383493.335105] EC = 0x25: DABT (current EL), IL = 32 bits [383493.335107] SET = 0, FnV = 0 [383493.335108] EA = 0, S1PTW = 0 [383493.335109] FSC = 0x04: level 0 translation fault [383493.335110] Data abort info: [383493.335111] ISV = 0, ISS = 0x00000044 [383493.364739] CM = 0, WnR = 1 [383493.367793] [dead000000000108] address between user and kernel address ranges [383493.375021] Internal error: Oops: 96000044 [#1] PREEMPT SMP [383493.437574] CPU: 63 PID: 27895 Comm: dma0chan0-copy2 Kdump: loaded Tainted: GO 5.17.0-rc4+ #2 [383493.457851] pstate: 204000c9 (nzCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--) [383493.465331] pc : vchan_tx_submit+0x64/0xa0 [383493.469957] lr : vchan_tx_submit+0x34/0xa0 This occurs because the transmission timed out, and that's due to data race. Each thread rewrite channels's descriptor as soon as device_issue_pending is called. It leads to the situation that the driver thinks that it uses the right descriptor in interrupt handler while channels's descriptor has been changed by other thread. The descriptor which in fact reported interrupt will not be handled any more, as well as its tx->callback. That's why timeout reports. With current fixes channels' descriptor changes it's value only when it has been used. A new descriptor is acquired from vc->desc_issued queue that is already filled with descriptors that are ready to be sent. Threads have no direct access to DMA channel descriptor. In case of channel's descriptor is busy, try to submit to HW again when a descriptor is completed. In this case, vc->desc_issued may be empty when hisi_dma_start_transfer is called, so delete error reporting on this. Now it is just possible to queue a descriptor for further processing. Fixes: e9f08b65250d ("dmaengine: hisilicon: Add Kunpeng DMA engine support") Signed-off-by: Jie Hai <haijie1@huawei.com> Acked-by: Zhou Wang <wangzhou1@hisilicon.com> Link: https://lore.kernel.org/r/20220830062251.52993-4-haijie1@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04dmaengine: hisilicon: Fix CQ head updateJie Hai1-5/+3
After completion of data transfer of one or multiple descriptors, the completion status and the current head pointer to submission queue are written into the CQ and interrupt can be generated to inform the software. In interrupt process CQ is read and cq_head is updated. hisi_dma_irq updates cq_head only when the completion status is success. When an abnormal interrupt reports, cq_head will not update which will cause subsequent interrupt processes read the error CQ and never report the correct status. This patch updates cq_head whenever CQ is accessed. Fixes: e9f08b65250d ("dmaengine: hisilicon: Add Kunpeng DMA engine support") Signed-off-by: Jie Hai <haijie1@huawei.com> Acked-by: Zhou Wang <wangzhou1@hisilicon.com> Link: https://lore.kernel.org/r/20220830062251.52993-3-haijie1@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04dmaengine: hisilicon: Disable channels when unregister hisi_dmaJie Hai1-5/+9
When hisi_dma is unloaded or unbinded, all of channels should be disabled. This patch disables DMA channels when driver is unloaded or unbinded. Fixes: e9f08b65250d ("dmaengine: hisilicon: Add Kunpeng DMA engine support") Signed-off-by: Jie Hai <haijie1@huawei.com> Acked-by: Zhou Wang <wangzhou1@hisilicon.com> Link: https://lore.kernel.org/r/20220830062251.52993-2-haijie1@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04ipmi:ipmb: Fix a vague comment and a typoCorey Minyard1-2/+2
Sending an IPMI response message gets a reponse to the response, but the comment saying that just said "response response", which is hard to understand. Also fix an obvious typo. Reported-by: Shaomin Deng <dengshaomin@cdjrlc.com> Signed-off-by: Corey Minyard <cminyard@mvista.com>
2022-09-04dmaengine: idxd: avoid deadlock in process_misc_interrupts()Jerry Snitselaar1-2/+0
idxd_device_clear_state() now grabs the idxd->dev_lock itself, so don't grab the lock prior to calling it. This was seen in testing after dmar fault occurred on system, resulting in lockup stack traces. Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: Dave Jiang <dave.jiang@intel.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: dmaengine@vger.kernel.org Fixes: cf4ac3fef338 ("dmaengine: idxd: fix lockdep warning on device driver removal") Signed-off-by: Jerry Snitselaar <jsnitsel@redhat.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20220823163709.2102468-1-jsnitsel@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04arm64: dts: rockchip: Add initial support for Pine64 PinePhone ProMartijn Braam2-0/+399
This is a basic DT containing regulators and UART, intended to be a base that myself and others can add additional nodes in future patches. Tested to work: booting from eMMC/SD, output over UART. https://wiki.pine64.org/wiki/PinePhone_Pro This is derived from the community pine64-org repo[0] with fixes from https://megous.com/git/linux. 0. https://gitlab.com/pine64-org/linux/-/commit/261d3b5f8ac503f97da810986d1d6422430c8531 Signed-off-by: Martijn Braam <martijn@brixit.nl> Co-developed-by: Kamil Trzciński <ayufan@ayufan.eu> [no SoB, but Kamil is happy for this patch to be submitted] Co-developed-by: Ondrej Jirman <megi@xff.cz> Signed-off-by: Ondrej Jirman <megi@xff.cz> Co-developed-by: Tom Fitzhenry <tom@tom-fitzhenry.me.uk> Signed-off-by: Tom Fitzhenry <tom@tom-fitzhenry.me.uk> Reviewed-by: Caleb Connolly <kc@postmarketos.org> Reviewed-by: Nícolas F. R. A. Prado <n@nfraprado.net> Tested-by: Nícolas F. R. A. Prado <n@nfraprado.net> Link: https://lore.kernel.org/r/20220829050040.17330-2-tom@tom-fitzhenry.me.uk Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-09-04dt-bindings: arm: rockchip: Add PinePhone Pro bindingsTom Fitzhenry1-0/+5
Document board compatible names for Pine64 PinePhonePro. https://wiki.pine64.org/wiki/PinePhone_Pro Signed-off-by: Tom Fitzhenry <tom@tom-fitzhenry.me.uk> Reviewed-by: Caleb Connolly <kc@postmarketos.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220815123004.252014-2-tom@tom-fitzhenry.me.uk Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-09-04dmaengine: qcom: gpi: Add SM6350 supportLuca Weiss1-0/+1
The Qualcomm SM6350 platform does, like the SM8450, provide a set of GPI controllers with an ee-offset of 0x10000. Add this to the driver. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220812082721.1125759-3-luca.weiss@fairphone.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04dt-bindings: dmaengine: qcom: gpi: add compatible for SM6350Luca Weiss1-0/+1
Document the compatible for GPI DMA controller on SM6350 SoC. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220812082721.1125759-2-luca.weiss@fairphone.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04arm64: dts: rockchip: Set RK3399-Gru PCLK_EDP to 24 MHzzain wang1-0/+8
We've found the AUX channel to be less reliable with PCLK_EDP at a higher rate (typically 25 MHz). This is especially important on systems with PSR-enabled panels (like Gru-Kevin), since we make heavy, constant use of AUX. According to Rockchip, using any rate other than 24 MHz can cause "problems between syncing the PHY an PCLK", which leads to all sorts of unreliabilities around register operations. Fixes: d67a38c5a623 ("arm64: dts: rockchip: move core edp from rk3399-kevin to shared chromebook") Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: zain wang <wzz@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> Link: https://lore.kernel.org/r/20220830131212.v2.1.I98d30623f13b785ca77094d0c0fd4339550553b6@changeid Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-09-04arm64: dts: rockchip: Add dts for a rk3399 based board EAIDK-610Andy Yan2-0/+940
EAIDK-610 is from OPEN AI LAB and popularly used by university students. Specification: - Rockchip RK3399 - LPDDR3 4GB - TF sd scard slot - eMMC - AP6255 for WiFi + BT - Gigabit ethernet - HDMI out - 40 pin header - USB 2.0 x 2 - USB 3.0 x 1 - USB 3.0 Type-C x 1 - 12V DC Power supply This patch is test on Armbain and Glodroid with HDMI/GPU/USB HOST/Type-C ADB/WIFI/BT. Signed-off-by: Andy Yan <andyshrk@163.com> Link: https://lore.kernel.org/r/20220709103016.2754044-1-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-09-04dt-bindings: arm: rockchip: Add EAIDK-610Andy Yan1-0/+5
EAIDK-610 is a rk3399 based board from OPEN AI LAB and popularly used by university students. Specification: - Rockchip RK3399 - LPDDR3 4GB - TF sd scard slot - eMMC - AP6255 for WiFi + BT - Gigabit ethernet - HDMI out - 40 pin header - USB 2.0 x 2 - USB 3.0 x 1 - USB 3.0 Type-C x 1 - 12V DC Power supply Signed-off-by: Andy Yan <andyshrk@163.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220709103001.2753992-1-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-09-04dt-bindings: vendor-prefixes: Add OPEN AI LABAndy Yan1-0/+2
Add vendor prefixes for OPEN AI LAB. Signed-off-by: Andy Yan <andyshrk@163.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220709102942.2753939-1-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-09-04dt-bindings: dma: arm,pl330: Add missing 'iommus' propertyRob Herring1-0/+6
The pl330 can be behind an IOMMU which is the case for Arm Juno board. Add the 'iommus' property allowing for 1 IOMMU entry per channel for writes and 1 IOMMU entry for reads. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220801210237.1501488-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04arm64: dts: rockchip: add csi dphy node to rk356xMichael Riesch1-0/+12
Add the MIPI CSI DPHY node to the RK356x device tree. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20220720091527.1270365-4-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-09-04dt-bindings: iio: adc: Add max11205 documentation fileRamona Bolboaca2-0/+77
Add bindings documentation file and MAINTAINERS entry for MAX11205. Signed-off-by: Ramona Bolboaca <ramona.bolboaca@analog.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220831133021.215625-1-ramona.bolboaca@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2022-09-04iio: magnetometer: yamaha-yas530: Use dev_err_probe()Andy Shevchenko1-10/+6
Unify error message format by using dev_err_probe(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220831141530.80572-3-andriy.shevchenko@linux.intel.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2022-09-04iio: magnetometer: yamaha-yas530: Make strings const in chip infoAndy Shevchenko1-2/+2
For better compiler coverage mark strings consts in the chip info. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220831141530.80572-2-andriy.shevchenko@linux.intel.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2022-09-04iio: magnetometer: yamaha-yas530: Use pointers as driver dataAndy Shevchenko1-10/+13
Unify ID tables to use pointers for driver data. It will allow to simplify the driver later on. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220831141530.80572-1-andriy.shevchenko@linux.intel.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2022-09-04arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-ProFrank Wunderlich1-0/+117
Add Nodes to Bananapi-R2-Pro board to support PCIe v3 and set PCIe related regulators to always on. Suggested-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Link: https://lore.kernel.org/r/20220825193836.54262-6-linux@fw-web.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-09-04arm64: dts: rockchip: Add PCIe v3 nodes to rk3568Frank Wunderlich1-0/+122
Add nodes to rk356x devicetree to support PCIe v3. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Link: https://lore.kernel.org/r/20220825193836.54262-5-linux@fw-web.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-09-04dt-bindings: soc: grf: add pcie30-{phy,pipe}-grfFrank Wunderlich1-0/+3
Add compatibles for PCIe v3 General Register Files. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220825193836.54262-3-linux@fw-web.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-09-04phy: rockchip-inno-usb2: Return zero after otg syncPeter Geis1-4/+6
The otg sync state patch reuses the ret variable, but fails to set it to zero after use. This leads to a situation when the otg port is in peripheral mode where the otg phy aborts halfway through setup. It also fails to account for a failure to register the extcon notifier. Fix this by using our own variable and skipping otg sync in case of failure. Fixes: 8dc60f8da22f ("phy: rockchip-inno-usb2: Sync initial otg state") Reported-by: Markus Reichl <m.reichl@fivetechno.de> Reported-by: Michael Riesch <michael.riesch@wolfvision.net> Signed-off-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Michael Riesch <michael.riesch@wolfvision.net> Tested-by: Markus Reichl <m.reichl@fivetechno.de> Reviewed-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220902184543.1234835-1-pgwipeout@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-04phy: amlogic: use devm_clk_get_enabled() to simplify the codeHeiner Kallweit1-26/+6
Simplify the code by using devm_clk_get_enabled(). Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/9308a2a3-e828-bd9d-ab83-a68376aab5c3@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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