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2022-08-29drm/amd/display: Cursor lag with PSR1 eDPGabe Teeger1-5/+1
[Why] On edp with psr1, we do not provide updates of the cursor position regularly to firmware like with PSR2. To send updates regularly, the flag enable_sw_cntl_psr has to equal 1, but cursor update should be provided regularly to FW regardless of that flag. [How] Ensure that we always send cursor updates to firmware when PSR version equals 1. Reviewed-by: Robin Chen <robin.chen@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Add DC debug option to force LTTPR modeMichael Strauss2-0/+5
[WHY] Useful for external teams debugging LTTPR issues Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: add a override flag as wa for some specific dongleLeo Chen1-0/+1
[Why & How] Add a override flag as wa for some specific dongle Co-authored-by: Leo Chen <sancchen@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Leo Chen <SanChuan.Chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29arm64: dts: qcom: sa8295p-adp: disallow regulator mode switchesJohan Hovold1-11/+0
Do not allow the RPMh regulators to switch to low-power mode with an exception for the UFS regulators (l3c, l6c, l10c and l17c) as UFS supports an idle mode. This specifically avoids having regulators be but in low-power mode when only some consumers specify loads while the actual total load really warrants high-power mode. Fixes: 519183af39b2 ("arm64: dts: qcom: add SA8540P and ADP") Link: https://lore.kernel.org/all/YtkrDcjTGhpaU1e0@hovoldconsulting.com Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220803121942.30236-4-johan+linaro@kernel.org
2022-08-29arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13s: disallow regulator mode switchesJohan Hovold1-10/+0
Do not allow the RPMh regulators to switch to low-power mode. This specifically avoids having regulators be but in low-power mode when only some consumers specify loads while the actual total load really warrants high-power mode. Fixes: 32c231385ed4 ("arm64: dts: qcom: sc8280xp: add Lenovo Thinkpad X13s devicetree") Link: https://lore.kernel.org/all/YtkrDcjTGhpaU1e0@hovoldconsulting.com Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220803121942.30236-3-johan+linaro@kernel.org
2022-08-29arm64: dts: qcom: sc8280xp-crd: disallow regulator mode switchesJohan Hovold1-9/+0
Do not allow the RPMh regulators to switch to low-power mode with an exception for the UFS regulators (l7c and l3d) as UFS supports an idle mode. This specifically avoids having regulators be but in low-power mode when only some consumers specify loads while the actual total load really warrants high-power mode. Fixes: ccd3517faf18 ("arm64: dts: qcom: sc8280xp: Add reference device") Link: https://lore.kernel.org/all/YtkrDcjTGhpaU1e0@hovoldconsulting.com Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220803121942.30236-2-johan+linaro@kernel.org
2022-08-29arm64: dts: qcom: sc7280: Update lpasscore nodeSatya Priya1-2/+2
To maintain consistency with other lpass nodes(lpass_audiocc, lpass_aon and lpass_hm), update lpasscore to lpass_core. Fixes: 9499240d15f2 ("arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1660107909-27947-4-git-send-email-quic_c_skakit@quicinc.com
2022-08-29arm64: dts: qcom: sc7280: Update lpassaudio clock controller for resetsTaniya Das1-0/+1
The lpass audio supports TX/RX/WSA block resets. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1660107909-27947-3-git-send-email-quic_c_skakit@quicinc.com
2022-08-29arm64: dts: qcom: sc7280: Cleanup the lpasscc nodeSatya Priya1-3/+2
Remove "cc" regmap from lpasscc node which is overlapping with the lpass_aon regmap. Fixes: 422a295221bb ("arm64: dts: qcom: sc7280: Add clock controller nodes") Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1660107909-27947-2-git-send-email-quic_c_skakit@quicinc.com
2022-08-29ARM: dts: qcom: msm8660-surf: move fixed regulator out of socKrzysztof Kozlowski1-9/+7
Fixed regulators, like stub for SDCC Power, are not part of SoC, so they should be outside of the soc node. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220810080516.166866-4-krzysztof.kozlowski@linaro.org
2022-08-29ARM: dts: qcom: msm8660: override nodes by labelKrzysztof Kozlowski1-21/+20
Using node paths to extend or override a device tree node is error prone. If there was a typo error, a new node will be created instead of extending the existing node. This will lead to run-time errors that could be hard to detect. A mistyped label on the other hand, will cause a dtc compile error (during build time). This also reduces the indentation making the code easier to read. The pre/post DTBS are the same. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220810080516.166866-3-krzysztof.kozlowski@linaro.org
2022-08-29ARM: dts: qcom: msm8226: override nodes by labelKrzysztof Kozlowski1-4/+2
Using node paths to extend or override a device tree node is error prone. If there was a typo error, a new node will be created instead of extending the existing node. This will lead to run-time errors that could be hard to detect. A mistyped label on the other hand, will cause a dtc compile error (during build time). This also reduces the indentation making the code easier to read. The pre/post DTBS are the same. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220810080516.166866-2-krzysztof.kozlowski@linaro.org
2022-08-29ARM: dts: qcom: msm8960: override nodes by labelKrzysztof Kozlowski2-284/+283
Using node paths to extend or override a device tree node is error prone. If there was a typo error, a new node will be created instead of extending the existing node. This will lead to run-time errors that could be hard to detect. A mistyped label on the other hand, will cause a dtc compile error (during build time). This also reduces the indentation making the code easier to read. The pre/post DTBS are the same. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220810080516.166866-1-krzysztof.kozlowski@linaro.org
2022-08-29drm/amd/display: Only commit SubVP state after pipe programmingAlvin Lee1-8/+7
[Description] We only want to commit the SubVP config to DMCUB after the main and phantom pipe programming has completed. Commiting the state early can cause issues such as P-State being allowed by the HW early which causes the SubVP state machine to go into a bad state Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/bridge: ps8640: Add double reset T4 and T5 to power-on sequenceHsin-Yi Wang1-0/+5
The double reset power-on sequence is a workaround for the hardware flaw in some chip that SPI Clock output glitch and cause internal MPU unable to read firmware correctly. The sequence is suggested in ps8640 application note. Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: Rock Chiu <rock.chiu@paradetech.corp-partner.google.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20220815093905.134164-1-hsinyi@chromium.org
2022-08-29drm/amd/display: Remove assert from PHY state updateTaimur Hassan1-3/+1
[Why & How] In some cases, there are calls to transition from TX_ON to TX_ON. This is expected, so do not assert. However, these are redundant, so return prematurely. Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: set dig fifo read start level to 7 before dig fifo resetWang Fudong1-0/+5
[Why] DIG_FIFO_ERROR = 1 caused mst daisy chain 2nd monitor black. [How] We need to set dig fifo read start level = 7 before dig fifo reset during dig fifo enable according to hardware designer's suggestion. If it is zero, it will cause underflow or overflow and DIG_FIFO_ERROR = 1. Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Wang Fudong <Fudong.Wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29arm64: dts: qcom: sm6350: Add GPI DMA nodesLuca Weiss1-0/+59
Add nodes for the gpi_dma0 and gpi_dma1 which are (optionally) used for various i2c busses based on the qup firmware configuration. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220812082721.1125759-4-luca.weiss@fairphone.com
2022-08-29drm/amdgpu: Fix use-after-free in amdgpu_cs_ioctlYuBiao Wang1-1/+4
[Why] In amdgpu_cs_ioctl, amdgpu_job_free could be performed ealier if there is -ERESTARTSYS error. In this case, job->hw_fence could be not initialized yet. Putting hw_fence during amdgpu_job_free could lead to a use-after-free warning. [How] Check if drm_sched_job_init is performed before job_free by checking s_fence. v2: Check hw_fence.ops instead since it could be NULL if fence is not initialized. Reverse the condition since !=NULL check is discouraged in kernel. Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Fix OTG H timing reset for dcn314Duncan Ma1-1/+2
[Why] When ODM is enabled, H timing control register reset to 0. Div mode manual field get overwritten causing no display on certain modes for dcn314. [How] Use REG_UPDATE instead of REG_SET to set div_mode field. Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Duncan Ma <duncan.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Refine aux transaction before retrieve capsLewis Huang1-11/+34
[Why] LTTPR caps will read fail if aux channel is not active. [How] 1.Perform 600 read upto 10 retry with 1ms delay in between. 2.If fail, return false and trigger another retry detection. 3.If pass, read LTTPR caps in retrieve link caps. Reviewed-by: Jimmy Kizito <Jimmy.Kizito@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Lewis Huang <Lewis.Huang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programmingGeorge Shen2-6/+6
[Why] Each index in the DPSTREAMCLK_CNTL register phyiscally maps 1-to-1 with HPO stream encoder instance. On the other hand, each index in DTBCLK_P_CNTL physically maps 1-to-1 with OTG instance. Current DCN32 DPSTREAMCLK_CLK programing assumes that OTG instance always maps 1-to-1 with HPO stream encoder instance. This is not always guaranteed and can result in blackscreen. [How] Program the correct dpstreamclk instance with the correct dtbclk_p source. Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Don't choose SubVP display if ActiveMargin > 0Alvin Lee3-4/+20
[Description] There can be SubVP scheduling issues if a SubVP display is chosen has ActiveDramClockChangeLatency > 0. Block this case for now, and enable Vactive case (later) to handle this. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Set ODM policy based on number of DSC slicesTaimur Hassan3-2/+8
[Why & How] Add addtional check in CalculateODMMode for cases where the ODM combine is needed due to number of DSC slices. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: 3.2.200Aric Cyr1-1/+1
This version brings along following fixes: - Modify pipe split policy - Fix odm 2:1 policy in 4k144 mode - Correct HDMI ODM combine policy - Change AUX NACK behavior - Change runtime initialization for DCN32/321 - Fix cursor flicker in PSRSU - Fix k1/k2 divider for virtual signal for DCN32 - Free phantom plane after removing the context - Add interface to track PHY state - Add SubVP scaling case - Add log clock table for SMU - Fix atomic_check check - Fix SMU 13.0.0 driver_if header - Fix doorbells allocation Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amdgpu: add missing pci_disable_device() in amdgpu_pmops_runtime_resume()Yang Yingliang1-1/+4
Add missing pci_disable_device() if amdgpu_device_resume() fails. Fixes: 8e4d5d43cc6c ("drm/amdgpu: Handling of amdgpu_device_resume return value for graceful teardown") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Fix variable dereferenced before checksunliming1-1/+3
Fixes the following smatch warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c:311 dc_dmub_srv_p_state_delegate() warn: variable dereferenced before check 'dc' (see line 309) Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: sunliming <sunliming@kylinos.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amdgpu: Remove the unneeded result variableye xingchen1-4/+1
Return the value sdma_v5_2_start() directly instead of storing it in another redundant variable. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amdgpu: Update mes_v11_api_def.hGraham Sider2-1/+3
New GFX11 MES FW adds the trap_en bit. For now hardcode to 1 (traps enabled). Signed-off-by: Graham Sider <Graham.Sider@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amdgpu: disable FRU access on special SIENNA CICHLID cardGuchun Chen1-2/+7
Below driver load error will be printed, not friendly to end user. amdgpu: ATOM BIOS: 113-D603GLXE-077 [drm] FRU: Failed to get size field [drm:amdgpu_fru_get_product_info [amdgpu]] *ERROR* Failed to read FRU Manufacturer, ret:-5 Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29arm64: dts: qcom: sdm845: Add the RPMh stats nodeAbel Vesa1-0/+5
SDM845 is a special case compared to the other platforms that use RPMh stats, since it only has 2 stats (aosd and cxsd), while the others have a 3rd one (ddr). So lets add the node but with a SDM845 dedicated compatible to make the driver aware of the different stats config. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Caleb Connolly <caleb.connolly@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220812101240.1869605-3-abel.vesa@linaro.org
2022-08-29arm64: dts: qcom: sdm845: Reduce reg size for aoss_qmpAbel Vesa1-1/+1
Like on the other platforms that provide RPMh stats, on SDM845, the aoss_qmp reg size needs to be reduced to its actual size of 0x400, otherwise it will overlap with the RPMh stats reg base, node that will be added later on. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220812101240.1869605-1-abel.vesa@linaro.org
2022-08-29dt-bindings: soc: qcom: stats: Document SDM845 compatibleAbel Vesa1-0/+1
SDM845 is a special case compared to the other platforms that use RPMh stats, since it only has 2 stats (aosd and cxsd), while the others have a 3rd one (ddr). So in order for the driver to use the dedicated stats config, we added the SDM845 dedicated compatible, which we document here. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220812101240.1869605-4-abel.vesa@linaro.org
2022-08-29soc: qcom: stats: Add SDM845 stats config and compatibleAbel Vesa1-0/+9
SDM845 is a special case compared to the other platforms that use RPMh stats, since it only has 2 stats (aosd and cxsd), while the others have a 3rd one (ddr). So lets add dedicated stats config and compatible for SDM845 to make the driver aware of this num_records difference. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220812101240.1869605-2-abel.vesa@linaro.org
2022-08-29arm64: dts: qcom: pm6150l: add missing adc channelsLuca Weiss1-0/+19
Add the missing adc channels and add pre-scaling property to die_temp channel, as per downstream dts. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220812114614.1195679-1-luca.weiss@fairphone.com
2022-08-29dt-bindings: firmware: document Qualcomm SM6115 SCMAdam Skladowski1-0/+1
Document the compatible for Qualcomm SM6115 SCM. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220815100952.23795-8-a39.skl@gmail.com
2022-08-29arm64: dts: qcom: sm8150: switch TCSR mutex to MMIOKrzysztof Kozlowski1-8/+3
The TCSR mutex bindings allow device to be described only with address space (so it uses MMIO, not syscon regmap). This seems reasonable as TCSR mutex is actually a dedicated IO address space and it also fixes DT schema checks: qcom/sm8150-mtp.dtb: hwlock: 'reg' is a required property qcom/sm8150-mtp.dtb: hwlock: 'syscon' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220819083209.50844-17-krzysztof.kozlowski@linaro.org
2022-08-29arm64: dts: qcom: sm8150: split TCSR halt regs out of mutexKrzysztof Kozlowski1-1/+6
The TCSR halt regs are next to TCSR mutex (in one address block called TCSR_MUTEX), so before converting the TCSR mutex into device with address space, we need to split the halt regs to its own syscon device. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220819083209.50844-16-krzysztof.kozlowski@linaro.org
2022-08-29arm64: dts: qcom: sdm630: switch TCSR mutex to MMIOKrzysztof Kozlowski1-8/+3
The TCSR mutex bindings allow device to be described only with address space (so it uses MMIO, not syscon regmap). This seems reasonable as TCSR mutex is actually a dedicated IO address space and it also fixes DT schema checks: qcom/sdm636-sony-xperia-ganges-mermaid.dtb: hwlock: 'reg' is a required property qcom/sdm636-sony-xperia-ganges-mermaid.dtb: hwlock: 'syscon' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220819083209.50844-15-krzysztof.kozlowski@linaro.org
2022-08-29arm64: dts: qcom: sdm630: split TCSR halt regs out of mutexKrzysztof Kozlowski1-1/+6
The TCSR halt regs are next to TCSR mutex (in one address block called TCSR_MUTEX), so before converting the TCSR mutex into device with address space, we need to split the halt regs to its own syscon device. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220819083209.50844-14-krzysztof.kozlowski@linaro.org
2022-08-29arm64: dts: qcom: qcs404: switch TCSR mutex to MMIOKrzysztof Kozlowski1-8/+3
The TCSR mutex bindings allow device to be described only with address space (so it uses MMIO, not syscon regmap). This seems reasonable as TCSR mutex is actually a dedicated IO address space and it also fixes DT schema checks: qcom/qcs404-evb-4000.dtb: hwlock: 'reg' is a required property qcom/qcs404-evb-4000.dtb: hwlock: 'syscon' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220819083209.50844-13-krzysztof.kozlowski@linaro.org
2022-08-29arm64: dts: qcom: sdm845: switch TCSR mutex to MMIOKrzysztof Kozlowski1-8/+3
The TCSR mutex bindings allow device to be described only with address space (so it uses MMIO, not syscon regmap). This seems reasonable as TCSR mutex is actually a dedicated IO address space and it also fixes DT schema checks: qcom/sdm845-shift-axolotl.dtb: hwlock: 'reg' is a required property qcom/sdm845-shift-axolotl.dtb: hwlock: 'syscon' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220819083209.50844-12-krzysztof.kozlowski@linaro.org
2022-08-29arm64: dts: qcom: sdm845: split TCSR halt regs out of mutexKrzysztof Kozlowski1-2/+7
The TCSR halt regs are next to TCSR mutex (in one address block called TCSR_MUTEX), so before converting the TCSR mutex into device with address space, we need to split the halt regs to its own syscon device. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220819083209.50844-11-krzysztof.kozlowski@linaro.org
2022-08-29arm64: dts: qcom: sc7280: split TCSR halt regs out of mutexKrzysztof Kozlowski1-7/+12
The TCSR halt regs are next to TCSR mutex (in one address block called TCSR_MUTEX), so before converting the TCSR mutex into device with address space, we need to split the halt regs to its own syscon device. This also describes more accurately the devices and their IO address space, and allows to remove incorrect syscon compatible from TCSR mutex: qcom/sc7280-herobrine-crd.dtb: hwlock@1f40000: compatible: ['qcom,tcsr-mutex', 'syscon'] is too long Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220819083209.50844-10-krzysztof.kozlowski@linaro.org
2022-08-29arm64: dts: qcom: sc7180: switch TCSR mutex to MMIOKrzysztof Kozlowski1-8/+3
The TCSR mutex bindings allow device to be described only with address space (so it uses MMIO, not syscon regmap). This seems reasonable as TCSR mutex is actually a dedicated IO address space and it also fixes DT schema checks: qcom/sc7180-trogdor-wormdingler-rev1-inx.dtb: hwlock: 'reg' is a required property qcom/sc7180-trogdor-wormdingler-rev1-inx.dtb: hwlock: 'syscon' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220819083209.50844-9-krzysztof.kozlowski@linaro.org
2022-08-29arm64: dts: qcom: sc7180: split TCSR halt regs out of mutexKrzysztof Kozlowski1-4/+9
The TCSR halt regs are next to TCSR mutex (in one address block called TCSR_MUTEX), so before converting the TCSR mutex into device with address space, we need to split the halt regs to its own syscon device. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220819083209.50844-8-krzysztof.kozlowski@linaro.org
2022-08-29arm64: dts: qcom: sc7180: add missing TCSR syscon compatibleKrzysztof Kozlowski1-1/+1
TCSR syscon node should come with dedicated compatible. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220819083209.50844-7-krzysztof.kozlowski@linaro.org
2022-08-29arm64: dts: qcom: msm8998: switch TCSR mutex to MMIOKrzysztof Kozlowski1-8/+3
The TCSR mutex bindings allow device to be described only with address space (so it uses MMIO, not syscon regmap). This seems reasonable as TCSR mutex is actually a dedicated IO address space and it also fixes DT schema checks: qcom/msm8998-asus-novago-tp370ql.dtb: hwlock: 'reg' is a required property qcom/msm8998-asus-novago-tp370ql.dtb: hwlock: 'syscon' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220819083209.50844-6-krzysztof.kozlowski@linaro.org
2022-08-29arm64: dts: qcom: msm8998: split TCSR halt regs out of mutexKrzysztof Kozlowski1-2/+7
The TCSR halt regs are next to TCSR mutex (in one address block called TCSR_MUTEX), so before converting the TCSR mutex into device with address space, we need to split the halt regs to its own syscon device. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220819083209.50844-5-krzysztof.kozlowski@linaro.org
2022-08-29arm64: dts: qcom: msm8996: switch TCSR mutex to MMIOKrzysztof Kozlowski1-8/+3
The TCSR mutex bindings allow device to be described only with address space (so it uses MMIO, not syscon regmap). This seems reasonable as TCSR mutex is actually a dedicated IO address space and it also fixes DT schema checks: qcom/msm8996-xiaomi-natrium.dtb: hwlock: 'reg' is a required property qcom/msm8996-xiaomi-natrium.dtb: hwlock: 'syscon' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220819083209.50844-4-krzysztof.kozlowski@linaro.org
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