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2022-08-23dt-bindings: PCI: qcom: Add SC8280XP to bindingJohan Hovold1-1/+49
Add the SC8280XP platform to the binding. SC8280XP use four host interrupts for MSI routing so remove the obsolete comment referring to newer chipsets supporting one or eight interrupts (e.g. for backwards compatibility). Link: https://lore.kernel.org/r/20220714071348.6792-3-johan+linaro@kernel.org Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
2022-08-23dt-bindings: PCI: qcom: Enumerate platforms with single msi interruptJohan Hovold1-2/+15
Explicitly enumerate the older platforms that have a single msi host interrupt. This allows for adding further platforms with, for example, four msi interrupts without resorting to nested conditionals. Drop the redundant comment about older chipsets instead of moving it. Link: https://lore.kernel.org/r/20220714071348.6792-2-johan+linaro@kernel.org Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
2022-08-23arm64: dts: exynos: Add SysMMU nodes for Exynos850Sam Protsenko1-0/+45
Add all SysMMU nodes to Exynos850 SoC device tree. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220809113323.29965-10-semen.protsenko@linaro.org
2022-08-23arm64: dts: exynos: Add CMU_AUD, CMU_IS and CMU_MFCMSCL for Exynos850Sam Protsenko1-0/+38
Add missing clock domains to Exynos850 SoC device tree. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220809113323.29965-9-semen.protsenko@linaro.org
2022-08-23arm64: dts: exynosautov9: add fsys0/1 clock DT nodesChanho Park1-0/+28
Add cmu_fsys0 and cmu_fsys1 for PCIe clocks and USB/MMC clocks respectively. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> [krzk: put nodes ordered by unit address] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/50f8145bca30cf5c900359d0b78c1c617090e021.1659054220.git.chanho61.park@samsung.com
2022-08-23clk: samsung: exynos850: Implement CMU_MFCMSCL domainSam Protsenko1-0/+176
CMU_MFCMSCL clock domain provides clocks for MFC (Multi-Format Codec), JPEG Codec and Scaler IP-cores. According to Exynos850 TRM, CMU_MFCMSCL generates MFC, M2M, MCSC and JPEG clocks for BLK_MFCMSCL. This patch adds next clocks: - bus clocks in CMU_TOP for CMU_MFCMSCL - all internal CMU_MFCMSCL clocks - leaf clocks for MFCMSCL, TZPC (TrustZone Protection Controller), JPEG codec, M2M (Memory-to-Memory), MCSC (Multi-Channel Scaler), MFC (Multi-Format Codec), PPMU (Platform Performance Monitoring Unit), SysMMU and SysReg MFCMSCL related gate clocks in CMU_TOP were marked as CLK_IS_CRITICAL, because: 1. All of those have to be enabled in order to read /sys/kernel/debug/clk/clk_summary file 2. When some user driver (e.g. exynos-sysmmu) disables some derived leaf clock, it can lead to CMU_TOP clocks disable, which then makes the system hang. To prevent that, the CLK_IS_CRITICAL flag is used, as CLK_IGNORE_UNUSED is not enough. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220809113323.29965-8-semen.protsenko@linaro.org
2022-08-23clk: samsung: exynos850: Implement CMU_IS domainSam Protsenko1-0/+199
CMU_IS clock domain provides clocks for IS IP-core (Image Signal Processing Subsystem). According to Exynos850 TRM, CMU_IS generates CSIS, IPP, ITP, VRA and GDC clocks for BLK_IS. This patch adds next clocks: - bus clocks in CMU_TOP needed for CMU_IS - all internal CMU_IS clocks - leaf clocks for IS IP-core, CSIS (Camera Serial Interface Slave), D_TZPC (TrustZone Protection Controller), CSIS DMA, GDC (Geometric Distortion Correction), IPP (Image Preprocessing Processing core), ITP (Image Texture Processing core), MCSC (Multi-Channel Scaler), VRA (Visual Recognition Accelerator), PPMU (Platform Performance Monitoring Unit), SysMMU and SysReg IS related gate clocks in CMU_TOP were marked as CLK_IS_CRITICAL, because: 1. All of those have to be enabled in order to read /sys/kernel/debug/clk/clk_summary file 2. When some user driver (e.g. exynos-sysmmu) disables some derived leaf clock, it can lead to CMU_TOP clocks disable, which then makes the system hang. To prevent that, the CLK_IS_CRITICAL flag is used, as CLK_IGNORE_UNUSED is not enough. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220809113323.29965-7-semen.protsenko@linaro.org
2022-08-23clk: samsung: exynos850: Implement CMU_AUD domainSam Protsenko1-0/+302
CMU_AUD clock domain provides clocks for ABOX IP-core (audio subsystem). According to Exynos850 TRM, CMU_AUD generates Cortex-A32 clock, bus clock and audio clocks for BLK_AUD. This patch adds next clocks: - bus clocks in CMU_TOP needed for CMU_AUD - all internal CMU_AUD clocks - leaf clocks for Cortex-A32, Speedy FM, UAIF0..UAIF6 (Unified Audio Interface), CNT (counter), ABOX IP-core, ASB (Asynchronous Bridge), DAP (Debug Access Port), I2S Codec MCLK, D_TZPC (TrustZone Protection Controller), GPIO, PPMU (Platform Performance Monitoring Unit), SysMMU, SysReg and WDT ABOX clock was marked as CLK_IGNORE_UNUSED, as system hangs on boot otherwise. Once ABOX driver is implemented, maybe it can be handled there instead. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220809113323.29965-6-semen.protsenko@linaro.org
2022-08-23clk: samsung: exynos850: Style fixesSam Protsenko1-3/+2
Fix some typos in comments and do small coding style improvements. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220809113323.29965-5-semen.protsenko@linaro.org
2022-08-23usb: dwc3: qcom: suppress unused-variable warningJohan Hovold1-1/+1
The dwc3_qcom_read_usb2_speed() helper is now only called when the controller is acting as host, but the compiler will warn that the hcd variable is unused in gadget-only W=1 builds. Fixes: c06795f114a6 ("usb: dwc3: qcom: fix gadget-only builds") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20220822100550.3039-1-johan+linaro@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-08-23clk: samsung: exynosautov9: add fsys1 clock supportChanho Park1-0/+130
CMU_FSYS1 provides clocks for USB(2 x USB3.1 Gen-1, 2 x USB 2.0) and mmc. For MMC clocks, PLL_MMC(PLL0831X type) is also supported as a PLL source clock provider. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/d4aa967538fed9667e9550a256e545026fc2fa8d.1659054220.git.chanho61.park@samsung.com
2022-08-23clk: samsung: exynosautov9: add fsys0 clock supportChanho Park1-0/+243
CMU_FSYS0 block provides clocks for PCIe Gen3 1 x 4Lanes and 2 x 2 Lanes. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/ae84d4a0487a5299076bfeef5732579f5207acf9.1659054220.git.chanho61.park@samsung.com
2022-08-23clk: samsung: exynosautov9: correct register offsets of peric0/c1Chanho Park1-10/+10
Some register offsets of peric0 and peric1 cmu blocks need to be corrected and re-ordered by numerical order. Fixes: f2dd366992d0 ("clk: samsung: exynosautov9: add cmu_peric0 clock support") Fixes: b35f27fe73d8 ("clk: samsung: exynosautov9: add cmu_peric1 clock support") Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220727021357.152421-4-chanho61.park@samsung.com
2022-08-23clk: samsung: exynosautov9: add missing gate clks for peric0/c1Chanho Park1-0/+8
"gout_peric0_pclk_1" and "gout_peric1_pclk_1" should be added to peric0 and peric1 respectively. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220727021357.152421-3-chanho61.park@samsung.com
2022-08-23Merge branch 'for-v6.0/samsung-clk-dt-bindings' into next/clkKrzysztof Kozlowski4-29/+344
Merge bindings with clock IDs for ExynosAutov9 and Exynos850. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-08-23xfrm: Drop unused argumentHongbin Wang1-8/+7
Drop unused argument from xfrm_policy_match, __xfrm_policy_eval_candidates and xfrm_policy_eval_candidates. No functional changes intended. Signed-off-by: Hongbin Wang <wh_bin@126.com> Signed-off-by: Steffen Klassert <steffen.klassert@secunet.com>
2022-08-23dt-bindings: clock: exynos850: Add Exynos850 CMU_MFCMSCLSam Protsenko2-1/+56
CMU_MFCMSCL generates MFC, M2M, MCSC and JPEG clocks for BLK_MFCMSCL. Add clock indices and binding documentation for CMU_MFCMSCL. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220809113323.29965-4-semen.protsenko@linaro.org
2022-08-23dt-bindings: clock: exynos850: Add Exynos850 CMU_ISSam Protsenko2-1/+64
CMU_IS generates CSIS, IPP, ITP, VRA and GDC clocks for BLK_IS. Add clock indices and bindings documentation for CMU_IS domain. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220809113323.29965-3-semen.protsenko@linaro.org
2022-08-23dt-bindings: clock: exynos850: Add Exynos850 CMU_AUDSam Protsenko2-1/+86
CMU_AUD generates Cortex-A32 clock, bus clock and audio clocks for BLK_AUD. Add clock indices and binding documentation for CMU_AUD. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220809113323.29965-2-semen.protsenko@linaro.org
2022-08-23smb3: missing inode locks in zero rangeDavid Howells1-25/+30
smb3 fallocate zero range was not grabbing the inode or filemap_invalidate locks so could have race with pagemap reinstantiating the page. Cc: stable@vger.kernel.org Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Steve French <stfrench@microsoft.com>
2022-08-23dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1Chanho Park1-0/+44
Add "samsung,exynosautov9-cmu-fsys0/1" compatibles to illustrate cmu_fsys0 and fsys1 for Exynos Auto v9 SoC. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/49eaadecfb346982dff46cffb870400b76a4e281.1659054220.git.chanho61.park@samsung.com
2022-08-23dt-bindings: clock: exynosautov9: add fsys1 clock definitionsChanho Park1-0/+25
Add fsys1(for usb and mmc) clock definitions. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/debb6335cb2bcc935f7572bed25d76a85e80cfaa.1659054220.git.chanho61.park@samsung.com
2022-08-23dt-bindings: clock: exynosautov9: add fys0 clock definitionsChanho Park1-0/+43
Add fsys0(for PCIe) clock definitions. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/6f70a59164ad2c5ce5581047ca39a91afc1105d9.1659054220.git.chanho61.park@samsung.com
2022-08-23clk: samsung: exynos7885: Add TREX clocksDavid Virag1-7/+42
TREX D Core and P core clocks seem to be related to the BTS (Bus Traffic Shaper) inside the Exynos7885 SoC, and are needed for the SoC to function correctly. When clocks are cut from TREX D Core, the eMMC and the framebuffer stops working properly. Other unknown things may stop working as well. When clocks are cut from TREX P Core, the system locks up needing a hard reset. Add these clocks and mark them critical so that they are always on. Signed-off-by: David Virag <virag.david003@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220601233743.56317-5-virag.david003@gmail.com
2022-08-23clk: samsung: exynos7885: Implement CMU_FSYS domainDavid Virag1-0/+158
CMU_FSYS clock domain provides clocks for FSYS IP-core providing clocks for all MMC devices on Exynos7885, and USB30DRD. Add clocks: - Bus clocks in CMU_TOP needed for CMU_FSYS - All clocks in CMU_FSYS needed for MMC devices Signed-off-by: David Virag <virag.david003@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220601233743.56317-4-virag.david003@gmail.com
2022-08-23dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1Chanho Park1-28/+28
There are duplicated definitions of peric0 and peric1 cmu blocks. Thus, they should be defined correctly as numerical order. Fixes: 680e1c8370a2 ("dt-bindings: clock: add clock binding definitions for Exynos Auto v9") Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220727021357.152421-2-chanho61.park@samsung.com
2022-08-23clk: samsung: exynos-clkout: Use of_device_get_match_data()Minghao Chi (CGEL ZTE)1-4/+2
Use of_device_get_match_data() to simplify the code. Signed-off-by: Minghao Chi (CGEL ZTE) <chi.minghao@zte.com.cn> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220307033546.2075097-1-chi.minghao@zte.com.cn
2022-08-22net/mlx5: TC, Add support for SF tunnel offloadRoi Dayan2-3/+10
VF tunnel flow already exists and SF tunnel is the same flow. Support offloading of tunneling over SF device by allow to attach an encap route over SF and set to use indirect flow table on SF. Signed-off-by: Roi Dayan <roid@nvidia.com> Reviewed-by: Mark Bloch <mbloch@nvidia.com> Reviewed-by: Maor Dickman <maord@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-08-22net/mlx5: E-Switch, Move send to vport meta rule creationRoi Dayan6-94/+90
Move the creation of the rules from offloads fdb table init to per rep vport init. This way the driver will creating the send to vport meta rule on any representor, e.g. SF representors. Signed-off-by: Roi Dayan <roid@nvidia.com> Reviewed-by: Mark Bloch <mbloch@nvidia.com> Reviewed-by: Maor Dickman <maord@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-08-22net/mlx5: E-Switch, Split creating fdb tables into smaller chunksRoi Dayan1-124/+206
Split esw_create_offloads_fdb_tables() into smaller functions. This will help maintenance. Signed-off-by: Roi Dayan <roid@nvidia.com> Reviewed-by: Mark Bloch <mbloch@nvidia.com> Reviewed-by: Maor Dickman <maord@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-08-22net/mlx5: E-Switch, Add default drop rule for unmatched packetsJianbo Liu2-3/+94
The ft_offloads table serves to steer packets, which are from the eswitch, to the representor associated with the packets' source vport. Previously, if a packet's source vport or metadata was not associated with any representor, it was forwarded to the uplink representor. The representor got packets it shouldn't have as they weren't coming from the uplink vport. One such effect of this breakage can be observed if the uplink representor is attached to a bridge, where such illegal packets will be broadcast to the remaining ports, flooding the switch with illegal packets. In the case where IB loopback (e.g, SNAP) is enabled, all transmitted packets would be looped back, and received by the uplink representor, and result in an infinite feedback loop. Therefore, block this hole by adding a default drop rule to the ft_offloads table, so that all unmatched packets with no associated representor are dropped. Signed-off-by: Jianbo Liu <jianbol@nvidia.com> Reviewed-by: Gavi Teitz <gavi@nvidia.com> Reviewed-by: Mark Bloch <mbloch@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-08-22net/mlx5e: Completely eliminate priv from fs.hLama Kayal4-94/+100
Complete the decoupling process of flow steering from en.h. Signed-off-by: Lama Kayal <lkayal@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-08-22net/mlx5e: Make all ttc functions of en_fs get fs struct as argumentLama Kayal4-36/+43
Let all ttc creation be independent of priv, and pass relevant members of priv only. Signed-off-by: Lama Kayal <lkayal@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-08-22net/mlx5e: Make flow steering arfs independent of privLama Kayal6-62/+74
Decouple arfs flow steering functionality from priv. Make all arfs functions defined under fs.h get flow_steering struct as an argument, thus helping with the process of decoupling the whole flow steering API from en.h. Signed-off-by: Lama Kayal <lkayal@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-08-22net/mlx5e: Introduce flow steering debug macrosLama Kayal4-76/+76
Introduce flow steering debug macros family, fs_*. These macros bring clean finish to the decoupling of flow steering process such that all flow steering flows can report warnings and provide debug information via these exclusive macros. Signed-off-by: Lama Kayal <lkayal@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-08-22net/mlx5e: Separate ethtool_steering from fs.h and make privateLama Kayal8-38/+65
Create a new fs_ethtool.h header file, where ethtool steering init and cleanup functions are declared in it. Make mlx5e_ethtool_steering struct private and declare at en_fs_ethtool.c. Signed-off-by: Lama Kayal <lkayal@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-08-22net/mlx5e: Directly get flow_steering struct as input when init/cleanup ethtool steeringLama Kayal5-20/+20
Let both mlx5e_ethtool_init_steering and mlx5e_ethtool_cleanup_steering get ethtool steering struct as input instead of priv, as passing priv is obsolete. Also modify other function through the flow similarly. Signed-off-by: Lama Kayal <lkayal@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-08-22net/mlx5e: Convert ethtool_steering member of flow_steering struct to pointerLama Kayal1-8/+33
Convert mlx5e_ethtool_steering member of mlx5e_flow_steering to a pointer, and allocate dynamically for each profile at flow_steering init. Signed-off-by: Lama Kayal <lkayal@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-08-22net/mlx5e: Drop priv argument of ptp function in en_fsLama Kayal3-16/+18
Both mlx5e_ptp_alloc_rx_fs and mlx5e_ptp_free_rx_fs only make use of two priv member, pass them directly instead. This will help dropping priv from all en_fs file. Signed-off-by: Lama Kayal <lkayal@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-08-22net/mlx5e: Decouple fs_tcp from en.hLama Kayal4-59/+59
Make flow steering files fs_tcp.c/h independent of en.h such that they go through the flow steering API only. Make error reports be via mlx5_core API instead of netdev_err API, this to ensure a safe decoupling from en.h, and prevent redundant argument passing. Signed-off-by: Lama Kayal <lkayal@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-08-22net/mlx5e: Decouple fs_tt_redirect from en.hLama Kayal5-99/+103
Make flow steering files fs_tt_redirect.c/h independent of en.h such that it goes through the flow steering API only. Make error reports be via mlx5_core API instead of netdev_err API, this to ensure a safe decoupling from en.h, and prevent redundant argument passing. Signed-off-by: Lama Kayal <lkayal@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-08-22net/mlx5e: Introduce flow steering APILama Kayal14-193/+415
Move mlx5e_flow_steering struct to fs_en.c to make it private. Introduce flow_steering API and let other files go through it. Signed-off-by: Lama Kayal <lkayal@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-08-22MAINTAINERS: add include/dt-bindings/input to INPUT DRIVERSLukas Bulwahn1-0/+1
Maintainers of the directory Documentation/devicetree/bindings/input are also the maintainers of the corresponding directory include/dt-bindings/input. Add the file entry for include/dt-bindings/input to the appropriate section in MAINTAINERS. Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com> Link: https://lore.kernel.org/r/20220613115654.28117-1-lukas.bulwahn@gmail.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2022-08-22scsi: mpi3mr: Support SAS transport class callbacksSreekanth Reddy4-2/+914
Add support for the following SAS transport class callbacks: - get_linkerrors - get_enclosure_identifier - get_bay_identifier - phy_reset - phy_enable - set_phy_speed - smp_handler Link: https://lore.kernel.org/r/20220804131226.16653-14-sreekanth.reddy@broadcom.com Reviewed-by: Himanshu Madhani <himanshu.madhani@oracle.com> Signed-off-by: Sreekanth Reddy <sreekanth.reddy@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2022-08-22scsi: mpi3mr: Add framework to issue MPT transport cmdsSreekanth Reddy4-1/+249
Add framework to issue MPT transport commands to controllers. Also issue the MPT transport commands to get the manufacturing info of SAS expander device. Link: https://lore.kernel.org/r/20220804131226.16653-13-sreekanth.reddy@broadcom.com Reviewed-by: Himanshu Madhani <himanshu.madhani@oracle.com> Signed-off-by: Sreekanth Reddy <sreekanth.reddy@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2022-08-22scsi: mpi3mr: Add SAS SATA end devices to STLSreekanth Reddy3-17/+235
Register/unregister the SAS, SATA devices to SCSI Transport Layer(STL) whenever the corresponding device is added/removed from topology. Link: https://lore.kernel.org/r/20220804131226.16653-12-sreekanth.reddy@broadcom.com Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Himanshu Madhani <himanshu.madhani@oracle.com> Signed-off-by: Sreekanth Reddy <sreekanth.reddy@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2022-08-22scsi: mpi3mr: Get target object based on rphySreekanth Reddy4-10/+86
When device is registered with the STL then get the corresponding device's target object using the rphy in below callback functions: - mpi3mr_target_alloc() - mpi3mr_slave_alloc() - mpi3mr_slave_configure() - mpi3mr_slave_destroy() Link: https://lore.kernel.org/r/20220804131226.16653-11-sreekanth.reddy@broadcom.com Reviewed-by: Himanshu Madhani <himanshu.madhani@oracle.com> Signed-off-by: Sreekanth Reddy <sreekanth.reddy@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2022-08-22scsi: mpi3mr: Add expander devices to STLSreekanth Reddy3-9/+432
Register/unregister the expander devices to SCSI Transport Layer(STL) whenever the corresponding expander is added/removed from topology. Link: https://lore.kernel.org/r/20220804131226.16653-10-sreekanth.reddy@broadcom.com Reviewed-by: Himanshu Madhani <himanshu.madhani@oracle.com> Signed-off-by: Sreekanth Reddy <sreekanth.reddy@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2022-08-22scsi: mpi3mr: Enable STL on HBAs where multipath is disabledSreekanth Reddy3-4/+46
Register the SAS, SATA devices to SCSI Transport Layer (STL) only if multipath capability is disabled in the controller's firmware. Link: https://lore.kernel.org/r/20220804131226.16653-9-sreekanth.reddy@broadcom.com Reviewed-by: Himanshu Madhani <himanshu.madhani@oracle.com> Signed-off-by: Sreekanth Reddy <sreekanth.reddy@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2022-08-22scsi: mpi3mr: Add helper functions to manage device's portSreekanth Reddy3-1/+539
Add the following helper functions: - Update the host phys with STL - Remove the device's SAS port with STL Link: https://lore.kernel.org/r/20220804131226.16653-8-sreekanth.reddy@broadcom.com Reviewed-by: Himanshu Madhani <himanshu.madani@oracle.com> Signed-off-by: Sreekanth Reddy <sreekanth.reddy@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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