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2022-07-08dt-bindings: input: Add fsl,scu-key yaml fileAbel Vesa2-14/+40
In order to replace the fsl,scu txt file from bindings/arm/freescale, we need to split it between the right subsystems. This patch documents separately the 'keys' child node of the SCU main node. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-07-08dt-bindings: pinctrl: imx: Add fsl,scu-iomux yaml fileAbel Vesa2-40/+74
In order to replace the fsl,scu txt file from bindings/arm/freescale, we need to split it between the right subsystems. This patch documents separately the 'iomux/pinctrl' child node of the SCU main node. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-07-08dt-bindings: clk: imx: Add fsl,scu-clk yaml fileAbel Vesa2-31/+43
In order to replace the fsl,scu txt file from bindings/arm/freescale, we need to split it between the right subsystems. This patch documents separately the 'clock' child node of the SCU main node. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-07-08ARM: dts: kswitch-d10: use open drain mode for coma-mode pinsMichael Walle1-4/+4
The driver use the coma-mode pins as open-drain. Flag them in the device tree accordingly. This avoids the following error: [ 14.114180] gpio-2007 (coma-mode): enforced open drain please flag it properly in DT/ACPI DSDT/board file Fixes: 46a9556d977e ("ARM: dts: kswitch-d10: enable networking") Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220704150808.1104295-1-michael@walle.cc
2022-07-08memory: tegra: Add MGBE memory clients for Tegra234Thierry Reding1-0/+80
Tegra234 has multiple network interfaces with each their own memory clients and stream IDs to allow for proper isolation. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08Merge branch 'for-5.20/dt-bindings' into for-5.20/memoryThierry Reding7-0/+343
2022-07-08soc: mediatek: mutex: Simplify with devm_platform_get_and_ioremap_resource()AngeloGioacchino Del Regno1-12/+6
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. While at it, also remove a redundant call to of_address_to_resource(), as this was getting the address of the same resource index 0: we can as well get the iostart from the 'regs' pointer. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220623121701.107512-1-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-07-08soc: mediatek: pm-domains: Add support for Helio X10 MT6795AngeloGioacchino Del Regno2-0/+117
Add pm-domains (mtcmos) data for MediaTek Helio X10 MT6795 SoC. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220503141441.125852-3-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-07-08dt-bindings: power: Add MediaTek Helio X10 MT6795 power domainsAngeloGioacchino Del Regno2-0/+18
Add power domains dt-bindings for MediaTek Helio X10 (MT6795). Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220503141441.125852-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-07-08dt-bindings: arm: tegra: Add NVIDIA Tegra234 CBB 2.0 bindingSumit Gupta1-0/+74
Add device-tree binding documentation to represent the Control Backbone (CBB) version 2.0 used on Tegra234 SoCs. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08dt-bindings: arm: tegra: Add NVIDIA Tegra194 AXI2APB bindingSumit Gupta1-0/+40
Add device-tree binding documentation to represent the AXI2APB bridges used by Control Backbone (CBB) 1.0 on Tegra194 SoCs. All errors for APB slaves are reported as slave error because APB bas single bit to report error. So, CBB driver needs to further check error status registers of all the AXI2APB bridges to find error type. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08dt-bindings: arm: tegra: Add NVIDIA Tegra194 CBB 1.0 bindingSumit Gupta1-0/+97
Add device-tree binding documentation to represent the Control Backbone (CBB) version 1.0 used on Tegra194 SoCs. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08dt-bindings: memory: Add Tegra234 MGBE memory clientsThierry Reding1-0/+20
Add the memory client and stream ID definitions for the MGBE hardware found on Tegra234 SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08dt-bindings: Add Tegra234 MGBE clocks and resetsThierry Reding2-0/+109
Add the clocks and resets used by the MGBE Ethernet hardware found on Tegra234 SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08dt-bindings: power: Add Tegra234 MGBE power domainsThierry Reding1-0/+1
Add power domain IDs for the four MGBE power partitions found on Tegra234. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: dts: imx8mp: add NoC nodePeng Fan1-0/+20
Add i.MX8MP NoC node to make the interconnect i.MX8MP driver could work. Currently dynamic frequency scaling of the i.MX8MP NoC has not been supported, only NoC initial settings are configured by interconnect driver. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Georgi Djakov <djakov@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-07-08ARM: dts: colibri-imx6ull: fix snvs pinmux groupMax Krummenacher1-2/+7
A pin controlled by the iomuxc-snvs pin controller must be specified under the dtb's iomuxc-snvs node. Move the one and only pin of that category from the iomuxc node and set the pinctrl-0 using it accordingly. Fixes: 2aa9d6201949 ("ARM: dts: imx6ull-colibri: add touchscreen device nodes") Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-07-08optee: smc_abi.c: fix wrong pointer passed to IS_ERR/PTR_ERR()Yang Yingliang1-2/+2
In optee_smc_do_call_with_arg() there is a code path when the argument struct for RPC is passed appended to the primary argument struct. When the address of the RPC struct is retrieved there's an invalid check for success. It should be 'rpc_arg' pass to IS_ERR/PTR_ERR(). Fixes: ed8faf6c8f8c ("optee: add OPTEE_SMC_CALL_WITH_RPC_ARG and OPTEE_SMC_CALL_WITH_REGD_ARG") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> [jw: added background to the problem] Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2022-07-08PCI: hv: Take a const cpumask in hv_compose_msi_req_get_cpu()Samuel Holland1-1/+1
The cpumask that is passed to this function ultimately comes from irq_data_get_effective_affinity_mask(), which was recently changed to return a const cpumask pointer. The first level of functions handling the affinity mask were updated, but not this helper function. Fixes: 4d0b8298818b ("genirq: Return a const cpumask from irq_data_get_affinity_mask") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Michael Kelley <mikelley@microsoft.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220708004931.1672-1-samuel@sholland.org
2022-07-08Merge tag 'zynqmp-dt-for-v5.20' of https://github.com/Xilinx/linux-xlnx into arm/dtArnd Bergmann8-7/+94
arm64: dts: ZynqMP DT changes for v5.20 - Extend gpio-zynq DT binding (compatible, power-domains, gpio-line-names) - Fix sm-k26 gpio comment - Wire AMS device - Align gpio-keys node names with dtschema * tag 'zynqmp-dt-for-v5.20' of https://github.com/Xilinx/linux-xlnx: arm64: dts: xilinx: align gpio-key node names with dtschema arm64: dts: zynqmp: add AMS driver to device tree dt-bindings: gpio: zynq: Describe gpio-line-names arm64: zynqmp: Fix comment about number of gpio line names dt-bindings: gpio: zynq: Add power-domains dt-bindings: gpio: zynq: Add missing compatible strings Link: https://lore.kernel.org/r/452e8c68-b63b-f4f6-a937-67f65c64a8a0@monstr.eu Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-08Merge tag 'zynq-dt-for-v5.20' of https://github.com/Xilinx/linux-xlnx into arm/dtArnd Bergmann2-3/+3
ARM: Zynq DT changes for v5.20 - Align gpio-keys node names with dtschema * tag 'zynq-dt-for-v5.20' of https://github.com/Xilinx/linux-xlnx: ARM: dts: xilinx: align gpio-key node names with dtschema Link: https://lore.kernel.org/r/87d2bd4a-b90d-6396-17c5-c95ac64d17d0@monstr.eu Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-08MAINTAINERS: Remove iommu@lists.linux-foundation.orgJoerg Roedel1-11/+0
The IOMMU mailing list has moved to iommu@lists.linux.dev and the old list should bounce by now. Remove it from the MAINTAINERS file. Cc: stable@vger.kernel.org Signed-off-by: Joerg Roedel <jroedel@suse.de> Link: https://lore.kernel.org/r/20220706103331.10215-1-joro@8bytes.org
2022-07-08crypto: testmgr - populate RSA CRT parameters in RSA test vectorsIgnat Korchagin1-21/+100
Changes from v1: * replace some accidental spaces with tabs In commit f145d411a67e ("crypto: rsa - implement Chinese Remainder Theorem for faster private key operations") we have started to use the additional primes and coefficients for RSA private key operations. However, these additional parameters are not present (defined as 0 integers) in the RSA test vectors. Some parameters were borrowed from OpenSSL, so I was able to find the source. I could not find the public source for 1 vector though, so had to recover the parameters by implementing Appendix C from [1]. [1]: https://nvlpubs.nist.gov/nistpubs/SpecialPublications/NIST.SP.800-56Br1.pdf Fixes: f145d411a67e ("crypto: rsa - implement Chinese Remainder Theorem for faster private key operations") Reported-by: Tasmiya Nalatwad <tasmiya@linux.vnet.ibm.com> Signed-off-by: Ignat Korchagin <ignat@cloudflare.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-08crypto: inside-secure - fix packed bit-field result descriptorOfer Heifetz1-9/+9
When mixing bit-field and none bit-filed in packed struct the none bit-field starts at a distinct memory location, thus adding an additional byte to the overall structure which is used in memory zero-ing and other configuration calculations. Fix this by removing the none bit-field that has a following bit-field. Signed-off-by: Ofer Heifetz <oferh@marvell.com> Acked-by: Antoine Tenart <atenart@kernel.org> Acked-by: Antoine Tenart <atenart@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-08crypto: hisilicon - Kunpeng916 crypto driver don't sleep when in softirqZhengchao Shao2-8/+8
When kunpeng916 encryption driver is used to deencrypt and decrypt packets during the softirq, it is not allowed to use mutex lock. Fixes: 915e4e8413da ("crypto: hisilicon - SEC security accelerator driver") Signed-off-by: Zhengchao Shao <shaozhengchao@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-08crypto: hisilicon/sec - don't sleep when in softirqZhengchao Shao2-11/+11
When kunpeng920 encryption driver is used to deencrypt and decrypt packets during the softirq, it is not allowed to use mutex lock. The kernel will report the following error: BUG: scheduling while atomic: swapper/57/0/0x00000300 Call trace: dump_backtrace+0x0/0x1e4 show_stack+0x20/0x2c dump_stack+0xd8/0x140 __schedule_bug+0x68/0x80 __schedule+0x728/0x840 schedule+0x50/0xe0 schedule_preempt_disabled+0x18/0x24 __mutex_lock.constprop.0+0x594/0x5dc __mutex_lock_slowpath+0x1c/0x30 mutex_lock+0x50/0x60 sec_request_init+0x8c/0x1a0 [hisi_sec2] sec_process+0x28/0x1ac [hisi_sec2] sec_skcipher_crypto+0xf4/0x1d4 [hisi_sec2] sec_skcipher_encrypt+0x1c/0x30 [hisi_sec2] crypto_skcipher_encrypt+0x2c/0x40 crypto_authenc_encrypt+0xc8/0xfc [authenc] crypto_aead_encrypt+0x2c/0x40 echainiv_encrypt+0x144/0x1a0 [echainiv] crypto_aead_encrypt+0x2c/0x40 esp_output_tail+0x348/0x5c0 [esp4] esp_output+0x120/0x19c [esp4] xfrm_output_one+0x25c/0x4d4 xfrm_output_resume+0x6c/0x1fc xfrm_output+0xac/0x3c0 xfrm4_output+0x64/0x130 ip_build_and_send_pkt+0x158/0x20c tcp_v4_send_synack+0xdc/0x1f0 tcp_conn_request+0x7d0/0x994 tcp_v4_conn_request+0x58/0x6c tcp_v6_conn_request+0xf0/0x100 tcp_rcv_state_process+0x1cc/0xd60 tcp_v4_do_rcv+0x10c/0x250 tcp_v4_rcv+0xfc4/0x10a4 ip_protocol_deliver_rcu+0xf4/0x200 ip_local_deliver_finish+0x58/0x70 ip_local_deliver+0x68/0x120 ip_sublist_rcv_finish+0x70/0x94 ip_list_rcv_finish.constprop.0+0x17c/0x1d0 ip_sublist_rcv+0x40/0xb0 ip_list_rcv+0x140/0x1dc __netif_receive_skb_list_core+0x154/0x28c __netif_receive_skb_list+0x120/0x1a0 netif_receive_skb_list_internal+0xe4/0x1f0 napi_complete_done+0x70/0x1f0 gro_cell_poll+0x9c/0xb0 napi_poll+0xcc/0x264 net_rx_action+0xd4/0x21c __do_softirq+0x130/0x358 irq_exit+0x11c/0x13c __handle_domain_irq+0x88/0xf0 gic_handle_irq+0x78/0x2c0 el1_irq+0xb8/0x140 arch_cpu_idle+0x18/0x40 default_idle_call+0x5c/0x1c0 cpuidle_idle_call+0x174/0x1b0 do_idle+0xc8/0x160 cpu_startup_entry+0x30/0x11c secondary_start_kernel+0x158/0x1e4 softirq: huh, entered softirq 3 NET_RX 0000000093774ee4 with preempt_count 00000100, exited with fffffe00? Fixes: 416d82204df4 ("crypto: hisilicon - add HiSilicon SEC V2 driver") Signed-off-by: Zhengchao Shao <shaozhengchao@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-08crypto: hisilicon/sec - fix inconsistent argumentJianglei Nie1-1/+1
The argument passed to sec_queue_aw_alloc() should be SEC_QUEUE_AW_FROCE_NOALLOC instead of SEC_QUEUE_AR_FROCE_NOALLOC. Signed-off-by: Jianglei Nie <niejianglei2021@163.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-08crypto: nx - Hold the reference returned by of_find_compatible_nodeLiang He1-1/+4
In nx842_pseries_init(), we should hold the reference returned by of_find_compatible_node() and use it to call of_node_put to keep refcount balance. Signed-off-by: Liang He <windhl@126.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-08crypto: amcc - Hold the reference returned by of_find_compatible_nodeLiang He1-16/+24
In crypto4xx_probe(), we should hold the reference returned by of_find_compatible_node() and use it to call of_node_put to keep refcount balance. Signed-off-by: Liang He <windhl@126.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-08crypto: vmx - Fix warning on p8_ghash_algHerbert Xu1-0/+1
The compiler complains that p8_ghash_alg isn't declared which is because the header file aesp8-ppc.h isn't included in ghash.c. This patch fixes the warning. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Acked-by: Breno Leitao <leitao@debian.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-08crypto: qat - expose device config through sysfs for 4xxxGiovanni Cabiddu2-4/+115
qat_4xxx devices can be configured to allow either crypto or compression operations. At the moment, devices are configured statically according to the following rule: - odd numbered devices assigned to compression services - even numbered devices assigned to crypto services Expose the sysfs attribute /sys/bus/pci/devices/<BDF>/qat/cfg_services to allow to detect the configuration of a device and to change it. The `cfg_service` attribute is only exposed for qat_4xxx devices and it is limited to two configurations: (1) "sym;asym" for crypto services and "dc" for compression services. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Co-developed-by: Tomasz Kowallik <tomaszx.kowalik@intel.com> Signed-off-by: Tomasz Kowallik <tomaszx.kowalik@intel.com> Reviewed-by: Adam Guerin <adam.guerin@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Reviewed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Vladis Dronov <vdronov@redhat.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-08crypto: qat - relocate and rename adf_sriov_prepare_restart()Giovanni Cabiddu3-27/+28
The function adf_sriov_prepare_restart() is used in adf_sriov.c to stop and shutdown a device preserving its configuration. Since this function will be re-used by the logic that allows to reconfigure the device through sysfs, move it to adf_init.c and rename it as adf_dev_shutdown_cache_cfg(); Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Adam Guerin <adam.guerin@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Reviewed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Vladis Dronov <vdronov@redhat.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-08crypto: qat - change behaviour of adf_cfg_add_key_value_param()Giovanni Cabiddu1-1/+40
The function adf_cfg_add_key_value_param() allows to insert duplicates entries in the key value store of the driver. Change the behaviour of that function to the following policy: - if the key doesn't exist, add it; - if the key already exists with a different value, then delete it and replace it with a new one containing the new value; - if the key exists with the same value, then return without doing anything. The behaviour of this function has been changed in order to easily update key-values in the driver database. In particular this is required to update the value of the ServiceEnables key used to change the service loaded on a device. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Adam Guerin <adam.guerin@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Reviewed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Vladis Dronov <vdronov@redhat.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-08crypto: qat - expose device state through sysfs for 4xxxGiovanni Cabiddu8-1/+151
Expose the device state through an attribute in sysfs and allow to change it. This is to stop and shutdown a QAT device in order to change its configuration. The state attribute has been added to a newly created `qat` attribute group which will contain all _QAT specific_ attributes. The logic that implements the sysfs entries is part of a new file, adf_sysfs.c. This exposes an entry point to allow the driver to create attributes. The function that creates the sysfs attributes is called from the probe function of the driver and not in the state machine init function to allow the change of states even if the device is in the down state. In order to restore the device configuration between a transition from down to up, the function that configures the devices has been abstracted into the HW data structure. The `state` attribute is only exposed for qat_4xxx devices. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Co-developed-by: Tomasz Kowallik <tomaszx.kowalik@intel.com> Signed-off-by: Tomasz Kowallik <tomaszx.kowalik@intel.com> Reviewed-by: Adam Guerin <adam.guerin@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Reviewed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Vladis Dronov <vdronov@redhat.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-08Merge tag 'zynq-soc-for-v5.20' of https://github.com/Xilinx/linux-xlnx into arm/socArnd Bergmann1-0/+1
ARM: Zynq SoC changes for v5.20 - Fix refcount leak in zynq_get_revision() * tag 'zynq-soc-for-v5.20' of https://github.com/Xilinx/linux-xlnx: cpufreq: zynq: Fix refcount leak in zynq_get_revision Link: https://lore.kernel.org/r/e1d0a721-afa4-93a0-7119-0e4481a0624b@monstr.eu Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-08Merge tag 'zynqmp-soc-for-v5.20' of https://github.com/Xilinx/linux-xlnx into arm/socArnd Bergmann3-4/+24
arm64: ZynqMP SoC changes for v5.20 - Register SGI separately out of EEMI * tag 'zynqmp-soc-for-v5.20' of https://github.com/Xilinx/linux-xlnx: firmware: xilinx: Add TF_A_PM_REGISTER_SGI SMC call Link: https://lore.kernel.org/r/0196d1f3-e9c7-ef51-143d-e98b14980f63@monstr.eu Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-08Merge tag 'reset-fixes-for-v5.19' of git://git.pengutronix.de/pza/linux into arm/fixesArnd Bergmann1-1/+1
Reset controller fixes for v5.19 Fix the MAINTAINERS entry for the Synopsys AXS10x reset controller driver, which still points to a nonexistent .txt file after the device tree binding .yaml conversion. Also, fix the devm_reset_control_bulk_get_optional_exclusive() call, which was defective since its introduction due to a copy & paste error. * tag 'reset-fixes-for-v5.19' of git://git.pengutronix.de/pza/linux: reset: Fix devm bulk optional exclusive control getter MAINTAINERS: rectify entry for SYNOPSYS AXS10x RESET CONTROLLER DRIVER Link: https://lore.kernel.org/r/20220707101344.3329314-1-p.zabel@pengutronix.de Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-08MAINTAINERS: add polarfire rng, pci and clock driversConor Dooley1-1/+4
Hardware random, PCI and clock drivers for the PolarFire SoC have been upstreamed but are not covered by the MAINTAINERS entry, so add them. Daire is the author of the clock & PCI drivers, so add him as a maintainer in place of Lewis. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20220707142041.4096246-1-conor.dooley@microchip.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-07riscv: don't warn for sifive erratas in modulesHeiko Stuebner1-1/+2
The SiFive errata code contains code checking applicable erratas vs. actually applied erratas to suggest missing erratas to the user when their Kconfig options are not enabled. In the main kernel image one can be quite sure that all available erratas appear at least once, so that check will succeed. On the other hand modules can very well not use any errata-relevant code, so the newly added module-alternative support may also patch the module code, but not touch SiFive-specific erratas at all. So to restore the original behaviour don't warn when patching modules. This will keep the warning if necessary for the main kernel image but prevent spurious warnings for modules. Of course having such a vendor-specific warning may not be needed at all, as CONFIG_ERRATA_SIFIVE is selected by CONFIG_SOC_SIFIVE and the individual erratas are default-y so disabling them requires deliberate action anyway. But for now just restore the old behaviour. Fixes: a8e910168bba ("riscv: implement module alternatives") Reported-by: Ron Economos <re@w6rz.net> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Ron Economos <re@w6rz.net> Link: https://lore.kernel.org/r/20220608120849.1695191-1-heiko@sntech.de Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-07-08dt-bindings: opp: accept array of frequenciesKrzysztof Kozlowski1-0/+10
Devices might need to control several clocks when scaling the frequency and voltage. Allow passing array of clock frequencies, similarly to the voltages. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2022-07-08OPP: Make dev_pm_opp_set_opp() independent of frequencyViresh Kumar2-16/+40
dev_pm_opp_set_opp() can be called for any device, it may or may not have a frequency value associated with it. If a frequency value isn't available, we pass 0 to _set_opp(). Make it optional instead by making _set_opp() accept a pointer instead, as the frequency value is anyway available in the OPP. This makes dev_pm_opp_set_opp() and _set_opp() completely independent of any special key value. Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2022-07-08OPP: Reuse _opp_compare_key() in _opp_add_static_v2()Viresh Kumar2-2/+8
Reuse _opp_compare_key() in _opp_add_static_v2() instead of just comparing frequency while finding suspend frequency. Also add a comment over _opp_compare_key() explaining its return values. Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2022-07-08OPP: Remove rate_not_available parameter to _opp_add()Viresh Kumar3-9/+7
commit 32715be4fe95 ("opp: Fix adding OPP entries in a wrong order if rate is unavailable") removed the only user of this field, get rid of rest of it now. Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2022-07-08OPP: Use consistent names for OPP table instancesViresh Kumar3-15/+16
The OPP table is called "opp_table" at most of the places and "table" at few. Make all of them follow the same naming convention, "opp_table". Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2022-07-08OPP: Use generic key finding helpers for bandwidth keyViresh Kumar1-68/+15
Use the recently added generic key findings helpers to find bandwidth key values. Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2022-07-08OPP: Use generic key finding helpers for level keyViresh Kumar1-53/+10
Use the recently added generic key findings helpers to find level key values. Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2022-07-08OPP: Add generic key finding helpers and use them for freq APIsViresh Kumar1-99/+130
There are three type of helpers, to find exact, ceil, and floor values, replicated for multiple key types, freq, level, bw. And all of these helpers share a lot of boilerplate code. Add generic key finding helpers to reduce code redundancy. Also update the freq finder helpers to use the new infrastructure. Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2022-07-08OPP: Remove dev_pm_opp_find_freq_ceil_by_volt()Viresh Kumar2-62/+0
This was added few years back, but the code that was supposed to use it never got merged. Remove the unused helper. Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2022-07-08OPP: Remove custom OPP helper supportViresh Kumar3-188/+2
The only user of the custom helper is migrated to use dev_pm_opp_set_config_regulators() interface. Remove the now unused custom OPP helper support. This cleans up _set_opp() and leaves a single code path to be used by all users. Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2022-07-08OPP: ti: Migrate to dev_pm_opp_set_config_regulators()Viresh Kumar1-41/+34
The OPP core now provides dev_pm_opp_set_config_regulators() interface, which needs the platforms to just set the OPP voltages instead of both clk and voltage. The clock is set by the OPP core instead and hence reduces code redundancy. Migrate the only user of the custom set_opp() to dev_pm_opp_set_config_regulators(). Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>