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2022-07-05arm64/sysreg: Convert LOREA_EL1 to automatic generationMark Brown2-1/+6
Convert LOREA_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-24-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert LORSA_EL1 to automatic generationMark Brown2-1/+8
Convert LORSA_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-23-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert ID_AA64ISAR2_EL1 to automatic generationMark Brown2-27/+33
Automatically generate defines for ID_AA64ISAR2_EL1, using the definitions in DDI0487H.a. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-22-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert ID_AA64ISAR1_EL1 to automatic generationMark Brown2-34/+83
Automatically generate defines for ID_AA64ISAR1_EL1, using the definitions in DDI0487H.a. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-21-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert GMID to automatic generationMark Brown2-1/+5
Automatically generate the register definitions for GMID as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-20-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert DCZID_EL0 to automatic generationMark Brown2-5/+6
Convert DCZID_EL0 to automatic register generation as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-19-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert CTR_EL0 to automatic generationMark Brown2-16/+21
Convert CTR_EL0 to automatic register generation as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-18-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 definition namesMark Brown8-43/+43
Normally we include the full register name in the defines for fields within registers but this has not been followed for ID registers. In preparation for automatic generation of defines add the _EL1s into the defines for ID_AA64ISAR2_EL1 to follow the convention. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-17-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Add _EL1 into ID_AA64ISAR1_EL1 definition namesMark Brown7-102/+102
Normally we include the full register name in the defines for fields within registers but this has not been followed for ID registers. In preparation for automatic generation of defines add the _EL1s into the defines for ID_AA64ISAR1_EL1 to follow the convention. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-16-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Remove defines for RPRES enumerationMark Brown1-2/+0
We have defines for the RPRES enumeration in ID_AA64ISAR2 which do not follow our normal conventions. Since these defines are never used just remove them. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-15-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Standardise naming for ID_AA64ZFR0_EL1 fieldsMark Brown2-38/+38
The various defines for bitfields in ID_AA64ZFR0_EL1 do not follow our conventions for register field names, they omit the _EL1, they don't use specific defines for enumeration values and they don't follow the naming in the architecture in some cases. In preparation for automatic generation bring them into line with convention. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-14-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Standardise naming for ID_AA64SMFR0_EL1 enumsMark Brown3-31/+31
We have a series of defines for enumeration values we test for in the fields in ID_AA64SMFR0_EL1 which do not follow our usual convention of including the EL1 in the name and having _IMP at the end of the basic "feature present" define. In preparation for automatic register generation bring the defines into sync with convention, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-13-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Standardise naming for WFxT definesMark Brown3-8/+8
The defines for WFxT refer to the feature as WFXT and use SUPPORTED rather than IMP. In preparation for automatic generation of defines update these to be more standard. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-12-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Make BHB clear feature defines match the architectureMark Brown3-3/+3
The architecture refers to the field identifying support for BHB clear as BC but the kernel has called it CLEARBHB. In preparation for generation of defines for ID_AA64ISAR2_EL1 rename to use the architecture's naming. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-11-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Align pointer auth enumeration defines with architectureMark Brown2-29/+29
The defines used for the pointer authentication feature enumerations do not follow the naming convention we've decided to use where we name things after the architecture feature that introduced. Prepare for generating the defines for the ISA ID registers by updating to use the feature names. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-10-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/mte: Standardise GMID field name definitionsMark Brown3-4/+4
Usually our defines for bitfields in system registers do not include a SYS_ prefix but those for GMID do. In preparation for automatic generation of defines remove that prefix. No functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-9-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Standardise naming for DCZID_EL0 field namesMark Brown2-4/+4
The constants defining field names for DCZID_EL0 do not include the _EL0 that is included as part of our standard naming scheme. In preparation for automatic generation of the defines add the _EL0 in. No functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-8-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Standardise naming for CTR_EL0 fieldsMark Brown7-43/+45
cache.h contains some defines which are used to represent fields and enumeration values which do not follow the standard naming convention used for when we automatically generate defines for system registers. Update the names of the constants to reflect standardised naming and move them to sysreg.h. There is also a helper CTR_L1IP() which was open coded and has been converted to use SYS_FIELD_GET(). Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-7-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/cache: Restrict which headers are included in __ASSEMBLY__Mark Brown1-6/+5
Future changes to generate register definitions automatically will cause this header to be included in a linker script. This will mean that headers it in turn includes that are not safe for use in such a context (eg, due to the use of assembler macros) cause build problems. Avoid these issues by moving the affected includes and associated defines to the section of the file already guarded by ifndef __ASSEMBLY__. Suggested-by: Will Deacon <will@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-6-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Add SYS_FIELD_GET() helperMark Brown1-0/+3
Add a SYS_FIELD_GET() helper to match SYS_FIELD_PREP(), providing a simplified interface to FIELD_GET() when using the generated defines with standardized naming. Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220704170302.2609529-5-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Allow leading blanks on comments in sysreg fileMark Brown1-1/+1
Currently we only accept comments where the # is placed at the start of a line, allow leading blanks so we can format comments inside definitions in a more pleasing manner. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-4-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/idreg: Fix tab/space damageMark Brown1-7/+7
Quite a few of the overrides in idreg-override.c have a mix of tabs and spaces in their definitions, fix these. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-3-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/cpuinfo: Remove references to reserved cache typeMark Brown2-9/+15
In 155433cb365ee466 ("arm64: cache: Remove support for ASID-tagged VIVT I-caches") we removed all the support fir AIVIVT cache types and renamed all references to the field to say "unknown" since support for AIVIVT caches was removed from the architecture. Some confusion has resulted since the corresponding change to the architecture left the value named as AIVIVT but documented it as reserved in v8, refactor the code so we don't define the constant instead. This will help with automatic generation of this register field since it means we care less about the correspondence with the ARM. No functional change, the value displayed to userspace is unchanged. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-2-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/mm: Define defer_reserve_crashkernel()Anshuman Khandual3-6/+9
Crash kernel memory reservation gets deferred, when either CONFIG_ZONE_DMA or CONFIG_ZONE_DMA32 config is enabled on the platform. This deferral also impacts overall linear mapping creation including the crash kernel itself. Just encapsulate this deferral check in a new helper for better clarity. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20220705062556.1845734-1-anshuman.khandual@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64: dts: exynosautov9: add usi device tree nodesChanho Park1-0/+1067
Universal Serial Interface (USI) supports three types of serial interface such as Universal Asynchronous Receiver and Transmitter (UART), Serial Peripheral Interface (SPI), and Inter-Integrated Circuit (I2C). Each protocols can be working independently and configured as one of those using external configuration inputs. Exynos Auto v9 SoC support 12 USIs. When a USI uses two pins such as i2c and 3 wire uarts(RX/TX only), we can use remain two pins as i2c mode. So, we can define one USI node that includes serial/spi and hsi2c. usi_i2c nodes can be used only for i2c mode. We can have below combinations for one USI. 1) The usi node is used either 4 pin uart or 4 pin spi -> No usi_i2c can be used 2) The usi node is used 2 pin uart(RX/TX) and i2c(SDA/SCL) -> usi_i2c should be enabled to use the latter i2c 3) The usi node is used i2c(SDA/SCL) and i2c(SDA/SCL) -> usi_i2c should be enabled to use the latter i2c By default, all USIs are initially set to uart mode by below setting. samsung,mode = <USI_V2_UART>; You can change it either USI_V2_SPI or USI_V2_I2C. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220701015226.32781-6-chanho61.park@samsung.com
2022-07-05arm64: dts: exynosautov9: prepare usi0 changesChanho Park2-5/+7
Before adding whole USI nodes, this applies the changes of usi0 in advance. To be the usi0 and serian_0 nodes as SoC default, some properties should be moved to exynosautov9-sadk.dts. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220701015226.32781-5-chanho61.park@samsung.com
2022-07-05arm64: dts: exynosautov9: add pdma0 device tree nodeChanho Park1-0/+10
Add an ARM pl330 dma controller DT node as pdma0. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220701015226.32781-4-chanho61.park@samsung.com
2022-07-05dt-bindings: soc: samsung: usi: add exynosautov9-usi compatibleChanho Park1-2/+6
Add samsung,exynosautov9-usi dedicated compatible for representing USI of Exynos Auto v9 SoC. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220701015226.32781-2-chanho61.park@samsung.com
2022-07-05cxgb4: Use the bitmap API to allocate bitmapsChristophe JAILLET3-24/+17
Use bitmap_zalloc()/bitmap_free() instead of hand-writing them. It is less verbose and it improves the semantic. While at it, remove a useless bitmap_zero(). The bitmap is already zeroed when allocated. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/8a2168ef9871bd9c4f1cf19b8d5f7530662a5d15.1656866770.git.christophe.jaillet@wanadoo.fr Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-07-05arm64: dts: exynosautov9: correct spi11 pin namesChanho Park1-3/+3
They should be started with "gpp5-". Fixes: 31bbac5263aa ("arm64: dts: exynos: add initial support for exynosautov9 SoC") Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220627005832.8709-1-chanho61.park@samsung.com
2022-07-05net/mlx5: fix 32bit buildPaolo Abeni1-1/+2
We can't use the division operator on 64 bits integers, that breaks 32 bits build. Instead use the relevant helper. Fixes: 6ddac26cf763 ("net/mlx5e: Add support to modify hardware flow meter parameters") Acked-by: Saeed Mahameed <saeedm@nvidia.com> Link: https://lore.kernel.org/r/ecb00ddd1197b4f8a4882090206bd2eee1eb8b5b.1657005206.git.pabeni@redhat.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-07-05media: isl7998x: select V4L2_FWNODE to fix build errorRandy Dunlap1-0/+1
Fix build error when VIDEO_ISL7998X=y and V4L2_FWNODE=m by selecting V4L2_FWNODE. microblaze-linux-ld: drivers/media/i2c/isl7998x.o: in function `isl7998x_probe': (.text+0x8f4): undefined reference to `v4l2_fwnode_endpoint_parse' Cc: stable@vger.kernel.org # 5.18 and above Fixes: 51ef2be546e2 ("media: i2c: isl7998x: Add driver for Intersil ISL7998x") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: kernel test robot <lkp@intel.com> Cc: Marek Vasut <marex@denx.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Reviewed-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
2022-07-05bpf, samples: Remove AF_XDP samplesMagnus Karlsson7-3348/+0
Remove the AF_XDP samples from samples/bpf/ as they are dependent on the AF_XDP support in libbpf. This support has now been removed in the 1.0 release, so these samples cannot be compiled anymore. Please start to use libxdp instead. It is backwards compatible with the AF_XDP support that was offered in libbpf. New samples can be found in the various xdp-project repositories connected to libxdp and by googling. Signed-off-by: Magnus Karlsson <magnus.karlsson@intel.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Acked-by: Toke Høiland-Jørgensen <toke@redhat.com> Acked-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com> Acked-by: Jesper Dangaard Brouer <brouer@redhat.com> Link: https://lore.kernel.org/bpf/20220630093717.8664-1-magnus.karlsson@gmail.com
2022-07-05bpftool: Rename "bpftool feature list" into "... feature list_builtins"Quentin Monnet3-11/+11
To make it more explicit that the features listed with "bpftool feature list" are known to bpftool, but not necessary available on the system (as opposed to the probed features), rename the "feature list" command into "feature list_builtins". Note that "bpftool feature list" still works as before given that we recognise arguments from their prefixes; but the real name of the subcommand, in particular as displayed in the man page or the interactive help, will now include "_builtins". Since we update the bash completion accordingly, let's also take this chance to redirect error output to /dev/null in the completion script, to avoid displaying unexpected error messages when users attempt to tab-complete. Suggested-by: Daniel Borkmann <daniel@iogearbox.net> Signed-off-by: Quentin Monnet <quentin@isovalent.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Acked-by: Yonghong Song <yhs@fb.com> Link: https://lore.kernel.org/bpf/20220701093805.16920-1-quentin@isovalent.com
2022-07-05Merge branch 'fix-bridge_vlan_aware-sh-and-bridge_vlan_unaware-sh-with-iff_unicast_flt'Paolo Abeni1-1/+5
Vladimir Oltean says: ==================== Fix bridge_vlan_aware.sh and bridge_vlan_unaware.sh with IFF_UNICAST_FLT Make sure that h1 and h2 don't drop packets with a random MAC DA, which otherwise confuses these selftests. Also, fix an incorrect error message found during those failures. ==================== Link: https://lore.kernel.org/r/20220703073626.937785-1-vladimir.oltean@nxp.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-07-05selftests: forwarding: fix error message in learning_testVladimir Oltean1-1/+1
When packets are not received, they aren't received on $host1_if, so the message talking about the second host not receiving them is incorrect. Fix it. Fixes: d4deb01467ec ("selftests: forwarding: Add a test for FDB learning") Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-07-05selftests: forwarding: fix learning_test when h1 supports IFF_UNICAST_FLTVladimir Oltean1-0/+2
The first host interface has by default no interest in receiving packets MAC DA de:ad:be:ef:13:37, so it might drop them before they hit the tc filter and this might confuse the selftest. Enable promiscuous mode such that the filter properly counts received packets. Fixes: d4deb01467ec ("selftests: forwarding: Add a test for FDB learning") Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Tested-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-07-05selftests: forwarding: fix flood_unicast_test when h2 supports IFF_UNICAST_FLTVladimir Oltean1-0/+2
As mentioned in the blamed commit, flood_unicast_test() works by checking the match count on a tc filter placed on the receiving interface. But the second host interface (host2_if) has no interest in receiving a packet with MAC DA de:ad:be:ef:13:37, so its RX filter drops it even before the ingress tc filter gets to be executed. So we will incorrectly get the message "Packet was not flooded when should", when in fact, the packet was flooded as expected but dropped due to an unrelated reason, at some other layer on the receiving side. Force h2 to accept this packet by temporarily placing it in promiscuous mode. Alternatively we could either deliver to its MAC address or use tcpdump_start, but this has the fewest complications. This fixes the "flooding" test from bridge_vlan_aware.sh and bridge_vlan_unaware.sh, which calls flood_test from the lib. Fixes: 236dd50bf67a ("selftests: forwarding: Add a test for flooded traffic") Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Tested-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-07-05bpf: Omit superfluous address family check in __bpf_skc_lookupTobias Klauser1-3/+2
family is only set to either AF_INET or AF_INET6 based on len. In all other cases we return early. Thus the check against AF_UNSPEC can be omitted. Signed-off-by: Tobias Klauser <tklauser@distanz.ch> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Link: https://lore.kernel.org/bpf/20220630082618.15649-1-tklauser@distanz.ch
2022-07-05ARM: dts: stm32: Add ST MIPID02 bindings to AV96Marek Vasut1-0/+55
Add DT bindings for ST MIPID02 and DCMI to Avenger96 base DT. Both the ST MIPID02 and DCMI are disabled by default, as the AV96 camera module is optional. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for RCC pinMarek Vasut1-0/+15
Add another mux option for RCC pin, this is used on AV96 board for e.g. sensor clock supply. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for DCMI pinsMarek Vasut1-0/+37
Add another mux option for DCMI pins, this is used on AV96 board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add DHCOR based DRC Compact boardMarek Vasut3-0/+353
Add DT for DH DRC Compact unit, which is a universal controller device. The system has two ethernet ports, one CAN, RS485 and RS232, USB, uSD card slot, eMMC and SDIO Wi-Fi. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for UART5 pinsMarek Vasut1-0/+13
Add another mux option for UART5 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for UART4 pinsMarek Vasut1-0/+30
Add another mux option for UART4 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for UART3 pinsMarek Vasut1-0/+41
Add another mux option for UART3 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for SPI2 pinsMarek Vasut1-0/+15
Add another mux option for SPI2 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for CAN1 pinsMarek Vasut1-0/+20
Add another mux option for CAN1 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05dt-bindings: arm: stm32: Add compatible string for DH electronics DHCOR DRC CompactMarek Vasut1-1/+7
Add DT compatible string for DH electronics STM32MP15xx DHCOR on DRC Compact carrier board into YAML DT binding document. This system is a general purpose DIN Rail Controller design. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Fix SPI2 pinmux pin comments on stm32mp15Marek Vasut1-3/+3
Those pin comments refer to SPI2 pins, not SPI1 pins, update the comments. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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