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2022-05-04drm/amdgpu/sdma5: initialize sdma mqdJack Xiao1-0/+44
2022-05-04drm/amdgpu/sdma5.2: add mes support for sdma ib testJack Xiao1-14/+36
2022-05-04drm/amdgpu/sdma5.2: add mes support for sdma ring testJack Xiao1-11/+26
2022-05-04drm/amdgpu/sdma5.2: add mes queue fence handlingJack Xiao1-0/+18
2022-05-04drm/amdgpu/sdma5.2: associate mes queue id with fenceJack Xiao1-2/+4
2022-05-04drm/amdgpu/sdma5.2: initialize sdma mqdJack Xiao1-0/+44
2022-05-04drm/amdgpu/sdma: use per-ctx sdma csa address for mes sdma queueJack Xiao1-7/+15
2022-05-04drm/amdgpu: don't use kiq to flush gpu tlb if mes enabledJack Xiao1-1/+1
2022-05-04drm/amdgpu/gfx10: add mes support for gfx ib testJack Xiao1-13/+33
2022-05-04drm/amdgpu/gfx10: add mes queue fence handlingJack Xiao1-20/+40
2022-05-04drm/amdgpu/mes: extend mes framework to support multiple mes pipesJack Xiao2-101/+149
2022-05-04drm/amdgpu: allocate doorbell index for mes kiqJack Xiao3-4/+8
2022-05-04drm/amdgpu: add mes_kiq module parameter v2Jack Xiao3-2/+19
2022-05-04drm/amdgpu: update mes process/gang/queue definitionsJack Xiao1-0/+59
2022-05-04dt-bindings: interrupt-controller: arm,gic-v3: Make the v2 compat requirements explicitMarc Zyngier1-2/+6
2022-05-04irqchip/gic-v3: Relax polling of GIC{R,D}_CTLR.RWPMarc Zyngier1-20/+18
2022-05-04irqchip/gic-v3: Detect LPI invalidation MMIO registersMarc Zyngier1-4/+16
2022-05-04regulator: core: Add error flags to sysfs attributesZev Weiss2-0/+126
2022-05-04regulator: dt-bindings: qcom,rpmh: document vdd-l7-bob-supply on PMR735AKrzysztof Kozlowski1-0/+1
2022-05-04regulator: dt-bindings: qcom,rpmh: document supplies per variantKrzysztof Kozlowski1-14/+242
2022-05-04regulator: dt-bindings: qcom,rpmh: update maintainersKrzysztof Kozlowski1-1/+2
2022-05-04ASoC: cs35l45: Enable BOOSTRichard Fitzgerald1-4/+0
2022-05-04ASoC: soc-generic-dmaengine-pcm: Use default config when none is givenSascha Hauer1-32/+25
2022-05-04ASoC: SOF: ipc3: Remove the ipc3-ops.h header filePeter Ujfalusi9-27/+9
2022-05-04ASoC: Pull in fixesMark Brown22-70/+124
2022-05-04arm64/sysreg: Generate definitions for TTBRn_EL1Mark Brown2-2/+14
2022-05-04arm64/sysreg: Generate definitions for ID_AA64ISAR0_EL1Mark Brown2-20/+67
2022-05-04arm64/sysreg: Enable automatic generation of system register definitionsMark Brown3-1/+16
2022-05-04arm64: Add sysreg header generation scriptingMark Rutland2-0/+309
2022-05-04arm64/sysreg: Standardise ID_AA64ISAR0_EL1 macro namesMark Brown4-66/+66
2022-05-04arm64: Update name of ID_AA64ISAR0_EL1_ATOMIC to reflect ARMMark Brown3-5/+5
2022-05-04arm64/sysreg: Define bits for previously RES1 fields in SCTLR_EL1Mark Brown1-21/+32
2022-05-04arm64/sysreg: Rename SCTLR_EL1_NTWE/TWI to SCTLR_EL1_nTWE/TWIMark Brown1-3/+3
2022-05-04arm64/mte: Make TCF field values and naming more standardMark Brown3-12/+14
2022-05-04arm64/mte: Make TCF0 naming and field values more standardMark Brown2-7/+7
2022-05-04arm64/sysreg: Introduce helpers for access to sysreg fieldsMark Brown1-0/+6
2022-05-04regulator: mt6315: Enforce regulator-compatible, not nameNícolas F. R. A. Prado1-1/+1
2022-05-04RDMA/rxe: Replace paylen by payloadBob Pearson1-6/+6
2022-05-04drm/amdgpu: use the whole doorbell space for mesJack Xiao1-12/+18
2022-05-04drm/amdgpu/gmc10: skip emitting pasid mapping packetJack Xiao1-0/+4
2022-05-04drm/amdgpu/gfx10: use INVALIDATE_TLBS to invalidate TLBs v2Jack Xiao1-7/+20
2022-05-04drm/amdgpu/gfx10: inherit vmid from mqdJack Xiao1-0/+8
2022-05-04drm/amdgpu/gfx10: associate mes queue id with fence v2Jack Xiao2-1/+4
2022-05-04drm/amdgpu/gfx10: use per ctx CSA for de metadataJack Xiao1-11/+28
2022-05-04drm/amdgpu/gfx10: use per ctx CSA for ce metadataJack Xiao1-9/+19
2022-05-04drm/amdgpu/gfx10: implement mqd functions of gfx/compute eng v2Jack Xiao1-55/+56
2022-05-04drm/amdgpu: assign the cpu/gpu address of fence from ringJack Xiao1-2/+2
2022-05-04drm/amdgpu: initialize/finalize the ring for mes queueJack Xiao1-41/+104
2022-05-04drm/amdgpu: use ring structure to access rptr/wptr v2Jack Xiao21-145/+128
2022-05-04drm/amdgpu: define ring structure to access rptr/wptr/fenceJack Xiao1-0/+6
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