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2022-05-02mtd: spi-nor: move spi_nor_write_ear() to winbond moduleMichael Walle4-40/+41
The "Extended Address Register" is winbond specific. If the flash is larger than 16MiB and is used in 3 byte address mode, it is used to set the remaining address bits. Move the write_ear() function, the opcode macros and the spimem op template into the winbond module and rename them accordingly. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220429100153.2338501-1-michael@walle.cc
2022-05-02mm/slub: remove unused kmem_cache_order_objects maxMiaohe Lin2-3/+0
max field holds the largest slab order that was ever used for a slab cache. But it's unused now. Remove it. Signed-off-by: Miaohe Lin <linmiaohe@huawei.com> Reviewed-by: Muchun Song <songmuchun@bytedance.com> Acked-by: David Rientjes <rientjes@google.com> Signed-off-by: Vlastimil Babka <vbabka@suse.cz> Link: https://lore.kernel.org/r/20220429090545.33413-1-linmiaohe@huawei.com
2022-05-02selftests: net: vrf_strict_mode_test: add support to select a test to runJaehee Park1-9/+39
Add a boilerplate test loop to run all tests in vrf_strict_mode_test.sh. Add a -t flag that allows a selected test to run. Remove the vrf_strict_mode_tests function which is now unused. Signed-off-by: Jaehee Park <jhpark1013@gmail.com> Reviewed-by: David Ahern <dsahern@kernel.org> Link: https://lore.kernel.org/r/20220429164658.GA656707@jaehee-ThinkPad-X1-Extreme Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-05-02mm: slab: fix comment for __assume_kmalloc_alignmentAndrey Konovalov1-3/+3
The comment next to the __assume_kmalloc_alignment definition is not precise: kmalloc relies on kmem_cache_alloc, so kmalloc technically returns pointers aligned to both ARCH_KMALLOC_MINALIGN and ARCH_SLAB_MINALIGN, not only to ARCH_KMALLOC_MINALIGN. (See create_kmalloc_cache()->create_boot_cache()->calculate_alignment() for SLAB and SLUB and __do_kmalloc_node() for SLOB.) Clarify the comment. The assumption specified by __assume_kmalloc_alignment is still correct, although it can be made stronger. I'll leave this to a separate patch. Signed-off-by: Andrey Konovalov <andreyknvl@google.com> Acked-by: David Rientjes <rientjes@google.com> Signed-off-by: Vlastimil Babka <vbabka@suse.cz> Link: https://lore.kernel.org/r/84d8142747230f2015eaf9705ee7c2e1a9f56596.1651161548.git.andreyknvl@google.com
2022-05-02mm: slab: fix comment for ARCH_KMALLOC_MINALIGNAndrey Konovalov1-1/+1
The comment next to the ARCH_KMALLOC_MINALIGN definition says that ARCH_KMALLOC_MINALIGN can be defined in arch headers. This is incorrect: it's actually ARCH_DMA_MINALIGN that can be defined there. Fix the comment. Signed-off-by: Andrey Konovalov <andreyknvl@google.com> Acked-by: David Rientjes <rientjes@google.com> Signed-off-by: Vlastimil Babka <vbabka@suse.cz> Link: https://lore.kernel.org/r/fe1ca7a25a054b61d1038686d07569416e287e7b.1651161548.git.andreyknvl@google.com
2022-05-02gpio: syscon: Remove usage of syscon_regmap_lookup_by_compatibleAlexander Shiyan1-26/+15
Since version 5.13, the standard syscon bindings have been added to all clps711x DT nodes, so we can now use the more general syscon_regmap_lookup_by_phandle function to get the syscon pointer. This patch removes the usage of the syscon_regmap_lookup_by_compatible function as it is no longer used in the driver. Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
2022-05-02drm/i915: move tons of power well initializers to rodataJani Nikula1-2/+2
Using compound literals for initialization can be tricky. Lacking a const qualifier, they won't end up in rodata, which is probably not expected or intended. Add const to move a whopping 136 initializers to rodata. Compare: $ objdump --syms drivers/gpu/drm/i915/display/intel_display_power_map.o | grep "\.rodata.*__compound_literal" $ objdump --syms drivers/gpu/drm/i915/display/intel_display_power_map.o | grep "\.data.*__compound_literal" Before and after the change. Fixes: c32ffce42aa5 ("drm/i915: Convert the power well descriptor domain mask to an array of domains") Fixes: 4a845ff0c0d4 ("drm/i915: Simplify power well definitions by adding power well instances") Cc: Imre Deak <imre.deak@intel.com> Cc: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220429142140.2671828-1-jani.nikula@intel.com
2022-05-02ARM: dts: stm32: add support for Protonic PRTT1x boardsOleksij Rempel5-0/+651
This boards are based on STM32MP151AAD3 and use 10BaseT1L for communication. - PRTT1C - 10BaseT1L switch - PRTT1S - 10BaseT1L CO2 sensor board - PRTT1A - 10BaseT1L multi functional controller Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-05-02ARM: dts: stm32: stm32mp15-pinctrl: add spi1-1 pinmux groupOleksij Rempel1-0/+15
Add spi1-1 pingroup as preparation for Protonic PRTT1C board. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-05-02dt-bindings: net: silabs,wfx: add prt,prtt1c-wfm200 antenna variantOleksij Rempel1-0/+1
Add compatible for wfm200 antenna configuration variant for Protonic PRTT1C board. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-05-02dt-bindings: arm: stm32: Add compatible strings for Protonic T1L boardsOleksij Rempel1-0/+8
This boards are based on STM32MP151AAD3 and use 10BaseT1L for communication. - PRTT1C - 10BaseT1L switch - PRTT1S - 10BaseT1L CO2 sensor board - PRTT1A - 10BaseT1L multi functional controller Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-05-02Merge branch 'devices-always-netif_f_lltx'Paolo Abeni2-49/+35
Peilin Ye says: ==================== devices always NETIF_F_LLTX v1: https://lore.kernel.org/netdev/cover.1650580763.git.peilin.ye@bytedance.com/ change since v1: - deleted "depends on patch..." in [1/2]'s commit message This patchset depends on these fixes [1], which has been merged into net-next. Since o_seqno is now atomic_t, we can always turn on NETIF_F_LLTX for [IP6]GRE[TAP] devices, since we no longer need the TX lock (&txq->_xmit_lock). We could probably do the same thing to [IP6]ERSPAN devices as well, but I'm not familiar with them yet. For example, ERSPAN devices are initialized as |= GRE_FEATURES in erspan_tunnel_init(), but I don't see IP6ERSPAN devices being initialized as |= GRE6_FEATURES. Where should we initialize IP6ERSPAN devices' ->features? Please suggest if I'm missing something, thanks! [1] https://lore.kernel.org/netdev/cover.1650575919.git.peilin.ye@bytedance.com/ ==================== Link: https://lore.kernel.org/r/cover.1651207788.git.peilin.ye@bytedance.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-05-02ip6_gre: Make IP6GRE and IP6GRETAP devices always NETIF_F_LLTXPeilin Ye1-21/+13
Recently we made o_seqno atomic_t. Stop special-casing TUNNEL_SEQ, and always mark IP6GRE[TAP] devices as NETIF_F_LLTX, since we no longer need the TX lock (&txq->_xmit_lock). Signed-off-by: Peilin Ye <peilin.ye@bytedance.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-05-02ip_gre: Make GRE and GRETAP devices always NETIF_F_LLTXPeilin Ye1-28/+22
Recently we made o_seqno atomic_t. Stop special-casing TUNNEL_SEQ, and always mark GRE[TAP] devices as NETIF_F_LLTX, since we no longer need the TX lock (&txq->_xmit_lock). Signed-off-by: Peilin Ye <peilin.ye@bytedance.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-05-02dt-bindings: arm: stm32: correct blank linesKrzysztof Kozlowski1-1/+2
Correct blank lines to precesily separate entries. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-05-02dt-bindings: arm: stm32: narrow DH STM32MP1 SoM boardsKrzysztof Kozlowski1-15/+22
The bindings for DH STM32MP1 SoM boards allows invalid combinations, e.g. st,stm32mp153 SoC on a dh,stm32mp157c-dhcom-som SoM. Split the enums to properly match valid setups. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-05-02x86/fpu: Cleanup variable shadowingThomas Gleixner1-1/+1
Addresses: warning: Local variable 'mask' shadows outer variable Remove extra variable declaration and switch the bit mask assignment to use BIT_ULL() while at it. Fixes: 522e92743b35 ("x86/fpu: Deduplicate copy_uabi_from_user/kernel_to_xstate()") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/lkml/202204262032.jFYKit5j-lkp@intel.com
2022-05-02can: ctucanfd: remove PCI module debug parametersPavel Pisa1-16/+6
This patch removes the PCI module debug parameters, which are not needed anymore, to make both checkpatch.pl and patchwork happy. Link: https://lore.kernel.org/all/1fd684bcf5ddb0346aad234072f54e976a5210fb.1650816929.git.pisa@cmp.felk.cvut.cz Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> [mkl: split into separate patches] Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2022-05-02can: ctucanfd: remove debug statementsPavel Pisa1-26/+0
This patch removes the debug statements from the driver to make checkpatch.pl and patchwork happy. Link: https://lore.kernel.org/all/1fd684bcf5ddb0346aad234072f54e976a5210fb.1650816929.git.pisa@cmp.felk.cvut.cz Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> [mkl: split into separate patches] Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2022-05-02can: ctucanfd: remove inline keyword from local static functionsPavel Pisa1-4/+3
This patch removes the inline keywords from the local static functions to make both checkpatch.pl and patchwork happy. Link: https://lore.kernel.org/all/1fd684bcf5ddb0346aad234072f54e976a5210fb.1650816929.git.pisa@cmp.felk.cvut.cz Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> [mkl: split into separate patches] Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2022-05-02can: ctucanfd: ctucan_platform_probe(): remove unnecessary print function dev_err()Jiapeng Chong1-1/+0
The print function dev_err() is redundant because platform_get_irq() already prints an error. Eliminate the follow coccicheck warnings: | drivers/net/can/ctucanfd/ctucanfd_platform.c:67:2-9: | line 67 is redundant because platform_get_irq() already prints an error. Link: https://lore.kernel.org/all/20220421203242.7335-1-jiapeng.chong@linux.alibaba.com Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Acked-by: Pave Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2022-05-02can: ctucanfd: remove unused including <linux/version.h>Jiapeng Chong1-1/+0
Eliminate the follow versioncheck warning: | drivers/net/can/ctucanfd/ctucanfd_base.c: 34 linux/version.h not needed. Link: https://lore.kernel.org/all/20220421202852.2693-1-jiapeng.chong@linux.alibaba.com Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Acked-by: Pave Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2022-05-02docs: networking: device drivers: can: ctucanfd: update author e-mailPavel Pisa1-1/+1
This patch updates the author's email address. Link: https://lore.kernel.org/all/e4396244da6b008c671def9f50bb983a10389863.1650816929.git.pisa@cmp.felk.cvut.cz Cc: Odrej Ille <ondrej.ille@gmail.com> Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> [mkl: split into separate patches] Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2022-05-02docs: networking: device drivers: can: add ctucanfd to indexPavel Pisa1-0/+1
This patch adds the ctucanfd-driver document to the index. Link: https://lore.kernel.org/all/e4396244da6b008c671def9f50bb983a10389863.1650816929.git.pisa@cmp.felk.cvut.cz Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> [mkl: split into separate patches] Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2022-05-02can: m_can: remove a copy of the NAPI_POLL_WEIGHT defineJakub Kicinski1-6/+3
Defining local versions of NAPI_POLL_WEIGHT with the same values in the drivers just makes refactoring harder. Link: https://lore.kernel.org/all/20220429174446.196655-1-kuba@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2022-05-02dt-bindings: can: renesas,rcar-canfd: Document RZ/G2UL supportBiju Das1-0/+1
Add CANFD binding documentation for Renesas R9A07G043 (RZ/G2UL) SoC. Link: https://lore.kernel.org/all/20220423130743.123198-1-biju.das.jz@bp.renesas.com Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2022-05-02x86/aperfperf: Make it correct on 32bit and UP kernelsThomas Gleixner1-3/+3
The utilization of arch_scale_freq_tick() for CPU frequency readouts is incomplete as it failed to move the function prototype and the define out of the CONFIG_SMP && CONFIG_X86_64 #ifdef. Make them unconditionally available. Fixes: bb6e89df9028 ("x86/aperfmperf: Make parts of the frequency invariance code unconditional") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/lkml/202205010106.06xRBR2C-lkp@intel.com
2022-05-02drm/nouveau: use drm_gem_plane_helper_prepare_fbChristian König1-3/+2
Instead of manually adjusting the plane state. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220429134230.24334-3-christian.koenig@amd.com
2022-05-02phy: rockchip-inno-usb2: Clean up some inconsistent indentingJiapeng Chong1-2/+2
Eliminate the follow smatch warning: drivers/phy/rockchip/phy-rockchip-inno-usb2.c:1203 rockchip_usb2phy_probe() warn: inconsistent indenting. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20220421203038.4550-1-jiapeng.chong@linux.alibaba.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-05-02drm: handle kernel fences in drm_gem_plane_helper_prepare_fb v2Christian König4-64/+62
drm_gem_plane_helper_prepare_fb() was using drm_atomic_set_fence_for_plane() which ignores all implicit fences when an explicit fence is already set. That's rather unfortunate when the fb still has a kernel fence we need to wait for to avoid presenting garbage on the screen. So instead update the fence in the plane state directly. While at it also take care of all potential GEM objects and not just the first one. Also remove the now unused drm_atomic_set_fence_for_plane() function, new drivers should probably use the atomic helpers directly. v2: improve kerneldoc, use local variable and num_planes, WARN_ON_ONCE on missing planes. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v1) Acked-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/20220429134230.24334-1-christian.koenig@amd.com
2022-05-02microblaze: fix typos in commentsJulia Lawall2-2/+2
Various spelling mistakes in comments. Detected with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Link: https://lore.kernel.org/r/20220430191122.8667-1-Julia.Lawall@inria.fr Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-05-01xtensa: clean up labels in the kernel entry assemblyMax Filippov1-47/+53
Don't use numeric labels for long jumps, use named local labels instead. Avoid conditional label definition. No functional changes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-01xtensa: don't leave invalid TLB entry in fast_store_prohibitedMax Filippov1-1/+5
When fast_store_prohibited needs to go to the C-level exception handler it leaves TLB entry that caused page fault in the TLB. If the faulting task gets switched to a different CPU and completes page table update there the TLB entry will get out of sync with the page table which may cause a livelock on access to that page. Invalidate faulting TLB entry on a slow path exit from the fast_store_prohibited. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-01xtensa: fix declaration of _SecondaryResetVector_text_*Max Filippov1-1/+1
Secondary reset vector is defined, compiled and used when CONFIG_SECONDARY_RESET_VECTOR is enabled, not only on SMP. Make declarations of _SecondaryResetVector_text_* symbols available accordingly. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-01irqchip: irq-xtensa-mx: fix initial IRQ affinityMax Filippov1-4/+14
When irq-xtensa-mx chip is used in non-SMP configuration its irq_set_affinity callback is not called leaving IRQ affinity set empty. As a result IRQ delivery does not work in that configuration. Initialize IRQ affinity of the xtensa MX interrupt distributor to CPU 0 for all external IRQ lines. Cc: stable@vger.kernel.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-01xtensa: enable ARCH_HAS_DEBUG_VM_PGTABLEMax Filippov2-1/+2
xtensa kernels successfully build and run with CONFIG_DEBUG_VM_PGTABLE=y, enable arch support for it. Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-01xtensa: add hibernation supportMax Filippov5-0/+129
Define ARCH_HIBERNATION_POSSIBLE in Kconfig and implement hibernation callbacks. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-01xtensa: support coprocessors on SMPMax Filippov11-67/+230
Current coprocessor support on xtensa only works correctly on uniprocessor configurations. Make it work on SMP too and keep it lazy. Make coprocessor_owner array per-CPU and move it to struct exc_table for easy access from the fast_coprocessor exception handler. Allow task to have live coprocessors only on single CPU, record this CPU number in the struct thread_info::cp_owner_cpu. Change struct thread_info::cpenable meaning to be 'coprocessors live on cp_owner_cpu'. Introduce C-level coprocessor exception handler that flushes and releases live coprocessors of the task taking 'coprocessor disabled' exception and call it from the fast_coprocessor handler when the task has live coprocessors on other CPU. Make coprocessor_flush_all and coprocessor_release_all work correctly when called from any CPU by sending IPI to the cp_owner_cpu. Add function coprocessor_flush_release_all to do flush followed by release atomically. Add function local_coprocessors_flush_release_all to flush and release all coprocessors on the local CPU and use it to flush coprocessor contexts from the CPU that goes offline. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-01xtensa: get rid of stack frame in coprocessor_flushMax Filippov1-6/+5
coprocessor_flush is an ordinary function, it can use all registers. Don't reserve stack frame for it and use a7 to preserve a0 around the context saving call. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-01xtensa: merge SAVE_CP_REGS_TAB and LOAD_CP_REGS_TABMax Filippov1-48/+37
Both tables share the same offset field but the different function pointers. Merge them into single table with 3-element entries to reduce code and data duplication. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-01xtensa: add xtensa_xsr macroMax Filippov1-0/+7
xtensa_xsr does the XSR instruction for the specified special register. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-01xtensa: handle coprocessor exceptions in kernel modeMax Filippov1-1/+1
In order to let drivers use xtensa coprocessors on behalf of the calling process the kernel must handle coprocessor exceptions from the kernel mode the same way as from the user mode. This is not sufficient to allow using coprocessors transparently in IRQ or softirq context. Should such users exist they must be aware of the context and do the right thing, e.g. preserve the coprocessor state and resore it after use. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-01xtensa: use callx0 opcode in fast_coprocessorMax Filippov1-10/+8
Instead of emulating call0 in fast_coprocessor use that opcode directly. Use 'ret' instead of 'jx a0'. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-01xtensa: clean up excsave1 initializationMax Filippov2-4/+3
Use xtensa_set_sr instead of inline assembly. Rename local variable exc_table in early_trap_init to avoid conflict with per-CPU variable of the same name. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-01xtensa: clean up declarations in coprocessor.hMax Filippov1-4/+3
Drop 'extern' from all function declarations. Add parameter names in declarations. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-01xtensa: clean up exception handler prototypesMax Filippov3-15/+13
Exception handlers are currently passed as void pointers because they may have one or two parameters. Only two handlers uses the second parameter and it is available in the struct pt_regs anyway. Make all handlers have only one parameter, introduce xtensa_exception_handler type for handlers and use it in trap_set_handler. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-01xtensa: clean up function declarations in traps.cMax Filippov2-32/+32
Drop 'extern' from all function declarations and move those that need to be visible from traps.c to traps.h. Add 'asmlinkage' to declarations of fucntions defined in assembly. Add 'static' to declarations and definitions only used locally. Add argument names in declarations. Drop unused second argument from do_multihit and do_page_fault. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-01xtensa: enable KCSANMax Filippov6-7/+73
Prefix arch-specific barrier macros with '__' to make use of instrumented generic macros. Prefix arch-specific bitops with 'arch_' to make use of instrumented generic functions. Provide stubs for 64-bit atomics when building with KCSAN. Disable KCSAN instrumentation in arch/xtensa/boot. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Marco Elver <elver@google.com>
2022-05-01xtensa: enable HAVE_VIRT_CPU_ACCOUNTING_GENMax Filippov2-1/+2
There's no direct cputime_t manipulation in the xtensa arch code, so generic virt CPU accounting may be enabled. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-01xtensa: enable context trackingMax Filippov3-1/+11
Put user exit context tracking call on the common kernel entry/exit path (function calls are impossible at earlier kernel entry stages because PS.EXCM is not cleared yet). Put user entry context tracking call on the user exit path. Syscalls go through this common code too, so nothing specific needs to be done for them. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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