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2022-04-20KVM: arm64: Introduce kvm_counter_compute_delta() helperMarc Zyngier1-7/+10
Refactor kvm_timer_compute_delta() and extract a helper that compute the delta (in ns) between a given timer and an arbitrary value. No functional change expected. Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220419182755.601427-5-maz@kernel.org
2022-04-20KVM: arm64: Simplify kvm_cpu_has_pending_timer()Marc Zyngier3-15/+2
kvm_cpu_has_pending_timer() ends up checking all the possible timers for a wake-up cause. However, we already check for pending interrupts whenever we try to wake-up a vcpu, including the timer interrupts. Obviously, doing the same work twice is once too many. Reduce this helper to almost nothing, but keep it around, as we are going to make use of it soon. Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220419182755.601427-4-maz@kernel.org
2022-04-20arm64: Use WFxT for __delay() when possibleMarc Zyngier1-1/+11
Marginally optimise __delay() by using a WFIT/WFET sequence. It probably is a win if no interrupt fires during the delay. Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20220419182755.601427-11-maz@kernel.org
2022-04-20arm64: Add wfet()/wfit() helpersMarc Zyngier1-0/+4
Just like we have helpers for WFI and WFE, add the WFxT versions. Note that the encoding is that reported by objdump, as no currrent toolchain knows about these instructions yet. Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20220419182755.601427-10-maz@kernel.org
2022-04-20arm64: Add HWCAP advertising FEAT_WFXTMarc Zyngier7-0/+12
In order to allow userspace to enjoy WFET, add a new HWCAP that advertises it when available. Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20220419182755.601427-9-maz@kernel.org
2022-04-20nfc: MAINTAINERS: add Bug entryKrzysztof Kozlowski1-0/+1
Add a Bug section, indicating preferred mailing method for bug reports, to NFC Subsystem entry. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-04-20soc: mediatek: cmdq: Use mailbox rx_callback instead of cmdq_task_cbChun-Kuang Hu2-28/+2
rx_callback is a standard mailbox callback mechanism and could cover the function of proprietary cmdq_task_cb, so use the standard one instead of the proprietary one. Client has changed to use the standard callback machanism and sync dma buffer in client driver, so remove the proprietary callback in cmdq helper. Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by: jason-jh.lin <jason-jh.lin@mediatek.com> Tested-by: jason-jh.lin <jason-jh.lin@mediatek.com> Link: https://lore.kernel.org/r/1650102868-26219-1-git-send-email-chunkuang.hu@kernel.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-04-20arm64: Add RV and RN fields for ESR_ELx_WFx_ISSMarc Zyngier1-0/+2
The ISS field exposed by ESR_ELx contain two additional subfields with FEAT_WFxT: - RN, the register number containing the timeout - RV, indicating if the register number is valid Describe these two fields according to the arch spec. No functional change. Reviewed-by: Joey Gouly <joey.gouly@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20220419182755.601427-3-maz@kernel.org
2022-04-20arm64: Expand ESR_ELx_WFx_ISS_TI to match its ARMv8.7 definitionMarc Zyngier1-2/+4
Starting with FEAT_WFXT in ARMv8.7, the TI field in the ISS that is reported on a WFx trap is expanded by one bit to allow the description of WFET and WFIT. Special care is taken to exclude the WFxT bit from the mask used to match WFI so that it also matches WFIT when trapped from EL0. Reviewed-by: Joey Gouly <joey.gouly@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20220419182755.601427-2-maz@kernel.org
2022-04-20dmaengine: hidma: In hidma_prep_dma_memset treat value as a single byteBen Walker1-1/+12
The value parameter is a single byte, so duplicate it to the 8 byte range that is used as the pattern. Signed-off-by: Ben Walker <benjamin.walker@intel.com> Cc: Sinan Kaya <okaya@kernel.org> Link: https://lore.kernel.org/r/20220301182551.883474-5-benjamin.walker@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: at_xdmac: In at_xdmac_prep_dma_memset, treat value as a single byteBen Walker1-1/+8
The value passed in to .prep_dma_memset is to be treated as a single byte repeating pattern. Signed-off-by: Ben Walker <benjamin.walker@intel.com> Cc: Ludovic Desroches <ludovic.desroches@microchip.com> Cc: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20220301182551.883474-4-benjamin.walker@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: at_hdmac: In atc_prep_dma_memset, treat value as a single byteBen Walker1-1/+9
The value passed in to .prep_dma_memset is to be treated as a single byte repeating pattern. Signed-off-by: Ben Walker <benjamin.walker@intel.com> Cc: Ludovic Desroches <ludovic.desroches@microchip.com> Cc: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20220301182551.883474-3-benjamin.walker@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: Document dmaengine_prep_dma_memsetBen Walker2-0/+14
Document this function to make clear the expected behavior of the 'value' parameter. It was intended to match the behavior of POSIX memset as laid out here: https://lore.kernel.org/dmaengine/YejrA5ZWZ3lTRO%2F1@matsya/ Signed-off-by: Ben Walker <benjamin.walker@intel.com> Link: https://lore.kernel.org/r/20220301182551.883474-2-benjamin.walker@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: idxd: move wq irq enabling to after device enableDave Jiang1-9/+9
Move the calling of request_irq() and other related irq setup code until after the WQ is successfully enabled. This reduces the amount of setup/teardown if the wq is not configured correctly and cannot be enabled. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/164642777730.179702.1880317757087484299.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: idxd: skip clearing device context when device is read-onlyDave Jiang1-0/+3
If the device shows up as read-only configuration, skip the clearing of the state as the context must be preserved for device re-enable after being disabled. Fixes: 0dcfe41e9a4c ("dmanegine: idxd: cleanup all device related bits after disabling device") Reported-by: Tony Zhu <tony.zhu@intel.com> Tested-by: Tony Zhu <tony.zhu@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/164971479479.2200566.13980022473526292759.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: idxd: add RO check for wq max_transfer_size writeDave Jiang1-0/+3
Block wq_max_transfer_size_store() when the device is configured as read-only and not configurable. Fixes: d7aad5550eca ("dmaengine: idxd: add support for configurable max wq xfer size") Reported-by: Bernice Zhang <bernice.zhang@intel.com> Tested-by: Bernice Zhang <bernice.zhang@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/164971488154.2200913.10706665404118545941.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: idxd: add RO check for wq max_batch_size writeDave Jiang1-0/+3
Block wq_max_batch_size_store() when the device is configured as read-only and not configurable. Fixes: e7184b159dd3 ("dmaengine: idxd: add support for configurable max wq batch size") Reported-by: Bernice Zhang <bernice.zhang@intel.com> Tested-by: Bernice Zhang <bernice.zhang@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/164971493551.2201159.1942042593642155209.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: idxd: fix retry value to be constant for duration of function callDave Jiang1-2/+2
When retries is compared to wq->enqcmds_retries each loop of idxd_enqcmds(), wq->enqcmds_retries can potentially changed by user. Assign the value of retries to wq->enqcmds_retries during initialization so it is the original value set when entering the function. Fixes: 7930d8553575 ("dmaengine: idxd: add knob for enqcmds retries") Suggested-by: Dave Hansen <dave.hansen@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/165031760154.3658664.1983547716619266558.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: idxd: match type for retries var in idxd_enqcmds()Dave Jiang1-1/+2
wq->enqcmds_retries is defined as unsigned int. However, retries on the stack is defined as int. Change retries to unsigned int to compare the same type. Fixes: 7930d8553575 ("dmaengine: idxd: add knob for enqcmds retries") Suggested-by: Thiago Macieira <thiago.macieira@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/165031747059.3658198.6035308204505664375.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: dw-edma: Fix inconsistent indentingJiapeng Chong1-9/+10
Eliminate the follow smatch warning: drivers/dma/dw-edma/dw-edma-v0-core.c:419 dw_edma_v0_core_start() warn: inconsistent indenting. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Link: https://lore.kernel.org/r/20220413023442.18856-1-jiapeng.chong@linux.alibaba.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: tegra: Remove unused including <linux/version.h>Jiapeng Chong1-1/+0
Eliminate the follow versioncheck warning: ./drivers/dma/tegra186-gpc-dma.c: 21 linux/version.h not needed. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Link: https://lore.kernel.org/r/20220413083842.69845-1-jiapeng.chong@linux.alibaba.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: add verification of DMA_INTERRUPT capability for dmatestDave Jiang1-3/+10
Looks like I forgot to add DMA_INTERRUPT cap setting to the idxd driver and dmatest is still working regardless of this mistake. Add an explicit check of DMA_INTERRUPT capability for dmatest to make sure the DMA device being used actually supports interrupt before the test is launched and also that the driver is programmed correctly. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/164978679251.2361020.5856734256126725993.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: mediatek: mtk-hsdma: use NULL instead of using plain integer as pointerHaowen Bai1-1/+1
This fixes the following sparse warnings: drivers/dma/mediatek/mtk-hsdma.c:604:26: warning: Using plain integer as NULL pointer Signed-off-by: Haowen Bai <baihaowen@meizu.com> Link: https://lore.kernel.org/r/1649750340-30777-1-git-send-email-baihaowen@meizu.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: pl08x: drop the useless functionHaowen Bai1-11/+0
Unneeded variable: "retval". Return "NULL" , so we have to make code clear. better way, drop the function. Signed-off-by: Haowen Bai <baihaowen@meizu.com> Link: https://lore.kernel.org/r/1649726180-13133-1-git-send-email-baihaowen@meizu.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: idxd: set max_xfer and max_batch for RO deviceDave Jiang1-0/+3
Load the max_xfer_size and max_batch_size values from the values read from registers to the shadow variables. This will allow the read-only device to display the correct values for the sysfs attributes. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/164971507673.2201761.11244446608988838897.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: idxd: set DMA_INTERRUPT cap bitDave Jiang1-0/+1
Even though idxd driver has always supported interrupt, it never actually set the DMA_INTERRUPT cap bit. Rectify this mistake so the interrupt capability is advertised. Reported-by: Ben Walker <benjamin.walker@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/164971497859.2201379.17925303210723708961.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: jz4780: set DMA maximum segment sizeAidan MacDonald1-0/+9
Set the maximum segment size, since the hardware can do transfers larger than the default 64 KiB returned by dma_get_max_seg_size(). The maximum segment size is limited by the 24-bit transfer count field in DMA descriptors. The number of bytes is equal to the transfer count times the transfer size unit, which is selected by the driver based on the DMA buffer address and length of the transfer. The size unit can be as small as 1 byte, so set the maximum segment size to 2^24-1 bytes to ensure the transfer count will not overflow regardless of the size unit selected by the driver. Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Link: https://lore.kernel.org/r/20220411153618.49876-1-aidanmacdonald.0x0@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20ARM: pxa: maybe fix gpio lookup tablesArnd Bergmann3-7/+7
From inspection I found a couple of GPIO lookups that are listed with device "gpio-pxa", but actually have a number from a different gpio controller. Try to rectify that here, with a guess of what the actual device name is. Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Cc: stable@vger.kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-04-20ARM: pxa: use pdev resource for palmld mmioArnd Bergmann4-7/+13
The palmld header is almost unused in drivers, the only remaining thing now is the PATA device address, which should really be passed as a resource. Cc: linux-ide@vger.kernel.org Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-04-20dmaengine: PTDMA: support polled modeIlya Novikov3-18/+47
If the DMA_PREP_INTERRUPT flag is not provided, run in polled mode, which significantly improves IOPS: more than twice on chunks < 4K. Signed-off-by: Ilya Novikov <i.m.novikov@yadro.com> Link: https://lore.kernel.org/r/20220413113733.59041-1-i.m.novikov@yadro.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dt-bindings: dmaengine: qcom: gpi: add compatible for sc7280Vinod Koul1-0/+1
Document the compatible for GPI DMA controller on SC7280 SoC Signed-off-by: Vinod Koul <vkoul@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220414064216.1182177-1-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dmaengine: plx_dma: Move spin_lock_bh() to spin_lock()Yunbo Yu1-2/+2
It is unnecessary to call spin_lock_bh() if you are already in a tasklet. Signed-off-by: Yunbo Yu <yuyunbo519@gmail.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com> Link: https://lore.kernel.org/r/20220418142021.1241558-1-yuyunbo519@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20dt-bindings: dmaengine: xilinx_dma: Add MCMDA channel ID index descriptionRadhey Shyam Pandey1-1/+5
MCDMA IP provides up to 16 multiple channels of data movement each on MM2S and S2MM paths. Inline with implementation, in the binding add description for the channel ID start index and mention that it's fixed irrespective of the MCDMA IP configuration(number of read/write channels). Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1649939061-6675-1-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-20Merge tag 'linux-can-next-for-5.19-20220419' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-nextDavid S. Miller30-47/+3382
Marc Kleine-Budde says: ==================== pull-request: can-next 2022-04-19 this is a pull request of 17 patches for net-next/master. The first 2 patches are by me and target the CAN driver infrastructure. One patch renames a function in the rx_offload helper the other one updates the CAN bitrate calculation to prefer small bit rate pre-scalers over larger ones, which is encouraged by the CAN in Automation. Kris Bahnsen contributes a patch to fix the links to Technologic Systems web resources in the sja1000 driver. Christophe Leroy's patch prepares the mpc5xxx_can driver for upcoming powerpc header cleanup. Minghao Chi's patch converts the flexcan driver to use pm_runtime_resume_and_get(). The next 2 patches target the Xilinx CAN driver. Lukas Bulwahn's patch fixes an entry in the MAINTAINERS file. A patch by me marks the bit timing constants as const. Wolfram Sang's patch documents r8a77961 support on the renesas,rcar-canfd bindings document. The next 2 patches are by me and add support for the mcp251863 chip to the mcp251xfd driver. The last 7 patches are by Pavel Pisa, Martin Jerabek et al. and add the ctucanfd driver for the CTU CAN FD IP Core. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2022-04-20net: stmmac: Use readl_poll_timeout_atomic() in atomic stateKevin Hao1-2/+2
The init_systime() may be invoked in atomic state. We have observed the following call trace when running "phc_ctl /dev/ptp0 set" on a Intel Agilex board. BUG: sleeping function called from invalid context at drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c:74 in_atomic(): 1, irqs_disabled(): 128, non_block: 0, pid: 381, name: phc_ctl preempt_count: 1, expected: 0 RCU nest depth: 0, expected: 0 Preemption disabled at: [<ffff80000892ef78>] stmmac_set_time+0x34/0x8c CPU: 2 PID: 381 Comm: phc_ctl Not tainted 5.18.0-rc2-next-20220414-yocto-standard+ #567 Hardware name: SoCFPGA Agilex SoCDK (DT) Call trace: dump_backtrace.part.0+0xc4/0xd0 show_stack+0x24/0x40 dump_stack_lvl+0x7c/0xa0 dump_stack+0x18/0x34 __might_resched+0x154/0x1c0 __might_sleep+0x58/0x90 init_systime+0x78/0x120 stmmac_set_time+0x64/0x8c ptp_clock_settime+0x60/0x9c pc_clock_settime+0x6c/0xc0 __arm64_sys_clock_settime+0x88/0xf0 invoke_syscall+0x5c/0x130 el0_svc_common.constprop.0+0x4c/0x100 do_el0_svc+0x7c/0xa0 el0_svc+0x58/0xcc el0t_64_sync_handler+0xa4/0x130 el0t_64_sync+0x18c/0x190 So we should use readl_poll_timeout_atomic() here instead of readl_poll_timeout(). Also adjust the delay time to 10us to fix a "__bad_udelay" build error reported by "kernel test robot <lkp@intel.com>". I have tested this on Intel Agilex and NXP S32G boards, there is no delay needed at all. So the 10us delay should be long enough for most cases. Fixes: ff8ed737860e ("net: stmmac: use readl_poll_timeout() function in init_systime()") Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-04-20Merge branch 'net-sched-flower-num-vlan-tags'David S. Miller4-31/+86
Boris Sukholitko says: ==================== net/sched: flower: match on the number of vlan tags Our customers in the fiber telecom world have network configurations where they would like to control their traffic according to the number of tags appearing in the packet. For example, TR247 GPON conformance test suite specification mostly talks about untagged, single, double tagged packets and gives lax guidelines on the vlan protocol vs. number of vlan tags. This is different from the common IT networks where 802.1Q and 802.1ad protocols are usually describe single and double tagged packet. GPON configurations that we work with have arbitrary mix the above protocols and number of vlan tags in the packet. The following patch series implement number of vlans flower filter. They add num_of_vlans flower filter as an alternative to vlan ethtype protocol matching. The end result is that the following command becomes possible: tc filter add dev eth1 ingress flower \ num_of_vlans 1 vlan_prio 5 action drop Also, from our logs, we have redirect rules such that: tc filter add dev $GPON ingress flower num_of_vlans $N \ action mirred egress redirect dev $DEV where N can range from 0 to 3 and $DEV is the function of $N. Also there are rules setting skb mark based on the number of vlans: tc filter add dev $GPON ingress flower num_of_vlans $N vlan_prio \ $P action skbedit mark $M More about the patch series: - patches 1-2 remove duplicate code by introducing is_key_vlan helper. - patch 3, 4 implement num_of_vlans in the dissector and in the flower. - patch 5 uses the num_of_vlans filter to allow further matching on vlan attributes. Complementary iproute2 patches are being sent separately. Thanks, Boris. - v4: rebased to the latest net-next - v3: - more example commands in patch 3 description (request by Jamal) - patch 5 description made clearer (thanks to Jiri) - v2: - add suitable subject prefixes - more evolved patch 5 description ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2022-04-20net/sched: flower: Consider the number of tags for vlan filtersBoris Sukholitko1-8/+16
Before this patch the existence of vlan filters was conditional on the vlan protocol being matched in the tc rule. For example, the following rule: tc filter add dev eth1 ingress flower vlan_prio 5 was illegal because vlan protocol (e.g. 802.1q) does not appear in the rule. Remove the above restriction by looking at the num_of_vlans filter to allow further matching on vlan attributes. The following rule becomes legal as a result of this commit: tc filter add dev eth1 ingress flower num_of_vlans 1 vlan_prio 5 because having num_of_vlans==1 implies that the packet is single tagged. Change is_vlan_key helper to look at the number of vlans in addition to the vlan ethertype. The outcome of this change is that outer (e.g. vlan_prio) and inner (e.g. cvlan_prio) tag vlan filters require the number of vlan tags to be greater then 0 and 1 accordingly. As a result of is_vlan_key change, the ethertype may be set to 0 when matching on the number of vlans. Update fl_set_key_vlan to avoid setting key, mask vlan_tpid for the 0 ethertype. Signed-off-by: Boris Sukholitko <boris.sukholitko@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-04-20net/sched: flower: Add number of vlan tags filterBoris Sukholitko2-0/+16
These are bookkeeping parts of the new num_of_vlans filter. Defines, dump, load and set are being done here. Signed-off-by: Boris Sukholitko <boris.sukholitko@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-04-20flow_dissector: Add number of vlan tags dissectorBoris Sukholitko2-0/+29
Our customers in the fiber telecom world have network configurations where they would like to control their traffic according to the number of tags appearing in the packet. For example, TR247 GPON conformance test suite specification mostly talks about untagged, single, double tagged packets and gives lax guidelines on the vlan protocol vs. number of vlan tags. This is different from the common IT networks where 802.1Q and 802.1ad protocols are usually describe single and double tagged packet. GPON configurations that we work with have arbitrary mix the above protocols and number of vlan tags in the packet. The goal is to make the following TC commands possible: tc filter add dev eth1 ingress flower \ num_of_vlans 1 vlan_prio 5 action drop From our logs, we have redirect rules such that: tc filter add dev $GPON ingress flower num_of_vlans $N \ action mirred egress redirect dev $DEV where N can range from 0 to 3 and $DEV is the function of $N. Also there are rules setting skb mark based on the number of vlans: tc filter add dev $GPON ingress flower num_of_vlans $N vlan_prio \ $P action skbedit mark $M This new dissector allows extracting the number of vlan tags existing in the packet. Signed-off-by: Boris Sukholitko <boris.sukholitko@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-04-20net/sched: flower: Reduce identation after is_key_vlan refactoringBoris Sukholitko1-16/+16
Whitespace only. Signed-off-by: Boris Sukholitko <boris.sukholitko@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-04-20net/sched: flower: Helper function for vlan ethtype checksBoris Sukholitko1-15/+17
There are somewhat repetitive ethertype checks in fl_set_key. Refactor them into is_vlan_key helper function. To make the changes clearer, avoid touching identation levels. This is the job for the next patch in the series. Signed-off-by: Boris Sukholitko <boris.sukholitko@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-04-20ar5523: Use kzalloc instead of kmalloc/memsetHaowen Bai1-2/+1
Use kzalloc rather than duplicating its implementation, which makes code simple and easy to understand. Signed-off-by: Haowen Bai <baihaowen@meizu.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-04-20net: dsa: realtek: remove realtek,rtl8367s stringLuiz Angelo Daros de Luca2-5/+0
There is no need to add new compatible strings for each new supported chip version. The compatible string is used only to select the subdriver (rtl8365mb.c or rtl8366rb.c). Once in the subdriver, it will detect the chip model by itself, ignoring which compatible string was used. Link: https://lore.kernel.org/netdev/20220414014055.m4wbmr7tdz6hsa3m@bang-olufsen.dk/ Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> Reviewed-by: Alvin Šipraga <alsi@bang-olufsen.dk> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Arınç ÜNAL <arinc.unal@arinc9.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-04-20dt-bindings: net: dsa: realtek: cleanup compatible stringsLuiz Angelo Daros de Luca1-21/+14
Compatible strings are used to help the driver find the chip ID/version register for each chip family. After that, the driver can setup the switch accordingly. Keep only the first supported model for each family as a compatible string and reference other chip models in the description. The removed compatible strings have never been used in a released kernel. CC: devicetree@vger.kernel.org Link: https://lore.kernel.org/netdev/20220414014055.m4wbmr7tdz6hsa3m@bang-olufsen.dk/ Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Alvin Šipraga <alsi@bang-olufsen.dk> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-04-20pinctrl: renesas: rzg2l: Restore pin config orderGeert Uytterhoeven1-1/+1
The PIN_CFG_* capabilities are always listed in the order they are defined, except in the "TMS/SWDIO" pin definition. Fix the order, to increase uniformity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/f9b18be9e5402531d058bd2479b4881377f9b8b6.1649857772.git.geert+renesas@glider.be
2022-04-20pinctrl: renesas: Remove unneeded #include <linux/init.h>Geert Uytterhoeven11-11/+0
The last __init annotations were removed from these source files almost one decade ago. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/fb71c409ea3ad76163496e305dc955ca8e84416d.1649681741.git.geert+renesas@glider.be
2022-04-20pinctrl: renesas: Select PINCTRL_RZG2L if ARCH_RZG2L is enabledLad Prabhakar1-3/+1
GPIO (PINCTRL) block is identical on Renesas RZ/G2L, RZ/G2UL and RZ/V2L SoC's, so instead of selecting PINCTRL_RZG2L config for each SoC select PINCTRL_RZG2L config option if ARCH_RZG2L is enabled. The ARCH_RZG2L config option is already selected by ARCH_R9A07G043, ARCH_R9A07G044 and ARCH_R9A07G054. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220406075318.14385-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-20pinctrl: renesas: rzg2l: Add RZ/G2UL supportBiju Das2-81/+124
RZ/G2UL SoC has fewer pins compared to RZ/G2L and the port pin definitions are different compared to RZ/G2L. This patch adds a new compatible to take care of these differences by adding r9a07g043_data with r9a07g043_gpio_configs and rzg2l_dedicated_pins.common. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220401180230.19950-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-20pinctrl: renesas: r8a77995: Add QSPI and RPC pins, groups, and functionsGeert Uytterhoeven1-0/+98
Add pins, groups, and functions for the SPI Multi I/O Bus Controller (RPC-IF) to the R8A77995 PFC driver. They are to be used when a QSPI Flash, Octal-SPI Flash, or HyperFlash is connected. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/19a3bccd0ec830846578a38b4c80dccb195109a0.1648547080.git.geert+renesas@glider.be
2022-04-20pinctrl: renesas: r8a77990: Add RPC pins, groups, and functionsGeert Uytterhoeven1-20/+61
Add pins, groups, and functions for the SPI Multi I/O Bus Controller (RPC-IF) to the R8A77990 PFC driver. They are to be used when an Octal-SPI Flash or HyperFlash is connected. Redefine the QSPI[01] pin groups using the RPC DQ[0:7] pin data, to save memory. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/ec9735bb3468225e04ac6cb95e11a0e237b2b9ed.1648547080.git.geert+renesas@glider.be