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2022-03-11Merge tag 'socfpga_dts_update_for_v5.18_part2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dtArnd Bergmann4-0/+20
SoCFPGA dts updates for v5.18, part 2 - More dt-bindings cleanup, this time, USB DWC2 properties - Add SDR EDAC dts entry for the N5X platform * tag 'socfpga_dts_update_for_v5.18_part2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: dts: n5x: add sdr edac support arm64: dts: agilex/stratix10: add clock-names to USB DWC2 node dt-bindings: usb: dwc2: add disable-over-current dt-bindings: usb: dwc2: add iommus dt-bindings: usb: dwc2: fix compatible of Intel Agilex Link: https://lore.kernel.org/r/20220310195740.151250-1-dinguyen@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-03-11Merge tag 'arm64_defconfig_for_v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/defconfigArnd Bergmann1-0/+1
ARM64 defconfig for v5.18 - Enable the Altera FPGA Manager CVP driver * tag 'arm64_defconfig_for_v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: defconfig: enable the CVP driver Link: https://lore.kernel.org/r/20220310195740.151250-2-dinguyen@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-03-11um: run_helper: Write error message to kernel log on exec failure on hostGlenn Washburn1-0/+5
The best place to log errors from the host side is in the kernel log within the UML guest. Letting the user now that exec() failed and why is very helpful when the user is trying to determine why some aspect of UML is not working. For instance, when telneting into the UML instance, if the connection is established and then immediately dropped, this may be due to exec() failing because in.telnetd is not found. Signed-off-by: Glenn Washburn <development@efficientek.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2022-03-11um: port_user: Improve error handling when port-helper is not foundGlenn Washburn1-0/+12
Check if port-helper exists and is executable. If not, write an error message to the kernel log with information to help the user diagnose the issue and exit with an error. If UML_PORT_HELPER was not set, write a message suggesting that the user set it. This makes it easier to understand why telneting to the UML instance is failing and what can be done to fix it. Signed-off-by: Glenn Washburn <development@efficientek.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2022-03-11um: port_user: Allow setting path to port-helper using UML_PORT_HELPER envvarGlenn Washburn1-0/+4
This is useful when the uml-utilities user-space package has not been installed by the administrator and an unprivileged user wants to be able to telnet into a UML instance. The user can install the port-helper binary to a writable path and set UML_PORT_HELPER. Fallback to using hardcoded path to port-helper if environment variable is not set. Signed-off-by: Glenn Washburn <development@efficientek.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2022-03-11um: port_user: Search for in.telnetd in PATHGlenn Washburn1-1/+1
This allows in.telnetd to be run from non-standard installation locations and is especially useful when running a UML instance as an unprivileged user on a system where the administrator has not installed the in.telnetd binary. Signed-off-by: Glenn Washburn <development@efficientek.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2022-03-11dmaengine: idxd: Remove useless DMA-32 fallback configurationChristophe JAILLET1-2/+0
As stated in [1], dma_set_mask() with a 64-bit mask never fails if dev->dma_mask is non-NULL. So, if it fails, the 32 bits case will also fail for the same reason. Simplify code and remove some dead code accordingly. [1]: https://lore.kernel.org/linux-kernel/YL3vSPK5DXTNvgdx@infradead.org/#t Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/009c80294dba72858cd8a6ed2ed81041df1b1e82.1642231430.git.christophe.jaillet@wanadoo.fr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-03-11dmaengine: qcom_hidma: Remove useless DMA-32 fallback configurationChristophe JAILLET1-3/+1
As stated in [1], dma_set_mask() with a 64-bit mask never fails if dev->dma_mask is non-NULL. So, if it fails, the 32 bits case will also fail for the same reason. Simplify code and remove some dead code accordingly. [1]: https://lore.kernel.org/linux-kernel/YL3vSPK5DXTNvgdx@infradead.org/#t Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/4deb32b0c7838da66608022c584326eb01d0da03.1642232106.git.christophe.jaillet@wanadoo.fr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-03-11um: clang: Strip out -mno-global-merge from USER_CFLAGSDavid Gow1-0/+4
The things built with USER_CFLAGS don't seem to recognise it as a compiler option, and print a warning: clang: warning: argument unused during compilation: '-mno-global-merge' [-Wunused-command-line-argument] Fixes: 744814d2fa ("um: Allow builds with Clang") Signed-off-by: David Gow <davidgow@google.com> Reviewed-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Richard Weinberger <richard@nod.at>
2022-03-11docs: UML: Mention telnetd for port channelVincent Whitchurch1-1/+5
It is not obvious from the documentation that using the "port" channel for the console requires telnetd to be installed (see port_connection() in arch/um/drivers/port_user.c). Mention this, and the fact that UML will not boot until a client connects. Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> Acked-by: Anton Ivanov <anton.ivanov@cambridgegreys.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2022-03-11um: Remove unused timeval_to_ns() functionDavid Gow1-6/+0
The timeval_to_ns() function doesn't appear to be used anywhere, as far as I (or git grep) can tell, and clang throws up a warning about it: ../arch/um/os-Linux/time.c:21:25: warning: unused function 'timeval_to_ns' [-Wunused-function] static inline long long timeval_to_ns(const struct timeval *tv) ^ 1 warning generated. Signed-off-by: David Gow <davidgow@google.com> Acked-By: Anton Ivanov <anton.ivanov@cambridgegreys.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2022-03-11um: Fix uml_mconsole stop/goAnton Ivanov1-1/+2
Moving to an EPOLL based IRQ controller broke uml_mconsole stop/go commands. This fixes it and restores stop/go functionality. Fixes: ff6a17989c08 ("Epoll based IRQ controller") Signed-off-by: Anton Ivanov <anton.ivanov@cambridgegreys.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2022-03-11um: Cleanup syscall_handler_t definition/cast, fix warningDavid Gow1-3/+2
The syscall_handler_t type for x86_64 was defined as 'long (*)(void)', but always cast to 'long (*)(long, long, long, long, long, long)' before use. This now triggers a warning (see below). Define syscall_handler_t as the latter instead, and remove the cast. This simplifies the code, and fixes the warning. Warning: In file included from ../arch/um/include/asm/processor-generic.h:13 from ../arch/x86/um/asm/processor.h:41 from ../include/linux/rcupdate.h:30 from ../include/linux/rculist.h:11 from ../include/linux/pid.h:5 from ../include/linux/sched.h:14 from ../include/linux/ptrace.h:6 from ../arch/um/kernel/skas/syscall.c:7: ../arch/um/kernel/skas/syscall.c: In function ‘handle_syscall’: ../arch/x86/um/shared/sysdep/syscalls_64.h:18:11: warning: cast between incompatible function types from ‘long int (*)(void)’ to ‘long int (*)(long int, long int, long int, long int, long int, long int)’ [ -Wcast-function-type] 18 | (((long (*)(long, long, long, long, long, long)) \ | ^ ../arch/x86/um/asm/ptrace.h:36:62: note: in definition of macro ‘PT_REGS_SET_SYSCALL_RETURN’ 36 | #define PT_REGS_SET_SYSCALL_RETURN(r, res) (PT_REGS_AX(r) = (res)) | ^~~ ../arch/um/kernel/skas/syscall.c:46:33: note: in expansion of macro ‘EXECUTE_SYSCALL’ 46 | EXECUTE_SYSCALL(syscall, regs)); | ^~~~~~~~~~~~~~~ Signed-off-by: David Gow <davidgow@google.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2022-03-11uml: net: vector: fix const issueJohannes Berg2-2/+2
Since the constification of MAC addresses, the argument to uml_vector_default_bpf() must be const. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Acked-By: anton ivanov <anton.ivanov@cambridgegreys.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2022-03-11um: Fix WRITE_ZEROES in the UBD DriverFrédéric Danis3-1/+17
Call to fallocate with FALLOC_FL_PUNCH_HOLE on a device backed by a sparse file can end up by missing data, zeroes data range, if the underlying file is used with a tool like bmaptool which will referenced only used spaces. Signed-off-by: Frédéric Danis <frederic.danis@collabora.com> Acked-by: Anton Ivanov <anton.ivanov@cambridgegreys.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2022-03-11um: Migrate vector drivers to NAPIAnton Ivanov2-57/+51
Migrate UML vector drivers from a bespoke scheduling mechanism to NAPI. Signed-off-by: Anton Ivanov <anton.ivanov@cambridgegreys.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2022-03-11um: Fix order of dtb unflatten/early initVincent Whitchurch1-1/+1
Scan the tree for reserved memory before unflattening it. As Rob Herring said: | These should be reversed. early_init_fdt_scan_reserved_mem() works on | the flat tree. Reserved memory needs to be reserved before | unflatten_device_tree() starts allocating memory. Though I imagine that | doesn't really matter for UML. Suggested-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/lkml/YeF%2FVbxo6fAt0WLp@robh.at.kernel.org/ Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2022-03-11um: fix and optimize xor select template for CONFIG64 and timetravel modeBenjamin Beichler1-1/+3
Due to dropped inclusion of asm-generic/xor.h, xor_block_8regs symbol is missing with CONFIG64 and break compilation, as the asm/xor_64.h also did not include it. The patch recreate the logic from arch/x86, which check whether AVX is available and add fallbacks for 32bit and 64bit config of um. A very minor additional "fix" is, the return of the macro parameter instead of NULL, as this is the original intent of the macro, but this does not change the actual behavior. Fixes: c0ecca6604b8 ("um: enable the use of optimized xor routines in UML") Signed-off-by: Benjamin Beichler <benjamin.beichler@uni-rostock.de> Acked-By: Anton Ivanov <anton.ivanov@cambridgegreys.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2022-03-11um: Document dtb command line optionAnton Ivanov1-0/+20
Add documentation for the dtb command line option and the ability to load/parse device trees. Signed-off-by: Anton Ivanov <anton.ivanov@cambridgegreys.com> Reviewed-by: Vincent Whitchurch <vincent.whitchurch@axis.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2022-03-11lib/logic_iomem: correct fallback config referencesJohannes Berg1-4/+4
Due to some renaming, we ended up with the "indirect iomem" naming in Kconfig, following INDIRECT_PIO. However, clearly I missed following through on that in the ifdefs, but so far INDIRECT_IOMEM_FALLBACK isn't used by any architecture. Reported-by: Lukas Bulwahn <lukas.bulwahn@gmail.com> Fixes: ca2e334232b6 ("lib: add iomem emulation (logic_iomem)") Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2022-03-11um: Remove duplicated include in syscalls_64.cYang Li1-1/+0
Fix following includecheck warning: ./arch/x86/um/syscalls_64.c: registers.h is included more than once. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Fixes: dbba7f704aa0 ("um: stop polluting the namespace with registers.h contents") Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2022-03-11MAINTAINERS: Update UserModeLinux entryRichard Weinberger1-2/+3
Add Johannes and form a maintainer group with on a common git repository. While we are here, remove inactive developers. Jeff, thanks for your great work! Signed-off-by: Richard Weinberger <richard@nod.at>
2022-03-11Merge branch irq/aic-v2 into irq/irqchip-nextMarc Zyngier4-90/+475
* irq/aic-v2: : . : Add support for the interrupt controller found is the latest : incarnation of Apple M1 systems, courtesy of Hector Martin. : . irqchip/apple-aic: Add support for AICv2 irqchip/apple-aic: Support multiple dies irqchip/apple-aic: Dynamically compute register offsets irqchip/apple-aic: Switch to irq_domain_create_tree and sparse hwirqs irqchip/apple-aic: Add Fast IPI support dt-bindings: interrupt-controller: apple,aic2: New binding for AICv2 PCI: apple: Change MSI handling to handle 4-cell AIC fwspec form Signed-off-by: Marc Zyngier <maz@kernel.org>
2022-03-11irqchip/apple-aic: Add support for AICv2Hector Martin1-33/+148
Introduce support for the new AICv2 hardware block in t6000/t6001 SoCs. It seems these blocks are missing the information required to compute the event register offset in the capability registers, so we specify that in the DT as a second reg entry. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220309192123.152028-8-marcan@marcan.st
2022-03-11irqchip/apple-aic: Support multiple diesHector Martin1-23/+54
Multi-die support in AICv2 uses several sets of IRQ registers. Introduce a die count and compute the register group offset based on the die ID field of the hwirq number, as reported by the hardware. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220309192123.152028-7-marcan@marcan.st
2022-03-11irqchip/apple-aic: Dynamically compute register offsetsHector Martin1-17/+55
This allows us to support AIC variants with different numbers of IRQs based on capability registers. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220309192123.152028-6-marcan@marcan.st
2022-03-11irqchip/apple-aic: Switch to irq_domain_create_tree and sparse hwirqsHector Martin1-32/+39
This allows us to directly use the hardware event number as the hwirq number. Since IRQ events have bit 16 set (type=1), FIQs now move to starting at hwirq number 0. This will become more important once multi-die support is introduced in a later commit. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220309192123.152028-5-marcan@marcan.st
2022-03-11irqchip/apple-aic: Add Fast IPI supportHector Martin1-13/+109
The newer AICv2 present in t600x SoCs does not have legacy IPI support at all. Since t8103 also supports Fast IPIs, implement support for this first. The legacy IPI code is left as a fallback, so it can be potentially used by older SoCs in the future. The vIPI code is shared; only the IPI firing/acking bits change for Fast IPIs. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220309192123.152028-4-marcan@marcan.st
2022-03-11dt-bindings: interrupt-controller: apple,aic2: New binding for AICv2Hector Martin2-1/+99
This new incompatible revision of the AIC peripheral introduces multi-die support. This binding is based on apple,aic, but changes interrupt-cells to add a new die argument. Also adds a second reg entry to specify the offset of the event register. Inexplicably, the capability registers allow us to compute other register offsets, but not this one. This allows us to keep forward-compatibility with future SoCs that will likely implement different die counts, thus shifting the event register. Apple also specify the offset explicitly in their device tree... Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220309192123.152028-3-marcan@marcan.st
2022-03-10net/mlx5e: Remove overzealous validations in netlink EEPROM queryGal Pressman1-23/+0
Unlike the legacy EEPROM callbacks, when using the netlink EEPROM query (get_module_eeprom_by_page) the driver should not try to validate the query parameters, but just perform the read requested by the userspace. Recent discussion in the mailing list: https://lore.kernel.org/netdev/20220120093051.70845141@kicinski-fedora-PC1C0HJN.hsd1.ca.comcast.net/ Signed-off-by: Gal Pressman <gal@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Maxim Mikityanskiy <maximmi@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-03-10net/mlx5: Parse module mapping using mlx5_ifcGal Pressman3-8/+7
The assumption that the first byte in the module mapping dword is the module number shouldn't be hard-coded in the driver, but come from mlx5_ifc structs. While at it, fix the incorrect width for the 'rx_lane' and 'tx_lane' fields. Signed-off-by: Gal Pressman <gal@nvidia.com> Reviewed-by: Maxim Mikityanskiy <maximmi@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-03-10net/mlx5: Query the maximum MCIA register read size from firmwareGal Pressman3-3/+10
The MCIA register supports either 12 or 32 dwords, use the correct value by querying the capability from the MCAM register. Signed-off-by: Gal Pressman <gal@nvidia.com> Reviewed-by: Maxim Mikityanskiy <maximmi@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-03-10net/mlx5: CT: Create smfs dr matchers dynamicallyPaul Blakey1-86/+92
SMFS dr matchers are processed sequentially in hardware according to their priorities, and not skipped if empty. Currently, smfs ct fs creates four predefined dr matchers per ct table (ct/ct nat) with hardcoded priority. Compared to dmfs ct fs using autogroups, this might cause additional hops in fastpath for traffic patterns that match later priorties, even if previous priorites are empty, e.g user only using ipv6 UDP traffic will have additional 3 hops. Create the matchers dynamically, using the highest priority available, on first rule usage, and remove them on last usage. Signed-off-by: Paul Blakey <paulb@nvidia.com> Reviewed-by: Oz Shlomo <ozsh@nvidia.com> Reviewed-by: Roi Dayan <roid@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-03-10net/mlx5: CT: Add software steering ct flow steering providerPaul Blakey6-7/+435
fs_core layer adds extra book keeping that is either unneeded for CT, or unused by the underlying software steering, such as allocating FTEs and FTE ids, saving the match key and mask, and autogroups management. On top of that, direct steering has a translation layer (fs_dr) from PRM commands to direct steering objects, for example, creating temporary dr_action objects. This has a performance impact when dealing with CT high insertion rate. To use direct steering (smfs) directly for ct, add a tc ct fs smfs implementation. Instead of dmfs autogroups, smfs ct fs uses one of 4 predefined dr matchers in CT and CT-NAT tables, for each combination of tuple ethertype (ipv4/ipv6), and tuple ip_proto (udp/tcp) that is currently used by nf flow table flow offload. At rule insertions, validate the flow rule fits one of the predfined matcher, and insert to it. To fill the dr_actions of the rule efficiently, create the fwd to post_ct tbl dr_action at fs init, the count dr_action at counter creation, and re-use the already pre-allocated modify header dr_action. Signed-off-by: Paul Blakey <paulb@nvidia.com> Reviewed-by: Oz Shlomo <ozsh@nvidia.com> Reviewed-by: Roi Dayan <roid@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-03-10net/mlx5: Add smfs lib to export direct steering API to CTPaul Blakey3-1/+105
Add a thin layer that exports selected direct steering (dr) API which will be used by a ct fs implementation in a following patch. Signed-off-by: Paul Blakey <paulb@nvidia.com> Reviewed-by: Mark Bloch <mbloch@nvidia.com> Reviewed-by: Roi Dayan <roid@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-03-10net/mlx5: DR, Add helper to get backing dr table from a mlx5 flow tablePaul Blakey2-0/+8
If sw steering was used to create the table, dr steeering fs creates a backing dr table for the mlx5 flow table. Add helper to return this table so it can be used to create matchers and add rules on it directly instead of passing via eswitch_offloads/fs_core insertion. Signed-off-by: Paul Blakey <paulb@nvidia.com> Reviewed-by: Oz Shlomo <ozsh@nvidia.com> Reviewed-by: Roi Dayan <roid@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-03-10net/mlx5: CT: Introduce a platform for multiple flow steering providersPaul Blakey4-4/+119
Currently, fs_core layer provides flow steering services to the driver including: autogroups, allocating FTEs (flow table entries) and FTE ids, and support of fte action modification. If then software steering is configured, rule insertion will go through a translation layer from firmware buffers to software steering objects (see fs_dr.c). The connection tracking table is a system table that is not directly controlled by the user and is a very high scale table. These fs_core services introduces an overhead that may be optimized by using software steering API directly. Introduce ct flow steering interface to allow multiple flow steering providers. Use the new interface to implement the current dmfs (device managed flow steering) provider which uses fs_core insertion. Signed-off-by: Paul Blakey <paulb@nvidia.com> Reviewed-by: Oz Shlomo <ozsh@nvidia.com> Reviewed-by: Roi Dayan <roid@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-03-10net/mlx5: Node-aware allocation for the doorbell pgdirTariq Toukan1-2/+2
The function is node-aware and gets the node as an argument. Use a node-aware allocation for the doorbell pgdir structure. Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Reviewed-by: Moshe Shemesh <moshe@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-03-10net/mlx5: Node-aware allocation for UARTariq Toukan1-3/+5
Prefer the aware allocation, use the device NUMA node. Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Reviewed-by: Moshe Shemesh <moshe@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-03-10net/mlx5: Node-aware allocation for the EQsTariq Toukan1-2/+4
Prefer the aware allocation, use the device NUMA node. Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Reviewed-by: Moshe Shemesh <moshe@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-03-10net/mlx5: Node-aware allocation for the EQ tableTariq Toukan1-1/+2
Prefer the aware allocation, use the device NUMA node. Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Reviewed-by: Moshe Shemesh <moshe@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-03-10net/mlx5: Node-aware allocation for the IRQ tableTariq Toukan1-1/+2
Prefer the aware allocation, use the device NUMA node. Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Reviewed-by: Moshe Shemesh <moshe@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-03-10net/mlx5: Delete useless module.h includeLeon Romanovsky18-18/+0
There is no need in include of module.h in the following files. Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-03-10net/mlx4: Delete useless moduleparam includeLeon Romanovsky1-1/+0
Remove inclusion of not used moduleparam.h. Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2022-03-11video: fbdev: kyro: make read-only array ODValues static constColin Ian King1-1/+1
Don't populate the read-only array ODValues on the stack but instead make it static const. Also makes the object code a little smaller. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Signed-off-by: Helge Deller <deller@gmx.de>
2022-03-11video: fbdev: offb: fix warning comparing pointer to 0Haowen Bai1-1/+1
Fix the following coccicheck warning: drivers/video/fbdev/offb.c:415:13-14: WARNING comparing pointer to 0 Signed-off-by: Haowen Bai <baihaowen@meizu.com> Signed-off-by: Helge Deller <deller@gmx.de>
2022-03-11dmaengine: sh: Kconfig: Add ARCH_R9A07G054 dependency for RZ_DMAC config optionLad Prabhakar1-3/+3
RZ/V2L DMA block is identical to one found on RZ/G2L SoC. This patch adds ARCH_R9A07G054 dependency for RZ_DMAC config option so that the driver can be enabled on RZ/V2L SoC. While at it, also update config help text. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20220221224321.11939-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-03-11dmaengine: ti: k3-psil: Add AM62x PSIL and PDMA dataVignesh Raghavendra4-1/+190
Add PSIL EP data and PDMA data for AM62x. [p.yadav@ti.com: Add CSIRX data] Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com> Link: https://lore.kernel.org/r/20220219083220.489420-3-vigneshr@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-03-11dmaengine: ti: k3-udma: Add AM62x DMSS supportVignesh Raghavendra1-0/+1
Attribute AM64x soc data to AM62x as well as the DMSS IP is similar b/w these two SoCs Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com> Link: https://lore.kernel.org/r/20220219083220.489420-2-vigneshr@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-03-11dmaengine: ti: cleanup commentsTom Rix3-9/+9
Remove the second 'the' Replacements completetion to completion seens to seen pendling to pending atleast to at least tranfer to transfer multibple to a multiple transfering to transferring Signed-off-by: Tom Rix <trix@redhat.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Link: https://lore.kernel.org/r/20220217182546.3266909-1-trix@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>