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2022-03-07ASoC: fsl_sai: Use better variable namesSascha Hauer1-8/+9
"ret" is normally used as a variable name for return values. In fsl_sai_set_bclk() it stores the difference between the desired rate and the rate we can archieve, so rename it to "diff". Also rename "savesub" to "bestdiff" as that stores the best difference we have found. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20220302083428.3804687-6-s.hauer@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: fsl_sai: store full version instead of major/minorSascha Hauer2-9/+5
The driver tests for the hardware revision being newer than 3.1 with (sai->verid.major >= 3 && sai->verid.minor >= 1). The result is obviously wrong for hardware revision 4.0. Fix this by storing the full version in a single variable and comparing to that one. No practical change at the moment as there is no 4.0 ip version currently. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20220302083428.3804687-5-s.hauer@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: fsl_sai: simplify register poking in fsl_sai_set_bclkAhmad Fatoum1-16/+13
Depending on SAI synchronization mode, the same value is either written to FSL_SAI_TCR2 or FSL_SAI_RCR2 or nothing is written at all. As the computation is the same either way, factor it out to make it clearer what the difference is. No functional change. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20220302083428.3804687-4-s.hauer@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: fsl_sai: simplify irq return valueSascha Hauer1-7/+4
Instead of using a boolean "irq_none" to describe the interrupt handlers return value use a variable of type irqreturn_t and return it directly. No functional change. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20220302083428.3804687-3-s.hauer@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: fsl_sai: Drop unnecessary definesSascha Hauer2-13/+6
The fsl_sai driver has FSL_FMT_TRANSMITTER and FSL_FMT_RECEIVER defines which are used in a single function only then are then only translated into a bool 'tx' variable. Drop the defines and pass the boolean value directly to fsl_sai_set_dai_sysclk_tr(). No functional change. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20220302083428.3804687-2-s.hauer@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: codecs: Add Awinic AW8738 audio amplifier driverJonathan Albrieux3-0/+116
The Awinic AW8738 is a simple audio amplifier using a single GPIO. The main difference to simple-amplifier is that there is a "one-wire pulse control" that allows configuring the amplifier to one of a few pre-defined modes. This can be used to configure the speaker-guard function (primarily the power limit for the amplifier). Add a simple driver that allows setting it up in the device tree with a specified mode number. Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com> Co-developed-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20220304102452.26856-3-stephan@gerhold.net Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: dt-bindings: Add schema for "awinic,aw8738"Stephan Gerhold1-0/+54
Add a DT schema for describing Awinic AW8738 audio amplifiers. They are fairly simple and controlled using a single GPIO. The number of pulses during power up selects one of a few pre-defined operation modes. This can be used to configure the speaker-guard function (primarily the power limit for the amplifier). Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20220304102452.26856-2-stephan@gerhold.net Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: audio_graph_card2: Add support for variable slot widthsRichard Fitzgerald3-0/+112
Some audio hardware cannot support the same slot width for all sample widths, or a slot width equal to the sample width for all sample widths. This is usually due either to limitations of the audio serial port or system clocking restrictions. A typical example would be: - 16-bit samples in 16-bit slots - 24-bit samples in 32-bit slots The new dai-tdm-slot-width-map property allows setting a mapping of sample widths and the corresponding tdm slot widths and slot counts. Although the slot count is usually the same for all cases this does allow for adding padding slots to maintain the same bitclk frequency. The property is added to each endpoint node that needs the component DAI to be told the TDM slot width and count. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> Link: https://lore.kernel.org/r/20220228172754.453783-3-rf@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: dt-bindings: audio-graph-port: Add dai-tdm-slot-width-mapRichard Fitzgerald1-0/+20
Some audio hardware cannot support a fixed slot width for all sample widths, or a slot width equal to the sample width for all sample widths. This is usually due either to limitations of the audio serial port or system clocking restrictions. This property allows setting a mapping of sample widths and the corresponding tdm slot widths. The slot count is also provided for each slot width - although this would almost always be the same for all slot widths this allows for possibly adding extra padding slots to maintain a fixed bitclock frequency. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> Link: https://lore.kernel.org/r/20220228172754.453783-2-rf@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: SOF: Intel: hda: clarify operator precedencePierre-Louis Bossart1-1/+1
cppcheck warning sound/soc/sof/intel/hda.c:545:46: style: Clarify calculation precedence for '&' and '?'. [clarifyCalculation] char *level = flags & SOF_DBG_DUMP_OPTIONAL ? KERN_DEBUG : KERN_ERR; Reviewed-by: Ranjani Sridharan <ranjani.sridharan@intel.com> Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20220304205733.62233-11-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: SOF: debug: clarify operator precedencePierre-Louis Bossart1-1/+1
cppcheck warning: for '&' and '?'. [clarifyCalculation] char *level = flags & SOF_DBG_DUMP_OPTIONAL ? KERN_DEBUG : KERN_ERR; ^ sound/soc/sof/debug.c:398:46: style: Clarify calculation precedence Reviewed-by: Ranjani Sridharan <ranjani.sridharan@intel.com> Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20220304205733.62233-10-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: SOF: fix 32 signed bit overflowCurtis Malainey2-2/+2
Shifting in a signed 32bit container past the signed bit is technically undefined behaviour. Fix by using unsigned types. Found via cppcheck. Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Reviewed-by: Liam Girdwood <liam.r.girdwood@intel.com> Signed-off-by: Curtis Malainey <cujomalainey@chromium.org> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20220304205733.62233-9-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: SOF: amd: Increase ACP_HW_SEM_RETRY_COUNT valueAjit Kumar Pandey1-1/+1
Host is trying to acquire semaphore lock based on HW_SEM_RETRY_COUNT value which is set to 10 by default. So host will loop for 10 times trying to acquire lock before giving error msg "Failed to acquire HW lock". Though this loop count of 10 is good enough with most of the times but we have observed such failure msg in very few cases(~5 %). Increase ACP_HW_SEM_RETRY_COUNT to avoid such issue and loop for a significant time period before throwing error. We're setting newer loop count to quite higher value of 10K but it's very unlikely that it will loop for this count, since for most of the cases lock will get acquired at much lesser loop iterations. Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20220304205733.62233-8-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: SOF: amd: Move group register configuration to acp-loaderAjit Kumar Pandey2-14/+9
We are using PTE_GRP1 for DMA operations to load firmware binaries but we are enabling PTE_GRP and flushing ATU cache much before in probe callbacks. This can cause issue if we try to load firmware runtime during system resume as probe callback will not be invoked hence PTE_GRP will not be enabled. Moreover it makes more sense to flush the cache after register configuration. Move PTE group register configuration to acp-loader within pre_fw_run callback to avoid such issue. Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20220304205733.62233-7-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: SOF: amd: Use semaphore register to synchronize ipc's irqAjit Kumar Pandey4-1/+30
Add lock and unlock around ipc irq handling code using hw semaphore register that exhibit special property for register read calls. As host and DSP firmware uses few shared registers, there is a possible race condition around those shared registers values. This lock ensure synchronization between Firmware and host ipc interrupts. Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20220304205733.62233-6-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: SOF: amd: Flush cache after ATU_BASE_ADDR_GRP register updateAjit Kumar Pandey1-0/+3
ACP_SRAM_PTE block has cache that needs to be flushed after every PTE updates. This patch updates ACPAXI2AXI_ATU_CTRL register to flush cache after updating PTE with stream physical address. Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20220304205733.62233-5-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: SOF: amd: Do not set ipc_pcm_params ops as it is optionalPeter Ujfalusi3-11/+0
The ipc_pcm_params() ops implementation for AMD is a NOP and since the callback is marked now as optional, it can be dropped along with the empty function. Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Reviewed-by: Rander Wang <rander.wang@intel.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20220304205733.62233-4-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: SOF: amd: acp-pcm: Take buffer information directly from runtimePeter Ujfalusi1-3/+4
Instead of using the values from ipc_params, take them directly from substream->runtime. This is in preparation of making the platform hw_params callback to be IPC agnostic. Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Reviewed-by: Rander Wang <rander.wang@intel.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20220304205733.62233-3-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: SOF: Intel: pci-tgl: add RPL-S supportGongjun Song1-0/+2
Add PCI DID for Intel Raptor Lake S. Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com> Signed-off-by: Gongjun Song <gongjun.song@intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20220304205733.62233-2-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: cs35l41: Fix DSP mbox start command and global enable orderLucas Tanure1-2/+2
Global enable must happen before CSPL_MBOX_CMD_RESUME command is sent. Move it to PRE_PMU as both events use SND_SOC_DAPM_OUT_DRV_E macro. Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20220303173059.269657-4-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: cs35l41: Fix max number of TX channelsLucas Tanure1-1/+1
This device only has 4 TX channels. Fixes: fe1024d50477b ("ASoC: cs35l41: Combine adjacent register writes") Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20220303173059.269657-3-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: cs35l41: Fix GPIO2 configurationDavid Rhodes1-2/+2
Fix GPIO2 polarity and direction configuration Fixes: fe1024d50477b ("ASoC: cs35l41: Combine adjacent register writes") Signed-off-by: David Rhodes <drhodes@opensource.cirrus.com> Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20220303173059.269657-2-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-08powerpc/kexec: Declare kexec_paca staticChristophe Leroy2-3/+1
kexec_paca is exclusively used in kexec/core_64.c Declare it static. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/094983ee851644165b7700c73cac63cfe20596cd.1646413435.git.christophe.leroy@csgroup.eu
2022-03-08powerpc/smp: Declare current_set staticChristophe Leroy2-2/+1
current_set extern not needed anymore since commit eafd825ed710 ("powerpc/64: Simplify __secondary_start paca->kstack handling") Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/a55eb65c9d7319f0af3c31e3f6ba36522f10003d.1646413435.git.christophe.leroy@csgroup.eu
2022-03-08powerpc: Cleanup asm-prototypes.cChristophe Leroy1-6/+0
Last call to sys_swapcontext() from ASM was removed by commit fbcee2ebe8ed ("powerpc/32: Always save non volatile GPRs at syscall entry") sys_debug_setcontext() prototype not needed anymore since commit f3675644e172 ("powerpc/syscalls: signal_{32, 64} - switch to SYSCALL_DEFINE") sys_switch_endian() prototype not needed anymore since commit 81dac8177862 ("powerpc/64: Make sys_switch_endian() traceable") Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> [mpe: Keep _mcount() prototype to avoid modpost errors] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/3ed660a585df2080ea8412ec20fbf652f5bf013a.1646413435.git.christophe.leroy@csgroup.eu
2022-03-08powerpc/ftrace: Use STK_GOT in ftrace_mprofile.SChristophe Leroy1-2/+2
Instead of open coding offset value 24, use STK_GOT when accessing got register in stack. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/9042bb30fa972056715fe5b6598a7c8049681293.1645099283.git.christophe.leroy@csgroup.eu
2022-03-08powerpc/ftrace: Regroup PPC64 specific operations in ftrace_mprofile.SChristophe Leroy1-5/+2
CONFIG_MPROFILE_KERNEL is only for PPC64 and ftrace_mprofile.o is build on PPC64 only when CONFIG_MPROFILE_KERNEL is defined. Move saving of r0 inside #ifdef PPC64 Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/619dfb672bf4f1b777a4b3f8b4f14e637fea2716.1645099283.git.christophe.leroy@csgroup.eu
2022-03-08powerpc/ftrace: Refactor ftrace_{regs_}callerChristophe Leroy1-102/+45
ftrace_caller() and frace_regs_caller() have now a lot in common. Refactor them using GAS macros. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Reviewed-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/9d7df9e4fc98a86051489f61d3c9bc67f92f7e27.1645099283.git.christophe.leroy@csgroup.eu
2022-03-08powerpc/ftrace: Don't use lmw/stmw in ftrace_regs_caller()Christophe Leroy1-8/+2
For the same reason as commit a85c728cb5e1 ("powerpc/32: Don't use lmw/stmw for saving/restoring non volatile regs"), don't use lmw/stmw in ftrace_regs_caller(). Use the same macros for PPC32 and PPC64. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/ec286d2cc6989668a96f14543275437d2f3f0e3a.1645099283.git.christophe.leroy@csgroup.eu
2022-03-08selftest/powerpc: Add PAPR sysfs attributes sniff testPratik R. Sampat4-0/+117
Include a testcase to check if the sysfs files for energy and frequency related have its related attribute files exist and populated Signed-off-by: Pratik R. Sampat <psampat@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220217105321.52941-3-psampat@linux.ibm.com
2022-03-08powerpc/pseries: Interface to represent PAPR firmware attributesPratik R. Sampat7-3/+399
Adds a syscall interface to represent the energy and frequency related PAPR attributes on the system using the new H_CALL "H_GET_ENERGY_SCALE_INFO". H_GET_EM_PARMS H_CALL was previously responsible for exporting this information in the lparcfg, however the H_GET_EM_PARMS H_CALL will be deprecated P10 onwards. The H_GET_ENERGY_SCALE_INFO H_CALL is of the following call format: hcall( uint64 H_GET_ENERGY_SCALE_INFO, // Get energy scale info uint64 flags, // Per the flag request uint64 firstAttributeId,// The attribute id uint64 bufferAddress, // Guest physical address of the output buffer uint64 bufferSize // The size in bytes of the output buffer ); As specified in PAPR+ v2.11, section 14.14.3. This H_CALL can query either all the attributes at once with firstAttributeId = 0, flags = 0 as well as query only one attribute at a time with firstAttributeId = id, flags = 1. The output buffer consists of the following 1. number of attributes - 8 bytes 2. array offset to the data location - 8 bytes 3. version info - 1 byte 4. A data array of size num attributes, which contains the following: a. attribute ID - 8 bytes b. attribute value in number - 8 bytes c. attribute name in string - 64 bytes d. attribute value in string - 64 bytes The new H_CALL exports information in direct string value format, hence a new interface has been introduced in /sys/firmware/papr/energy_scale_info to export this information to userspace so that the firmware can add new values without the need for the kernel to be changed. The H_CALL returns the name, numeric value and string value (if exists) The format of exposing the sysfs information is as follows: /sys/firmware/papr/energy_scale_info/ |-- <id>/ |-- desc |-- value |-- value_desc (if exists) |-- <id>/ |-- desc |-- value |-- value_desc (if exists) ... The energy information that is exported is useful for userspace tools such as powerpc-utils. Currently these tools infer the "power_mode_data" value in the lparcfg, which in turn is obtained from the to be deprecated H_GET_EM_PARMS H_CALL. On future platforms, such userspace utilities will have to look at the data returned from the new H_CALL being populated in this new sysfs interface and report this information directly without the need of interpretation. Signed-off-by: Pratik R. Sampat <psampat@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220217105321.52941-2-psampat@linux.ibm.com
2022-03-08powerpc/mce: Avoid using irq_work_queue() in realmodeGanesh Goudar8-59/+53
In realmode mce handler we use irq_work_queue() to defer the processing of mce events, irq_work_queue() can only be called when translation is enabled because it touches memory outside RMA, hence we enable translation before calling irq_work_queue and disable on return, though it is not safe to do in realmode. To avoid this, program the decrementer and call the event processing functions from timer handler. Signed-off-by: Ganesh Goudar <ganeshgr@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220120121931.517974-1-ganeshgr@linux.ibm.com
2022-03-08powerpc/mce: Modify the real address error logging messagesGanesh Goudar1-4/+4
To avoid ambiguity, modify the strings in real address error logging messages to "foreign/control memory" from "foreign", Since the error discriptions in P9 user manual and P10 user manual are different for same type of errors. P9 User Manual for MCE: DSISR:59 Host real address to foreign space during translation. DSISR:60 Host real address to foreign space on a load or store access. P10 User Manual for MCE: DSISR:59 D-side tablewalk used a host real address in the control memory address range. DSISR:60 D-side operand access to control memory address space. Signed-off-by: Ganesh Goudar <ganeshgr@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220107141428.67862-3-ganeshgr@linux.ibm.com
2022-03-08selftests/powerpc: Add test for real address error handlingGanesh Goudar4-1/+75
Add test for real address or control memory address access error handling, using NX-GZIP engine. The error is injected by accessing the control memory address using illegal instruction, on successful handling the process attempting to access control memory address using illegal instruction receives SIGBUS. Signed-off-by: Ganesh Goudar <ganeshgr@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220107141428.67862-2-ganeshgr@linux.ibm.com
2022-03-08powerpc/pseries: Parse control memory access errorGanesh Goudar1-4/+32
Add support to parse and log control memory access error for pseries. These changes are made according to PAPR v2.11 10.3.2.2.12. Signed-off-by: Ganesh Goudar <ganeshgr@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220107141428.67862-1-ganeshgr@linux.ibm.com
2022-03-08powerpc/bpf: Simplify bpf_to_ppc() and adopt it for powerpc64Naveen N. Rao4-104/+98
Convert bpf_to_ppc() to a macro to help simplify its usage since codegen_context is available in all places it is used. Adopt it also for powerpc64 for uniformity and get rid of the global b2p structure. Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/09f0540ce3e0cd4120b5b33993b5e73b6ef9e979.1644834730.git.naveen.n.rao@linux.vnet.ibm.com
2022-03-08powerpc64/bpf: Store temp registers' bpf to ppc mappingJordan Niethe1-111/+86
In bpf_jit_build_body(), the mapping of TMP_REG_1 and TMP_REG_2's bpf register to ppc register is evalulated at every use despite not changing. Instead, determine the ppc register once and store the result. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> [Rebased, converted additional usage sites] Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/0944e2f0fa6dd254ea401f1c946fb6c9a5294278.1644834730.git.naveen.n.rao@linux.vnet.ibm.com
2022-03-08powerpc/bpf: Use _Rn macros for GPRsNaveen N. Rao2-49/+49
Use _Rn macros to specify register names to make their usage clear. Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/7df626b8cdc6141d4295ac16137c82ad570b6637.1644834730.git.naveen.n.rao@linux.vnet.ibm.com
2022-03-08powerpc/bpf: Move bpf_jit64.h into bpf_jit_comp64.cNaveen N. Rao2-70/+53
There is no need for a separate header anymore. Move the contents of bpf_jit64.h into bpf_jit_comp64.c Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/b873a8e6eff7d91bf2a2cabdd53082aadfe20761.1644834730.git.naveen.n.rao@linux.vnet.ibm.com
2022-03-08powerpc/bpf: Cleanup bpf_jit.hNaveen N. Rao2-9/+3
- PPC_EX32() is only used by ppc32 JIT. Move it to bpf_jit_comp32.c - PPC_LI64() is only valid in ppc64. #ifdef it - PPC_FUNC_ADDR() is not used anymore. Remove it. Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/58f5b66b2f8546bbbee620f62103a8e97a63eb7c.1644834730.git.naveen.n.rao@linux.vnet.ibm.com
2022-03-08powerpc64/bpf: Get rid of PPC_BPF_[LL|STL|STLU] macrosNaveen N. Rao2-28/+15
All these macros now have a single user. Expand their usage in place. Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/e0526fc7633a34f983a7a330712b55bdfaf20482.1644834730.git.naveen.n.rao@linux.vnet.ibm.com
2022-03-08powerpc64/bpf: Convert some of the uses of PPC_BPF_[LL|STL] to PPC_BPF_[LD|STD]Naveen N. Rao1-11/+11
PPC_BPF_[LL|STL] are macros meant for scenarios where we may have to deal with a non-word aligned offset. Limit their usage to only those scenarios by converting the rest to just use PPC_BPF_[LD|STD]. Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/0eb472428165a307f6fdaf22b0c33cbf13a9a635.1644834730.git.naveen.n.rao@linux.vnet.ibm.com
2022-03-08powerpc/bpf: Rename PPC_BL_ABS() to PPC_BL()Naveen N. Rao2-4/+4
PPC_BL_ABS() is just doing a relative branch with link. The name suggests that it is for branching to an absolute address, which is incorrect. Rename the macro to a more appropriate PPC_BL(). Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/f0e57b6c7a6ee40dba645535b70da46f46e8af5e.1644834730.git.naveen.n.rao@linux.vnet.ibm.com
2022-03-08powerpc64/bpf: Optimize instruction sequence used for function callsNaveen N. Rao1-17/+13
When calling BPF helpers, we load the function address to call into a register. This can result in upto 5 instructions. Optimize this by instead using the kernel toc in r2 and adjusting offset to the BPF helper. This works since all BPF helpers are part of kernel text, and all BPF programs/functions utilize the kernel TOC. Further more: - load the actual function entry address in elf v1, rather than loading it through the function descriptor address. - load the Local Entry Point (LEP) in elf v2 skipping TOC setup. - consolidate code across elf abi v1 and v2 by using r12 on both. Reported-by: Anton Blanchard <anton@ozlabs.org> Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/1233c7544e60dcb021c52b1f840b0f21a87b33ed.1644834730.git.naveen.n.rao@linux.vnet.ibm.com
2022-03-08powerpc64/bpf elfv1: Do not load TOC before calling functionsNaveen N. Rao4-23/+30
BPF helpers always reside in core kernel and all BPF programs use the kernel TOC. As such, there is no need to load the TOC before calling helpers or other BPF functions. Drop code to do the same. Add a check to ensure we don't proceed if this assumption ever changes in future. Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/a3cd3da4d24d95d845cd10382b1af083600c9074.1644834730.git.naveen.n.rao@linux.vnet.ibm.com
2022-03-08powerpc64/bpf elfv2: Setup kernel TOC in r2 on entryNaveen N. Rao1-8/+8
In preparation for using kernel TOC, load the same in r2 on entry. With elfv1, the kernel TOC is already setup by our caller. We adjust the number of instructions to skip on a tail call accordingly. We get rid of the #ifdef in bpf_jit_emit_tail_call() since FUNCTION_DESCR_SIZE is itself under a #ifdef. Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/18a05a4ceec14a8617c9dd4b7128d0afa83fd14e.1644834730.git.naveen.n.rao@linux.vnet.ibm.com
2022-03-08powerpc64: Set PPC64_ELF_ABI_v[1|2] macros to 1Naveen N. Rao1-2/+2
Set macros to 1 so that they can be used with __is_defined(). Suggested-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/abad4868416ddfd42893f99c0cad8e5faf998095.1644834730.git.naveen.n.rao@linux.vnet.ibm.com
2022-03-08powerpc64/bpf: Use r12 for constant blindingNaveen N. Rao1-1/+1
In preparation for preserving kernel toc in r2, switch BPF_REG_AX from r2 to r12. r12 is not used by bpf JIT except during external helper/bpf calls, or with BPF_NOSPEC. These sequences aren't emitted when BPF_REG_AX is used for constant blinding and other purposes. Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/e109f98617eacb4512c17a48525e94eda42889e6.1644834730.git.naveen.n.rao@linux.vnet.ibm.com
2022-03-08powerpc64/bpf: Do not save/restore LR on each call to bpf_stf_barrier()Naveen N. Rao1-2/+1
Instead of saving and restoring LR before each invocation to bpf_stf_barrier(), set SEEN_FUNC flag so that we save/restore LR in prologue/epilogue. Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/4446f25478d82a2a4ac9dab2ebdfd88ddf923eb7.1644834730.git.naveen.n.rao@linux.vnet.ibm.com
2022-03-08powerpc/bpf: Handle large branch ranges with BPF_EXITNaveen N. Rao4-5/+33
In some scenarios, it is possible that the program epilogue is outside the branch range for a BPF_EXIT instruction. Instead of rejecting such programs, emit epilogue as an alternate exit point from the program. Track the location of the same so that subsequent exits can take either of the two paths. Reported-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/33aa2e92645a92712be23b18035a2c6dcb92ff8d.1644834730.git.naveen.n.rao@linux.vnet.ibm.com
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