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2021-12-31Docs: Fixes link to I2C specificationDeep Majumder1-3/+5
The link to the I2C specification is broken. Although "https://www.nxp.com" hosts Rev 7 (2021) of this specification, it is behind a login-wall. Thus, an additional link has been added (which doesn't require a login) and the NXP official docs link has been updated. Signed-off-by: Deep Majumder <deep@fastmail.in> [wsa: minor updates to text and commit message] Signed-off-by: Wolfram Sang <wsa@kernel.org>
2021-12-31i2c: validate user data in compat ioctlPavel Skripkin1-0/+3
Wrong user data may cause warning in i2c_transfer(), ex: zero msgs. Userspace should not be able to trigger warnings, so this patch adds validation checks for user data in compact ioctl to prevent reported warnings Reported-and-tested-by: syzbot+e417648b303855b91d8a@syzkaller.appspotmail.com Fixes: 7d5cb45655f2 ("i2c compat ioctls: move to ->compat_ioctl()") Signed-off-by: Pavel Skripkin <paskripkin@gmail.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2021-12-31ASoC: Merge fixesMark Brown12-76/+156
So we can send to Linus.
2021-12-31ASoC: cs35l41: Create shared function for boost configurationLucas Tanure3-103/+102
ASoC and HDA will use the same registers to configure internal boost for the device Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Link: https://lore.kernel.org/r/20211217115708.882525-7-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-12-31ASoC: cs35l41: Create shared function for setting channelsLucas Tanure3-27/+38
ASoC and HDA will use the same register to set channels for the device Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Link: https://lore.kernel.org/r/20211217115708.882525-6-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-12-31ASoC: cs35l41: Create shared function for errata patchesLucas Tanure3-89/+93
ASoC and HDA systems require the same errata patches, so move it to the shared code using a function the correctly applies the patches by revision Also, move CS35L41_DSP1_CCM_CORE_CTRL write to errata patch function as is required to be written at boot, but not in regmap_register_patch sequence as will affect waking up from hibernation Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Link: https://lore.kernel.org/r/20211217115708.882525-5-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-12-31ASoC: cs35l41: Move power initializations to reg_sequenceLucas Tanure2-15/+8
ASoC and HDA systems for all revisions of CS35L41 will benefit from having this initialization, so add it to reg_sequence of each revision By moving to reg_sequence all gains are set to zero. And boost, monitoring parts, and class D amplifier are disabled. Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Link: https://lore.kernel.org/r/20211217115708.882525-4-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-12-31ASoC: cs35l41: Move cs35l41_otp_unpack to shared codeLucas Tanure3-128/+122
ASoC and HDA will do the same cs35l41_otp_unpack, so move it to shared code Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Link: https://lore.kernel.org/r/20211217115708.882525-3-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-12-31ASoC: cs35l41: Convert tables to shared source codeLucas Tanure7-743/+755
To support CS35L41 in HDA systems the HDA driver for CS35L41 would have to duplicate some functions that already exist on ASoC driver So instead of duplicate the code, use the new lib source as a shared resource for both ASoC and HDA Also, change the way CONFIG_SND_SOC_CS35L41 is selected, as reported by Intel Kernel test robot, it is possible to build SND_SOC_CS35L41_SPI/I2C without the main driver, which would lead to build failures. Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/20211217115708.882525-2-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-12-31ASoC: mediatek: mt8195: add playback support to PCM1_BE dai_linkTrevor Wu2-0/+2
PCM1_BE should be a dai_link for both playback and capture. In the patch, the missing DPCM playback support is added. Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Link: https://lore.kernel.org/r/20211230084731.31372-3-trevor.wu@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-12-31ASoC: mediatek: mt8195: correct pcmif BE dai control flowTrevor Wu2-52/+22
Originally, the conditions for preventing reentry are not correct. dai->component->active is not the state specifically for pcmif dai, so it is not a correct condition to indicate the status of pcmif dai. On the other hand, snd_soc_dai_stream_actvie() in prepare ops for both playback and capture possibly return true at the first entry when these two streams are opened at the same time. In the patch, I refer to the implementation in mt8192-dai-pcm.c. Clock and enabling bit for PCMIF are managed by DAPM, and the condition for prepare ops is replaced by the status of dai widget. Fixes: 1f95c019115c ("ASoC: mediatek: mt8195: support pcm in platform driver") Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Link: https://lore.kernel.org/r/20211230084731.31372-2-trevor.wu@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-12-31Revert "serdev: BREAK/FRAME/PARITY/OVERRUN notification prototype V2"Greg Kroah-Hartman3-82/+0
This reverts commit d8e9a406a931f687945703a4bac45042eb81ce92. It needs some future changes as pointed out by Johan and is not ready to be merged just yet. Reported-by: Johan Hovold <johan@kernel.org> Cc: Magnus Damm <damm+renesas@opensource.se> Link: https://lore.kernel.org/r/Yc7oZ/1tu95Z4wPS@hovoldconsulting.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-12-31Merge tag 'nand/for-5.17' into mtd/nextMiquel Raynal18-413/+1910
Raw NAND core: * Export nand_read_page_hwecc_oob_first() GPMC memory controller for OMAP2 NAND controller: * GPMC: - Add support for AM64 SoC and allow build on K3 platforms - Use a compatible match table when checking for NAND controller - Use platform_get_irq() to get the interrupt Raw NAND controller drivers: * OMAP2 NAND controller: - Document the missing 'rb-gpios' DT property - Drop unused variable - Fix force_8bit flag behaviour for DMA mode - Move to exec_op interface - Use platform_get_irq() to get the interrupt * Renesas: - Add new NAND controller driver with its bindings and MAINTAINERS entry * Onenand: - Remove redundant variable ooblen * MPC5121: - Remove unused variable in ads5121_select_chip() * GPMI: - Add ERR007117 protection for nfc_apply_timings - Remove explicit default gpmi clock setting for i.MX6 - Use platform_get_irq_byname() to get the interrupt - Remove unneeded variable * Ingenic: - JZ4740 needs 'oob_first' read page function * Davinci: - Rewrite function description - Avoid duplicated page read - Don't calculate ECC when reading page Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2021-12-31Merge tag 'spi-nor/for-5.17' into mtd/nextMiquel Raynal23-821/+1072
SPI NOR core changes: - Add Pratyush as SPI NOR co-maintainer. - Flash parameters initialization was done in a spaghetti way. Clean flash parameters initialization. - Rework the flash_info flags and clarify where one should be used. - Initialize all flash parameters based on JESD216 SFDP where possible. Flash parameters and settings that are SFDP discoverable should not be duplicated via flash_info flags at flash declaration. - Remove debugfs entries that duplicate sysfs entries. SPI NOR manufacturer drivers changes: - Use late_init() hook in various drivers to make it clear that those flash parameters are either not declared in the JESD216 SFDP standard, or the SFDP tables which define those flash parameters are not defined by the flash. - Fix mtd size for s3an flashes. - Write 2 bytes when disabling Octal DTR mode: 1 byte long transactions are not allowed in 8D-8D-8D mode. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2021-12-31Merge tag 'cfi/for-5.17' into mtd/nextMiquel Raynal1-3/+5
Hyperbus changes for v5.17-rc1 Hyperbus changes: Couple of fixes in Renesas hyperbus rpc-if driver to avoid crash on module remove and for missing check for error value in probe. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2021-12-31Merge tag 'memory-controller-drv-omap-5.17' into nand/nextMiquel Raynal5-23/+65
Memory controller drivers for v5.17 - OMAP GPMC 1. Add support for AM64 SoC. 2. Minor improvement: use platform_get_irq(). [miquel.raynal@bootlin.com: A first commit introduced a new omap compatible and another moved the IDs to a header which created a conflict: moving the new ID as well in the header fixed it.] Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2021-12-31drm: Add orientation quirk for GPD Win MaxAnisse Astier1-0/+6
Panel is 800x1280, but mounted on a laptop form factor, sideways. Signed-off-by: Anisse Astier <anisse@astier.eu> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211229222200.53128-3-anisse@astier.eu
2021-12-31drm/i915/opregion: add support for mailbox #5 EDIDAnisse Astier3-1/+72
The ACPI OpRegion Mailbox #5 ASLE extension may contain an EDID to be used for the embedded display. Add support for using it via by adding the EDID to the list of available modes on the connector, and use it for eDP when available. If a panel's EDID is broken, there may be an override EDID set in the ACPI OpRegion mailbox #5. Use it if available. Fixes the GPD Win Max display. Based on original patch series by: Jani Nikula <jani.nikula@intel.com> https://patchwork.kernel.org/project/intel-gfx/patch/20200828061941.17051-1-jani.nikula@intel.com/ Changes: - EDID is copied and validated with drm_edid_is_valid - EDID is now only used as a fallback. - squashed the two patches Cc: Jani Nikula <jani.nikula@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Co-developed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Anisse Astier <anisse@astier.eu> Link: https://patchwork.freedesktop.org/patch/msgid/20211229222200.53128-2-anisse@astier.eu
2021-12-31net/mlx5: Set SMFS as a default steering mode if device supports itYevgeny Kliteynik1-0/+5
Set SMFS (SW-managed flow steering) as a default steering mode instead of DMFS (device-managed flow steering) In SMFS, the driver writes the STEs (Steering Table Entries) directly to the device's ICM, which allows for a higher rule insertion rate than through using FW command interface, as it is done in DMFS. SMFS/DMFS steering modes can be configured through devlink param 'flow_steering_mode'. The possible values are 'smfs' or 'dmfs'. The desired 'flow_steering_mode' param value should be set before enabling switchdev mode. Example: # devlink dev param set pci/0000:05:00.0 name flow_steering_mode smfs # devlink dev eswitch set pci/0000:05:00.0 mode switchdev Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Ignore modify TTL if device doesn't support itYevgeny Kliteynik2-4/+19
When modifying TTL, packet's csum has to be recalculated. Due to HW issue in ConnectX-5, csum recalculation for modify TTL is supported through a work-around that is specifically enabled by configuration. If the work-around isn't enabled, ignore the modify TTL action rather than adding an unsupported action. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Improve steering for empty or RX/TX-only matchersYevgeny Kliteynik4-130/+156
Every matcher has RX and TX paths. When a new matcher is created, its RX and TX start/end anchors are connected to the respective RX and TX anchors of the previous and next matchers. This creates a potential performance issue: when a certain rule is added to a matcher, in many cases it is RX or TX only rule, which may create a long chain of RX/TX-only paths w/o the actual rules. This patch aims to handle this issue. RX and TX matchers are now handled separately: matcher connection in the matchers chain is split into two separate lists: RX only and TX only. when a new matcher is created, it is initially created 'detached' - its RX/TX members are not inserted into the table's matcher list. When an actual rule is added, only its appropriate RX or TX nic matchers are then added to the table's nic matchers list and inserted into its place in the chain of matchers. I.e., if the rule that is being added is an RX-only rule, only the RX part of the matcher will be connected to the chain, while TX part of the matcher remains detached and doesn't prolong the TX chain of the matchers. Same goes for rule deletion: when the last RX/TX rule of the nic matcher is destroyed, the nic matcher is removed from its list. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Add support for matching on geneve_tlv_option_0_exist fieldYevgeny Kliteynik8-3/+90
Match on geneve_tlv_option_0_exist field on devices that support STEv1. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Support matching on tunnel headers 0 and 1Muhammad Sammar7-1/+79
Tunnel headers are generic encapsulation headers, applies for all tunneling protocols identified by the device native parser or by the programmable parser, this support will enable raw matching headers 0 and 1. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Add misc5 to match_param structsMuhammad Sammar4-1/+61
Add misc5 match params to enable matching tunnel headers. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com>
2021-12-31net/mlx5: Add misc5 flow table match parametersMuhammad Sammar4-3/+27
Add support for misc5 match parameter as per HW spec, this will allow matching on tunnel_header fields. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Warn on failure to destroy objects due to refcountYevgeny Kliteynik4-4/+4
Add WARN_ON_ONCE on refcount checks in SW steering object destructors Signed-off-by: Paul Blakey <paulb@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Add support for UPLINK destination typeYevgeny Kliteynik4-10/+34
Add support for a new destination type - UPLINK. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Add support for dumping steering infoMuhammad Sammar8-8/+688
Extend mlx5 debugfs support to present Software Steering resources: dr_domain including it's tables, matchers and rules. The interface is read-only. While dump is being presented, new steering rules cannot be inserted/deleted. The steering information is dumped in the CSV form with the following format: <object_type>,<object_ID>, <object_info>,...,<object_info> This data can be read at the following path: /sys/kernel/debug/mlx5/<BDF>/steering/fdb/<domain_handle> Example: # cat /sys/kernel/debug/mlx5/0000:82:00.0/steering/fdb/dmn_000018644 3100,0x55caa4621c50,0xee802,4,65533 3101,0x55caa4621c50,0xe0100008 Changes in V2: - Reduce temp hex buffer size and avoid unnecessary memset - Use bin2hex() instead of DIY loop - Don't check debugfs functions return values Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Add missing reserved fields to dr_match_paramMuhammad Sammar1-89/+124
Add the reserved fields to dr_match_param and arrange as mlx5_ifc_dr_match_param_bits. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com>
2021-12-31net/mlx5: DR, Add check for flex parser ID valueYevgeny Kliteynik2-2/+2
Allow only legal values for flex parser ID - values from 0 to 7. For other values skip the parser, and as a result the matcher creation will fail for using invalid flex parser ID. Signed-off-by: Hamdan Igbaria <hamdani@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Rename list field in matcher struct to list_nodeYevgeny Kliteynik3-15/+15
In dr_types structs, some list fields are list heads, and some are just list nodes that are stored on the other structs' lists. Rename the appropriate list field to reflect this distinction. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Remove unused struct member in matcherYevgeny Kliteynik1-1/+0
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Fix lower case macro prefix "mlx5_" to "MLX5_"Yevgeny Kliteynik3-3/+3
Macros prefix should be capital letters - fix the prefix in mlx5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Fix error flow in creating matcherYevgeny Kliteynik1-21/+32
The error code of nic matcher init functions wasn't checked. This patch improves the matcher init function and fix error flow bug: the handling of match parameter is moved into a separate function and error flow is simplified. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31crypto: qat - fix definition of ring reset resultsGiovanni Cabiddu1-4/+4
The ring reset result values are defined starting from 0x1 instead of 0. This causes out-of-tree drivers that support this message to understand that a ring reset failed even if the operation was successful. Fix by starting the definition of ring reset result values from 0. Fixes: 0bba03ce9739 ("crypto: qat - add PFVF support to enable the reset of ring pairs") Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reported-by: Adam Guerin <adam.guerin@intel.com> Reviewed-by: Marco Chiappero <marco.chiappero@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-12-31crypto: hisilicon - cleanup warning in qm_get_qos_value()Tom Rix1-1/+1
Building with clang static analysis returns this warning: qm.c:4382:11: warning: The left operand of '==' is a garbage value if (*val == 0 || *val > QM_QOS_MAX_VAL || ret) { ~~~~ ^ The call to qm_qos_value_init() can return an error without setting *val. So check ret before checking *val. Fixes: 72b010dc33b9 ("crypto: hisilicon/qm - supports writing QoS int the host") Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-12-31crypto: kdf - select SHA-256 required for self-testStephan Müller1-1/+1
The self test of the KDF is based on SHA-256. Thus, this algorithm must be present as otherwise a warning is issued. Reported-by: kernel test robot <oliver.sang@intel.com> Signed-off-by: Stephan Mueller <smueller@chronox.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-12-31crypto: x86/aesni - don't require alignment of dataJakub Kicinski1-2/+2
x86 AES-NI routines can deal with unaligned data. Crypto context (key, iv etc.) have to be aligned but we take care of that separately by copying it onto the stack. We were feeding unaligned data into crypto routines up until commit 83c83e658863 ("crypto: aesni - refactor scatterlist processing") switched to use the full skcipher API which uses cra_alignmask to decide data alignment. This fixes 21% performance regression in kTLS. Tested by booting with CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y (and running thru various kTLS packets). CC: stable@vger.kernel.org # 5.15+ Fixes: 83c83e658863 ("crypto: aesni - refactor scatterlist processing") Signed-off-by: Jakub Kicinski <kuba@kernel.org> Acked-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-12-31crypto: ccp - remove unneeded semicolonYang Li1-1/+1
Eliminate the following coccicheck warning: ./drivers/crypto/ccp/sev-dev.c:263:2-3: Unneeded semicolon Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-12-31crypto: stm32/crc32 - Fix kernel BUG triggered in probe()Marek Vasut1-2/+2
The include/linux/crypto.h struct crypto_alg field cra_driver_name description states "Unique name of the transformation provider. " ... " this contains the name of the chip or provider and the name of the transformation algorithm." In case of the stm32-crc driver, field cra_driver_name is identical for all registered transformation providers and set to the name of the driver itself, which is incorrect. This patch fixes it by assigning a unique cra_driver_name to each registered transformation provider. The kernel crash is triggered when the driver calls crypto_register_shashes() which calls crypto_register_shash(), which calls crypto_register_alg(), which calls __crypto_register_alg(), which returns -EEXIST, which is propagated back through this call chain. Upon -EEXIST from crypto_register_shash(), the crypto_register_shashes() starts unregistering the providers back, and calls crypto_unregister_shash(), which calls crypto_unregister_alg(), and this is where the BUG() triggers due to incorrect cra_refcnt. Fixes: b51dbe90912a ("crypto: stm32 - Support for STM32 CRC32 crypto module") Signed-off-by: Marek Vasut <marex@denx.de> Cc: <stable@vger.kernel.org> # 4.12+ Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Fabien Dessenne <fabien.dessenne@st.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: Lionel Debieve <lionel.debieve@st.com> Cc: Nicolas Toromanoff <nicolas.toromanoff@st.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-crypto@vger.kernel.org Acked-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-12-31crypto: s390/sha512 - Use macros instead of direct IV numbersTianjia Zhang1-16/+16
In the init functions of sha512 and sha384, the initial hash value use macros instead of numbers. Signed-off-by: Tianjia Zhang <tianjia.zhang@linux.alibaba.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-12-31crypto: sparc/sha - remove duplicate hash init functionTianjia Zhang3-80/+8
sha*_base_init() series functions has implemented the initialization of the hash context, this commit use sha*_base_init() function to replace repeated implementations. Signed-off-by: Tianjia Zhang <tianjia.zhang@linux.alibaba.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-12-31crypto: powerpc/sha - remove duplicate hash init functionTianjia Zhang3-63/+7
sha*_base_init() series functions has implemented the initialization of the hash context, this commit use sha*_base_init() function to replace repeated implementations. Signed-off-by: Tianjia Zhang <tianjia.zhang@linux.alibaba.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-12-31crypto: mips/sha - remove duplicate hash init functionTianjia Zhang3-87/+8
sha*_base_init() series functions has implemented the initialization of the hash context, this commit use sha*_base_init() function to replace repeated implementations. Signed-off-by: Tianjia Zhang <tianjia.zhang@linux.alibaba.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-12-31crypto: sha256 - remove duplicate generic hash init functionTianjia Zhang1-14/+2
crypto_sha256_init() and sha256_base_init() are the same repeated implementations, remove the crypto_sha256_init() in generic implementation, sha224 is the same process. Signed-off-by: Tianjia Zhang <tianjia.zhang@linux.alibaba.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-12-31crypto: jitter - add oversampling of noise sourceStephan Müller1-2/+21
The output n bits can receive more than n bits of min entropy, of course, but the fixed output of the conditioning function can only asymptotically approach the output size bits of min entropy, not attain that bound. Random maps will tend to have output collisions, which reduces the creditable output entropy (that is what SP 800-90B Section 3.1.5.1.2 attempts to bound). The value "64" is justified in Appendix A.4 of the current 90C draft, and aligns with NIST's in "epsilon" definition in this document, which is that a string can be considered "full entropy" if you can bound the min entropy in each bit of output to at least 1-epsilon, where epsilon is required to be <= 2^(-32). Note, this patch causes the Jitter RNG to cut its performance in half in FIPS mode because the conditioning function of the LFSR produces 64 bits of entropy in one block. The oversampling requires that additionally 64 bits of entropy are sampled from the noise source. If the conditioner is changed, such as using SHA-256, the impact of the oversampling is only one fourth, because for the 256 bit block of the conditioner, only 64 additional bits from the noise source must be sampled. This patch is derived from the user space jitterentropy-library. Signed-off-by: Stephan Mueller <smueller@chronox.de> Reviewed-by: Simo Sorce <simo@redhat.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-12-31MAINTAINERS: update SEC2 driver maintainers listKai Ye1-0/+1
Adding Kai Ye as SEC2 maintainer. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-12-30Input: spaceball - fix parsing of movement data packetsLeo L. Schwab1-2/+9
The spaceball.c module was not properly parsing the movement reports coming from the device. The code read axis data as signed 16-bit little-endian values starting at offset 2. In fact, axis data in Spaceball movement reports are signed 16-bit big-endian values starting at offset 3. This was determined first by visually inspecting the data packets, and later verified by consulting: http://spacemice.org/pdf/SpaceBall_2003-3003_Protocol.pdf If this ever worked properly, it was in the time before Git... Signed-off-by: Leo L. Schwab <ewhac@ewhac.org> Link: https://lore.kernel.org/r/20211221101630.1146385-1-ewhac@ewhac.org Cc: stable@vger.kernel.org Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2021-12-30Input: appletouch - initialize work before device registrationPavel Skripkin1-2/+2
Syzbot has reported warning in __flush_work(). This warning is caused by work->func == NULL, which means missing work initialization. This may happen, since input_dev->close() calls cancel_work_sync(&dev->work), but dev->work initalization happens _after_ input_register_device() call. So this patch moves dev->work initialization before registering input device Fixes: 5a6eb676d3bc ("Input: appletouch - improve powersaving for Geyser3 devices") Reported-and-tested-by: syzbot+b88c5eae27386b252bbd@syzkaller.appspotmail.com Signed-off-by: Pavel Skripkin <paskripkin@gmail.com> Link: https://lore.kernel.org/r/20211230141151.17300-1-paskripkin@gmail.com Cc: stable@vger.kernel.org Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2021-12-30bpf: Fix typo in a comment in bpf lpm_trie.Leon Huayra1-1/+1
Fix typo in a comment in trie_update_elem(). Signed-off-by: Leon Huayra <hffilwlqm@gmail.com> Signed-off-by: Alexei Starovoitov <ast@kernel.org> Link: https://lore.kernel.org/bpf/20211229144422.70339-1-hffilwlqm@gmail.com
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