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2022-09-20pinctrl: cy8c95x0: Lock register accesses in cy8c95x0_set_mux()Andy Shevchenko1-1/+6
It seems that cy8c95x0_set_mux() missed serialization of IO access. And its implementation looks half-baked. Add locking to the function. Fixes: e6cbbe42944d ("pinctrl: Add Cypress cy8c95x0 support") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220916205450.86278-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-09-20pinctrl: sunxi: sun50i-h5: Switch to use dev_err_probe() helperYang Yingliang1-6/+3
In the probe path, dev_err() can be replace with dev_err_probe() which will check if error code is -EPROBE_DEFER and and prints the error name. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220917122208.1894769-1-yangyingliang@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-09-20pinctrl: stm32: Switch to use dev_err_probe() helperYang Yingliang1-3/+2
In the probe path, dev_err() can be replace with dev_err_probe() which will check if error code is -EPROBE_DEFER and prints the error name. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220917122015.1893880-1-yangyingliang@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-09-20drm/hisilicon: Add depends on MMURandy Dunlap1-0/+1
The Kconfig symbol depended on MMU but was dropped by the commit acad3fe650a5 ("drm/hisilicon: Removed the dependency on the mmu") because it already had as a dependency ARM64 that already selects MMU. But later, commit a0f25a6bb319 ("drm/hisilicon/hibmc: Allow to be built if COMPILE_TEST is enabled") allowed the driver to be built for non-ARM64 when COMPILE_TEST is set but that could lead to unmet direct dependencies and linking errors. Prevent a kconfig warning when MMU is not enabled by making DRM_HISI_HIBMC depend on MMU. WARNING: unmet direct dependencies detected for DRM_TTM Depends on [n]: HAS_IOMEM [=y] && DRM [=m] && MMU [=n] Selected by [m]: - DRM_TTM_HELPER [=m] && HAS_IOMEM [=y] && DRM [=m] - DRM_HISI_HIBMC [=m] && HAS_IOMEM [=y] && DRM [=m] && PCI [=y] && (ARM64 || COMPILE_TEST [=y]) Fixes: acad3fe650a5 ("drm/hisilicon: Removed the dependency on the mmu") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Thomas Zimmermann <tzimmermann@suse.de> Cc: Xinliang Liu <xinliang.liu@linaro.org> Cc: Tian Tao <tiantao6@hisilicon.com> Cc: John Stultz <jstultz@google.com> Cc: Xinwei Kong <kong.kongxinwei@hisilicon.com> Cc: Chen Feng <puck.chen@hisilicon.com> Cc: Christian Koenig <christian.koenig@amd.com> Cc: Huang Rui <ray.huang@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220531025557.29593-1-rdunlap@infradead.org
2022-09-20fat: port to vfs{g,u}id_t and associated helpersChristian Brauner1-2/+3
A while ago we introduced a dedicated vfs{g,u}id_t type in commit 1e5267cd0895 ("mnt_idmapping: add vfs{g,u}id_t"). We already switched over a good part of the VFS. Ultimately we will remove all legacy idmapped mount helpers that operate only on k{g,u}id_t in favor of the new type safe helpers that operate on vfs{g,u}id_t. Cc: Seth Forshee (Digital Ocean) <sforshee@kernel.org> Cc: Christoph Hellwig <hch@lst.de> Cc: OGAWA Hirofumi <hirofumi@mail.parknet.co.jp> Cc: linux-fsdevel@vger.kernel.org Signed-off-by: Christian Brauner (Microsoft) <brauner@kernel.org> Acked-by: OGAWA Hirofumi <hirofumi@mail.parknet.co.jp>
2022-09-20drm: bridge/dw-hdmi-ahb-audio: use strscpy() is more robust and saferMinghao Chi1-3/+3
The implementation of strscpy() is more robust and safer. That's now the recommended way to copy NUL terminated strings. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Minghao Chi <chi.minghao@zte.com.cn> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20220919030401.211331-1-chi.minghao@zte.com.cn
2022-09-20clocksource/drivers/imx-sysctr: handle nxp,no-divider propertyPeng Fan1-2/+4
The previous hardware design embedds a internal divider for base clock. New design not has that divider, so check the nxp,no-divider property, if true, directly use base clock input, otherwise divide by 3 as before. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220902111207.2902493-3-peng.fan@oss.nxp.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-09-20dt-bindings: timer: nxp,sysctr-timer: add nxp,no-divider propertyPeng Fan1-0/+4
The base clock input to system counter is internally divided by 3 in previous design, but there is change that no divider now. So add a property to indicate that. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220902111207.2902493-2-peng.fan@oss.nxp.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-09-20clocksource/drivers/timer-ti-dm: Get clock in probe with devm_clk_get()Tony Lindgren1-15/+9
We can simplify the code a bit by getting the clock in probe, and using devm_clk_get(). This will also make further changes easier as the clock is available in probe instead of prepare. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20220815131250.34603-10-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-09-20clocksource/drivers/timer-ti-dm: Add flag to detect omap1Tony Lindgren1-3/+6
Let's make it clear that some features need to be tested currently on omap1. Only omap1 still uses platform_data. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20220815131250.34603-9-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-09-20clocksource/drivers/timer-ti-dm: Move struct omap_dm_timer fields to driverTony Lindgren2-91/+170
There is no longer any need to expose the elements of struct omap_dm_timer outside the driver. The pwm and remoteproc drivers just use struct omap_dm_timer as a cookie. Let's move the elements of struct omap_dm_timer into struct dmtimer that is private to the driver. To do this, we mostly rename omap_dm_timer to dmtimer in the driver. We keep omap_dm_timer only for the exposed functions in the platform_data for the pwm and remoteproc drivers. Let's also add a note about not using the exposed functions internally as those will get deprecated eventually in favor of Linux generic frameworks. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20220815131250.34603-8-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-09-20clocksource/drivers/timer-ti-dm: Use runtime PM directly and check errorsTony Lindgren1-26/+91
Use pm_runtime_resume_and_get() and check for a possible error returned. We want to do this as omap_dm_timer_enable() and omap_dm_timer_disable() are exposed to the pwm and remoteproc drivers, and in the following patch we turn struct omap_dm_timer into a cookie used by the exposed functions only. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20220815131250.34603-7-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-09-20clocksource/drivers/timer-ti-dm: Move private defines to the driverTony Lindgren2-62/+62
These defines are only used by timer-ti-dm driver. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20220815131250.34603-6-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-09-20clocksource/drivers/timer-ti-dm: Simplify register access furtherTony Lindgren2-17/+17
Let's unify register access and use dmtimer_read() and dmtimer_write() also for the timer revision specific registers like we now do for the shread registers. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20220815131250.34603-5-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-09-20clocksource/drivers/timer-ti-dm: Simplify register writes with dmtimer_write()Tony Lindgren1-53/+43
We can simplify register write access by checking for the register write posted mode in the write function. This way we can combine the functions for __omap_dm_timer_write() and omap_dm_timer_write_reg() into a single function dmtimer_write(). We update the shared register access first, the timer revision specific register access will be updated in a later patch. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20220815131250.34603-4-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-09-20clocksource/drivers/timer-ti-dm: Simplify register reads with dmtimer_read()Tony Lindgren1-47/+39
We can simplify register read access by checking for the register write posted mode in the read function. This way we can combine the functions for __omap_dm_timer_read() and omap_dm_timer_read_reg() into a single function dmtimer_read(). We update the shared register access first, the timer revision specific register access will be updated in a later patch. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20220815131250.34603-3-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-09-20clocksource/drivers/timer-ti-dm: Drop unused functionsTony Lindgren2-58/+0
We still have some unused functions left, let's drop them. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20220815131250.34603-2-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-09-20clocksource/drivers/timer-gxp: Add missing error handling in gxp_timer_probeLin Yujun1-1/+6
Add platform_device_put() to make sure to free the platform device in the event platform_device_add() fails. Fixes: 5184f4bf151b ("clocksource/drivers/timer-gxp: Add HPE GXP Timer") Signed-off-by: Lin Yujun <linyujun809@huawei.com> Link: https://lore.kernel.org/r/20220914033018.97484-1-linyujun809@huawei.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-09-20clocksource/drivers/arm_arch_timer: Fix handling of ARM erratum 858921Kunkun Jiang1-0/+2
The commit a38b71b0833e ("clocksource/drivers/arm_arch_timer: Move system register timer programming over to CVAL") moves the programming of the timers from the countdown timer (TVAL) over to the comparator (CVAL). This makes it necessary to read the counter when programming next event. However, the workaround of Cortex-A73 erratum 858921 does not set the corresponding set_next_event_phys and set_next_event_virt. Add the appropriate hooks to apply the erratum mitigation when programming the next timer event. Fixes: a38b71b0833e ("clocksource/drivers/arm_arch_timer: Move system register timer programming over to CVAL") Signed-off-by: Kunkun Jiang <jiangkunkun@huawei.com> Acked-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20220914061424.1260-1-jiangkunkun@huawei.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-09-20clocksource/drivers/exynos_mct: Enable building on ARTPECVincent Whitchurch1-1/+1
This timer block is used on ARTPEC-8. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> Link: https://lore.kernel.org/r/20220609112738.359385-5-vincent.whitchurch@axis.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-09-20clocksource/drivers/exynos_mct: Support local-timers propertyVincent Whitchurch1-6/+56
If the device tree indicates that the hardware requires that the processor only use certain local timers, respect that. Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220609112738.359385-4-vincent.whitchurch@axis.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-09-20clocksource/drivers/exynos_mct: Support frc-shared propertyVincent Whitchurch1-3/+18
When the FRC is shared with another main processor, the other processor is assumed to have started it and this processor should not write to the global registers. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> Link: https://lore.kernel.org/r/20220609112738.359385-3-vincent.whitchurch@axis.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-09-20dt-bindings: timer: exynos4210-mct: Add ARTPEC-8 MCT supportVincent Whitchurch1-0/+26
The ARTPEC-8 has an MCT with 4 global and 8 local timer interrupts. The SoC has a quad-core Cortex-A53 and a single-core Cortex-A5 which share one MCT with one global and eight local timers. The Cortex-A53 and Cortex-A5 do not have cache-coherency between them, and therefore run two separate kernels. The Cortex-A53 boots first and starts the global free-running counter and also registers a clock events device using the global timer. (This global timer clock events is usually replaced by arch timer clock events for each of the cores.) When the A5 boots (via the A53), it should not use the global timer interrupts or write to the global timer registers. This is because even if there are four global comparators, the control bits for all four are in the same registers, and we would need to synchronize between the cpus. Instead, the global timer FRC (already started by the A53) should be used as the clock source, and one of the local timers which are not used by the A53 can be used for clock events on the A5. To support this hardware, add a compatible for the MCT as well as two new properties to describe the hardware-mandated sharing of the FRC and dedicating local timers to specific processors. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> Link: https://lore.kernel.org/r/20220609112738.359385-2-vincent.whitchurch@axis.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-09-20clocksource/drivers/sun4i: Add definition of clear interruptVictor Hassan1-1/+2
To prevent misunderstanding, use TIMER_IRQ_CLEAR instead of TIMER_IRQ_EN in function sun4i_timer_clear_interrupt. Signed-off-by: Victor Hassan <victor@allwinnertech.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220906052056.43404-1-victor@allwinnertech.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-09-20mtd: fix repeated word in commentwangjianli1-1/+1
Delete the redundant word 'in'. Signed-off-by: wangjianli <wangjianli@cdjrlc.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220908122229.10814-1-wangjianli@cdjrlc.com
2022-09-20Merge branch 'dsa-changes-for-multiple-cpu-ports-part-4'Paolo Abeni27-87/+1064
Vladimir Oltean says: ==================== DSA changes for multiple CPU ports (part 4) Those who have been following part 1: https://patchwork.kernel.org/project/netdevbpf/cover/20220511095020.562461-1-vladimir.oltean@nxp.com/ part 2: https://patchwork.kernel.org/project/netdevbpf/cover/20220521213743.2735445-1-vladimir.oltean@nxp.com/ and part 3: https://patchwork.kernel.org/project/netdevbpf/cover/20220819174820.3585002-1-vladimir.oltean@nxp.com/ will know that I am trying to enable the second internal port pair from the NXP LS1028A Felix switch for DSA-tagged traffic via "ocelot-8021q". This series represents the final part of that effort. We have: - the introduction of new UAPI in the form of IFLA_DSA_MASTER, the iproute2 patch for which is here: https://patchwork.kernel.org/project/netdevbpf/patch/20220904190025.813574-1-vladimir.oltean@nxp.com/ - preparation for LAG DSA masters in terms of suppressing some operations for masters in the DSA core that simply don't make sense when those masters are a bonding/team interface - handling all the net device events that occur between DSA and a LAG DSA master, including migration to a different DSA master when the current master joins a LAG, or the LAG gets destroyed - updating documentation - adding an implementation for NXP LS1028A, where things are insanely complicated due to hardware limitations. We have 2 tagging protocols: * the native "ocelot" protocol (NPI port mode). This does not support CPU ports in a LAG, and supports a single DSA master. The DSA master can be changed between eno2 (2.5G) and eno3 (1G), but all ports must be down during the changing process, and user ports assigned to the old DSA master will refuse to come up if the user requests that during a "transient" state. * the "ocelot-8021q" software-defined protocol, where the Ethernet ports connected to the CPU are not actually "god mode" ports as far as the hardware is concerned. So here, static assignment between user and CPU ports is possible by editing the PGID_SRC masks for the port-based forwarding matrix, and "CPU ports in a LAG" simply means "a LAG like any other". The series was regression-tested on LS1028A using the local_termination.sh kselftest, in most of the possible operating modes and tagging protocols. I have not done a detailed performance evaluation yet, but using LAG, is possible to exceed the termination bandwidth of a single CPU port in an iperf3 test with multiple senders and multiple receivers. v1 at: https://patchwork.kernel.org/project/netdevbpf/cover/20220830195932.683432-1-vladimir.oltean@nxp.com/ Previous (older) RFC at: https://lore.kernel.org/netdev/20220523104256.3556016-1-olteanv@gmail.com/ ==================== Link: https://lore.kernel.org/r/20220911010706.2137967-1-vladimir.oltean@nxp.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-09-20net: dsa: felix: add support for changing DSA masterVladimir Oltean4-3/+122
Changing the DSA master means different things depending on the tagging protocol in use. For NPI mode ("ocelot" and "seville"), there is a single port which can be configured as NPI, but DSA only permits changing the CPU port affinity of user ports one by one. So changing a user port to a different NPI port globally changes what the NPI port is, and breaks the user ports still using the old one. To address this while still permitting the change of the NPI port, require that the user ports which are still affine to the old NPI port are down, and cannot be brought up until they are all affine to the same NPI port. The tag_8021q mode ("ocelot-8021q") is more flexible, in that each user port can be freely assigned to one CPU port or to the other. This works by filtering host addresses towards both tag_8021q CPU ports, and then restricting the forwarding from a certain user port only to one of the two tag_8021q CPU ports. Additionally, the 2 tag_8021q CPU ports can be placed in a LAG. This works by enabling forwarding via PGID_SRC from a certain user port towards the logical port ID containing both tag_8021q CPU ports, but then restricting forwarding per packet, via the LAG hash codes in PGID_AGGR, to either one or the other. When we change the DSA master to a LAG device, DSA guarantees us that the LAG has at least one lower interface as a physical DSA master. But DSA masters can come and go as lowers of that LAG, and ds->ops->port_change_master() will not get called, because the DSA master is still the same (the LAG). So we need to hook into the ds->ops->port_lag_{join,leave} calls on the CPU ports and update the logical port ID of the LAG that user ports are assigned to. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-09-20docs: net: dsa: update information about multiple CPU portsVladimir Oltean2-6/+128
DSA now supports multiple CPU ports, explain the use cases that are covered, the new UAPI, the permitted degrees of freedom, the driver API, and remove some old "hanging fruits". Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-09-20net: dsa: allow masters to join a LAGVladimir Oltean6-10/+310
There are 2 ways in which a DSA user port may become handled by 2 CPU ports in a LAG: (1) its current DSA master joins a LAG ip link del bond0 && ip link add bond0 type bond mode 802.3ad ip link set eno2 master bond0 When this happens, all user ports with "eno2" as DSA master get automatically migrated to "bond0" as DSA master. (2) it is explicitly configured as such by the user # Before, the DSA master was eno3 ip link set swp0 type dsa master bond0 The design of this configuration is that the LAG device dynamically becomes a DSA master through dsa_master_setup() when the first physical DSA master becomes a LAG slave, and stops being so through dsa_master_teardown() when the last physical DSA master leaves. A LAG interface is considered as a valid DSA master only if it contains existing DSA masters, and no other lower interfaces. Therefore, we mainly rely on method (1) to enter this configuration. Each physical DSA master (LAG slave) retains its dev->dsa_ptr for when it becomes a standalone DSA master again. But the LAG master also has a dev->dsa_ptr, and this is actually duplicated from one of the physical LAG slaves, and therefore needs to be balanced when LAG slaves come and go. To the switch driver, putting DSA masters in a LAG is seen as putting their associated CPU ports in a LAG. We need to prepare cross-chip host FDB notifiers for CPU ports in a LAG, by calling the driver's ->lag_fdb_add method rather than ->port_fdb_add. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-09-20net: dsa: propagate extack to port_lag_joinVladimir Oltean11-28/+60
Drivers could refuse to offload a LAG configuration for a variety of reasons, mainly having to do with its TX type. Additionally, since DSA masters may now also be LAG interfaces, and this will translate into a call to port_lag_join on the CPU ports, there may be extra restrictions there. Propagate the netlink extack to this DSA method in order for drivers to give a meaningful error message back to the user. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-09-20net: dsa: suppress device links to LAG DSA mastersVladimir Oltean1-6/+8
These don't work (print a harmless error about the operation failing) and make little sense to have anyway, because when a LAG DSA master goes away, we will introduce logic to move our CPU port back to the first physical DSA master. So suppress these device links in preparation for adding support for LAG DSA masters. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-09-20net: dsa: suppress appending ethtool stats to LAG DSA mastersVladimir Oltean1-0/+9
Similar to the discussion about tracking the admin/oper state of LAG DSA masters, we have the problem here that struct dsa_port *cpu_dp caches a single pair of orig_ethtool_ops and netdev_ops pointers. So if we call dsa_master_setup(bond0, cpu_dp) where cpu_dp is also the dev->dsa_ptr of one of the physical DSA masters, we'd effectively overwrite what we cached from that physical netdev with what replaced from the bonding interface. We don't need DSA ethtool stats on the bonding interface when used as DSA master, it's good enough to have them just on the physical DSA masters, so suppress this logic. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-09-20net: dsa: don't keep track of admin/oper state on LAG DSA mastersVladimir Oltean1-0/+12
We store information about the DSA master's state in cpu_dp->master_admin_up and cpu_dp->master_oper_up, and this assumes a bijective association between a CPU port and a DSA master. However, when we have CPU ports in a LAG (and DSA masters in a LAG too), the way in which we set up things is that the physical DSA masters still have dev->dsa_ptr pointing to our cpu_dp, but the bonding/team device itself also has its dev->dsa_ptr pointing towards one of the CPU port structures (the first one). So logically speaking, that first cpu_dp can't keep track of both the physical master's admin/oper state, and of the bonding master's state. This isn't even needed; the reason why we keep track of the DSA master's state is to know when it is available for Ethernet-based register access. For that use case, we don't even need LAG; we just need to decide upon one of the physical DSA masters (if there is more than 1 available) and use that. This change suppresses dsa_tree_master_{admin,oper}_state_change() calls on LAG DSA masters (which will be supported in a future change), to allow the tracking of just physical DSA masters. Link: https://lore.kernel.org/netdev/628cc94d.1c69fb81.15b0d.422d@mx.google.com/ Suggested-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-09-20net: dsa: allow the DSA master to be seen and changed through rtnetlinkVladimir Oltean9-1/+372
Some DSA switches have multiple CPU ports, which can be used to improve CPU termination throughput, but DSA, through dsa_tree_setup_cpu_ports(), sets up only the first one, leading to suboptimal use of hardware. The desire is to not change the default configuration but to permit the user to create a dynamic mapping between individual user ports and the CPU port that they are served by, configurable through rtnetlink. It is also intended to permit load balancing between CPU ports, and in that case, the foreseen model is for the DSA master to be a bonding interface whose lowers are the physical DSA masters. To that end, we create a struct rtnl_link_ops for DSA user ports with the "dsa" kind. We expose the IFLA_DSA_MASTER link attribute that contains the ifindex of the newly desired DSA master. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-09-20net: dsa: introduce dsa_port_get_master()Vladimir Oltean10-34/+38
There is a desire to support for DSA masters in a LAG. That configuration is intended to work by simply enslaving the master to a bonding/team device. But the physical DSA master (the LAG slave) still has a dev->dsa_ptr, and that cpu_dp still corresponds to the physical CPU port. However, we would like to be able to retrieve the LAG that's the upper of the physical DSA master. In preparation for that, introduce a helper called dsa_port_get_master() that replaces all occurrences of the dp->cpu_dp->master pattern. The distinction between LAG and non-LAG will be made later within the helper itself. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-09-20net: introduce iterators over synced hw addressesVladimir Oltean1-0/+6
Some network drivers use __dev_mc_sync()/__dev_uc_sync() and therefore program the hardware only with addresses with a non-zero sync_cnt. Some of the above drivers also need to save/restore the address filtering lists when certain events happen, and they need to walk through the struct net_device :: uc and struct net_device :: mc lists. But these lists contain unsynced addresses too. To keep the appearance of an elementary form of data encapsulation, provide iterators through these lists that only look at entries with a non-zero sync_cnt, instead of filtering entries out from device drivers. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-09-20drm/ast: Fix video broken in some resolutions on ast2600Jammy Huang1-2/+8
Some cases are not handled well for ast2600. Signed-off-by: Jammy Huang <jammy_huang@aspeedtech.com> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/20220916091706.4559-1-jammy_huang@aspeedtech.com
2022-09-20drm/ast: Add resolution support for 1152x864@75Jammy Huang2-0/+16
Add 1152x864 into support list. Signed-off-by: Jammy Huang <jammy_huang@aspeedtech.com> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/20220916085058.3386-1-jammy_huang@aspeedtech.com
2022-09-20mtd: rawnand: fsl_elbc: Fix none ECC modePali Rohár1-12/+16
Commit f6424c22aa36 ("mtd: rawnand: fsl_elbc: Make SW ECC work") added support for specifying ECC mode via DTS and skipping autodetection. But it broke explicit specification of HW ECC mode in DTS as correct settings for HW ECC mode are applied only when NONE mode or nothing was specified in DTS file. Also it started aliasing NONE mode to be same as when ECC mode was not specified and disallowed usage of ON_DIE mode. Fix all these issues. Use autodetection of ECC mode only in case when mode was really not specified in DTS file by checking that ecc value is invalid. Set HW ECC settings either when HW ECC was specified in DTS or it was autodetected. And do not fail when ON_DIE mode is set. Fixes: f6424c22aa36 ("mtd: rawnand: fsl_elbc: Make SW ECC work") Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <kabel@kernel.org> Reviewed-by: Marek Behún <kabel@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220707184328.3845-1-pali@kernel.org
2022-09-20mtd: nand: bbt: Use the bitmap API to allocate bitmapsChristophe JAILLET1-5/+2
Use bitmap_zalloc()/bitmap_free() instead of hand-writing them. It is less verbose and it improves the semantic. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/b18c2b6711b8930f0dfb8318b5d19ef6e41f0f9a.1656864573.git.christophe.jaillet@wanadoo.fr
2022-09-20mtd: rawnand: intel: Use devm_platform_ioremap_resource_byname()Martin Blumenstingl1-6/+4
Switch from open-coded platform_get_resource_byname() and devm_ioremap_resource() to devm_platform_ioremap_resource_byname() where possible to simplify the code. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220702231227.1579176-9-martin.blumenstingl@googlemail.com
2022-09-20mtd: rawnand: intel: Remove unused clk_rate member from struct ebu_nandMartin Blumenstingl1-2/+0
The clk_rate member from struct ebu_nand is only written but never read. Remove this unused and unneeded member. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220702231227.1579176-8-martin.blumenstingl@googlemail.com
2022-09-20mtd: rawnand: intel: Remove unused nand_pa member from ebu_nand_csMartin Blumenstingl1-2/+0
The nand_pa member from struct ebu_nand_cs is only written but never read. Remove this unused and unneeded member. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220702231227.1579176-7-martin.blumenstingl@googlemail.com
2022-09-20mtd: rawnand: intel: Don't re-define NAND_DATA_IFACE_CHECK_ONLYMartin Blumenstingl1-2/+0
NAND_DATA_IFACE_CHECK_ONLY is already defined in include/linux/mtd/rawnand.h which is also included by the driver. Drop the re-definition from the intel-nand-controller driver. Fixes: 0b1039f016e8a3 ("mtd: rawnand: Add NAND controller support on Intel LGM SoC") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220702231227.1579176-6-martin.blumenstingl@googlemail.com
2022-09-20mtd: rawnand: intel: Remove undocumented compatible stringMartin Blumenstingl1-1/+0
The "intel,nand-controller" compatible string is not part of the dt-bindings. Remove it from the driver as it's not supposed to be used without any documentation for it. Fixes: 0b1039f016e8a3 ("mtd: rawnand: Add NAND controller support on Intel LGM SoC") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220702231227.1579176-5-martin.blumenstingl@googlemail.com
2022-09-20mtd: rawnand: intel: Read the chip-select line from the correct OF nodeMartin Blumenstingl1-2/+9
The chip select has to be read from the flash node which is a child node of the NAND controller. Fixes: 0b1039f016e8a3 ("mtd: rawnand: Add NAND controller support on Intel LGM SoC") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220702231227.1579176-4-martin.blumenstingl@googlemail.com
2022-09-20dt-bindings: mtd: intel: lgm-nand: Fix maximum chip select valueMartin Blumenstingl1-1/+1
The Intel LGM NAND IP only supports two chip selects: There's only two CS and ADDR_SEL register sets. Fix the maximum allowed chip select value according to the dt-bindings. Fixes: 2f9cea8eae44f5 ("dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC") Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220702231227.1579176-3-martin.blumenstingl@googlemail.com
2022-09-20dt-bindings: mtd: intel: lgm-nand: Fix compatible stringMartin Blumenstingl1-3/+3
The driver which was added at the same time as the dt-bindings uses the compatible string "intel,lgm-ebunand". Use the same compatible string also in the dt-bindings and rename the bindings file accordingly. Fixes: 2f9cea8eae44f5 ("dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220702231227.1579176-2-martin.blumenstingl@googlemail.com
2022-09-20loongarch: efi: enable generic EFI compressed bootArd Biesheuvel3-3/+13
Wire up the generic EFI zboot support for LoongArch64 Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
2022-09-20riscv: efi: enable generic EFI compressed bootArd Biesheuvel3-1/+12
Wire up the generic EFI zboot support for RISC-V. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
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