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Certain pins, like SDcard related, do not have functions and such should
not be required:
sdc1-clk-pins: 'function' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220912061746.6311-6-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Matching PMIC GPIOs config nodes within a '-state' node by '.*' pattern
does not work as expected because of linux,phandle in the DTB:
'pins' is a required property
'function' is a required property
'rx', 'tx' do not match any of the regexes: 'pinctrl-[0-9]+'
[[59]] is not of type 'object'
Make the schema stricter and expect such nodes to be followed with a
'-pins' suffix.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220912061746.6311-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Bindings example should be indented with 4-spaces.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Iskren Chernev <iskren.chernev@gmail.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220912061746.6311-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Require function on GPIOs (so not on SD card pins).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Iskren Chernev <iskren.chernev@gmail.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220912061746.6311-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Matching PMIC GPIOs config nodes within a '-state' node by '.*' pattern
does not work as expected because of linux,phandle in the DTB:
'pins' is a required property
'function' is a required property
'rx', 'tx' do not match any of the regexes: 'pinctrl-[0-9]+'
[[59]] is not of type 'object'
Make the schema stricter and expect such nodes to be followed with a
'-pins' suffix.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Iskren Chernev <iskren.chernev@gmail.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220912061746.6311-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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According to the datasheet [1] at page 377, 4-bit bus width is turned on by
bit 2 of the Bus Width Register. Thus the current bitmask is wrong: define
BUS_WIDTH_4 BIT(1)
BIT(1) does not work but BIT(2) works. This has been verified on real MOXA
hardware with FTSDC010 controller revision 1_6_0.
The corrected value of BUS_WIDTH_4 mask collides with: define BUS_WIDTH_8
BIT(2). Additionally, 8-bit bus width mode isn't supported according to the
datasheet, so let's remove the corresponding code.
[1]
https://bitbucket.org/Kasreyn/mkrom-uc7112lx/src/master/documents/FIC8120_DS_v1.2.pdf
Fixes: 1b66e94e6b99 ("mmc: moxart: Add MOXA ART SD/MMC driver")
Signed-off-by: Sergei Antonov <saproj@gmail.com>
Cc: Jonas Jensen <jonas.jensen@gmail.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20220907205753.1577434-1-saproj@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Some devices expose an ultra-low-power (ULP) mode entry mask for
each channel. If the mask is set, the device cannot enter ULP so
long as the corresponding channel remains in an active state.
The vendor has advised setting the mask for any disabled channel.
To accommodate this suggestion, initially set all masks and then
clear them only if specified in the device tree.
Fixes: e505edaedcb9 ("Input: add support for Azoteq IQS7222A/B/C")
Signed-off-by: Jeff LaBundy <jeff@labundy.com>
Link: https://lore.kernel.org/r/20220908131548.48120-8-jeff@labundy.com
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
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Add a check to prevent sending undefined events, which ultimately
map to SYN_REPORT.
Fixes: e505edaedcb9 ("Input: add support for Azoteq IQS7222A/B/C")
Signed-off-by: Jeff LaBundy <jeff@labundy.com>
Link: https://lore.kernel.org/r/20220908131548.48120-7-jeff@labundy.com
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
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According to the datasheets, writing only 0xFF is sufficient to
elicit a communication window. Remove the superfluous 0x00 from
the force communication command.
Fixes: e505edaedcb9 ("Input: add support for Azoteq IQS7222A/B/C")
Signed-off-by: Jeff LaBundy <jeff@labundy.com>
Link: https://lore.kernel.org/r/20220908131548.48120-6-jeff@labundy.com
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
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When data crc occurs, the kernel will panic because host->cmd is null.
Signed-off-by: Wenchao Chen <wenchao.chen@unisoc.com>
Fixes: efe8f5c9b5e1 ("mmc: sdhci: Capture eMMC and SD card errors")
Cc: stable@vger.kernel.org
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20220907035847.13783-1-wenchao.chen666@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Clang warns:
drivers/power/supply/bq25890_charger.c:625:40: error: implicit conversion from enumeration type 'enum bq25890_fields' to different enumeration type 'enum bq25890_table_ids' [-Werror,-Wenum-conversion]
lval = bq25890_find_idx(val->intval, F_IINLIM);
~~~~~~~~~~~~~~~~ ^~~~~~~~
1 error generated.
Use the proper value from the right enumerated type, TBL_IINLIM, so
there is no more implcit conversion. The numerical values of F_IINLIM
and TBL_IINLIM happen to be the same so there is no change in behavior.
Fixes: 4a4748f28b0b ("power: supply: bq25890: Add support for setting IINLIM")
Link: https://github.com/ClangBuiltLinux/linux/issues/1707
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Most mmc blocks contain two pinctrls, default and sleep. But then
dt-schema complains about pinctrl-1 not being defined.
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Link: https://lore.kernel.org/r/20220910143213.477261-6-iskren.chernev@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Add rockchip,rk3128-dw-mshc compatible string.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/f2cb42c8-3664-a2d5-074d-5c9a10c693e8@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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The SDHI blocks on Renesas R-Car and RZ/G2 SoCs make use of IOMMU.
This patch fixes the below dtbs_check warnings:
arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dtb: mmc@ee100000: Unevaluated properties are not allowed ('iommus' was unexpected)
From schema: Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220831214314.7794-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Return the value cqhci_init() directly instead of storing it in another
redundant variable.
Reported-by: Zeal Robot <zealci@zte.com.cn>
Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20220830083349.276709-1-ye.xingchen@zte.com.cn
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Add SDIO interrupt support. Successfully tested on a S905X4-based
system (V3 register layout) with a BRCM4334 SDIO wifi module
(brcmfmac driver).
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Link: https://lore.kernel.org/r/27bffe3c-e579-3581-95e8-2587733487d2@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Constant IRQ_EN_MASK has no user currently. In preparation of adding
SDIO interrupt support, revive it and adjust it to our needs.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Link: https://lore.kernel.org/r/8056622f-2adf-4763-7423-9ccdf4ca78e1@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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dma_map_sg return 0 on error.
Signed-off-by: Jack Wang <jinpu.wang@ionos.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20220825074008.33349-3-jinpu.wang@ionos.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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dma_map_sg return 0 on error, also change the type for dma_len
from int to unsigned int.
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jack Wang <jinpu.wang@ionos.com>
Link: https://lore.kernel.org/r/20220825074008.33349-2-jinpu.wang@ionos.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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If clk_prepare_enable() fails, there is no point in calling
clk_disable_unprepare() in the error handling path.
Move the out_clk label at the right place.
Fixes: b6507596dfd6 ("MIPS: Alchemy: au1xmmc: use clk framework")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/21d99886d07fa7fcbec74992657dabad98c935c4.1661412818.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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dma-coherent is mentioned in almost all TI K3 platform mmc
nodes. Fix warning generated due to its missing match in
yaml schema.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220819190729.32358-3-a-nandan@ti.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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The delay parameter isn't set by any user, therefore simplify the code
and switch to the basic workqueue API w/o delay support. This also
reduces the size of struct mmc_host.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Link: https://lore.kernel.org/r/13d8200a-e2a8-d907-38ce-a16fc5ce14aa@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Document the compatible for SDHCI on SM6115.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220815100952.23795-4-a39.skl@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Currently, status is "Supported" not "Maintained" for SDHCI and CQHCI.
Amend MAINTAINERS accordingly.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20220815105905.65188-1-adrian.hunter@intel.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Mails to Piotr bounce with a :550 5.1.1 User Unknown and the last
mention of him on lore is the orphaning of Cadence NFC drivers.
Remove him from the binding too.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220811204024.182453-1-mail@conchuod.ie
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Add a compatible string for the MT6795 SoC's mtk-sd mmc controllers.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220729104441.39177-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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spi-max-frequency comes from spi-peripheral-props.yaml.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220727164202.385531-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Bayhub chips have better compatibility support for SDR50 than DDR50
and both mode have the same R/W performance when clock frequency >= 100MHz.
Disable DDR50 mode and use SDR50 instead.
Signed-off-by: Chevron Li <chevron.li@bayhubtech.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20220729100524.387-1-chevron.li@bayhubtech.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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As Ulf noted in [1], the maximum operating frequency
documented in the mmc-controller device-tree bindings
should be updated to the maximum frequency supported
by the mmc controller(s).
Without this fix in place, the 'make dtbs_check' reports
issues with 'max-frequency' value for ipq8074 sdhci node:
arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb: mmc@7824900:
max-frequency:0:0: 384000000 is greater than the maximum of 200000000
[1]. https://www.spinics.net/lists/kernel/msg4442049.html
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220726084520.2895454-1-bhupesh.sharma@linaro.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Use regmap_read_poll_timeout to poll I2S_CLR.
It also fixes the 'rockchip-i2s ff070000.i2s; fail to clear' when
the read of I2S_CLR exceeds the retry limit.
Fixes: 0ff9f8b9f592 ("ASoC: rockchip: i2s: Fix error code when fail to read I2S_CLR")
Signed-off-by: Judy Hsiao <judyhsiao@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Link: https://lore.kernel.org/r/20220914031234.2250298-1-judyhsiao@chromium.org
Signed-off-by: Mark Brown <broonie@kernel.org>
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Since commit 2848d34c3ba1 ("ASoC: tas2562: Fix mute/unmute") the
following build warning is seen:
sound/soc/codecs/tas2562.c:442:13: warning: variable 'ret' set but not used [-Wunused-but-set-variable]
Fix the warning by returning the 'ret' variable.
Fixes: 2848d34c3ba1 ("ASoC: tas2562: Fix mute/unmute")
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Martin PoviĊĦer <povik+lin@cutebit.org>
Link: https://lore.kernel.org/r/20220913231706.516849-1-festevam@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Pull devicetree fixes from Rob Herring:
- Update some stale binding maintainer emails
- Fix property name error in apple,aic binding
- Add missing param to of_dma_configure_id() stub
- Fix an off-by-one error in unflatten_dt_nodes()
* tag 'devicetree-fixes-for-6.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
dt-bindings: pinctrl: qcom: drop non-working codeaurora.org emails
dt-bindings: power: qcom,rpmpd: drop non-working codeaurora.org emails
dt-bindings: apple,aic: Fix required item "apple,fiq-index" in affinity description
dt-bindings: interconnect: fsl,imx8m-noc: drop Leonard Crestez
of/device: Fix up of_dma_configure_id() stub
MAINTAINERS: Update email of Neil Armstrong
of: fdt: fix off-by-one error in unflatten_dt_nodes()
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The Dell Precision 5570 uses the same 4-speakers-on-ALC289 just like the
previous Precision 5560. I replicated that patch onto this one, and can
confirm that the audio is much better (the woofers are now working);
I've tested it on my Dell Precision 5570.
Signed-off-by: Callum Osmotherly <callum.osmotherly@gmail.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/YyGbWM5wEoFMbW2v@piranha
Signed-off-by: Takashi Iwai <tiwai@suse.de>
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Define the memory region on RK3399 VOPs containing the gamma LUT at
base+0x2000.
Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Tested-by: Linus Heckemann <git@sphalerite.org>
Link: https://lore.kernel.org/r/20211019215843.42718-4-sigmaris@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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To 2.39
Signed-off-by: Steve French <stfrench@microsoft.com>
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Add missing spinlock to protect updates on tcon refcount in
cifs_put_tcon().
Fixes: d7d7a66aacd6 ("cifs: avoid use of global locks for high contention data")
Signed-off-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Reviewed-by: Ronnie Sahlberg <lsahlber@redhat.com>
Signed-off-by: Steve French <stfrench@microsoft.com>
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Add the device tree nodes to enable video output on the Station M2.
Enable the GPU and HDMI nodes and fix the GPU regulator range.
Signed-off-by: Furkan Kardame <f.kardame@manjaro.org>
Link: https://lore.kernel.org/r/20220627202208.45770-1-f.kardame@manjaro.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add rockchip,rk3128-grf compatible string.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/fddc23ff-0c87-4998-1bdf-4dbfa4c74046@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add rockchip,rk3128-pmu compatible string.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/faf2b30e-1a1a-0dc1-04ce-f40e5d758718@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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The mode_valid field in drm_connector_helper_funcs is expected to be of
type:
enum drm_mode_status (* mode_valid) (struct drm_connector *connector,
struct drm_display_mode *mode);
The mismatched return type breaks forward edge kCFI since the underlying
function definition does not match the function hook definition.
The return type of cdn_dp_connector_mode_valid should be changed from
int to enum drm_mode_status.
Reported-by: Dan Carpenter <error27@gmail.com>
Link: https://github.com/ClangBuiltLinux/linux/issues/1703
Cc: llvm@lists.linux.dev
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Reviewed-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20220913205555.155149-1-nhuck@google.com
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Add a driver to support the PLLs in PolarFire SoC's Clock Conditioning
Circuitry, an instance of which is located in each ordinal corner of
the FPGA. Only get_rate() is supported as these clocks are intended to
be statically configured by the FPGA design. Currently, the DLLs are
not supported by this driver. For more information on the hardware, see
"PolarFire SoC FPGA Clocking Resources" in the link below.
Link: https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220908143651.1252601-5-conor.dooley@microchip.com
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Each Clock Conditioning Circuitry block contains 2 PLLs and 2 DLLs.
The PLLs have 4 outputs each and the DLLs 2. Add 16 new IDs covering
these clocks. For more information on the CCC hardware, see the
"PolarFire SoC FPGA Clocking Resources" document at the link below.
Link: https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220908143651.1252601-4-conor.dooley@microchip.com
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On PolarFire SoC there are 4 PLL/DLL blocks, located in each of the
ordinal corners of the chip, which our documentation refers to as
"Clock Conditioning Circuitry". PolarFire SoC is an FPGA, these are
highly configurable & many of the input clocks are optional.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220908143651.1252601-3-conor.dooley@microchip.com
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The filename for a binding is supposed to match the first compatible,
but the mpfs-clkcfg file did not follow this policy. Rename it to match
so that when other mpfs clock bindings are added things make more sense.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220908143651.1252601-2-conor.dooley@microchip.com
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Padmarao wrote the driver in its original, pre upstream form.
Daire & myself have been responsible for getting it upstreamable and
subsequent development.
Move Daire out of the blurb & into a MODULE_AUTHOR entry & add entries
for myself and Padmarao.
While we are at it, convert the MODULE_LICENSE field to its preferred
form of "GPL".
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-15-conor.dooley@microchip.com
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With the reset code moved to the recently added reset controller, there
is no need for custom ops any longer. Remove the custom ops and the
custom struct by converting to a clk_gate.
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-14-conor.dooley@microchip.com
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The cfg_clk struct is now just a redefinition of the clk_divider struct
with custom implentations of the ops, that implement an extra level of
redirection. Remove the custom struct and replace it with clk_divider.
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-13-conor.dooley@microchip.com
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The register functions are now comprised of only a single operation
each and no longer add anything to the driver. Delete them.
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-12-conor.dooley@microchip.com
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The control reg addresses are known when the clocks are registered, so
we can, instead of assigning a base pointer to the structs, assign the
control reg addresses directly. Accordingly, remove the interim
variables used during reads/writes to those registers.
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-11-conor.dooley@microchip.com
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The id and offset are the only thing differentiating the clock structs
from "regular" clock structures. On the pretext of converting to more
normal structures, move the id and offset out of the clock structs and
into the hw structs instead.
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-10-conor.dooley@microchip.com
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Krzysztof Kozlowski
Sergei Antonov
Jeff LaBundy
Wenchao Chen
Nathan Chancellor
Iskren Chernev
Johan Jonker
Lad Prabhakar
ye xingchen
Heiner Kallweit
Jack Wang
Christophe JAILLET
Apurva Nandan
Adam Skladowski
Adrian Hunter
Conor Dooley
AngeloGioacchino Del Regno
Chevron Li
Bhupesh Sharma
Judy Hsiao
Fabio Estevam
Linus Torvalds
Callum Osmotherly
Hugh Cole-Baker
Steve French
Paulo Alcantara
Furkan Kardame
Nathan Huckleberry