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2013-09-17ARM: dts: Document the CCI PMU DT bindingsPunit Agrawal1-1/+47
The CCI PMU can profile bus transactions at the master and slave interfaces of the CCI. The PMU can be used to observe an aggregated view of the bus traffic between the various components connected to the CCI. Introduce a binding for the CCI PMU. The PMU node will be a sub-node of the CCI node. Cc: devicetree@vger.kernel.org Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2013-09-17ARM: dts: Improve CCI bindings documentationPunit Agrawal1-3/+9
Improve the description of the value types used in the CCI binding. Cc: devicetree@vger.kernel.org Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2013-05-29drivers: bus: add ARM CCI supportLorenzo Pieralisi1-0/+172
On ARM multi-cluster systems coherency between cores running on different clusters is managed by the cache-coherent interconnect (CCI). It allows broadcasting of TLB invalidates and memory barriers and it guarantees cache coherency at system level through snooping of slave interfaces connected to it. This patch enables the basic infrastructure required in Linux to handle and programme the CCI component. Non-local variables used by the CCI management functions called by power down function calls after disabling the cache must be flushed out to main memory in advance, otherwise incoherency of those values may occur if they are sitting in the cache of some other CPU when power down functions execute. Driver code ensures that relevant data structures are flushed from inner and outer caches after the driver probe is completed. CCI slave port resources are linked to set of CPUs through bus masters phandle properties that link the interface resources to masters node in the device tree. Documentation describing the CCI DT bindings is provided with the patch. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>