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2018-06-15docs: Fix more broken referencesMauro Carvalho Chehab1-4/+4
As we move stuff around, some doc references are broken. Fix some of them via this script: ./scripts/documentation-file-ref-check --fix Manually checked that produced results are valid. Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Takashi Iwai <tiwai@suse.de> Acked-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Miguel Ojeda <miguel.ojeda.sandonis@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org> Acked-by: Jonathan Corbet <corbet@lwn.net>
2017-11-09dt-bindings: Remove leading zeros from bindings notationMarco Franchi1-1/+1
Improve the binding example by removing all the leading zeros to fix the following dtc warnings: Warning (unit_address_format): Node /XXX unit name should not have leading 0s Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find ./Documentation/devicetree/bindings "*.txt"` Some unnecessary changes were manually fixed. Signed-off-by: Marco Franchi <marco.franchi@nxp.com> Signed-off-by: Rob Herring <robh@kernel.org>
2016-09-16drivers: clk: st: Handle clk synchronous mode for video clocksGabriel Fernandez1-0/+2
This patch configures the semi-synchronous mode of the video clocks of clkgenD2. Signed-off-by: Olivier Bideau <olivier.bideau@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-16drivers: clk: st: Add clock propagation for audio clocksGabriel Fernandez1-0/+2
This patch allows fine tuning of the quads FS for audio clocks accuracy. Signed-off-by: Olivier Bideau <olivier.bideau@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-16drivers: clk: st: Simplify clock binding of STiH4xx platformsGabriel Fernandez4-11/+10
This patch reworks the clock binding to avoid too much detail in DT. Now we have only compatible string per type of clock (remark from Rob https://lkml.org/lkml/2016/5/25/492) Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-16drivers: clk: st: Remove stih415-416 clock supportGabriel Fernandez7-235/+36
STiH415 and STiH416 platforms are no longer used. these platforms will be deprecated for the next kernel. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-25Documentation: dt: clock: fix spelling mistakesEric Engestrom1-1/+1
Signed-off-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Heiko Stuebner <heiko@sntech.de> [robh: s/describe/described/] Signed-off-by: Rob Herring <robh@kernel.org>
2015-10-08drivers: clk: st: Correct the pll-type for A9 for stih418Gabriel Fernandez1-0/+1
Add support for new PLL-type for stih418 A9-PLL. Currently the 407_A9_PLL type being used, it is corrected with this patch 4600c28 PLL allows to reach higher frequencies so its programming algorithm is extended. Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-22ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_xGabriel Fernandez1-2/+2
Use a generic name for this kind of PLL Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2014-10-29clk: st: Spelling s/stucture/structure/Geert Uytterhoeven1-1/+1
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2014-07-28clk: st: Adds Flexgen clock bindingGabriel FERNANDEZ2-0/+124
A Flexgen structure is composed by: - a clock cross bar (represented by a mux element) - a pre and final dividers (represented by a divider and gate elements) Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-28clk: st: Update ST clock binding documentationGabriel FERNANDEZ7-68/+94
Naming convention was changed in dts file but the clock binding documentation hasn't been updated. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-25clk: st: Adds quadfs clock bindingGabriel FERNANDEZ1-0/+45
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-25clk: st: Adds clockgen-vcc and clockgen-mux clock bindingGabriel FERNANDEZ2-0/+89
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-25clk: st: Adds clockgen clock bindingGabriel FERNANDEZ1-0/+48
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-25clk: st: Adds divmux and prediv clock bindingGabriel FERNANDEZ3-0/+168
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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