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2020-06-10Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxLinus Torvalds19-124/+694
Pull clk updates from Stephen Boyd: "This time around we have four lines of diff in the core framework, removing a function that isn't used anymore. Otherwise the main new thing for the common clk framework is that it is selectable in the Kconfig language now. Hopefully this will let clk drivers and clk consumers be testable on more than the architectures that support the clk framework. The goal is to introduce some Kunit tests for the framework. Outside of the core framework we have the usual set of various driver updates and non-critical fixes. The dirstat shows that the new Baikal-T1 driver is the largest addition this time around in terms of lines of code. After that the x86 (Intel), Qualcomm, and Mediatek drivers introduce many lines to support new or upcoming SoCs. After that the dirstat shows the usual suspects working on their SoC support by fixing minor bugs, correcting data and converting some of their DT bindings to YAML. Core: - Allow the COMMON_CLK config to be selectable New Drivers: - Clk driver for Baikal-T1 SoCs - Mediatek MT6765 clock support - Support for Intel Agilex clks - Add support for X1830 and X1000 Ingenic SoC clk controllers - Add support for the new Renesas RZ/G1H (R8A7742) SoC - Add support for Qualcomm's MSM8939 Generic Clock Controller Updates: - Support IDT VersaClock 5P49V5925 - Bunch of updates for HSDK clock generation unit (CGU) driver - Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs - Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver - Enable supply regulators for GPU gdscs on Qualcomm SoCs - Add support for Si5342, Si5344 and Si5345 chips - Support custom flags in Xilinx zynq firmware - Various small fixes to the Xilinx clk driver - A single minor rounding fix for the legacy Allwinner clock support - A few patches from Abel Vesa as preparation of adding audiomix clock support on i.MX - A couple of cleanups from Anson Huang for i.MX clk-sscg-pll and clk-pllv3 drivers - Drop dependency on ARM64 for i.MX8M clock driver, to support aarch32 mode on aarch64 hardware - A series from Peng Fan to improve i.MX8M clock drivers, using composite clock for core and bus clk slice - Set a better parent clock for flexcan on i.MX6UL to support CiA102 defined bit rates - A couple changes for EMC frequency scaling on Tegra210 - Support for CPU frequency scaling on Tegra20/Tegra30 - New clk gate for CSI test pattern generator on Tegra210 - Regression fixes for Samsung exynos542x and exynos5433 SoCs - Use of fallthrough; attribute for Samsung s3c24xx - Updates and fixup HDMI and video clocks on Meson8b - Fixup reset polarity on Meson8b - Fix GPU glitch free mux switch on Meson gx and g12 - A minor fix for the currently unused suspend/resume handling on Renesas RZ/A1 and RZ/A2 - Two more conversions of Renesas DT bindings to json-schema - Add support for the USB 2.0 clock selector on Renesas R-Car M3-W+" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (155 commits) clk: mediatek: Remove ifr{0,1}_cfg_regs structures clk: baikal-t1: remove redundant assignment to variable 'divider' clk: baikal-t1: fix spelling mistake "Uncompatible" -> "Incompatible" dt-bindings: clock: Add a missing include to MMP Audio Clock binding dt: Add bindings for IDT VersaClock 5P49V5925 clk: vc5: Add support for IDT VersaClock 5P49V6965 clk: Add Baikal-T1 CCU Dividers driver clk: Add Baikal-T1 CCU PLLs driver dt-bindings: clk: Add Baikal-T1 CCU Dividers binding dt-bindings: clk: Add Baikal-T1 CCU PLLs binding clk: mediatek: assign the initial value to clk_init_data of mtk_mux clk: mediatek: Add MT6765 clock support clk: mediatek: add mt6765 clock IDs dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC CLK: HSDK: CGU: add support for 148.5MHz clock CLK: HSDK: CGU: support PLL bypassing CLK: HSDK: CGU: check if PLL is bypassed first clk: clk-si5341: Add support for the Si5345 series ...
2020-06-09dt-bindings: clock: Add a missing include to MMP Audio Clock bindingLubomir Rintel1-0/+1
The include file for input clock in the example was missing, breaking the validation. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reported-by: Rob Herring <robh+dt@kernel.org> Link: https://lore.kernel.org/r/20200605065258.567858-1-lkundrak@v3.sk Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-03dt-bindings: clock: Add documentation for X1830 bindings.周琰杰 (Zhou Yanjie)1-0/+2
Add documentation for the clock bindings of the X1830 Soc from Ingenic. Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Signed-off-by: Rob Herring <robh@kernel.org>
2020-06-01Merge branches 'clk-vc5', 'clk-hsdk', 'clk-mediatek' and 'clk-baikal' into clk-nextStephen Boyd3-0/+320
- Support IDT VersaClock 5P49V5925 - Bunch of updates for HSDK clock generation unit (CGU) driver - New clk driver for Baikal-T1 SoCs * clk-vc5: dt: Add bindings for IDT VersaClock 5P49V5925 clk: vc5: Add support for IDT VersaClock 5P49V6965 * clk-hsdk: CLK: HSDK: CGU: add support for 148.5MHz clock CLK: HSDK: CGU: support PLL bypassing CLK: HSDK: CGU: check if PLL is bypassed first * clk-mediatek: clk: mediatek: assign the initial value to clk_init_data of mtk_mux clk: mediatek: Add MT6765 clock support clk: mediatek: add mt6765 clock IDs dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC * clk-baikal: clk: Add Baikal-T1 CCU Dividers driver clk: Add Baikal-T1 CCU PLLs driver dt-bindings: clk: Add Baikal-T1 CCU Dividers binding dt-bindings: clk: Add Baikal-T1 CCU PLLs binding
2020-06-01Merge branches 'clk-mmp', 'clk-intel', 'clk-ingenic', 'clk-qcom' and 'clk-silabs' into clk-nextStephen Boyd8-23/+180
- Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs - Add support for X1830 and X1000 Ingenic SoC clk controllers - Add support for Qualcomm's MSM8939 Generic Clock Controller - Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver - Enable supply regulators for GPU gdscs on Qualcomm SoCs - Add support for Si5342, Si5344 and Si5345 chips * clk-mmp: clk: mmp2: Add audio clock controller driver dt-bindings: clock: Add Marvell MMP Audio Clock Controller binding clk: mmp2: Add support for power islands dt-bindings: marvell,mmp2: Add ids for the power domains dt-bindings: clock: Make marvell,mmp2-clock a power controller clk: mmp2: Add the audio clock clk: mmp2: Add the I2S clocks clk: mmp2: Rename mmp2_pll_init() to mmp2_main_clk_init() clk: mmp2: Move thermal register defines up a bit dt-bindings: marvell,mmp2: Add clock id for the Audio clock dt-bindings: marvell,mmp2: Add clock id for the I2S clocks clk: mmp: frac: Allow setting bits other than the numerator/denominator clk: mmp: frac: Do not lose last 4 digits of precision * clk-intel: clk: intel: remove redundant initialization of variable rate64 clk: intel: Add CGU clock driver for a new SoC dt-bindings: clk: intel: Add bindings document & header file for CGU * clk-ingenic: clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unused clk: X1000: Add FIXDIV for SSI clock of X1000. dt-bindings: clock: Add and reorder ABI for X1000. clk: Ingenic: Add CGU driver for X1830. dt-bindings: clock: Add X1830 clock bindings. clk: Ingenic: Adjust cgu code to make it compatible with X1830. clk: Ingenic: Remove unnecessary spinlock when reading registers. * clk-qcom: clk: qcom: Add missing msm8998 ufs_unipro_core_clk_src dt-bindings: clock: Add YAML schemas for QCOM A53 PLL clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller clk: qcom: gcc: Add support for Secure control source clock dt-bindings: clock: Add gcc_sec_ctrl_clk_src clock ID clk: qcom: gcc: Add support for a new frequency for SC7180 clk: qcom: Add DT bindings for MSM8939 GCC clk: qcom: gcc: Add missing UFS clocks for SM8150 clk: qcom: gcc: Add GPU and NPU clocks for SM8150 clk: qcom: mmcc-msm8996: Properly describe GPU_GX gdsc clk: qcom: gdsc: Handle GDSC regulator supplies clk: qcom: msm8916: Fix the address location of pll->config_reg * clk-silabs: clk: clk-si5341: Add support for the Si5345 series
2020-06-01Merge branches 'clk-unisoc', 'clk-trivial', 'clk-bcm', 'clk-st' and 'clk-ast2600' into clk-nextStephen Boyd1-0/+1
* clk-unisoc: clk: sprd: add mipi_csi_xx gate clocks clk: sprd: add dt-bindings include for mipi_csi_xx clocks dt-bindings: clk: sprd: add mipi_csi_xx clocks for SC9863A clk: sprd: check its parent status before reading gate clock clk: sprd: return correct type of value for _sprd_pll_recalc_rate clk: sprd: mark the local clock symbols static * clk-trivial: clk: versatile: remove redundant assignment to pointer clk clk: clk-xgene: Fix a typo in Kconfig clk: Remove unused inline function clk_debug_reparent * clk-bcm: clk: bcm2835: Constify struct debugfs_reg32 clk: bcm2835: Remove casting to bcm2835_clk_register clk: bcm2835: Fix return type of bcm2835_register_gate * clk-st: clk: clk-flexgen: fix clock-critical handling * clk-ast2600: clk: ast2600: Fix AHB clock divider for A1
2020-06-01Merge branches 'clk-tegra', 'clk-imx', 'clk-zynq', 'clk-socfpga', 'clk-at91' and 'clk-ti' into clk-nextStephen Boyd1-0/+46
- Support custom flags in Xilinx zynq firmware - Various small fixes to the Xilinx clk driver - Support for Intel Agilex clks * clk-tegra: clk: tegra: Add Tegra210 CSI TPG clock gate clk: tegra30: Use custom CCLK implementation clk: tegra20: Use custom CCLK implementation clk: tegra: cclk: Add helpers for handling PLLX rate changes clk: tegra: pll: Add pre/post rate-change hooks clk: tegra: Add custom CCLK implementation clk: tegra: Remove the old emc_mux clock for Tegra210 clk: tegra: Implement Tegra210 EMC clock clk: tegra: Export functions for EMC clock scaling clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210 clk: tegra: Rename Tegra124 EMC clock source file dt-bindings: clock: tegra: Add clock ID for CSI TPG clock * clk-imx: clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice clk: imx: add imx8m_clk_hw_composite_bus clk: imx: add mux ops for i.MX8M composite clk clk: imx8m: migrate A53 clk root to use composite core clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code clk: imx8mp: Define gates for pll1/2 fixed dividers clk: imx: imx8mp: fix pll mux bit clk: imx8m: drop clk_hw_set_parent for A53 dt-bindings: clocks: imx8mp: Add ids for audiomix clocks clk: imx: Add helpers for passing the device as argument clk: imx: pll14xx: Add the device as argument when registering clk: imx: gate2: Allow single bit gating clock clk: imx: clk-pllv3: Use readl_relaxed_poll_timeout() for PLL lock wait clk: imx: clk-sscg-pll: Remove unnecessary blank lines clk: imx: drop the dependency on ARM64 for i.MX8M clk: imx7ulp: make it easy to change ARM core clk clk: imx: imx6ul: change flexcan clock to support CiA bitrates * clk-zynq: clk: zynqmp: Make zynqmp_clk_get_max_divisor static clk: zynqmp: Update fraction clock check from custom type flags clk: zynqmp: Add support for custom type flags clk: zynqmp: fix memory leak in zynqmp_register_clocks clk: zynqmp: Fix invalid clock name queries clk: zynqmp: Fix divider2 calculation clk: zynqmp: Limit bestdiv with maxdiv * clk-socfpga: clk: socfpga: agilex: add clock driver for the Agilex platform dt-bindings: documentation: add clock bindings information for Agilex clk: socfpga: add const to _ops data structures clk: socfpga: remove clk_ops enable/disable methods clk: socfpga: stratix10: use new parent data scheme * clk-at91: clk: at91: allow setting all PMC clock parents via DT clk: at91: allow setting PCKx parent via DT clk: at91: optimize pmc data allocation clk: at91: pmc: decrement node's refcount clk: at91: pmc: do not continue if compatible not located clk: at91: Add peripheral clock for PTC * clk-ti: clk: ti: dra7: remove two unused symbols clk: ti: dra7xx: fix RNG clock parent clk: ti: dra7xx: mark MCAN clock as DRA76x only clk: ti: dra7xx: fix gpu clkctrl parent clk: ti: omap5: Add proper parent clocks for l4-secure clocks clk: ti: omap4: Add proper parent clocks for l4-secure clocks clk: ti: composite: fix memory leak
2020-05-30dt: Add bindings for IDT VersaClock 5P49V5925Adam Ford1-0/+1
IDT VersaClock 5 5P49V6965 has 5 clock outputs, 4 fractional dividers. Signed-off-by: Adam Ford <aford173@gmail.com> Link: https://lkml.kernel.org/r/20200404161537.2312297-2-aford173@gmail.com Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-30dt-bindings: clk: Add Baikal-T1 CCU Dividers bindingSerge Semin1-0/+188
After being gained by the CCU PLLs the signals must be transformed to be suitable for the clock-consumers. This is done by a set of dividers embedded into the CCU. A first block of dividers is used to create reference clocks for AXI-bus of high-speed peripheral IP-cores of the chip. The second block dividers alter the PLLs output signals to be then consumed by SoC peripheral devices. Both block DT nodes are ordinary clock-providers with standard set of properties supported. But in addition to that each clock provider can be used to reset the corresponding clock domain. This makes the AXI-bus and System Devices CCU DT nodes to be also reset-providers. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Arnd Bergmann <arnd@arndb.de> Cc: linux-mips@vger.kernel.org Link: https://lore.kernel.org/r/20200526222056.18072-3-Sergey.Semin@baikalelectronics.ru Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-30dt-bindings: clk: Add Baikal-T1 CCU PLLs bindingSerge Semin1-0/+131
Baikal-T1 Clocks Control Unit is responsible for transformation of a signal coming from an external oscillator into clocks of various frequencies to propagate them then to the corresponding clocks consumers (either individual IP-blocks or clock domains). In order to create a set of high-frequency clocks the external signal is firstly handled by the embedded into CCU PLLs. So the corresponding dts-node is just a normal clock-provider node with standard set of properties. Note as being part of the Baikal-T1 System Controller its DT node is supposed to be a child the system controller node. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Arnd Bergmann <arnd@arndb.de> Cc: linux-mips@vger.kernel.org Link: https://lore.kernel.org/r/20200526222056.18072-2-Sergey.Semin@baikalelectronics.ru Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-29dt-bindings: clock: Convert i.MX8QXP LPCG to json-schemaAnson Huang2-51/+73
Convert the i.MX8QXP LPCG binding to DT schema format using json-schema. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> [robh: add additionalProperties] Signed-off-by: Rob Herring <robh@kernel.org>
2020-05-28clk: clk-si5341: Add support for the Si5345 seriesMike Looijmans1-1/+10
Add support for the Si5342, Si5344 and Si5345 chips. These are equivalent to the Si5341 family, but with more clock input options (which are not supported yet by this driver). Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Link: https://lkml.kernel.org/r/20200507061544.11388-1-mike.looijmans@topic.nl Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-28dt-bindings: clock: Convert i.MX1 clock to json-schemaAnson Huang2-26/+51
Convert the i.MX1 clock binding to DT schema format using json-schema. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Rob Herring <robh@kernel.org>
2020-05-28dt-bindings: clock: Convert i.MX21 clock to json-schemaAnson Huang2-27/+51
Convert the i.MX21 clock binding to DT schema format using json-schema, can NOT find any CCM interrupt info from reference manual and DT file, so interrupts property is removed from original binding doc. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Rob Herring <robh@kernel.org>
2020-05-28dt-bindings: clock: Convert i.MX25 clock to json-schemaAnson Huang2-160/+186
Convert the i.MX25 clock binding to DT schema format using json-schema. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Rob Herring <robh@kernel.org>
2020-05-28dt-bindings: clock: Convert i.MX27 clock to json-schemaAnson Huang2-27/+55
Convert the i.MX27 clock binding to DT schema format using json-schema. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Rob Herring <robh@kernel.org>
2020-05-28dt-bindings: clock: Convert i.MX23 clock to json-schemaAnson Huang2-70/+92
Convert the i.MX23 clock binding to DT schema format using json-schema. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Rob Herring <robh@kernel.org>
2020-05-28dt-bindings: clock: Convert i.MX28 clock to json-schemaAnson Huang2-93/+115
Convert the i.MX28 clock binding to DT schema format using json-schema. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Rob Herring <robh@kernel.org>
2020-05-28dt-bindings: clock: Convert i.MX31 clock to json-schemaAnson Huang2-90/+120
Convert the i.MX31 clock binding to DT schema format using json-schema. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Rob Herring <robh@kernel.org>
2020-05-28dt-bindings: clock: Convert i.MX35 clock to json-schemaAnson Huang2-114/+139
Convert the i.MX35 clock binding to DT schema format using json-schema. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Rob Herring <robh@kernel.org>
2020-05-28dt-bindings: clock: Convert i.MX5 clock to json-schemaAnson Huang2-28/+65
Convert the i.MX5 clock binding to DT schema format using json-schema. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Rob Herring <robh@kernel.org>
2020-05-28dt-bindings: clock: Convert i.MX7D clock to json-schemaAnson Huang2-13/+65
Convert the i.MX7D clock binding to DT schema format using json-schema. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Rob Herring <robh@kernel.org>
2020-05-27clk: lochnagar: Move binding over to dtschemaCharles Keepax2-94/+78
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Rob Herring <robh@kernel.org>
2020-05-27dt-bindings: clock: Convert i.MX6UL clock to json-schemaAnson Huang2-13/+66
Convert the i.MX6UL clock binding to DT schema format using json-schema. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org>
2020-05-27dt-bindings: clock: Convert i.MX6SLL clock to json-schemaAnson Huang2-36/+66
Convert the i.MX6SLL clock binding to DT schema format using json-schema. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org>
2020-05-27dt-bindings: clock: Convert i.MX6SL clock to json-schemaAnson Huang2-10/+48
Convert the i.MX6SL clock binding to DT schema format using json-schema. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org>
2020-05-27dt-bindings: clock: Convert i.MX6SX clock to json-schemaAnson Huang2-13/+70
Convert the i.MX6SX clock binding to DT schema format using json-schema. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org>
2020-05-27dt-bindings: clock: Convert i.MX6Q clock to json-schemaAnson Huang2-41/+72
Convert the i.MX6Q clock binding to DT schema format using json-schema. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org>
2020-05-27dt-bindings: clock: Add Marvell MMP Audio Clock Controller bindingLubomir Rintel1-0/+74
This describes the bindings for a controller that generates master and bit clocks for the I2S interface. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200519224151.2074597-13-lkundrak@v3.sk Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-27dt-bindings: clock: Make marvell,mmp2-clock a power controllerLubomir Rintel1-0/+5
This is a binding for the MMP2 power management units. As such apart from providing the clocks, they also manage the power islands. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200519224151.2074597-10-lkundrak@v3.sk Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-26dt-bindings: clk: sprd: add mipi_csi_xx clocks for SC9863AChunyan Zhang1-0/+1
mipi_csi_xx clocks are used by camera sensors. Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/20200527053638.31439-3-zhang.lyra@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-26dt-bindings: clock: Add YAML schemas for QCOM A53 PLLSivaprakash Murugesan2-22/+40
This patch adds schema for primary CPU PLL found on few Qualcomm platforms. Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lkml.kernel.org/r/1588573803-3823-1-git-send-email-sivaprak@codeaurora.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-26dt-bindings: documentation: add clock bindings information for AgilexDinh Nguyen1-0/+46
Document the Agilex clock bindings, and add the clock header file. The clock header is an enumeration of all the different clocks on the Agilex platform. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/20200512181647.5071-4-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-26dt-bindings: clk: intel: Add bindings document & header file for CGURahul Tanwar1-0/+44
Clock generation unit(CGU) is a clock controller IP of Intel's Lightning Mountain(LGM) SoC. Add DT bindings include file and document for CGU clock controller driver of LGM. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com> Link: https://lkml.kernel.org/r/8dce2be13195aab20c6b11fca6af0fffe22d5241.1587102634.git.rahul.tanwar@linux.intel.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-20dt-bindings: clock: renesas: mstp: Convert to json-schemaGeert Uytterhoeven2-60/+82
Convert the Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks Device Tree binding documentation to json-schema. Drop R-Car Gen2 compatible values, which were obsoleted by the unified "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT bindings. Replace the obsolete example for R-Car H2 by an example that is still valid. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200508100321.6720-1-geert+renesas@glider.be
2020-05-18dt-bindings: clock: renesas: div6: Convert to json-schemaGeert Uytterhoeven2-40/+60
Convert the Renesas CPG DIV6 Clock Device Tree binding documentation to json-schema. Drop R-Car Gen2 compatible values, which were obsoleted by the unified "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT bindings. Update the example to match reality. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200507075026.31941-1-geert+renesas@glider.be
2020-05-14clk: qcom: Add DT bindings for MSM8939 GCCBryan O'Donoghue1-0/+3
Add compatible strings and the include files for the MSM8939 GCC. Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-arm-msm@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Tested-by: Vincent Knecht <vincent.knecht@mailoo.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lkml.kernel.org/r/20200512115023.2856617-2-bryan.odonoghue@linaro.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-14clk: qcom: mmcc-msm8996: Properly describe GPU_GX gdscBjorn Andersson1-0/+4
The GPU_GX GDSC depends on both GPU GDSC being enabled and that the VDD_GX rail is powered, so update the description of the node to cover these requirements. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lkml.kernel.org/r/20200417070044.1376212-3-bjorn.andersson@linaro.org Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-14dt-bindings: Fix incorrect 'reg' property sizesRob Herring13-28/+23
The examples template is a 'simple-bus' with a size of 1 cell for had between 2 and 4 cells which really only errors on I2C or SPI type devices with a single cell. The easiest fix in most cases is to change the 'reg' property to for 1 cell address and size. In some cases with child devices having 2 cells, that doesn't make sense so a bus node is needed. Acked-by: Stephen Boyd <sboyd@kernel.org> # clk Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Rob Herring <robh@kernel.org>
2020-05-11dt-bindings: clock: Convert ingenic,cgu.txt to YAMLPaul Cercueil2-57/+122
Convert the ingenic,cgu.txt doc file to ingenic,cgu.yaml. The binding documentation has been updated as well. The node can have a child node that corresponds to the USB PHY, which happens to be present in the middle of the CGU registers. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Rob Herring <robh@kernel.org>
2020-05-03dt-bindings: clock: Convert Calxeda clock bindings to json-schemaAndre Przywara2-17/+82
Convert the Calxeda clock bindings to DT schema format using json-schema. This just covers the actual PLL and divider clock nodes. In the actual DTs they are somewhat unconnected (no ranges or bus compatible) children of the sregs node, but for the actual clock bindings this is not relevant. One oddity is that the addresses are relative to the parent node, without that being pronounced using a ranges property. But this is too late to fix now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org>
2020-05-03dt-bindings: Remove cases of 'allOf' containing a '$ref'Rob Herring1-3/+2
json-schema versions draft7 and earlier have a weird behavior in that any keywords combined with a '$ref' are ignored (silently). The correct form was to put a '$ref' under an 'allOf'. This behavior is now changed in the 2019-09 json-schema spec and '$ref' can be mixed with other keywords. The json-schema library doesn't yet support this, but the tooling now does a fixup for this and either way works. This has been a constant source of review comments, so let's change this treewide so everyone copies the simpler syntax. Scripted with ruamel.yaml with some manual fixups. Some minor whitespace changes from the script. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Maxime Ripard <mripard@kernel.org> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-By: Vinod Koul <vkoul@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Wolfram Sang <wsa@the-dreams.de> # for I2C Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> #for-iio Reviewed-by: Stephen Boyd <sboyd@kernel.org> # clock Signed-off-by: Rob Herring <robh@kernel.org>
2020-04-28dt-bindings: clock: renesas: cpg-mssr: Document r8a7742 bindingLad Prabhakar1-0/+1
Add binding documentation for the RZ/G1H (R8A7742) Clock Pulse Generator driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1587678050-23468-7-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-04-17Merge branch 'dt/linus' into dt/nextRob Herring1-1/+1
2020-04-16dt-bindings: Clean-up schema indentation formattingRob Herring3-21/+20
Fix various inconsistencies in schema indentation. Most of these are list indentation which should be 2 spaces more than the start of the enclosing keyword. This doesn't matter functionally, but affects running scripts which do transforms on the schema files. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Maxime Ripard <mripard@kernel.org> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-By: Vinod Koul <vkoul@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Rob Herring <robh@kernel.org>
2020-04-14dt-bindings: clock: syscon-icst: Remove unneeded unit nameFabio Estevam1-1/+1
The following warnings are seen with 'make dt_binding_check': Documentation/devicetree/bindings/clock/arm,syscon-icst.example.dts:17.16-24.11: Warning (unit_address_vs_reg): /example-0/clock@00: node has a unit name, but no reg or ranges property Documentation/devicetree/bindings/clock/arm,syscon-icst.example.dts:17.16-24.11: Warning (unit_address_format): /example-0/clock@00: unit name should not have leading 0s Fix them by removing the unneeded clock unit name. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
2020-04-14dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add r8a77961 supportYoshihiro Shimoda1-1/+3
This patch adds support for r8a77961 (R-Car M3-W+). To avoid confusion between R-Car M3-W (R8A77960) and R-Car M3-W+ (R8A77961), this patch also updates the comment of "renesas,r8a7796-rcar-usb2-clock-sel". Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1585200608-30103-1-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-04-05Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxLinus Torvalds20-324/+720
Pull clk updates from Stephen Boyd: "There's not much to see in the core framework this time around. Instead the majority of the diff is the normal collection of driver additions for new SoCs and non-critical clk data fixes and updates. The framework must be middle aged. The two biggest directories in the diffstat show that the Qualcomm and Unisoc support added a handful of big drivers for new SoCs but that's not really the whole story because those new drivers tend to add large numbers of lines of clk data. There's a handful of AT91 clk drivers added this time around too and a bunch of improvements to drivers like the i.MX driver. All around lots of updates and fixes in various clk drivers which is good to see. The core framework has only one real major change which has been baking in next for the past couple months. It fixes the framework so that it stops caching a clk's phase when the phase clk_op returns an error. Before this change we would consider some negative errno as a phase and that just doesn't make sense. Core: - Don't show clk phase when it is invalid New Drivers: - Add support for Unisoc SC9863A clks - Qualcomm SM8250 RPMh and MSM8976 RPM clks - Qualcomm SM8250 Global Clock Controller (GCC) support - Qualcomm SC7180 Modem Clock Controller (MSS CC) support - EHRPWM's TimeBase clock(TBCLK) for TI AM654 SoCs - Support PMC clks on at91sam9n12, at91rm9200, sama5d3, and at91sam9g45 SoCs Updates: - GPU GX GDSC support on Qualcomm sc7180 - Fixes and improvements for the Marvell MMP2/MMP3 SoC clk drivers - A series from Anson to convert i.MX8 clock bindings to json-schema - Update i.MX pll14xx driver to include new frequency entries for pll1443x table, and return error for invalid PLL type - Add missing of_node_put() call for a number of i.MX clock drivers - Drop flag CLK_IS_CRITICAL from 'A53_CORE' mux clock, as we already have the flag on its child cpu clock - Fix a53 cpu clock for i.MX8 drivers to get it source from ARM PLL via CORE_SEL slice, and source from A53 CCM clk root when we need to change ARM PLL frequency. Thus, we can support core running above 1GHz safely - Update i.MX pfdv2 driver to check zero rate and use determine_rate for getting the best rate - Add CLKO2 for imx8mm, SNVS clock for imx8mn, and PXP clock for imx7d - Remove PMC clks from Tegra clk driver - Improved clock/reset handling for the Renesas R-Car USB2 Clock Selector - Conversion to json-schema of the Renesas CPG/MSSR DT bindings - Add Crypto clocks on Renesas R-Car M3-W/W+, M3-N, E3, and D3 - Add RPC (QSPI/HyperFLASH) clocks on Renesas R-Car H3, M3-W/W+, and M3-N - Update Amlogic audio clock gate hierarchy for meson8 and gxbb - Update Amlogic g12a spicc clock sources - Support for Ingenic X1000 TCU clks" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (146 commits) clk: sprd: fix to get a correct ibias of pll dt-bindings: imx8mm-clock: Fix the file path dt-bindings: imx8mq-clock: Fix the file path clk: qcom: rpmh: Drop unnecessary semicolons clk: qcom: rpmh: Simplify clk_rpmh_bcm_send_cmd() clk: tegra: Use NULL for pointer initialization clk: sprd: add clocks support for SC9863A clk: sprd: support to get regmap from parent node clk: sprd: Add macros for referencing parents without strings clk: sprd: Add dt-bindings include file for SC9863A dt-bindings: clk: sprd: add bindings for sc9863a clock controller dt-bindings: clk: sprd: rename the common file name sprd.txt to SoC specific clk: sprd: add gate for pll clocks MAINTAINERS: dt: update reference for arm-integrator.txt clk: mmp2: Fix bit masks for LCDC I/O and pixel clocks clk: mmp2: Add clock for fifth SD HCI on MMP3 dt-bindings: marvell,mmp2: Add clock id for the fifth SD HCI on MMP3 clk: mmp2: Add clocks for the thermal sensors dt-bindings: marvell,mmp2: Add clock ids for the thermal sensors clk: mmp2: add the GPU clocks ...
2020-04-03Merge branches 'clk-unisoc', 'clk-tegra', 'clk-qcom' and 'clk-imx' into clk-nextStephen Boyd11-96/+385
- Add support for Unisoc SC9863A clks - GPU GX GDSC support on Qualcomm sc7180 - Qualcomm SM8250 RPMh and MSM8976 RPM clks - Qualcomm SM8250 Global Clock Controller (GCC) support - Qualcomm SC7180 Modem Clock Controller (MSS CC) support * clk-unisoc: clk: sprd: fix to get a correct ibias of pll clk: sprd: add clocks support for SC9863A clk: sprd: support to get regmap from parent node clk: sprd: Add macros for referencing parents without strings clk: sprd: Add dt-bindings include file for SC9863A dt-bindings: clk: sprd: add bindings for sc9863a clock controller dt-bindings: clk: sprd: rename the common file name sprd.txt to SoC specific clk: sprd: add gate for pll clocks * clk-tegra: clk: tegra: Use NULL for pointer initialization clk: tegra: Remove audio clocks configuration from clock driver clk: tegra: Remove tegra_pmc_clk_init along with clk ids clk: tegra: Remove CLK_M_DIV fixed clocks clk: tegra: Fix Tegra PMC clock out parents clk: tegra: Add Tegra OSC to clock lookup clk: tegra: Add support for OSC_DIV fixed clocks dt-bindings: soc: tegra-pmc: Add ID for Tegra PMC 32 kHz blink clock dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings dt-bindings: tegra: Convert Tegra PMC bindings to YAML dt-bindings: clock: tegra: Add IDs for OSC clocks * clk-qcom: (21 commits) clk: qcom: rpmh: Drop unnecessary semicolons clk: qcom: rpmh: Simplify clk_rpmh_bcm_send_cmd() clk: qcom: gcc: Add USB3 PIPE clock and GDSC for SM8150 ipq806x: gcc: Added the enable regs and mask for PRNG clk: qcom: Add modem clock controller driver for SC7180 clk: qcom: gcc: Add support for modem clocks in GCC dt-bindings: clock: Add YAML schemas for the QCOM MSS clock bindings clk: qcom: clk-rpm: add missing rpm clk for ipq806x clk: qcom: gcc: Add global clock controller driver for SM8250 dt-bindings: clock: Add SM8250 GCC clock bindings clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLs clk: qcom: clk-alpha-pll: Refactor trion PLL clk: qcom: clk-alpha-pll: Use common names for defines dt-bindings: clock: rpmcc: Document msm8976 compatible clk: qcom: smd: Add support for MSM8976 rpm clocks clk: qcom: clk-rpmh: Wait for completion when enabling clocks clk: qcom: rpmh: Add support for RPMH clocks on SM8250 dt-bindings: clock: Add RPMHCC bindings for SM8250 clk: qcom: alpha-pll: Make error prints more informative clk: qcom: gpucc: Add support for GX GDSC for SC7180 ... * clk-imx: (43 commits) dt-bindings: imx8mm-clock: Fix the file path dt-bindings: imx8mq-clock: Fix the file path clk: imx: clk-gate2: Pass the device to the register function clk: imx7d: Add PXP clock clk: imx8mq: A53 core clock no need to be critical clk: imx8mp: A53 core clock no need to be critical clk: imx8mm: A53 core clock no need to be critical clk: imx8mn: A53 core clock no need to be critical clk: imx: pllv4: use prepare/unprepare clk: imx: pfdv2: determine best parent rate clk: imx: pfdv2: switch to use determine_rate clk: imx: Fix division by zero warning on pfdv2 clk: imx: clk-sscg-pll: Drop unnecessary initialization clk: imx: pll14xx: Return error if pll type is invalid clk: imx: imx8mp: fix a53 cpu clock clk: imx: imx8mn: fix a53 cpu clock clk: imx: imx8mm: fix a53 cpu clock clk: imx: imx8mq: fix a53 cpu clock clk: imx8mp: Rename the IMX8MP_CLK_HDMI_27M clock clk: imx8mn: Remove unused includes ...
2020-04-03Merge branches 'clk-ti', 'clk-ingenic', 'clk-typo', 'clk-at91', 'clk-mmp2' and 'clk-arm-icst' into clk-nextStephen Boyd6-125/+202
- EHRPWM's TimeBase clock(TBCLK) for TI AM654 SoCs - Support PMC clks on at91sam9n12, at91rm9200, sama5d3, and at91sam9g45 SoCs - Fixes and improvements for the Marvell MMP2/MMP3 SoC clk drivers * clk-ti: clk: keystone: Add new driver to handle syscon based clocks dt-bindings: clock: Add binding documentation for TI EHRPWM TBCLK * clk-ingenic: clk: ingenic/TCU: Fix round_rate returning error clk: ingenic/jz4770: Exit with error if CGU init failed clk: JZ4780: Add function for enable the second core. clk: Ingenic: Add support for TCU of X1000. * clk-typo: clk: Fix trivia typo in comment exlusive => exclusive * clk-at91: clk: at91: add at91rm9200 pmc driver clk: at91: add at91sam9n12 pmc driver clk: at91: add sama5d3 pmc driver clk: at91: add at91sam9g45 pmc driver clk: at91: usb: introduce num_parents in driver's structure clk: at91: usb: use proper usbs_mask clk: at91: sam9x60: fix usb clock parents clk: at91: usb: continue if clk_hw_round_rate() return zero clk: at91: sam9x60: Don't use audio PLL * clk-mmp2: clk: mmp2: Fix bit masks for LCDC I/O and pixel clocks clk: mmp2: Add clock for fifth SD HCI on MMP3 dt-bindings: marvell,mmp2: Add clock id for the fifth SD HCI on MMP3 clk: mmp2: Add clocks for the thermal sensors dt-bindings: marvell,mmp2: Add clock ids for the thermal sensors clk: mmp2: add the GPU clocks dt-bindings: marvell,mmp2: Add clock ids for the GPU clocks clk: mmp2: Add PLLs that are available on MMP3 dt-bindings: marvell,mmp2: Add clock ids for MMP3 PLLs clk: mmp2: Check for MMP3 dt-bindings: clock: Add MMP3 compatible string clk: mmp2: Stop pretending PLL outputs are constant clk: mmp2: Add support for PLL clock sources dt-bindings: clock: Convert marvell,mmp2-clock to json-schema clk: mmp2: Constify some strings clk: mmp2: Remove a unused prototype * clk-arm-icst: MAINTAINERS: dt: update reference for arm-integrator.txt clk: versatile: Add device tree probing for IM-PD1 clocks clk: versatile: Export icst_clk_setup() dt-bindings: clock: Create YAML schema for ICST clocks
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