linux-dev - Linux kernel development work

Age	Commit message (Collapse)	Author	Files	Lines
2017-12-11	media: dt-bindings: media: xilinx: fix typo in example	Akinobu Mita	1	-1/+1
	Fix typo s/:/;/ Cc: Rob Herring <robh+dt@kernel.org> Cc: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
2016-04-25	[media] Documentation: dt: media: fix spelling mistake	Eric Engestrom	1	-1/+1
	Fix spelling mistake. Signed-off-by: Eric Engestrom <eric@engestrom.ch> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
2015-04-03	[media] v4l: xilinx: Add Test Pattern Generator driver	Laurent Pinchart	1	-0/+71
	The TPG generates multiple static or dynamic test patterns. The driver currently hardcodes the pattern to the moving box pattern. Signed-off-by: Christian Kohn <christian.kohn@xilinx.com> Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
2015-04-03	[media] v4l: xilinx: Add Video Timing Controller driver	Laurent Pinchart	1	-0/+33
	The Video Timing Controller (VTC) includes a timing detector and/or a timing generator. Only the generator is currently supported. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
2015-04-03	[media] v4l: xilinx: Add Xilinx Video IP core	Laurent Pinchart	2	-0/+90
	Xilinx platforms have no hardwired video capture or video processing interface. Users create capture and memory to memory processing pipelines in the FPGA fabric to suit their particular needs, by instantiating video IP cores from a large library. The Xilinx Video IP core is a framework that models a video pipeline described in the device tree and expose the pipeline to userspace through the media controller and V4L2 APIs. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>