linux-dev - Linux kernel development work

Age	Commit message (Collapse)	Author	Files	Lines
2019-10-03	reset: uniphier-glue: Add Pro5 USB3 support	Kunihiko Hayashi	1	-2/+3
	Pro5 SoC has same scheme of USB3 reset as Pro4, so the data for Pro5 is equivalent to Pro4. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2019-01-07	dt-bindings: reset: uniphier: Add AHCI core reset description	Kunihiko Hayashi	1	-0/+3
	Add compatible strings for reset control of AHCI core implemented in UniPhier SoCs. The reset control belongs to AHCI glue layer. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2019-01-07	dt-bindings: reset: uniphier: Replace the expression of USB3 with generic peripherals	Kunihiko Hayashi	1	-11/+11
	Replace the expression of "USB3 glue layer" with the glue layer of the generic peripherals to allow other devices to use it. The reset control belongs to this glue layer. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-07-16	dt-bindings: reset: uniphier: add USB3 core reset support	Kunihiko Hayashi	1	-0/+56
	Add DT bindings for reset control of USB3 core implemented in UniPhier SoCs. The reset control belongs to USB3 glue layer. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-10-05	reset: uniphier: add PXs3 reset data	Masahiro Yamada	1	-0/+3
	Add basic reset data for Socionext's new SoC PXs3. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-08-14	reset: uniphier: add analog amplifiers reset control	Katsuhiro Suzuki	1	-0/+25
	Add a reset line for analog signal amplifier core (ADAMV) on UniPhier LD11/LD20 SoCs. Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-08-11	reset: uniphier: remove sLD3 SoC support	Masahiro Yamada	1	-2/+0
	This SoC is too old. It is difficult to maintain any longer. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-01-20	reset: uniphier: add compatible string for LD11 SD-reset block	Masahiro Yamada	1	-23/+24
	The LD11 SoC is equipped with not only MIO-reset but also SD-reset for controlling RST_n pin of the eMMC device. Update the binding document and remove unneeded "." from each line in itemization. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-10-22	reset: uniphier: rename MIO reset to SD reset for Pro5, PXs2, LD20 SoCs	Masahiro Yamada	1	-31/+31
	I made a mistake as for naming for this block. The MIO block is not implemented for these 3 SoCs in the first place. The current naming will be a trouble if an SoC with both MIO and SD-ctrl blocks appear in the future. This driver has just been merged in the previous merge window. Rename it before the release. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-24	reset: uniphier: add reset controller driver for UniPhier SoCs	Masahiro Yamada	1	-0/+93
	This is the initial commit for UniPhier reset controller driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>