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2022-08-24platform/chrome: cros_ec: Expose suspend_timeout_ms in debugfsEvan Green1-0/+22
In modern Chromebooks, the embedded controller has a mechanism where it will watch a hardware-controlled line that toggles in suspend, and wake the system up if an expected sleep transition didn't occur. This can be very useful for detecting power management issues where the system appears to suspend, but doesn't actually reach its lowest expected power states. Sometimes it's useful in debug and test scenarios to be able to control the duration of that timeout, or even disable the EC timeout mechanism altogether. Add a debugfs control to set the timeout to values other than the EC-defined default, for more convenient debug and development iteration. Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-by: Prashant Malani <pmalani@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Guenter Roeck <groeck@chromium.org> Link: https://lore.kernel.org/r/20220822144026.v3.1.Idd188ff3f9caddebc17ac357a13005f93333c21f@changeid [tzungbi: fix one nit in Documentation/ABI/testing/debugfs-cros-ec.] Signed-off-by: Tzung-Bi Shih <tzungbi@kernel.org>
2022-08-23dt-bindings: net: tja11xx: add nxp,refclk_in propertyWei Fang1-0/+17
TJA110x REF_CLK can be configured as interface reference clock intput or output when the RMII mode enabled. This patch add the property to make the REF_CLK can be configurable. Signed-off-by: Wei Fang <wei.fang@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-08-23docs: netlink: basic introduction to NetlinkJakub Kicinski3-0/+656
Provide a bit of a brain dump of netlink related information as documentation. Hopefully this will be useful to people trying to navigate implementing YAML based parsing in languages we won't be able to help with. I started writing this doc while trying to figure out what it'd take to widen the applicability of YAML to good old rtnl, but the doc grew beyond that as it usually happens. In all honesty a lot of this information is new to me as I usually follow the "copy an existing example, drink to forget" process of writing netlink user space, so reviews will be much appreciated. Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Acked-by: Jonathan Corbet <corbet@lwn.net> Link: https://lore.kernel.org/r/20220819200221.422801-2-kuba@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-08-23PM6125 regulator supportMark Brown2-11/+47
Merge series from Iskren Chernev <iskren.chernev@gmail.com>: This patch series adds SPMI and SMD regulator support for the PM6125 found on SM4250/SM6115 SoCs from QCom. This code has been tested on: * OnePlus Nord N100 (oneplus,billie2, SoC sm4250) * Redmi 9T (redmi,lemon, SoC sm6115) The main source used for this change is qpnp pm6125 support patch from caf [1]: [1]: https://source.codeaurora.org/quic/la/kernel/msm-5.4/commit/?h=kernel.lnx.5.4.r1-rel&id=d1220daeffaa440ffff0a8c47322eb0033bf54f5 v3: https://lkml.org/lkml/2022/7/31/303 v2: https://lkml.org/lkml/2022/7/26/885 v1: https://lkml.org/lkml/2021/8/28/144 Changes from v3: - fix compilation issue reported by kernel test robot - reorder HFSMPS/LDO+FTSMPS patches - add new slew-rate computation for HFSMPS - add proper pull-down support for new regs - name new regs/vals after HFSMPS instead of FTSMPS - address indentation/newline issues reported by Krzysztof - improve commit messages on SPMI/RPM related patches Changes from v2: - split spmi new regulator support in 2 patches - FTS and LDOs now have set_load and set_pull_down ops - add better commit messages on spmi patches - fix sob header order - fix tested device info (Redmi 9T, NOT Xiaomi 9T) - improve formatting in spmi binding docs - sort alphabetically in smd binding docs - sort alphabetically spmi pmics - sort alphabetically smd pmics Changes from v1: - add dt-bindings - split SPMI patch into new reg types and the new PMIC - add correct supply mapping Iskren Chernev (13): dt-bindings: regulator: qcom_spmi: Improve formatting of if-then blocks dt-bindings: regulator: qcom_spmi: Document PM6125 PMIC dt-bindings: regulator: qcom_smd: Sort compatibles alphabetically dt-bindings: regulator: qcom_smd: Document PM6125 PMIC regulator: qcom_spmi: Add support for HFSMPS regulator type regulator: qcom_spmi: Add support for LDO_510 and FTSMPS regulator: qcom_spmi: Sort pmics alphabetically (part 1) regulator: qcom_spmi: Sort pmics alphabetically (part 2) regulator: qcom_spmi: Add PM6125 PMIC support regulator: qcom_smd: Sort pmics alphabetically (part 1) regulator: qcom_smd: Sort pmics alphabetically (part 2) regulator: qcom_smd: Sort pmics alphabetically (part 3) regulator: qcom_smd: Add PM6125 RPM regulators .../regulator/qcom,smd-rpm-regulator.yaml | 26 +- .../regulator/qcom,spmi-regulator.yaml | 32 ++ drivers/regulator/qcom_smd-regulator.c | 400 ++++++++++-------- drivers/regulator/qcom_spmi-regulator.c | 378 ++++++++++++----- 4 files changed, 551 insertions(+), 285 deletions(-) -- 2.37.1
2022-08-23Add support for TI TPS65219 PMIC.Mark Brown1-0/+173
Merge series from Jerome Neanne <jneanne@baylibre.com>: This driver supports - 3 Buck regulators and 4 LDOs - low-power standby mode - warm/soft reset - basic fault handling (via interrupts). - power button Not implemented - DVS 1-Regulators: Full implementation and test Visual check: cat /sys/kernel/debug/regulator/regulator_summary Full validation requires userspace-consumer and virtual-regulator LDO1 is not used and output can be probbed on TP84.
2022-08-23ASoC: dt-bindings: Add missing (unevaluated|additional)Properties on child nodesRob Herring11-2/+39
In order to ensure only documented properties are present, node schemas must have unevaluatedProperties or additionalProperties set to false (typically). Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220823145649.3118479-8-robh@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-23Use devm helpers for regulator get and enableMark Brown1-0/+4
Merge series from Matti Vaittinen <mazziesaccount@gmail.com>: Use devm helpers for regulator get and enable NOTE: The series depends on commit ee94aff2628b ("Devm helpers for regulator get and enable") which currently sits in Mark's regulator/for-next A few* drivers seem to pattern demonstrated by pseudocode: - devm_regulator_get() - regulator_enable() - devm_add_action_or_reset(regulator_disable()) devm helpers for this pattern were added to remove bunch of code from drivers. Typically following: - replace 3 calls (devm_regulator_get[_optional](), regulator_enable(), devm_add_action_or_reset()) with just one (devm_regulator_get_enable[_optional]()). - drop disable callback. I believe this simplifies things by removing some dublicated code. This series reowrks a few drivers. There is still plenty of fish in the sea for people who like to improve the code (or count the beans ;]). Finally - most of the converted drivers have not been tested (other than compile-tested) due to lack of HW. All reviews and testing is _highly_ appreciated (as always!). Revision history: v3: - Drop already applied helper patches - Add a few more drivers RFCv1 => v2: - Add devm_regulator_bulk_get_enable() and devm_regulator_bulk_put() - Convert a couple of drivers to use the new devm_regulator_bulk_get_enable(). - Squash all IIO patches into one. Patch 1: Add new devm-helper APIs to docs. Patch 2: simplified CLK driver(s) Patch 3: simplified GPU driver(s) Patch 4 - 5: simplified hwmon driver(s) Patch 6 - 14: simplified IIO driver(s) --- Matti Vaittinen (14): docs: devres: regulator: Add new get_enable functions to devres.rst clk: cdce925: simplify using devm_regulator_get_enable() gpu: drm: simplify drivers using devm_regulator_*get_enable*() hwmon: lm90: simplify using devm_regulator_get_enable() hwmon: adm1177: simplify using devm_regulator_get_enable() iio: ad7192: Simplify using devm_regulator_get_enable() iio: ltc2688: Simplify using devm_regulator_*get_enable() iio: bmg160_core: Simplify using devm_regulator_*get_enable() iio: st_lsm6dsx: Simplify using devm_regulator_*get_enable() iio: ad7476: simplify using devm_regulator_get_enable() iio: ad7606: simplify using devm_regulator_get_enable() iio: max1241: simplify using devm_regulator_get_enable() iio: max1363: simplify using devm_regulator_get_enable() iio: hmc425a: simplify using devm_regulator_get_enable() .../driver-api/driver-model/devres.rst | 4 +++ drivers/clk/clk-cdce925.c | 21 +++---------- drivers/gpu/drm/bridge/sii902x.c | 22 ++------------ drivers/gpu/drm/meson/meson_dw_hdmi.c | 23 ++------------ drivers/hwmon/adm1177.c | 27 ++--------------- drivers/hwmon/lm90.c | 15 ++-------- drivers/iio/adc/ad7192.c | 15 ++-------- drivers/iio/adc/ad7476.c | 11 +------ drivers/iio/adc/ad7606.c | 22 ++------------ drivers/iio/adc/ad7606.h | 1 - drivers/iio/adc/max1241.c | 28 ++--------------- drivers/iio/adc/max1363.c | 11 +------ drivers/iio/amplifiers/hmc425a.c | 17 +---------- drivers/iio/dac/ltc2688.c | 23 ++------------ drivers/iio/gyro/bmg160_core.c | 24 ++------------- drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h | 2 -- drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c | 30 ++++--------------- 17 files changed, 41 insertions(+), 255 deletions(-) -- 2.37.1 -- Matti Vaittinen, Linux device drivers ROHM Semiconductors, Finland SWDC Kiviharjunlenkki 1E 90220 OULU FINLAND ~~~ "I don't think so," said Rene Descartes. Just then he vanished ~~~ Simon says - in Latin please. ~~~ "non cogito me" dixit Rene Descarte, deinde evanescavit ~~~ Thanks to Simon Glass for the translation =]
2022-08-23regulator: dt-bindings: Add TI TPS65219 PMIC bindingsJerome Neanne1-0/+173
Add TPS65219 PMIC bindings using json-schema. Describe required properties and regname-supply. regname-supply is required when bypass mode is used for a regulator. Describes regulator topology. Interrupts support. Add a power-button property to configure the EN/PB/VSENSE pin as a powerbutton: TPS65219 has a multipurpose pin called EN/PB/VSENSE that can be either: - EN in which case it functions as an enable pin. - VSENSE which compares the voltages and triggers an automatic on/off request. - PB in which case it can be configured to trigger an interrupt to the SoC. ti,power-button reflects the last one of those options where the board has a button wired to the pin and triggers an interrupt on pressing it. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Signed-off-by: Jerome Neanne <jneanne@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220805121852.21254-5-jneanne@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-23regulator: qcom_smd: Document PM6125 PMICIskren Chernev1-0/+4
Document the pm6125 compatible string and available regulators in the QCom SMD RPM regulator documentation. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220802221112.2280686-5-iskren.chernev@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-23regulator: qcom_smd: Sort compatibles alphabeticallyIskren Chernev1-11/+11
As requested by Krzysztof Kozlowski. Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220802221112.2280686-4-iskren.chernev@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-23regulator: qcom_spmi: Document PM6125 PMICIskren Chernev1-0/+20
Add support for pm6125 compatible string and add relevant supplies in QCom SPMI regulator documentation. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220802221112.2280686-3-iskren.chernev@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-23regulator: qcom_spmi: Improve formatting of if-then blocksIskren Chernev1-0/+12
Add a newline between if-then blocks for different compatible PMICs. Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220802221112.2280686-2-iskren.chernev@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-23regulator: dt-bindings: Add missing (unevaluated|additional)Properties on child nodesRob Herring8-0/+23
In order to ensure only documented properties are present, node schemas must have unevaluatedProperties or additionalProperties set to false (typically). Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220823145649.3118479-7-robh@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-23dt-bindings: interrupt-controller: arm,gic: Support two address and size cellsJean-Philippe Brucker1-2/+2
It should be valid for a GICv2m node, child of a GICv2 node, to use two cells per reg address and size. The QEMU virt device-tree currently fails validation because the schema imposes a single address and size cell. Amend the rule. Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220822152224.507497-4-jean-philippe@linaro.org
2022-08-23dt-bindings: interrupt-controller: arm,gic-v3: Make 'interrupts' optionalJean-Philippe Brucker1-1/+0
A GICv3 implementation without virtualization, such as the base QEMU virt machine (without -M virtualization=on), does not issue maintenance interrupts. Therefore its device-tree node does not need an 'interrupts' property. Currently, validating the QEMU virt device-tree throws a warning that 'interrupts' is missing. Make it optional. Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220822152224.507497-3-jean-philippe@linaro.org
2022-08-23dt-bindings: PCI: mediatek-gen3: Add support for MT8188 and MT8195Jianjun Wang1-2/+11
MT8188 and MT8195 are ARM platform SoCs with the same PCIe IP as MT8192. Also add new clock name "peri_mem" since the MT8188 and MT8195 use clock "peri_mem" instead of "top_133m". Link: https://lore.kernel.org/r/20220802120624.19258-1-jianjun.wang@mediatek.com Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-08-23spi: dt-bindings: snps,dw-apb-ssi: drop ref from reg-io-widthKrzysztof Kozlowski1-1/+0
reg-io-width is a standard property, so no need for defining its type Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220823100937.386880-1-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-23docs: devres: regulator: Add new get_enable functions to devres.rstMatti Vaittinen1-0/+4
Add the new devm_regulator_get_enable() and devm_regulator_get_enable_optional() to devres.rst Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com> Link: https://lore.kernel.org/r/55efb5a23822b8e1558d560a6ad906eadbc39a17.1660934107.git.mazziesaccount@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-23arm64: errata: add detection for AMEVCNTR01 incrementing incorrectlyIonela Voinescu1-0/+2
The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate as the system counter. On affected Cortex-A510 cores, AMEVCNTR01 increments incorrectly giving a significantly higher output value. This results in inaccurate task scheduler utilization tracking and incorrect feedback on CPU frequency. Work around this problem by returning 0 when reading the affected counter in key locations that results in disabling all users of this counter from using it either for frequency invariance or as FFH reference counter. This effect is the same to firmware disabling affected counters. Details on how the two features are affected by this erratum: - AMU counters will not be used for frequency invariance for affected CPUs and CPUs in the same cpufreq policy. AMUs can still be used for frequency invariance for unaffected CPUs in the system. Although unlikely, if no alternative method can be found to support frequency invariance for affected CPUs (cpufreq based or solution based on platform counters) frequency invariance will be disabled. Please check the chapter on frequency invariance at Documentation/scheduler/sched-capacity.rst for details of its effect. - Given that FFH can be used to fetch either the core or constant counter values, restrictions are lifted regarding any of these counters returning a valid (!0) value. Therefore FFH is considered supported if there is a least one CPU that support AMUs, independent of any counters being disabled or affected by this erratum. Clarifying comments are now added to the cpc_ffh_supported(), cpu_read_constcnt() and cpu_read_corecnt() functions. The above is achieved through adding a new erratum: ARM64_ERRATUM_2457168. Signed-off-by: Ionela Voinescu <ionela.voinescu@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: James Morse <james.morse@arm.com> Link: https://lore.kernel.org/r/20220819103050.24211-1-ionela.voinescu@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2022-08-23arm64: fix rodata=fullMark Rutland1-0/+2
On arm64, "rodata=full" has been suppored (but not documented) since commit: c55191e96caa9d78 ("arm64: mm: apply r/o permissions of VM areas to its linear alias as well") As it's necessary to determine the rodata configuration early during boot, arm64 has an early_param() handler for this, whereas init/main.c has a __setup() handler which is run later. Unfortunately, this split meant that since commit: f9a40b0890658330 ("init/main.c: return 1 from handled __setup() functions") ... passing "rodata=full" would result in a spurious warning from the __setup() handler (though RO permissions would be configured appropriately). Further, "rodata=full" has been broken since commit: 0d6ea3ac94ca77c5 ("lib/kstrtox.c: add "false"/"true" support to kstrtobool()") ... which caused strtobool() to parse "full" as false (in addition to many other values not documented for the "rodata=" kernel parameter. This patch fixes this breakage by: * Moving the core parameter parser to an __early_param(), such that it is available early. * Adding an (optional) arch hook which arm64 can use to parse "full". * Updating the documentation to mention that "full" is valid for arm64. * Having the core parameter parser handle "on" and "off" explicitly, such that any undocumented values (e.g. typos such as "ful") are reported as errors rather than being silently accepted. Note that __setup() and early_param() have opposite conventions for their return values, where __setup() uses 1 to indicate a parameter was handled and early_param() uses 0 to indicate a parameter was handled. Fixes: f9a40b089065 ("init/main.c: return 1 from handled __setup() functions") Fixes: 0d6ea3ac94ca ("lib/kstrtox.c: add "false"/"true" support to kstrtobool()") Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Ard Biesheuvel <ardb@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Jagdish Gediya <jvgediya@linux.ibm.com> Cc: Matthew Wilcox <willy@infradead.org> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Will Deacon <will@kernel.org> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20220817154022.3974645-1-mark.rutland@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2022-08-23docs/arm64: elf_hwcaps: unify newlines in HWCAP listsMartin Liška1-10/+0
Unify horizontal spacing (remove extra newlines) which are sensitive to visual presentation by Sphinx. Fixes: 5e64b862c482 ("arm64/sme: Basic enumeration support") Signed-off-by: Martin Liska <mliska@suse.cz> Reviewed-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/84e3d6cc-75cf-d6f3-9bb8-be02075aaf6d@suse.cz Signed-off-by: Will Deacon <will@kernel.org>
2022-08-23dt-bindings: PCI: qcom: Add SA8540P to bindingJohan Hovold1-0/+3
SA8540P is a new platform related to SC8280XP but which uses a single host interrupt for MSI routing. Link: https://lore.kernel.org/r/20220714071348.6792-4-johan+linaro@kernel.org Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Brian Masney <bmasney@redhat.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
2022-08-23dt-bindings: PCI: qcom: Add SC8280XP to bindingJohan Hovold1-1/+49
Add the SC8280XP platform to the binding. SC8280XP use four host interrupts for MSI routing so remove the obsolete comment referring to newer chipsets supporting one or eight interrupts (e.g. for backwards compatibility). Link: https://lore.kernel.org/r/20220714071348.6792-3-johan+linaro@kernel.org Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
2022-08-23dt-bindings: PCI: qcom: Enumerate platforms with single msi interruptJohan Hovold1-2/+15
Explicitly enumerate the older platforms that have a single msi host interrupt. This allows for adding further platforms with, for example, four msi interrupts without resorting to nested conditionals. Drop the redundant comment about older chipsets instead of moving it. Link: https://lore.kernel.org/r/20220714071348.6792-2-johan+linaro@kernel.org Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
2022-08-23dt-bindings: clock: exynos850: Add Exynos850 CMU_MFCMSCLSam Protsenko1-0/+25
CMU_MFCMSCL generates MFC, M2M, MCSC and JPEG clocks for BLK_MFCMSCL. Add clock indices and binding documentation for CMU_MFCMSCL. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220809113323.29965-4-semen.protsenko@linaro.org
2022-08-23dt-bindings: clock: exynos850: Add Exynos850 CMU_ISSam Protsenko1-0/+25
CMU_IS generates CSIS, IPP, ITP, VRA and GDC clocks for BLK_IS. Add clock indices and bindings documentation for CMU_IS domain. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220809113323.29965-3-semen.protsenko@linaro.org
2022-08-23dt-bindings: clock: exynos850: Add Exynos850 CMU_AUDSam Protsenko1-0/+19
CMU_AUD generates Cortex-A32 clock, bus clock and audio clocks for BLK_AUD. Add clock indices and binding documentation for CMU_AUD. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220809113323.29965-2-semen.protsenko@linaro.org
2022-08-23dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1Chanho Park1-0/+44
Add "samsung,exynosautov9-cmu-fsys0/1" compatibles to illustrate cmu_fsys0 and fsys1 for Exynos Auto v9 SoC. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/49eaadecfb346982dff46cffb870400b76a4e281.1659054220.git.chanho61.park@samsung.com
2022-08-22scsi: ufs: wb: Add explicit flush sysfs attributeJinyoung Choi1-0/+9
There is the following quirk to bypass "WB Flush" in Write Booster. - UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL If this quirk is not set, there is no knob that can control "WB Flush". There are three flags that control Write Booster Feature: 1. WB ON/OFF 2. WB Hibern Flush ON/OFF (implicitly) 3. WB Flush ON/OFF (explicit) The sysfs attribute that controls the WB was implemented. (1) In the case of "Hibern Flush", it is always good to turn on. Control may not be required. (2) Finally, "Flush" may be necessary because the Auto-Hibern8 is not supported in a specific environment. So the sysfs attribute that controls this is necessary. (3) Link: https://lore.kernel.org/r/20220804075354epcms2p8c21c894b4e28840c5fc651875b7f435f@epcms2p8 Reviewed-by: Avri Altman <avri.altman@wdc.com> Signed-off-by: Jinyoung Choi <j-young.choi@samsung.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2022-08-22dt-bindings: add documentation of xilinx clocking wizardShubhrajyoti Datta1-0/+77
Add the devicetree binding for the xilinx clocking wizard. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Link: https://lore.kernel.org/r/20220411100443.15132-2-shubhrajyoti.datta@xilinx.com Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-08-22dt-bindings: net: dsa: make phylink bindings required for CPU/DSA portsVladimir Oltean1-0/+17
It is desirable that new DSA drivers are written to expect that all their ports register with phylink, and not rely on the DSA core's workarounds to skip this process. To that end, DSA is being changed to warn existing drivers when such DT blobs are in use, and to opt new drivers out of the workarounds. Introduce another layer of validation in the DSA DT schema, and assert that CPU and DSA ports must have phylink-related properties present. Suggested-by: Rob Herring <robh+dt@kernel.org> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-08-22dt-bindings: net: dsa: rzn1-a5psw: add missing CPU port phy-mode to exampleVladimir Oltean1-0/+2
To prevent warnings during "make dt_bindings_check" after dsa-port.yaml will make phylink properties mandatory, add phy-mode = "internal" to the example. This new property is taken straight out of the SoC dtsi at arch/arm/boot/dts/r9a06g032.dtsi, so it seems likely that only the example needs to be fixed, rather than DT blobs in circulation. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-08-22dt-bindings: net: dsa: microchip: add missing CPU port phy-mode to exampleVladimir Oltean1-0/+4
The ksz_switch_chips[] element for KSZ9477 says that port 5 is an xMII port and it supports speeds of 10/100/1000. The device tree example does declare a fixed-link at 1000, and RGMII is the only one of those modes that supports this speed, so use this phy-mode. The microchip,ksz8565 compatible string is not supported by the microchip driver, however on Microchip's product page it says that there are 5 ports, 4 of which have internal PHYs and the 5th is an MII/RMII/RGMII port. It's a bit strange that this is port@6, but it is probably just the way it is. Select an RGMII phy-mode for this one as well. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-08-22dt-bindings: net: dsa: b53: add missing CPU port phy-mode to exampleVladimir Oltean1-0/+2
Looking at b53_srab_phylink_get_caps() I get no indication of what PHY modes does port 8 support, since it is implemented circularly based on the p->mode retrieved from the device tree (and in PHY_INTERFACE_MODE_NA it reports nothing to supported_interfaces). However if I look at the b53_switch_chips[] element for BCM58XX_DEVICE_ID, I see that port 8 is the IMP port, and SRAB means the IMP port is internal to the SoC. So use phy-mode = "internal" in the example. Note that this will make b53_srab_phylink_get_caps() go through the "default" case and report PHY_INTERFACE_MODE_INTERNAL to supported_interfaces, which is probably a good thing. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-08-22dt-bindings: net: dsa: hellcreek: add missing CPU port phy-mode/fixed-link to exampleVladimir Oltean1-0/+6
Looking at hellcreek_phylink_get_caps(), I see that depending on whether is_100_mbits is set, speeds of 1G or of 100M will be advertised. The de1soc_r1_pdata sets is_100_mbits to true. The PHY modes declared in the capabilities are MII, RGMII and GMII. GMII doesn't support 100Mbps, and as for RGMII, it would be a bit implausible to me to support this PHY mode but limit it to only 25 MHz. So I've settled on MII as a phy-mode in the example, and a fixed-link of 100Mbps. As a side note, there exists such a thing as "rev-mii", because the MII protocol is asymmetric, and "mii" is the designation for the MAC side (expected to be connected to a PHY), and "rev-mii" is the designation for the PHY side (expected to be connected to a MAC). I wonder whether "mii" or "rev-mii" should actually be used here, since this is a CPU port and presumably connected to another MAC. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Kurt Kanzenbach <kurt@linutronix.de> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-08-22dt-bindings: net: dsa: xrs700x: add missing CPU port phy-mode to exampleVladimir Oltean1-0/+2
Judging by xrs700x_phylink_get_caps(), I deduce that this switch supports the RGMII modes on port 3, so state this phy-mode in the example, such that users are encouraged to not rely on avoiding phylink for this port. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-08-22dt-bindings: clock: gpio-gate-clock: Convert to json-schemaConor Dooley4-23/+44
Convert the simple GPIO clock gate Device Tree binding to json-schema and fix-up references to this file in other text format bindings. Jyri Sarha is the file's only editor/author so they have been added as maintainer of the new yaml binding. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220727131015.2073100-1-conor.dooley@microchip.com Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-08-22dt-bindings: clock: Move versaclock.h to dt-bindings/clockLukas Bulwahn1-2/+2
Most of the clock related dt-binding header files are located in dt-bindings/clock folder. It would be good to keep all the similar header files at a single location. This was discovered while investigating the state of ownership of the files in include/dt-bindings/ according to the MAINTAINERS file. This change here is similar to commit 8e28918a85a0 ("dt-bindings: clock: Move ti-dra7-atl.h to dt-bindings/clock") and commit 35d35aae8177 ("dt-bindings: clock: Move at91.h to dt-bindigs/clock"). Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com> Link: https://lore.kernel.org/r/20220613081632.2159-3-lukas.bulwahn@gmail.com Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-08-22dt-bindings: clock: Move lochnagar.h to dt-bindings/clockLukas Bulwahn1-1/+1
Most of the clock-related dt-binding header files are located in include/dt-bindings/clock. It would be good to keep all the similar header files at a single location. This was discovered while investigating the state of ownership of the files in include/dt-bindings/ according to the MAINTAINERS file. This change here is similar to commit 8e28918a85a0 ("dt-bindings: clock: Move ti-dra7-atl.h to dt-bindings/clock") and commit 35d35aae8177 ("dt-bindings: clock: Move at91.h to dt-bindigs/clock"). Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com> Link: https://lore.kernel.org/r/20220613081632.2159-2-lukas.bulwahn@gmail.com Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-08-22dt-bindings: arm,versatile-sysreg: Convert to DT schema formatRob Herring2-10/+35
Convert the arm,versatile-sysreg binding to DT schema format. The original binding was missing 'simple-mfd' and a 'panel' sub node which the only user (versatile-ab.dts) of this binding has. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220810160341.51995-3-robh@kernel.org
2022-08-22dt-bindings: display: arm,versatile-tft-panel: Drop erroneous properties in exampleRob Herring1-3/+0
The 'arm,versatile-sysreg' node in the example should not have '#address-cells' and '#size-cells' properties as the child node doesn't have 'reg'. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220810160341.51995-2-robh@kernel.org
2022-08-22dt-bindings: gpu: arm,mali: restrict opp-table to objectsKrzysztof Kozlowski2-2/+4
Simple 'opp-table:true' accepts a boolean property as opp-table, so restrict it to object to properly enforce real OPP table nodes. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220818061713.9611-1-krzysztof.kozlowski@linaro.org
2022-08-22dt-bindings: interconnect: restrict opp-table to objectsKrzysztof Kozlowski3-3/+6
Simple 'opp-table:true' accepts a boolean property as opp-table, so restrict it to object to properly enforce real OPP table nodes. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220818061653.9524-1-krzysztof.kozlowski@linaro.org
2022-08-22dt-bindings: memory-controllers: fsl,imx8m-ddrc: restrict opp-table to objectsKrzysztof Kozlowski1-1/+2
Simple 'opp-table:true' accepts a boolean property as opp-table, so restrict it to object to properly enferce real OPP table nodes. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220818061549.9087-1-krzysztof.kozlowski@linaro.org
2022-08-22coresight: docs: Fix a broken referenceChristophe JAILLET1-1/+2
Since the commit in Fixes: tag, "coresight-cpu-debug.txt" has been turned into "arm,coresight-cpu-debug.yaml". Update the doc accordingly to avoid a 'make htmldocs' warning Fixes: 66d052047ca8 ("dt-bindings: arm: Convert CoreSight CPU debug to DT schema") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: James Clark <james.clark@arm.com> Link: https://lore.kernel.org/r/c7f864854e9e03916017712017ff59132c51c338.1659251193.git.christophe.jaillet@wanadoo.fr Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
2022-08-22Remove DECnet support from kernelStephen Hemminger5-256/+8
DECnet is an obsolete network protocol that receives more attention from kernel janitors than users. It belongs in computer protocol history museum not in Linux kernel. It has been "Orphaned" in kernel since 2010. The iproute2 support for DECnet was dropped in 5.0 release. The documentation link on Sourceforge says it is abandoned there as well. Leave the UAPI alone to keep userspace programs compiling. This means that there is still an empty neighbour table for AF_DECNET. The table of /proc/sys/net entries was updated to match current directories and reformatted to be alphabetical. Signed-off-by: Stephen Hemminger <stephen@networkplumber.org> Acked-by: David Ahern <dsahern@kernel.org> Acked-by: Nikolay Aleksandrov <razor@blackwall.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-08-22dt-bindings: net: ethernet-controller: add QUSGMII modeMaxime Chevallier1-0/+1
Add a new QUSGMII mode, standing for "Quad Universal Serial Gigabit Media Independent Interface", a derivative of USGMII which, similarly to QSGMII, allows to multiplex 4 1Gbps links to a Quad-PHY. The main difference with QSGMII is that QUSGMII can include an extension instead of the standard 7bytes ethernet preamble, allowing to convey arbitrary data such as Timestamps. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-08-22net: phy: Introduce QUSGMII PHY modeMaxime Chevallier1-0/+9
The QUSGMII mode is a derivative of Cisco's USXGMII standard. This standard is pretty similar to SGMII, but allows for faster speeds, and has the build-in bits for Quad and Octa variants (like QSGMII). The main difference with SGMII/QSGMII is that USXGMII/QUSGMII re-uses the preamble to carry various information, named 'Extensions'. As of today, the USXGMII standard only mentions the "PCH" extension, which is used to convey timestamps, allowing in-band signaling of PTP timestamps without having to modify the frame itself. This commit adds support for that mode. When no extension is in use, it behaves exactly like QSGMII, although it's not compatible with QSGMII. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-08-22dt-bindings: pinctrl: aspeed: Add missing properties to examplesRob Herring3-0/+16
The aspeed pinctrl parent node (SCU) in the examples is missing various properties. Add the properties in preparation for the SCU schema. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220810161635.73936-2-robh@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-22dt-bindings: pinctrl: rockchip: Document RV1126 pinctrlJagan Teki1-0/+1
Document dt-bindings for RV1126 SoC pinctrl support. Cc: linux-gpio@vger.kernel.org Cc: Linus Walleij <linus.walleij@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20220818124132.125304-7-jagan@edgeble.ai Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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