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2021-12-08drm/i915/rpl-s: Enable guc submission by defaultAnusha Srivatsa1-1/+1
Though, RPL-S is defined as subplatform of ADL-S, unlike ADL-S, it has GuC submission by default. v2: Remove extra parenthesis (Jani) v3: s/IS_RAPTORLAKE/IS_ADLS_RPLS (Jani) Cc: dri-devel@lists.freedesktop.org Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211203063545.2254380-4-anusha.srivatsa@intel.com
2021-12-08drm/i915/rpl-s: Add PCH Support for Raptor Lake SAnusha Srivatsa2-0/+2
Add the PCH ID for RPL-S. v2: Self contained commit message (Jani) Cc: dri-devel@lists.freedesktop.org Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211203063545.2254380-3-anusha.srivatsa@intel.com
2021-12-08drm/i915/rpl-s: Add PCI IDS for Raptor Lake SAnusha Srivatsa6-0/+23
Raptor Lake S(RPL-S) is a version 12 Display, Media and Render. For all i915 purposes it is the same as Alder Lake S (ADL-S). Introduce RPL-S as a subplatform of ADL-S. This patch adds PCI ids for RPL-S. BSpec: 53655 Cc: x86@kernel.org Cc: dri-devel@lists.freedesktop.org Cc: Ingo Molnar <mingo@redhat.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Acked-by: Dave Hansen <dave.hansen@linux.intel.com> # arch/x86 Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211203063545.2254380-2-anusha.srivatsa@intel.com
2021-12-07drm/i915: Allow cdclk squasher to be reconfigured liveVille Syrjälä1-3/+37
Supposedly we should be able to change the cdclk squasher waveform even when many pipes are active. Make it so. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211119131348.725220-6-mika.kahola@intel.com
2021-12-07drm/i915/display/dg2: Read CD clock from squasher tableMika Kahola1-1/+16
To calculate CD clock with squasher unit, we set CD clock ratio to fixed value of 34. The CD clock value is read from CD clock squasher table. BSpec: 54034 v2: Read ratio from register (Ville) Drop unnecessary local variable (Ville) Get CD clock from the given table v3: Calculate CD clock frequency based on waveform bit pattern (Ville) [v4: vsyrjala: Actually do a proper blind readout from the hardware] [v5: vsyrjala: Use has_cdclk_squasher()] Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211119131348.725220-5-mika.kahola@intel.com
2021-12-07drm/i915/display/dg2: Set CD clock squashing registersMika Kahola2-1/+48
Set CD clock squashing registers based on selected CD clock. v2: use slk_cdclk_decimal() to compute decimal values instead of a specific table (Ville) Set waveform based on CD clock table (Ville) Drop unnecessary local variable (Ville) v3: Correct function naming (Ville) Correct if-else structure (Ville) [v4: vsyrjala: Fix spaces vs. tabs] [v5: vsyrjala: Fix cd2x divider calculation (Uma), Add warn to waveform lookup (Uma), Handle bypass freq in waveform lookup, Generalize waveform handling in bxt_set_cdclk()] Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211119131348.725220-4-mika.kahola@intel.com
2021-12-07drm/i915/display/dg2: Sanitize CD clockMika Kahola1-3/+12
In case of CD clock squashing the divider is always 1. We don't need to calculate the divider in use so let's skip that for DG2. v2: Drop unnecessary local variable (Ville) v3: Avoid if-else structure (Ville) [v4: vsyrjala: Fix cd2x divider calculation (Uma), Introduce has_cdclk_squasher()] Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211119131348.725220-3-mika.kahola@intel.com
2021-12-07drm/i915/display/dg2: Introduce CD clock squashing tableMika Kahola2-6/+14
For CD clock squashing method, we need to define corresponding CD clock table for reference clocks, dividers and ratios for all CD clock options. BSpec: 54034 v2: Add CD squashing waveforms as part of CD clock table (Ville) v3: Waveform is 16 bits wide (Ville) [v4: vsyrjala: Nuke the non-squasher based table, Set .divider=2 for consistency, Pack intel_cdclk_vals a bit nicer] v5: Fix error in waveform value (Swati) v6 (Lucas): Rebase on upstream v7 (MattR): Drop 40.8, 81.6, and 122.4 MHz frequencies to reflect new bspec update. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211119131348.725220-2-mika.kahola@intel.com
2021-12-07drm/i915/ddi: add use_edp_hobl() and use_edp_low_vswing() helpersJani Nikula1-58/+36
Localize HOBL and low vswing VBT lookups to a couple of small helpers, and get rid of a bunch of local variables. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211203131318.2885969-1-jani.nikula@intel.com
2021-12-07drm/i915/snps: use div32 version of MPLLB word clock for UHBRJani Nikula2-0/+3
The mode set sequence for 128b/132b requires setting the div32 version of MPLLB clock. Bspec: 53880, 54128 Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211202144456.2541305-1-jani.nikula@intel.com
2021-12-07drm/i915/xelpd: Add Pipe Color Lut caps to platform configUma Shankar1-1/+4
XE_LPD has 128 Lut entries for Degamma, with additional 3 entries for extended range. It has 511 entries for gamma with additional 2 entries for extended range. v2: Updated lut size for 10bit gamma, added lut_tests (Ville) v3: Dropped the gamma lut tests fields (Ville) Signed-off-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211207071135.3660332-4-uma.shankar@intel.com
2021-12-07drm/i915/xelpd: Enable Pipe DegammaUma Shankar1-3/+11
Enable Pipe Degamma for XE_LPD. Extend the legacy implementation to incorparate the extended lut size for XE_LPD. v2: Added a helper for degamma lut size (Ville) Signed-off-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211207071135.3660332-3-uma.shankar@intel.com
2021-12-07drm/i915/xelpd: Enable Pipe color support for D13 platformUma Shankar1-0/+9
Enable pipe color support for Display 13 platforms. Currently limit to just 10bit gamma and later extend it for logarithmic gamma, once the new UAPI is agreed by community and implemented by a userspace consumer. v2: Updated dev_priv to i915 (Ville) Signed-off-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211207071135.3660332-2-uma.shankar@intel.com
2021-12-06drm/i915/dmc: Change max DMC FW size on ADL-PMadhumitha Tolakanahalli Pradeep1-1/+3
Increase the max size of DMC on ADL-P to account for support of new features in the current/upcoming DMC versions. Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211207023718.322349-1-madhumitha.tolakanahalli.pradeep@intel.com
2021-12-03drm/i915/adlp: Remove require_force_probe protectionClint Taylor1-1/+0
Remove force probe protection from ADL_P platform. Did not obsevre warnings, errors, flickering or any visual defects while doing ordinary tasks like browsing and editing documents in a two monitor setup. For more info drm-tip idle run results : https://intel-gfx-ci.01.org/tree/drm-tip/drmtip.html? Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Jon Bloomfield <jon.bloomfield@intel.com> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211204010140.22839-1-clinton.a.taylor@intel.com
2021-12-03drm/i915/adl_p: Add ddc pin mappingTejas Upadhyay2-2/+19
From VBT, ddc pin info suggests the following mapping: VBT DRIVER DDI TC1->ddc_pin=3 should translate to PORT_TC1->0x9 DDI TC2->ddc_pin=4 should translate to PORT_TC2->0xa DDI TC3->ddc_pin=5 should translate to PORT_TC3->0xb DDI TC4->ddc_pin=6 should translate to PORT_TC4->0xc Adding pin map to facilitate this translation as we cannot use existing icl ddc pin map due to conflict with DDI C and DDI TC1 info. Bspec:20124 v2: - Changed Author to Tejas Upadhyay Cc: Clinton Taylor <Clinton.A.Taylor@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Acked-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> Signed-off-by: Raviteja Goud Talla <ravitejax.goud.talla@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211203073720.3823371-1-ravitejax.goud.talla@intel.com
2021-12-03drm/i915: Get rid of the "sizes are 0 based" stuffVille Syrjälä2-26/+6
Replace the "sizes are 0 based" stuff with just straight up -1 where needed. Less confusing all around. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211201152552.7821-4-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2021-12-03drm/i915/fbc: Pimp the FBC debugfs outputVille Syrjälä1-0/+18
Now that each plane tracks its own no_fbc_reason we can print that out in debugfs, and we can also show which plane is currently selected for FBC duty. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-21-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2021-12-03drm/i915/fbc: No FBC+double wide pipeVille Syrjälä1-0/+5
FBC and double wide pipe are mutually exclusive. Disable FBC when we have to resort to double wide. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-20-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2021-12-03drm/i915/fbc: s/parms/fbc_state/Ville Syrjälä1-70/+68
Rename the 'params' to just fbc state. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-19-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2021-12-03drm/i915/fbc: Move plane pointer into intel_fbc_stateVille Syrjälä1-28/+26
Currently we track the FBC plane as a pointer under intel_fbc and also as a i9xx_plane_id under intel_fbc_state. Just store the pointer once in the fbc state. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-18-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2021-12-03drm/i915/fbc: Nuke state_cacheVille Syrjälä1-107/+62
fbc->state_cache has now become useless. We can simply update the reg params directly from the plane/crtc states during __intel_fbc_enable(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-17-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2021-12-03drm/i915/fbc: Disable FBC fully on FIFO underrunVille Syrjälä1-21/+8
Currently a FIFO underrun just causes FBC to be deactivated, and later checks then prevent it from being reactivated. We can simpify our lives a bit by logically disabling FBC on FIFO underruns. This avoids the funny intermediate state where FBC is logically enabled but can't actually be activated. v2: intel_wait_for_vblank() is no more Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-16-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2021-12-03drm/i915/fbc: Move stuff from intel_fbc_can_enable() into intel_fbc_check_plane()Ville Syrjälä1-12/+10
Don't really see a good reason why we can't just do the vgpu and modparam checks already in intel_fbc_check_plane(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-15-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2021-12-03drm/i915/fbc: Allocate intel_fbc dynamicallyVille Syrjälä4-98/+113
In the future we may have more than one FBC instance on some platforms. So let's just allocate it dynamically. This also lets us fully hide the implementation from prying eyes. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-14-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2021-12-03drm/i915/fbc: Introduce intel_fbc_add_plane()Ville Syrjälä4-8/+33
In order to better encapsulate the FBC implementation introduce a small helper to do the plane<->FBC instance association. We'll also try to structure the plane init code such that introducing multiple FBC instances will be easier down the line. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-13-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2021-12-03drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.cVille Syrjälä3-82/+82
In order to encapsulate FBC harder let's just move the debugfs stuff into intel_fbc.c. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-12-ville.syrjala@linux.intel.com Acked-by: Jani Nikula <jani.nikula@intel.com>
2021-12-03drm/i915/fbc: Pass i915 instead of FBC instance to FBC underrun stuffVille Syrjälä4-18/+16
The underrun code doesn't need to know any details about FBC, so just pass in the whole device rather than a specific FBC instance. We could make this a bit more fine grained by also passing in the pipe to intel_fbc_handle_fifo_underrun_irq() and letting the FBC code figure which FBC instance (if any) is active on said pipe. But that seems a bit overkill for this so don't bother. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-11-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2021-12-03drm/i915/fbc: Flatten __intel_fbc_pre_update()Ville Syrjälä1-21/+21
Use an early return to flatten most of __intel_fbc_pre_update(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-10-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2021-12-03drm/i915/fbc: Track FBC usage per-planeVille Syrjälä3-119/+121
In the future we may have multiple planes on the same pipe capable of using FBC. Prepare for that by tracking FBC usage per-plane rather than per-crtc. v2: s/intel_get_crtc_for_pipe/intel_crtc_for_pipe/ Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-9-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2021-12-03drm/i915/fbc: Pass around FBC instance instead of crtcVille Syrjälä1-17/+12
Pass the FBC instance instead of the crtc to a bunch of places. We also adjust intel_fbc_post_update() to do the intel_fbc_get_reg_params() things instead of doing it from the lower level function (which also gets called for front buffer tracking). Nothing in there will change during front buffer updates. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-8-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2021-12-03drm/i915/fbc: Reuse the same struct for the cache and paramsVille Syrjälä2-58/+40
The FBC state cache and params are now nearly identical. Just use the same structure for both. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-7-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2021-12-03drm/i915/fbc: Nuke more FBC stateVille Syrjälä2-85/+67
There isn't a good reason why we'd have to cache all this plane state stuff in the FBC state. Instead we can just pre-calculate what FBC will really need. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-6-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2021-12-03drm/i915/fbc: Relocate intel_fbc_override_cfb_stride()Ville Syrjälä1-21/+21
Move intel_fbc_override_cfb_stride() next to its cousins. Helps with later patches. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-5-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2021-12-03drm/i915/fbc: Nuke lots of crap from intel_fbc_state_cacheVille Syrjälä5-207/+166
There's no need to store all this stuff in intel_fbc_state_cache. Just check it all against the plane/crtc states and store only what we need. Probably more should get nuked still, but this is a start. So what we'll do is: - each plane will check its own state and update its local no_fbc_reason - the per-plane no_fbc_reason (if any) then gets propagated to the cache->no_fbc_reason while doing the actual update - fbc->no_fbc_reason gets updated in the end with either the value from the cache or directly from frontbuffer tracking It's still a bit messy, but should hopefuly get cleaned up more in the future. At least now we can observe each plane's reasons for rejecting FBC now more consistently, and we don't have so mcuh redundant state store all over the place. v2: store no_fbc_reason per-plane instead of per-pipe Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-4-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2021-12-03drm/i915/fbc: Pass whole plane state to intel_fbc_min_limit()Ville Syrjälä1-3/+4
No reason to burden the caller with the details on how the minimum compression limit is calculated, so just pass in the whole plane state instead of just the cpp value. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-3-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2021-12-03drm/i915/fbc: Eliminate racy intel_fbc_is_active() usageVille Syrjälä1-7/+2
The ilk fbc watermark computation uses intel_fbc_is_active() which is racy since we don't know whether FBC will be enabled or not at some point. So let's just assume it will be if both HAS_FBC() and the modparam agree. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-2-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2021-12-03drm/i915: Rename PLANE_CUS_CTL Y plane bitsVille Syrjälä2-8/+8
Rename the PLANE_CUS_CTL Y plane selection bits to actually say "Y plane". Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211201152552.7821-6-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2021-12-03drm/i915: Rename plane YUV order bitsVille Syrjälä3-12/+12
Rename the YUV byte order bits to be a bit more consistent. v2: Deal with gvt Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211201152552.7821-3-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2021-12-03drm/i915: Get rid of the 64bit PLANE_CC_VAL mmioVille Syrjälä2-10/+13
Let's just stick to 32bit mmio accesses so we can get rid of the bare "uncore" reg access in display code. The register are defined as 32bit in the spec anyway. We could define a 64bit "de" variant I suppose, but doesn't really make much sense just for this one case, and when we start to use the DSB for this stuff we'd also need another 64bit variant for that. Just easier to do 32bit always. While at it we can reorder stuff a bit so that we write the registers in order of increasing offset (more or less). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211201152552.7821-2-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2021-12-03drm/i915/display: stop including i915_drv.h from intel_display_types.hJani Nikula8-9/+22
Break the dependency on i915_drv.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ee740f494e416d875e057c2eda585f4e66d65500.1638366969.git.jani.nikula@intel.com
2021-12-03drm/i915/display: convert dp_to_i915() to a macroJani Nikula1-5/+1
Avoid looking into the guts of struct drm_i915_private in headers. Again, converting an inline function to a macro is less than ideal, but avoids having to pull in i915_drv.h just for the to_i915() part. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ed6c43455d13c90ebfed442b196625af5e6ede88.1638366969.git.jani.nikula@intel.com
2021-12-03drm/i915: move enum hpd_pin to intel_display.hJani Nikula2-24/+24
It's not the ideal location, but a better alternative than i915_drv.h. The goal is to break the intel_display_types.h to i915_drv.h dependency. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/9f882eff78cdc6b28c18e73f5e53f57e413240dc.1638366969.git.jani.nikula@intel.com
2021-12-03drm/i915: split out intel_pm_types.hJani Nikula3-63/+78
This is far from ideal, but it reduces the i915_drv.h dependency from intel_display_types.h. Maybe in the future we'll need a better split. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/c6c60d9a8f6dcd1fa2f4b187000c5bb6843a1371.1638366969.git.jani.nikula@intel.com
2021-12-03drm/i915/fb: move intel_fb_uses_dpt to intel_fb.c and un-inlineJani Nikula3-10/+12
Move fb functions where they belong, and un-inline to avoid looking into struct drm_i915_private guts in header files. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/4aa89f113ce6d840d62f50c989e2a1415483557c.1638366969.git.jani.nikula@intel.com
2021-12-03drm/i915/crtc: un-inline some crtc functions and move to intel_crtc.[ch]Jani Nikula3-44/+52
Move a number of crtc/pipe related functions to intel_crtc.[ch], and un-inline to avoid looking into struct drm_i915_private guts in header files. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/c0be2adc4a7f7e72a47e12a57f742aaa42b813e6.1638366969.git.jani.nikula@intel.com
2021-12-03drm/i915/selftest: Disable IRQ for timestamp calculationAnshuman Gupta1-2/+2
gt_pm selftest calculates engine ticks cycles and wall time cycles by delta of respective engine elapsed TIMESTAMP and ktime for period of 1000us. It compares the engine ticks cycles with wall time cycles. Disable local cpu interrupt so that interrupt handler does not switch out the thread during measure_clocks() and prevent miscalculation of engine tick cycles. v2: - nuke preempt_{disable,enable}, as disable_local_irq() disable the preemption. (Chris) Cc: Chris P Wilson <chris.p.wilson@intel.com> Cc: Badal Nilawar <badal.nilawar@intel.com> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211130132005.6305-1-anshuman.gupta@intel.com
2021-12-02drm/i915/dg2: extend Wa_1409120013 to DG2Matt Atwood1-2/+2
Extend existing workaround 1409120013 to DG2. Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211116174818.2128062-6-matthew.d.roper@intel.com
2021-12-02drm/i915/dg2: Add Wa_14010547955Matt Roper2-2/+7
This workaround is documented a bit strangely in the bspec; it's listed as an A0 workaround, but the description clarifies that the workaround is implicitly handled by the hardware and what the driver really needs to do is program a chicken bit to reenable some internal behavior. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211116174818.2128062-3-matthew.d.roper@intel.com
2021-12-02drm/i915/dg2: s/DISP_STEPPING/DISPLAY_STEPPING/Matt Roper1-1/+1
Commit cd0fcf5af791 ("drm/i915: rename DISP_STEPPING->DISPLAY_STEP and GT_STEPPING->GT_STEP") renamed all platforms' display stepping tests, but the DG2 patches were still in-flight at that time and did not incorporate the new naming scheme. Rename DG2's macro now for consistency with other platforms. Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211116174818.2128062-2-matthew.d.roper@intel.com
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