linux-dev - Linux kernel development work

Age	Commit message (Collapse)	Author	Files	Lines
2016-04-12	ARM: dts: am335x: Provide NAND ready pin	Roger Quadros	1	-0/+1
	On these boards NAND ready pin status is avilable over GPMC_WAIT0 pin. For NAND we don't use GPMC wait pin monitoring but get the NAND Ready/Busy# status using GPIOlib. GPMC driver provides the WAIT0 pin status over GPIOlib. Read speed increases from 7869 KiB/ to 8875 KiB/s and write speed was unchanged at 5100 KiB/s. Measured using mtd_speedtest.ko on am335x-evm. Cc: Teresa Remmet <t.remmet@phytec.de> Cc: Ilya Ledvich <ilya@compulab.co.il> Cc: Yegor Yefremov <yegorslists@googlemail.com> Cc: Rostislav Lisovy <lisovy@gmail.com> Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-02-26	ARM: dts: am335x: Disable wait pin monitoring for NAND	Roger Quadros	1	-3/+0
	The NAND Ready/Busy# line is connected to GPMC_WAIT0 pin and can't be used for wait state insertion for NAND I/O read/write. So disable read/write wait monitoring as per Reference Manual's suggestion [1]. [1] AM335x TRM: SPRUH73L: 7.1.3.3.12.2 NAND Device-Ready Pin Cc: Teresa Remmet <t.remmet@phytec.de> Cc: Ilya Ledvich <ilya@compulab.co.il> Cc: Yegor Yefremov <yegorslists@googlemail.com> Cc: Rostislav Lisovy <lisovy@gmail.com> Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-02-26	ARM: dts: am335x: Fix NAND device nodes	Roger Quadros	1	-0/+5
	Add compatible id, GPMC register resource and interrupt resource to NAND controller nodes. The GPMC node will provide an interrupt controller for the NAND IRQs. Cc: Teresa Remmet <t.remmet@phytec.de> Cc: Ilya Ledvich <ilya@compulab.co.il> Cc: Yegor Yefremov <yegorslists@googlemail.com> Cc: Rostislav Lisovy <lisovy@gmail.com> Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-11-30	ARM: dts: am335x-phycore-som: Use AM33XX_IOPAD pinmux macro	Javier Martinez Canillas	1	-30/+30
	Use the pinmux IOPAD macro to define the register absolute physical address instead of the offset from the padconf base address. This makes the DTS easier to read since matches the addresses listed in the Technical Reference Manual. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-10-12	ARM: dts: am335x-wega: Clean up regulators	Teresa Remmet	1	-17/+19
	Cleaned up the regulators on the wega board. Created a simple bus, renamed the regulators according to the schematics and added missing regulator on wega. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-09-14	ARM: dts: am335x-phycore-som: Fix mpu voltage	Teresa Remmet	1	-2/+2
	Fix the mpu voltage as it is set too low for the silicon revision 2.1. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-07-21	ARM: dts: Add support for phyCORE-AM335x SoM	Teresa Remmet	1	-0/+368
	phyCORE-AM335x is a SoM (System on Module) containing a AM335x SOC. The module can be connected to different carrier boards. Some hardware parts are configurable on the phyCORE-AM335x. So they are disabled on default in this som dtsi file. They will be enabled in the board dts files, when populated. * RAM up to 1GiB * PMIC * NAND flash up to 1GiB * Eth PHY on SOM: 1x RMII * SPI NOR flash 8MiB (optional) * i2c RTC (optional) * i2c EEPROM 4kiB (optional) Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Tony Lindgren <tony@atomide.com>