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The pinfunc definitions are ordered by mux_reg and so automatically by
conf_reg, too. PAD_TDO is the only pad that has a conf_reg but no
mux_reg. Put it to the place where it its in the order of conf_regs
instead of the top.
Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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This was introduced in commit 18e2b50407fb ("ARM: dts: imx25-pinfunc:
more defines").
Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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With the SION bit set a pin can be read as GPIO even though it's not muxed
as GPIO. This is useful at times. The downside however is that the signal
is not only routed to the GPIO IP but also all other IPs that can make use
of the pin. This resulted in more than one issue for me in the past. Things
like spi transfers that result in usb reenumeration or setting a GPIO to a
value that triggers an RTS irq for an UART.
This convinces me that the SION bit does more harm than good and so all
SION bits are removed that are not known to be needed.
Note that this has no influence on GPIOs under Linux as the gpio-mxc
driver just reports the level the pin is driven to for outputs and not
the level as seen on the pin.
If this commit introduces a regression for you, please report which SION
bit is essential for your setup.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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With SION set the level on such a pin is reported to the UART. So for
example when the CS5 pin is configured for GPIO mode and the level
changes this triggers an RTS interrupt on uart5.
Adding some severity to this issue: The imx uart driver currently
doesn't handle correctly irqs for changes on RI and DCD which are
enabled automatically when the respective UART is driven in DTE mode
(that is, has the fsl,dte-mode property set in the device tree). This
results in a stuck machine because the irq isn't cleared and so stalls
the CPU.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Apart from a few additions this also contains two fixes where the daisy
chain input selection register was missing. Moreover dropped _MUX from
some pins for consistency.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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This patch adds some values that are needed for an out-of-tree device
tree I'm currently working with.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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This patch adds some not yet defined pinfunctions. It also adds two
comments about mistakes in the i.MX25 reference manual so it is easier
to spot the difference between reference manual and pinfunction
definitions.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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input values are only useful for pin functions which define a input
register. This patch removes all input values of pin functions which do
not have an input configuration register.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Add some defines currently missing, fix ordering to make the list
sorted by (mux_reg, mux_val), make sure pins are grouped by mux_reg.
The same definitions are missing from the old pinmux header
(arch/arm/mach-imx/iomux-mx25.h) but as only legacy machine support uses
that and therefor the existing list is obviously good enough I didn't
spend the effort to add the corresponding definitions there, too.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Noticed while looking over the pad definitions. None of the bogus
definitions is used in-tree.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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This patch adds pin configurations for:
- csi aud6
- cspi1 uart3
- csi uart5
- cc
- csi sdhc2
- csi cspi3
- sd1 cspi2
- cspi1 pwm
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: devicetree@vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Eric Bénard <eric@eukrea.com>
Signed-off-by: Denis Carikli <denis@eukrea.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Uwe Kleine-König
Uwe Kleine-König
Markus Pargmann
Michael Grzeschik
Denis Carikli