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Update i.MX6ULL iomux header according to latest reference
manual Rev.1, 11/2017.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Signals available on both i.MX6UL and i.MX6ULL should have the same name
because it is the case of all others common signals, it avoids to make
mistakes (use the wrong ones) and it makes writing device tree files
less complicated. For example:
imx6ul-imx6ull-board.dtsi:
...
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
>;
};
imx6ul-board.dts:
#include <imx6ul.dtsi>
#include <imx6ul-imx6ull-board.dtsi>
...
imx6ull-board.dts:
#include <imx6ull.dtsi>
#include <imx6ul-imx6ull-board.dtsi>
...
Without this patch, the imx6ull-board.dtb will use
MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX instead of
MX6ULL_PAD_UART5_RX_DATA__UART5_DCE_RX and the uart5 will be
misconfigured.
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The iMX6ULL UART5_RTS_B_DATA_SELECT_INPUT DAISY Register has some different
bit definitions to that same register in the i.MX6UL.
The bits for the i.MX6UL:
000 CSI_DATA03_ALT8 — Selecting Pad: CSI_DATA03 for Mode: ALT8
001 GPIO1_IO08_ALT8 — Selecting Pad: GPIO1_IO08 for Mode: ALT8
010 GPIO1_IO09_ALT8 — Selecting Pad: GPIO1_IO09 for Mode: ALT8
011 ENET1_RX_EN_ALT1 — Selecting Pad: ENET1_RX_EN for Mode: ALT1
100 ENET1_TX_DATA0_ALT1 — Selecting Pad: ENET1_TX_DATA0 for Mode: ALT1
101 CSI_DATA02_ALT8 — Selecting Pad: CSI_DATA02 for Mode: ALT8
But for the i.MX6ULL:
000 CSI_DATA03_ALT8 — Selecting Pad: CSI_DATA03 for Mode: ALT8
001 GPIO1_IO08_ALT8 — Selecting Pad: GPIO1_IO08 for Mode: ALT8
010 GPIO1_IO09_ALT8 — Selecting Pad: GPIO1_IO09 for Mode: ALT8
011 UART1_CTS_B_ALT9 — Selecting Pad: UART1_CTS_B for Mode: ALT9
100 UART1_RTS_B_ALT9 — Selecting Pad: UART1_RTS_B for Mode: ALT9
101 ENET1_RX_EN_ALT1 — Selecting Pad: ENET1_RX_EN for Mode: ALT1
110 ENET1_TX_DATA0_ALT1 — Selecting Pad: ENET1_TX_DATA0 for Mode: ALT1
111 CSI_DATA02_ALT8 — Selecting Pad: CSI_DATA02 for Mode: ALT8
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The iMX6ULL UART5_RX_DATA_SELECT_INPUT DAISY Register has some different
bit definitions to that same register in the iMX6UL.
The bits for the iMX6UL:
000 CSI_DATA00_ALT8 — Selecting Pad: CSI_DATA00 for Mode: ALT8
001 CSI_DATA01_ALT8 — Selecting Pad: CSI_DATA01 for Mode: ALT8
010 GPIO1_IO04_ALT8 — Selecting Pad: GPIO1_IO04 for Mode: ALT8
011 GPIO1_IO05_ALT8 — Selecting Pad: GPIO1_IO05 for Mode: ALT
100 UART5_TX_DATA_ALT0 — Selecting Pad: UART5_TX_DATA for Mode: ALT
101 UART5_RX_DATA_ALT0 — Selecting Pad: UART5_RX_DATA for Mode: ALT
But for the iMX6ULL:
000 CSI_DATA00_ALT8 — Selecting Pad: CSI_DATA00 for Mode: ALT8
001 CSI_DATA01_ALT8 — Selecting Pad: CSI_DATA01 for Mode: ALT8
010 GPIO1_IO04_ALT8 — Selecting Pad: GPIO1_IO04 for Mode: ALT8
011 GPIO1_IO05_ALT8 — Selecting Pad: GPIO1_IO05 for Mode: ALT
100 UART1_TX_DATA_ALT9 — Selecting Pad: UART1_TX_DATA for Mode: ALT9
101 UART1_RX_DATA_ALT9 — Selecting Pad: UART1_RX_DATA for Mode: ALT9
110 UART5_TX_DATA_ALT0 — Selecting Pad: UART5_TX_DATA for Mode: ALT0
111 UART5_RX_DATA_ALT0 — Selecting Pad: UART5_RX_DATA for Mode: ALT0
Specifically for a board I am working on with the serial console on UART5
I need to be able to enable UART5_RX_DATA_ALT0 mode. There is no definition
for the iMX6ULL version of that in imx6ul-pinfunc.h or imx6ull-pinfunc.h.
Add definitions for the missing UART5 input select register bits of the
iMX6ULL.
Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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It is the 10th processor in the well-known imx6 series, and derived
from imx6ul but cost optimized. The more information about imx6ull
can be found at:
http://www.nxp.com/products/microcontrollers-and-processors/
arm-processors/i.mx-applications-processors/i.mx-6-processors
/i.mx6qp/i.mx-6ull-single-core-processor-with-arm-cortex-a7-core
:i.MX6ULL
imx6ul.dtsi is the SoC common stuff for both imx6ul and imx6ull;
imx6ul-14x14-evk.dts is the board common stuff for both imx6ul
and imx6ull 14x14 evk. In this patch, for SoC part, the
imx6ull.dtsi includes imx6ul.dtsi; for board part, imx6ull-14x14-evk.dts
includes imx6ul-14x14-evk.dts.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Anson Huang
Sébastien Szymanski
Stefan Wahren
Greg Ungerer
Peter Chen