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2013-05-23ARM: dts: lpc32xx: cpus/cpu nodes dts updatesLorenzo Pieralisi1-2/+6
This patch updates the in-kernel dts files according to the latest cpus and cpu bindings updates for ARM. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2012-11-14ARM: LPC32xx: Add the motor PWM to base dts fileAlban Bedel1-0/+7
Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-07-20ARM: LPC32xx: Add PWM to base dts fileAlexandre Pereira da Silva1-0/+5
Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com> Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-06-14ARM: LPC32xx: Fix lpc32xx.dtsi status property: "disable" -> "disabled"Roland Stigge1-7/+7
This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-06-14ARM: LPC32xx: High Speed UART configuration via DTRoland Stigge1-5/+11
This patch fixes the DTS files for the High Speed UARTs 1, 2 and 7 of the LPC32xx SoC, adjusting the compatible strings, adding interrupts and status configuration. On the PHY3250 reference board, UART2 is enabled. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2012-06-14ARM: LPC32xx: DT conversion of Standard UARTsRoland Stigge1-8/+26
This patch switches from static serial driver initialization to devicetree configuration. This way, the Standard UARTs of the LPC32xx SoC can be enabled individually via DT. E.g., instead of Kconfig configuration, the phy3250.dts activates UARTs 3 and 5. Signed-off-by: Roland Stigge <stigge@antcom.de> Tested-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2012-06-14ARM: LPC32xx: DTS adjustment for using pl18x primecellRoland Stigge1-1/+2
This patch adjusts the dts files to reference the pl18x primecell driver correctly. Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-06-14ARM: LPC32xx: DTS adjustment for key matrix controllerRoland Stigge1-0/+2
This patch connects the lpc32xx-key driver to the LPC32xx platform (via lpc32xx.dtsi), and more specifically to the reference board via its dts file. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2012-06-14ARM: LPC32xx: Adjust dtsi file for MLC controller configurationRoland Stigge1-2/+3
This patch takes into account that the MTD NAND MLC controller needs more registers, located actually before the previously allocated memory range, already starting at 200a8000 instead of 200b0000. Further, the interrupt for the controller is configured. Signed-off-by: Roland Stigge <stigge@antcom.de> Tested-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2012-05-30ARM: LPC32xx: Adjust dts files to gpio dt bindingRoland Stigge1-39/+2
The GPIO devicetree binding in 3.5 doesn't register the various LPC32xx GPIO banks via DT subnodes but always all at once, and changes the gpio referencing to 3 cells (bank, gpio, flags). This patch adjusts the DTS files to this binding that was just accepted to the gpio subsystem. Signed-off-by: Roland Stigge <stigge@antcom.de> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-04-22ARM: LPC32xx: DTS files for device tree conversionRoland Stigge1-0/+292
This patch adds the dts files for the reference machine of LPC32xx: * arch/arm/boot/dts/lpc32xx.dtsi: Include for devices based on LPC32xx * arch/arm/boot/dts/phy3250.dts: Board support for PHYTEC phyCORE-LPC3250 Signed-off-by: Roland Stigge <stigge@antcom.de>
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