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2014-06-10Merge branch 'for-v3.16/ti-clk-drv' of github.com:t-kristo/linux-pm into clk-nextMike Turquette1-1/+1
2014-06-06ARM: dts: OMAP5/DRA7: use omap5-mpu-dpll-clock capable of dealing with higher frequenciesNishanth Menon1-1/+1
OMAP5432, DRA75x and DRA72x have MPU DPLLs that need Duty Cycle Correction(DCC) to operate safely at frequencies >= 1.4GHz. Switch to "ti,omap5-mpu-dpll-clock" compatible property which provides this support. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-05-23ARM: dts: omap5-clocks.dtsi: add ti, set-rate-parent to dss_dss_clkTomi Valkeinen1-0/+1
Add ti,set-rate-parent to dss_dss_clk so that the DSS driver can set the rate. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-05-23ARM: dts: omap54xx-clocks: Correct abe_iclk clock nodePeter Ujfalusi1-4/+5
abe_iclk's parent is aess_fclk and not abe_clk. Also correct the parameters for clock rate calculation as used for OMAP4 since in PRCM level there's no difference between the two platform regarding to AESS/ABE clocking. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-05-23ARM: dts: omap54xx-clocks: remove the autoidle properties for clock nodesPeter Ujfalusi1-48/+0
In OMAP5 bit 8 in PRCM registers are not defined (Reserved) unlike their counterpart in OMAP4. It is better to not write to these bits. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-01-17ARM: dts: omap5 clock dataTero Kristo1-0/+1399
This patch creates a unique node for each clock in the OMAP5 power, reset and clock manager (PRCM). Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>